14634 lines
1.3 MiB
14634 lines
1.3 MiB
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_pmgr_h__
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#define __ga102_dev_pmgr_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PMGR 0x0000E7FF:0x0000D000 /* RW--D */
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#define NV_GPIO 0x00021FFF:0x00021000 /* RW--D */
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#define NV_PMGR_I2C0 0x0000D01F:0x0000D000
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#define NV_PMGR_I2C1 0x0000D03F:0x0000D020
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#define NV_PMGR_I2C2 0x0000D05F:0x0000D040
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#define NV_PMGR_I2C3 0x0000D07F:0x0000D060
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#define NV_PMGR_I2C4 0x0000D09F:0x0000D080
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#define NV_PMGR_I2C5 0x0000D0BF:0x0000D0A0
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#define NV_PMGR_I2C6 0x0000D0DF:0x0000D0C0
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#define NV_PMGR_I2C7 0x0000D0FF:0x0000D0E0
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#define NV_PMGR_I2C8 0x0000D11F:0x0000D100
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#define NV_PMGR_I2C9 0x0000D13F:0x0000D120
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#define NV_GPIO_PRIV_OUTPUT 0x0002109F:0x00021000
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#define NV_GPIO_OUTPUT 0x0002129F:0x00021200
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#define NV_GPIO_PAD 0x0002169F:0x00021600
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#define NV_GPIO_INTR 0x0002174F:0x00021600
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#define NV_PMGR_PRIV_GPIO_IN 0x0000D5DF:0x0000D580
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#define NV_PMGR_GPIO_IN 0x0000D79F:0x0000D740
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#define NV_PMGR_PRIV_0 0x0000D7CB:0x0000D7A0
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#define NV_PMGR_PRIV_1 0x0000D7DF:0x0000D7CC
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#define NV_PMGR_PRIV_2 0x0000D92F:0x0000D7E0
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#define NV_PMGR_DP_AUX 0x0000DBFF:0x0000D930
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#define NV_PMGR_INTR_0 0x0000DEAC:0x0000DC00
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#define NV_PMGR_MUTEX 0x0000DFDF:0x0000DF00 /* RW--D */
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#define NV_PMGR_SCRATCHS 0x0000DFEF:0x0000DFE0
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#define NV_PMGR_PRIV_3 0x0000E03F:0x0000E000
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#define NV_PMGR_INTR_1 0x0000E113:0x0000E040
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#define NV_PMGR_GPIO_1 0x0000E123:0x0000E114
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#define NV_PMGR_PRIV_4 0x0000E1B7:0x0000E124
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#define NV_PMGR_GPIO_2 0x0000E1BF:0x0000E1B8
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#define NV_PMGR_PRIV_5_1 0x0000E1FC:0x0000E1C0
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#define NV_PMGR_ROM 0x0000E21C:0x0000E200
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#define NV_PMGR_PRIV_5_2 0x0000E287:0x0000E220
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#define NV_PMGR_GPIO_3 0x0000E28B:0x0000E288
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#define NV_PMGR_PRIV_6 0x0000E28F:0x0000E28C
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#define NV_PMGR_SECURE 0x0000E2B7:0x0000E290
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#define NV_PMGR_PRIV_7 0x0000E2BF:0x0000E2B8
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#define NV_PMGR_RCV_33_18_SEL 0x0000E2CF:0x0000E2C0
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#define NV_PMGR_PAD 0x0000E2F7:0x0000E2D0
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#define NV_PMGR_PRIV_8 0x0000E37F:0x0000E2F8
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#define NV_PMGR_SECURE_SCRATCH_PRIV 0x0000E47F:0x0000E380
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#define NV_PMGR_NON_SILICON_VERIF_0 0x0000E48F:0x0000E480
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#define NV_PMGR_NON_SILICON_VERIF_1 0x0000E49F:0x0000E490
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#define NV_PMGR_SPI 0x0000E5B3:0x0000E4A0
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#define NV_PMGR_DP_OVER_USB 0x0000E5CF:0x0000E5B4
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#define NV_PMGR_PRIV_9 0x0000E5FF:0x0000E5D0
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#define NV_PMGR_MIO 0x0000E67F:0x0000E600
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#define NV_PMGR_PRIV_10 0x0000E71F:0x0000E680
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#define NV_PMGR_PRIV_11 0x0000E7FF:0x0000E72C
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#define NV_PMGR_CR__BASE 0x0000E400
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK 0x0000D7A0 /* RWI4R */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_i2c0_wr_secure" /* */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001
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#define NV_PMGR_I2C0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK 0x0000D7A4 /* RWI4R */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_i2c1_wr_secure"/* */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001
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#define NV_PMGR_I2C1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK 0x0000D7A8 /* RWI4R */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_i2c2_wr_secure"/* */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "opt_secure_pmgr_i2c2_wr_secure"/* */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED_FUSE0 0x000FFFFF /* RWI-V */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT_FUSE1 0x0008014F /* RW--V */
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001
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#define NV_PMGR_I2C2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK 0x0000D7AC /* RWI4R */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_i2c3_wr_secure"/* */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001
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#define NV_PMGR_I2C3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK 0x0000D7B0 /* RWI4R */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_i2c4_wr_secure"/* */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001
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#define NV_PMGR_I2C4_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK 0x0000D7B4 /* RWI4R */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_i2c5_wr_secure"/* */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001
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#define NV_PMGR_I2C5_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK 0x0000D7B8 /* RWI4R */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_i2c6_wr_secure"/* */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001
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#define NV_PMGR_I2C6_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK 0x0000D7BC /* RWI4R */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_i2c7_wr_secure"/* */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001
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#define NV_PMGR_I2C7_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK 0x0000D7C0 /* RWI4R */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_i2c8_wr_secure"/* */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001
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#define NV_PMGR_I2C8_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK 0x0000D7C4 /* RWI4R */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_i2c9_wr_secure"/* */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001
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#define NV_PMGR_I2C9_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000
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#define NV_PMGR_I2C_PRIV_LEVEL_MASK(i) (0x0000D7A0 + (i) * 0x4) /* RW-4A */
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#define NV_PMGR_I2C_PRIV_LEVEL_MASK__SIZE_1 10 /* */
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#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4
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#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001
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#define NV_PMGR_I2C_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK 0x0000D7CC /* RWI4R */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_padctl_wr_secure"/* */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_PADCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_PRIV_LEVEL_MASK 0x00021800 /* RWI4R */
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#define NV_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_padctl_wr_secure"/* */
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#define NV_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00 0x00021000 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_0_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_00_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01 0x00021004 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_1_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_01_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02 0x00021008 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_2_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_02_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03 0x0002100C /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_3_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_03_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04 0x00021010 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_4_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_04_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05 0x00021014 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_5_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_05_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06 0x00021018 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_6_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_06_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07 0x0002101C /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_7_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_07_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08 0x00021020 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_8_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_08_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09 0x00021024 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_9_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_09_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10 0x00021028 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_10_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_10_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11 0x0002102C /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_11_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_11_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12 0x00021030 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_12_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_12_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13 0x00021034 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_13_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_13_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14 0x00021038 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_14_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_14_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15 0x0002103C /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_15_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_15_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16 0x00021040 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_16_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_16_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17 0x00021044 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_17_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_17_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18 0x00021048 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_18_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_18_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19 0x0002104C /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_19_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_19_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20 0x00021050 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_20_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_20_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21 0x00021054 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_21_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_21_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22 0x00021058 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_22_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_22_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23 0x0002105C /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_23_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_23_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24 0x00021060 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_24_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_24_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25 0x00021064 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_25_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_25_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26 0x00021068 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_26_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_26_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27 0x0002106C /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_27_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_27_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28 0x00021070 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_28_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_28_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29 0x00021074 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_29_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_29_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30 0x00021078 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_30_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_30_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31 0x0002107C /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_31_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_31_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32 0x00021080 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_32_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_32_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33 0x00021084 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_33_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_33_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34 0x00021088 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_34_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_34_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35 0x0002108C /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_35_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_35_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36 0x00021090 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_36_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_36_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37 0x00021094 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_37_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_37_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38 0x00021098 /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_38_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_38_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39 0x0002109C /* RWI4R */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_out_39_wr_secure"/* */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_GPIO_OUT_PRIV_LEVEL_MASK_39_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK 0x0000D580 /* RWI4R */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_1_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_01_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK 0x0000D584 /* RWI4R */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_2_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_02_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK 0x0000D588 /* RWI4R */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_3_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_03_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK 0x0000D58C /* RWI4R */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_4_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_04_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK 0x0000D590 /* RWI4R */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_5_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_05_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK 0x0000D594 /* RWI4R */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_6_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_06_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK 0x0000D598 /* RWI4R */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_7_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_07_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK 0x0000D59C /* RWI4R */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_8_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_08_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK 0x0000D5A0 /* RWI4R */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_9_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_09_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK 0x0000D5A4 /* RWI4R */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_10_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_10_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK 0x0000D5A8 /* RWI4R */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_11_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_11_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK 0x0000D5AC /* RWI4R */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_12_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_12_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK 0x0000D5B0 /* RWI4R */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_13_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_13_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK 0x0000D5B4 /* RWI4R */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_14_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_14_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK 0x0000D5B8 /* RWI4R */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_15_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_15_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK 0x0000D5BC /* RWI4R */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_16_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_16_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK 0x0000D5C0 /* RWI4R */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_17_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_17_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK 0x0000D5C4 /* RWI4R */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_18_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_18_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK 0x0000D5C8 /* RWI4R */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_19_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_19_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK 0x0000D5CC /* RWI4R */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_20_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_20_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK 0x0000D5D0 /* RWI4R */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_21_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_21_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK 0x0000D5D4 /* RWI4R */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_22_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_22_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK 0x0000D5D8 /* RWI4R */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_23_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_23_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK 0x0000D5DC /* RWI4R */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_gpio_input_cntl_24_wr_secure"/* */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_IN_24_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK 0x0000D7D0 /* RWI4R */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_rom_wr_secure" /* */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_ROM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK 0x0000D7D4 /* RWI4R */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_pwr_wr_secure" /* */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_PWR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK 0x0000D7D8 /* RW-4R */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLE 0x0000000F /* RW--V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLE 0x00000008 /* RW--V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RWI-V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLE 0x0000000F /* RW--V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLE 0x00000008 /* RW--V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RW--V */
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#define NV_PMGR_ROM_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0x0008014F /* RWI-V */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK 0x0000D7DC /* RWI4R */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "opt_secure_pmgr_fan_wr_secure" /* */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWI-V */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_FAN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK 0x0000D7E0 /* RWI4R */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_GPIO_OUT_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_I2C_CNTL(i) (0x0000D000 + (i) * 0x20) /* RW-4A */
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#define NV_PMGR_I2C_CNTL__SIZE_1 10 /* */
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#define NV_PMGR_I2C_CNTL_GEN_START 0:0 /* RWIVF */
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#define NV_PMGR_I2C_CNTL_GEN_START_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_CNTL_GEN_START_NO 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_CNTL_GEN_START_YES 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_CNTL_GEN_STOP 1:1 /* RWIVF */
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#define NV_PMGR_I2C_CNTL_GEN_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_CNTL_GEN_STOP_NO 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_CNTL_GEN_STOP_YES 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_CNTL_CMD 3:2 /* RWIVF */
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#define NV_PMGR_I2C_CNTL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_CNTL_CMD_NONE 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_CNTL_CMD_READ 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_CNTL_CMD_WRITE 0x00000002 /* RW--V */
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#define NV_PMGR_I2C_CNTL_CMD_RESET 0x00000003 /* RW--V */
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#define NV_PMGR_I2C_CNTL_GEN_RAB 4:4 /* RWIVF */
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#define NV_PMGR_I2C_CNTL_GEN_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_CNTL_GEN_RAB_NO 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_CNTL_GEN_RAB_YES 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_CNTL_INTR_WHEN_DONE 5:5 /* RWIVF */
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#define NV_PMGR_I2C_CNTL_INTR_WHEN_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_CNTL_INTR_WHEN_DONE_NO 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_CNTL_INTR_WHEN_DONE_YES 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_CNTL_BURST_SIZE 21:6 /* RWIVF */
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#define NV_PMGR_I2C_CNTL_BURST_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_CNTL_BURST_SIZE_MAXIMUM 0x00000004 /* RW--V */
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#define NV_PMGR_I2C_CNTL_GEN_NACK 28:28 /* RWIVF */
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#define NV_PMGR_I2C_CNTL_GEN_NACK_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C_CNTL_GEN_NACK_NO 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_CNTL_GEN_NACK_YES 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_CNTL_STATUS 30:29 /* R-IVF */
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#define NV_PMGR_I2C_CNTL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C_CNTL_STATUS_OKAY 0x00000000 /* R---V */
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#define NV_PMGR_I2C_CNTL_STATUS_NO_ACK 0x00000001 /* R---V */
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#define NV_PMGR_I2C_CNTL_STATUS_TIMEOUT 0x00000002 /* R---V */
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#define NV_PMGR_I2C_CNTL_STATUS_BUS_BUSY 0x00000003 /* R---V */
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#define NV_PMGR_I2C_CNTL_CYCLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C_CNTL_CYCLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_CNTL_CYCLE_DONE 0x00000000 /* R---V */
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#define NV_PMGR_I2C_CNTL_CYCLE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_I2C_CNTL_CYCLE_TRIGGER 0x00000001 /* -W--V */
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#define NV_PMGR_I2C_ADDR(i) (0x0000D004 + (i) * 0x20) /* RW-4A */
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#define NV_PMGR_I2C_ADDR__SIZE_1 10 /* */
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#define NV_PMGR_I2C_ADDR_DAB 9:0 /* RWIVF */
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#define NV_PMGR_I2C_ADDR_DAB_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C_ADDR_TEN_BIT 10:10 /* RWIVF */
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#define NV_PMGR_I2C_ADDR_TEN_BIT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_ADDR_TEN_BIT_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_ADDR_TEN_BIT_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_ADDR_RAB 18:11 /* RWIVF */
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#define NV_PMGR_I2C_ADDR_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_TIMING(i) (0x0000D008 + (i) * 0x20) /* RW-4A */
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#define NV_PMGR_I2C_TIMING__SIZE_1 10 /* */
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#define NV_PMGR_I2C_TIMING_SCL_PERIOD 11:0 /* RWIVF */
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#define NV_PMGR_I2C_TIMING_SCL_PERIOD_INIT 0x0000010E /* RWI-V */
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#define NV_PMGR_I2C_TIMING_SCL_PERIOD_100KHZ 0x0000011D /* RW--V */
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#define NV_PMGR_I2C_TIMING_SCL_PERIOD_200KHZ 0x00000087 /* RW--V */
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#define NV_PMGR_I2C_TIMING_SCL_PERIOD_300KHZ 0x0000005A /* RW--V */
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#define NV_PMGR_I2C_TIMING_SCL_PERIOD_400KHZ 0x00000046 /* RW--V */
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#define NV_PMGR_I2C_TIMING_SCL_PERIOD_500KHZ 0x00000036 /* RW--V */
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#define NV_PMGR_I2C_TIMING_SCL_PERIOD_600KHZ 0x0000002D /* RW--V */
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#define NV_PMGR_I2C_TIMING_SCL_PERIOD_800KHZ 0x00000022 /* RW--V */
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#define NV_PMGR_I2C_TIMING_SCL_PERIOD_1000KHZ 0x0000001B /* RW--V */
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#define NV_PMGR_I2C_TIMING_IGNORE_ACK 15:15 /* RWIVF */
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#define NV_PMGR_I2C_TIMING_IGNORE_ACK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_TIMING_IGNORE_ACK_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_TIMING_IGNORE_ACK_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_TIMING_TIMEOUT_CLK_CNT 23:16 /* RWIVF */
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#define NV_PMGR_I2C_TIMING_TIMEOUT_CLK_CNT_INIT 0x00000001 /* R-I-V */
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#define NV_PMGR_I2C_TIMING_TIMEOUT_CHECK 24:24 /* RWIVF */
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#define NV_PMGR_I2C_TIMING_TIMEOUT_CHECK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_TIMING_TIMEOUT_CHECK_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_TIMING_TIMEOUT_CHECK_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_DATA(i) (0x0000D00C + (i) * 0x20) /* RW-4A */
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#define NV_PMGR_I2C_DATA__SIZE_1 10 /* */
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#define NV_PMGR_I2C_DATA_VALUE 31:0 /* RWIUF */
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#define NV_PMGR_I2C_DATA_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C_POLL(i) (0x0000D010 + (i) * 0x20) /* RW-4A */
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#define NV_PMGR_I2C_POLL__SIZE_1 10 /* */
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#define NV_PMGR_I2C_POLL_PERIOD 23:0 /* RWIVF */
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#define NV_PMGR_I2C_POLL_PERIOD_INIT 0x000F4240 /* R-I-V */
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#define NV_PMGR_I2C_POLL_INITIAL_DEV_STATUS 25:24 /* RWIVF */
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#define NV_PMGR_I2C_POLL_INITIAL_DEV_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_POLL_INITIAL_DEV_STATUS_UNKNOWN 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_POLL_INITIAL_DEV_STATUS_ABSENT 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_POLL_INITIAL_DEV_STATUS_PRESENT 0x00000002 /* RW--V */
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#define NV_PMGR_I2C_POLL_MODE 30:30 /* RWIVF */
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#define NV_PMGR_I2C_POLL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_POLL_MODE_DEVICE_DETECT 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_POLL_MODE_MASK_COMPARE 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_POLL_ENABLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C_POLL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_POLL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_POLL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_OVERRIDE(i) (0x0000D014 + (i) * 0x20) /* RW-4A */
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#define NV_PMGR_I2C_OVERRIDE__SIZE_1 10 /* */
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#define NV_PMGR_I2C_OVERRIDE_SCL 0:0 /* RWIVF */
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#define NV_PMGR_I2C_OVERRIDE_SCL_OUT_ZERO 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_OVERRIDE_SCL_OUT_ONE 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C_OVERRIDE_SDA 1:1 /* RWIVF */
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#define NV_PMGR_I2C_OVERRIDE_SDA_OUT_ZERO 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_OVERRIDE_SDA_OUT_ONE 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C_OVERRIDE_SIGNALS 2:2 /* RWIVF */
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#define NV_PMGR_I2C_OVERRIDE_SIGNALS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_OVERRIDE_SIGNALS_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_OVERRIDE_SIGNALS_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_OVERRIDE_PMU 3:3 /* RWIVF */
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#define NV_PMGR_I2C_OVERRIDE_PMU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_OVERRIDE_PMU_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_OVERRIDE_PMU_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_OVERRIDE_SCLPAD_IN 4:4 /* R--VF */
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#define NV_PMGR_I2C_OVERRIDE_SCLPAD_IN_ZERO 0x00000000 /* R---V */
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#define NV_PMGR_I2C_OVERRIDE_SCLPAD_IN_ONE 0x00000001 /* R---V */
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#define NV_PMGR_I2C_OVERRIDE_SDAPAD_IN 5:5 /* R--VF */
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#define NV_PMGR_I2C_OVERRIDE_SDAPAD_IN_ZERO 0x00000000 /* R---V */
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#define NV_PMGR_I2C_OVERRIDE_SDAPAD_IN_ONE 0x00000001 /* R---V */
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#define NV_PMGR_I2C_STEREO(i) (0x0000D018 + (i) * 0x20) /* RW-4A */
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#define NV_PMGR_I2C_STEREO__SIZE_1 10 /* */
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#define NV_PMGR_I2C_STEREO_SDA 2:0 /* RWIVF */
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#define NV_PMGR_I2C_STEREO_SDA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_STEREO_SDA_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_STEREO_SDA_HEAD0_STEREO 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_STEREO_SDA_HEAD1_STEREO 0x00000002 /* RW--V */
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#define NV_PMGR_I2C_STEREO_SDA_HEAD2_STEREO 0x00000003 /* RW--V */
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#define NV_PMGR_I2C_STEREO_SDA_HEAD3_STEREO 0x00000004 /* RW--V */
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#define NV_PMGR_I2C_STEREO_SDA_HEAD_STEREO(i) ((i) + 1) /* */
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#define NV_PMGR_I2C_STEREO_SDA_HEAD_STEREO__SIZE_1 4 /* */
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#define NV_PMGR_I2C_STEREO_SCL 3:3 /* RWIVF */
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#define NV_PMGR_I2C_STEREO_SCL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_STEREO_SCL_LOW 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_STEREO_SCL_HIGH 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_STEREO_HEAD0_INV 4:4 /* RWIVF */
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#define NV_PMGR_I2C_STEREO_HEAD0_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_STEREO_HEAD0_INV_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_STEREO_HEAD0_INV_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_STEREO_HEAD1_INV 5:5 /* RWIVF */
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#define NV_PMGR_I2C_STEREO_HEAD1_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_STEREO_HEAD1_INV_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_STEREO_HEAD1_INV_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_STEREO_HEAD2_INV 6:6 /* RWIVF */
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#define NV_PMGR_I2C_STEREO_HEAD2_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_STEREO_HEAD2_INV_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_STEREO_HEAD2_INV_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_STEREO_HEAD3_INV 7:7 /* RWIVF */
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#define NV_PMGR_I2C_STEREO_HEAD3_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C_STEREO_HEAD3_INV_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_I2C_STEREO_HEAD3_INV_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_I2C_STEREO_HEAD_INV(i) (4+(i)):(4+(i)) /* */
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#define NV_PMGR_I2C_STEREO_HEAD_INV__SIZE_1 4 /* */
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#define NV_PMGR_I2C_STEREO_HEAD_INV_DISABLE 0x00000000 /* */
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#define NV_PMGR_I2C_STEREO_HEAD_INV_ENABLE 0x00000001 /* */
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#define NV_PMGR_I2C_POLL2(i) (0x0000D01C + (i) * 0x20) /* RW-4A */
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#define NV_PMGR_I2C_POLL2__SIZE_1 10 /* */
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#define NV_PMGR_I2C_POLL2_MASK 15:0 /* RWIVF */
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#define NV_PMGR_I2C_POLL2_MASK_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C_POLL2_DATA 31:16 /* R-IVF */
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#define NV_PMGR_I2C_POLL2_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C0_CNTL 0x0000D000 /* RW-4R */
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#define NV_PMGR_I2C0_CNTL__PRIV_LEVEL_MASK 0x0000D7A0 /* */
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#define NV_PMGR_I2C0_CNTL_GEN_START 0:0 /* RWIVF */
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#define NV_PMGR_I2C0_CNTL_GEN_START_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_CNTL_GEN_STOP 1:1 /* RWIVF */
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#define NV_PMGR_I2C0_CNTL_GEN_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_CNTL_CMD 3:2 /* RWIVF */
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#define NV_PMGR_I2C0_CNTL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_CNTL_GEN_RAB 4:4 /* RWIVF */
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#define NV_PMGR_I2C0_CNTL_GEN_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_CNTL_INTR_WHEN_DONE 5:5 /* RWIVF */
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#define NV_PMGR_I2C0_CNTL_INTR_WHEN_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_CNTL_BURST_SIZE 21:6 /* RWIVF */
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#define NV_PMGR_I2C0_CNTL_BURST_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_CNTL_GEN_NACK 28:28 /* RWIVF */
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#define NV_PMGR_I2C0_CNTL_GEN_NACK_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C0_CNTL_STATUS 30:29 /* R-IVF */
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#define NV_PMGR_I2C0_CNTL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C0_CNTL_CYCLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C0_CNTL_CYCLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_ADDR 0x0000D004 /* RW-4R */
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#define NV_PMGR_I2C0_ADDR__PRIV_LEVEL_MASK 0x0000D7A0 /* */
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#define NV_PMGR_I2C0_ADDR_DAB 9:0 /* RWIVF */
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#define NV_PMGR_I2C0_ADDR_DAB_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C0_ADDR_TEN_BIT 10:10 /* RWIVF */
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#define NV_PMGR_I2C0_ADDR_TEN_BIT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_ADDR_RAB 18:11 /* RWIVF */
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#define NV_PMGR_I2C0_ADDR_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_TIMING 0x0000D008 /* RW-4R */
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#define NV_PMGR_I2C0_TIMING__PRIV_LEVEL_MASK 0x0000D7A0 /* */
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#define NV_PMGR_I2C0_TIMING_SCL_PERIOD 11:0 /* RWIVF */
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#define NV_PMGR_I2C0_TIMING_SCL_PERIOD_INIT 0x0000010E /* RWI-V */
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#define NV_PMGR_I2C0_TIMING_IGNORE_ACK 15:15 /* RWIVF */
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#define NV_PMGR_I2C0_TIMING_IGNORE_ACK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_TIMING_TIMEOUT_CLK_CNT 23:16 /* RWIVF */
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#define NV_PMGR_I2C0_TIMING_TIMEOUT_CLK_CNT_INIT 0x00000001 /* R-I-V */
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#define NV_PMGR_I2C0_TIMING_TIMEOUT_CHECK 24:24 /* RWIVF */
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#define NV_PMGR_I2C0_TIMING_TIMEOUT_CHECK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_DATA 0x0000D00C /* RW-4R */
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#define NV_PMGR_I2C0_DATA__PRIV_LEVEL_MASK 0x0000D7A0 /* */
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#define NV_PMGR_I2C0_DATA_VALUE 31:0 /* RWIUF */
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#define NV_PMGR_I2C0_DATA_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C0_POLL 0x0000D010 /* RW-4R */
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#define NV_PMGR_I2C0_POLL__PRIV_LEVEL_MASK 0x0000D7A0 /* */
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#define NV_PMGR_I2C0_POLL_PERIOD 23:0 /* RWIVF */
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#define NV_PMGR_I2C0_POLL_PERIOD_INIT 0x000F4240 /* R-I-V */
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#define NV_PMGR_I2C0_POLL_INITIAL_DEV_STATUS 25:24 /* RWIVF */
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#define NV_PMGR_I2C0_POLL_INITIAL_DEV_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_POLL_MODE 30:30 /* RWIVF */
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#define NV_PMGR_I2C0_POLL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_POLL_ENABLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C0_POLL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_OVERRIDE 0x0000D014 /* RW-4R */
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#define NV_PMGR_I2C0_OVERRIDE__PRIV_LEVEL_MASK 0x0000D7A0 /* */
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#define NV_PMGR_I2C0_OVERRIDE_SCL 0:0 /* RWIVF */
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#define NV_PMGR_I2C0_OVERRIDE_SCL_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C0_OVERRIDE_SDA 1:1 /* RWIVF */
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#define NV_PMGR_I2C0_OVERRIDE_SDA_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C0_OVERRIDE_SIGNALS 2:2 /* RWIVF */
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#define NV_PMGR_I2C0_OVERRIDE_SIGNALS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_OVERRIDE_PMU 3:3 /* RWIVF */
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#define NV_PMGR_I2C0_OVERRIDE_PMU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_OVERRIDE_SCLPAD_IN 4:4 /* R--VF */
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#define NV_PMGR_I2C0_OVERRIDE_SDAPAD_IN 5:5 /* R--VF */
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#define NV_PMGR_I2C0_STEREO 0x0000D018 /* RW-4R */
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#define NV_PMGR_I2C0_STEREO__PRIV_LEVEL_MASK 0x0000D7A0 /* */
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#define NV_PMGR_I2C0_STEREO_SDA 2:0 /* RWIVF */
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#define NV_PMGR_I2C0_STEREO_SDA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_STEREO_SCL 3:3 /* RWIVF */
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#define NV_PMGR_I2C0_STEREO_SCL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_STEREO_HEAD0_INV 4:4 /* RWIVF */
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#define NV_PMGR_I2C0_STEREO_HEAD0_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_STEREO_HEAD1_INV 5:5 /* RWIVF */
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#define NV_PMGR_I2C0_STEREO_HEAD1_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_STEREO_HEAD2_INV 6:6 /* RWIVF */
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#define NV_PMGR_I2C0_STEREO_HEAD2_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_STEREO_HEAD3_INV 7:7 /* RWIVF */
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#define NV_PMGR_I2C0_STEREO_HEAD3_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C0_POLL2 0x0000D01C /* RW-4R */
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#define NV_PMGR_I2C0_POLL2__PRIV_LEVEL_MASK 0x0000D7A0 /* */
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#define NV_PMGR_I2C0_POLL2_MASK 15:0 /* RWIVF */
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#define NV_PMGR_I2C0_POLL2_MASK_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C0_POLL2_DATA 31:16 /* R-IVF */
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#define NV_PMGR_I2C0_POLL2_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C1_CNTL 0x0000D020 /* RW-4R */
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#define NV_PMGR_I2C1_CNTL__PRIV_LEVEL_MASK 0x0000D7A4 /* */
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#define NV_PMGR_I2C1_CNTL_GEN_START 0:0 /* RWIVF */
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#define NV_PMGR_I2C1_CNTL_GEN_START_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_CNTL_GEN_STOP 1:1 /* RWIVF */
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#define NV_PMGR_I2C1_CNTL_GEN_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_CNTL_CMD 3:2 /* RWIVF */
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#define NV_PMGR_I2C1_CNTL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_CNTL_GEN_RAB 4:4 /* RWIVF */
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#define NV_PMGR_I2C1_CNTL_GEN_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_CNTL_INTR_WHEN_DONE 5:5 /* RWIVF */
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#define NV_PMGR_I2C1_CNTL_INTR_WHEN_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_CNTL_BURST_SIZE 21:6 /* RWIVF */
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#define NV_PMGR_I2C1_CNTL_BURST_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_CNTL_GEN_NACK 28:28 /* RWIVF */
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#define NV_PMGR_I2C1_CNTL_GEN_NACK_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C1_CNTL_STATUS 30:29 /* R-IVF */
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#define NV_PMGR_I2C1_CNTL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C1_CNTL_CYCLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C1_CNTL_CYCLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_ADDR 0x0000D024 /* RW-4R */
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#define NV_PMGR_I2C1_ADDR__PRIV_LEVEL_MASK 0x0000D7A4 /* */
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#define NV_PMGR_I2C1_ADDR_DAB 9:0 /* RWIVF */
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#define NV_PMGR_I2C1_ADDR_DAB_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C1_ADDR_TEN_BIT 10:10 /* RWIVF */
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#define NV_PMGR_I2C1_ADDR_TEN_BIT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_ADDR_RAB 18:11 /* RWIVF */
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#define NV_PMGR_I2C1_ADDR_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_TIMING 0x0000D028 /* RW-4R */
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#define NV_PMGR_I2C1_TIMING__PRIV_LEVEL_MASK 0x0000D7A4 /* */
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#define NV_PMGR_I2C1_TIMING_SCL_PERIOD 11:0 /* RWIVF */
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#define NV_PMGR_I2C1_TIMING_SCL_PERIOD_INIT 0x0000010E /* RWI-V */
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#define NV_PMGR_I2C1_TIMING_IGNORE_ACK 15:15 /* RWIVF */
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#define NV_PMGR_I2C1_TIMING_IGNORE_ACK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_TIMING_TIMEOUT_CLK_CNT 23:16 /* RWIVF */
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#define NV_PMGR_I2C1_TIMING_TIMEOUT_CLK_CNT_INIT 0x00000001 /* R-I-V */
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#define NV_PMGR_I2C1_TIMING_TIMEOUT_CHECK 24:24 /* RWIVF */
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#define NV_PMGR_I2C1_TIMING_TIMEOUT_CHECK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_DATA 0x0000D02C /* RW-4R */
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#define NV_PMGR_I2C1_DATA__PRIV_LEVEL_MASK 0x0000D7A4 /* */
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#define NV_PMGR_I2C1_DATA_VALUE 31:0 /* RWIUF */
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#define NV_PMGR_I2C1_DATA_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C1_POLL 0x0000D030 /* RW-4R */
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#define NV_PMGR_I2C1_POLL__PRIV_LEVEL_MASK 0x0000D7A4 /* */
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#define NV_PMGR_I2C1_POLL_PERIOD 23:0 /* RWIVF */
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#define NV_PMGR_I2C1_POLL_PERIOD_INIT 0x000F4240 /* R-I-V */
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#define NV_PMGR_I2C1_POLL_INITIAL_DEV_STATUS 25:24 /* RWIVF */
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#define NV_PMGR_I2C1_POLL_INITIAL_DEV_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_POLL_MODE 30:30 /* RWIVF */
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#define NV_PMGR_I2C1_POLL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_POLL_ENABLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C1_POLL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_OVERRIDE 0x0000D034 /* RW-4R */
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#define NV_PMGR_I2C1_OVERRIDE__PRIV_LEVEL_MASK 0x0000D7A4 /* */
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#define NV_PMGR_I2C1_OVERRIDE_SCL 0:0 /* RWIVF */
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#define NV_PMGR_I2C1_OVERRIDE_SCL_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C1_OVERRIDE_SDA 1:1 /* RWIVF */
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#define NV_PMGR_I2C1_OVERRIDE_SDA_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C1_OVERRIDE_SIGNALS 2:2 /* RWIVF */
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#define NV_PMGR_I2C1_OVERRIDE_SIGNALS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_OVERRIDE_PMU 3:3 /* RWIVF */
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#define NV_PMGR_I2C1_OVERRIDE_PMU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_OVERRIDE_SCLPAD_IN 4:4 /* R--VF */
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#define NV_PMGR_I2C1_OVERRIDE_SDAPAD_IN 5:5 /* R--VF */
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#define NV_PMGR_I2C1_STEREO 0x0000D038 /* RW-4R */
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#define NV_PMGR_I2C1_STEREO__PRIV_LEVEL_MASK 0x0000D7A4 /* */
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#define NV_PMGR_I2C1_STEREO_SDA 2:0 /* RWIVF */
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#define NV_PMGR_I2C1_STEREO_SDA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_STEREO_SCL 3:3 /* RWIVF */
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#define NV_PMGR_I2C1_STEREO_SCL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_STEREO_HEAD0_INV 4:4 /* RWIVF */
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#define NV_PMGR_I2C1_STEREO_HEAD0_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_STEREO_HEAD1_INV 5:5 /* RWIVF */
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#define NV_PMGR_I2C1_STEREO_HEAD1_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_STEREO_HEAD2_INV 6:6 /* RWIVF */
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#define NV_PMGR_I2C1_STEREO_HEAD2_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_STEREO_HEAD3_INV 7:7 /* RWIVF */
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#define NV_PMGR_I2C1_STEREO_HEAD3_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C1_POLL2 0x0000D03C /* RW-4R */
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#define NV_PMGR_I2C1_POLL2__PRIV_LEVEL_MASK 0x0000D7A4 /* */
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#define NV_PMGR_I2C1_POLL2_MASK 15:0 /* RWIVF */
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#define NV_PMGR_I2C1_POLL2_MASK_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C1_POLL2_DATA 31:16 /* R-IVF */
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#define NV_PMGR_I2C1_POLL2_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C2_CNTL 0x0000D040 /* RW-4R */
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#define NV_PMGR_I2C2_CNTL__PRIV_LEVEL_MASK 0x0000D7A8 /* */
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#define NV_PMGR_I2C2_CNTL_GEN_START 0:0 /* RWIVF */
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#define NV_PMGR_I2C2_CNTL_GEN_START_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_CNTL_GEN_STOP 1:1 /* RWIVF */
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#define NV_PMGR_I2C2_CNTL_GEN_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_CNTL_CMD 3:2 /* RWIVF */
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#define NV_PMGR_I2C2_CNTL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_CNTL_GEN_RAB 4:4 /* RWIVF */
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#define NV_PMGR_I2C2_CNTL_GEN_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_CNTL_INTR_WHEN_DONE 5:5 /* RWIVF */
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#define NV_PMGR_I2C2_CNTL_INTR_WHEN_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_CNTL_BURST_SIZE 21:6 /* RWIVF */
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#define NV_PMGR_I2C2_CNTL_BURST_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_CNTL_GEN_NACK 28:28 /* RWIVF */
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#define NV_PMGR_I2C2_CNTL_GEN_NACK_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C2_CNTL_STATUS 30:29 /* R-IVF */
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#define NV_PMGR_I2C2_CNTL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C2_CNTL_CYCLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C2_CNTL_CYCLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_ADDR 0x0000D044 /* RW-4R */
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#define NV_PMGR_I2C2_ADDR__PRIV_LEVEL_MASK 0x0000D7A8 /* */
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#define NV_PMGR_I2C2_ADDR_DAB 9:0 /* RWIVF */
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#define NV_PMGR_I2C2_ADDR_DAB_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C2_ADDR_TEN_BIT 10:10 /* RWIVF */
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#define NV_PMGR_I2C2_ADDR_TEN_BIT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_ADDR_RAB 18:11 /* RWIVF */
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#define NV_PMGR_I2C2_ADDR_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_TIMING 0x0000D048 /* RW-4R */
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#define NV_PMGR_I2C2_TIMING__PRIV_LEVEL_MASK 0x0000D7A8 /* */
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#define NV_PMGR_I2C2_TIMING_SCL_PERIOD 11:0 /* RWIVF */
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#define NV_PMGR_I2C2_TIMING_SCL_PERIOD_INIT 0x0000010E /* RWI-V */
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#define NV_PMGR_I2C2_TIMING_IGNORE_ACK 15:15 /* RWIVF */
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#define NV_PMGR_I2C2_TIMING_IGNORE_ACK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_TIMING_TIMEOUT_CLK_CNT 23:16 /* RWIVF */
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#define NV_PMGR_I2C2_TIMING_TIMEOUT_CLK_CNT_INIT 0x00000001 /* R-I-V */
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#define NV_PMGR_I2C2_TIMING_TIMEOUT_CHECK 24:24 /* RWIVF */
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#define NV_PMGR_I2C2_TIMING_TIMEOUT_CHECK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_DATA 0x0000D04C /* RW-4R */
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#define NV_PMGR_I2C2_DATA__PRIV_LEVEL_MASK 0x0000D7A8 /* */
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#define NV_PMGR_I2C2_DATA_VALUE 31:0 /* RWIUF */
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#define NV_PMGR_I2C2_DATA_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C2_POLL 0x0000D050 /* RW-4R */
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#define NV_PMGR_I2C2_POLL__PRIV_LEVEL_MASK 0x0000D7A8 /* */
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#define NV_PMGR_I2C2_POLL_PERIOD 23:0 /* RWIVF */
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#define NV_PMGR_I2C2_POLL_PERIOD_INIT 0x000F4240 /* R-I-V */
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#define NV_PMGR_I2C2_POLL_INITIAL_DEV_STATUS 25:24 /* RWIVF */
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#define NV_PMGR_I2C2_POLL_INITIAL_DEV_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_POLL_MODE 30:30 /* RWIVF */
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#define NV_PMGR_I2C2_POLL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_POLL_ENABLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C2_POLL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_OVERRIDE 0x0000D054 /* RW-4R */
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#define NV_PMGR_I2C2_OVERRIDE__PRIV_LEVEL_MASK 0x0000D7A8 /* */
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#define NV_PMGR_I2C2_OVERRIDE_SCL 0:0 /* RWIVF */
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#define NV_PMGR_I2C2_OVERRIDE_SCL_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C2_OVERRIDE_SDA 1:1 /* RWIVF */
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#define NV_PMGR_I2C2_OVERRIDE_SDA_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C2_OVERRIDE_SIGNALS 2:2 /* RWIVF */
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#define NV_PMGR_I2C2_OVERRIDE_SIGNALS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_OVERRIDE_PMU 3:3 /* RWIVF */
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#define NV_PMGR_I2C2_OVERRIDE_PMU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_OVERRIDE_SCLPAD_IN 4:4 /* R--VF */
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#define NV_PMGR_I2C2_OVERRIDE_SDAPAD_IN 5:5 /* R--VF */
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#define NV_PMGR_I2C2_STEREO 0x0000D058 /* RW-4R */
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#define NV_PMGR_I2C2_STEREO__PRIV_LEVEL_MASK 0x0000D7A8 /* */
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#define NV_PMGR_I2C2_STEREO_SDA 2:0 /* RWIVF */
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#define NV_PMGR_I2C2_STEREO_SDA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_STEREO_SCL 3:3 /* RWIVF */
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#define NV_PMGR_I2C2_STEREO_SCL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_STEREO_HEAD0_INV 4:4 /* RWIVF */
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#define NV_PMGR_I2C2_STEREO_HEAD0_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_STEREO_HEAD1_INV 5:5 /* RWIVF */
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#define NV_PMGR_I2C2_STEREO_HEAD1_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_STEREO_HEAD2_INV 6:6 /* RWIVF */
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#define NV_PMGR_I2C2_STEREO_HEAD2_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_STEREO_HEAD3_INV 7:7 /* RWIVF */
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#define NV_PMGR_I2C2_STEREO_HEAD3_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C2_POLL2 0x0000D05C /* RW-4R */
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#define NV_PMGR_I2C2_POLL2__PRIV_LEVEL_MASK 0x0000D7A8 /* */
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#define NV_PMGR_I2C2_POLL2_MASK 15:0 /* RWIVF */
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#define NV_PMGR_I2C2_POLL2_MASK_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C2_POLL2_DATA 31:16 /* R-IVF */
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#define NV_PMGR_I2C2_POLL2_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C3_CNTL 0x0000D060 /* RW-4R */
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#define NV_PMGR_I2C3_CNTL__PRIV_LEVEL_MASK 0x0000D7AC /* */
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#define NV_PMGR_I2C3_CNTL_GEN_START 0:0 /* RWIVF */
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#define NV_PMGR_I2C3_CNTL_GEN_START_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_CNTL_GEN_STOP 1:1 /* RWIVF */
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#define NV_PMGR_I2C3_CNTL_GEN_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_CNTL_CMD 3:2 /* RWIVF */
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#define NV_PMGR_I2C3_CNTL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_CNTL_GEN_RAB 4:4 /* RWIVF */
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#define NV_PMGR_I2C3_CNTL_GEN_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_CNTL_INTR_WHEN_DONE 5:5 /* RWIVF */
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#define NV_PMGR_I2C3_CNTL_INTR_WHEN_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_CNTL_BURST_SIZE 21:6 /* RWIVF */
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#define NV_PMGR_I2C3_CNTL_BURST_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_CNTL_GEN_NACK 28:28 /* RWIVF */
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#define NV_PMGR_I2C3_CNTL_GEN_NACK_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C3_CNTL_STATUS 30:29 /* R-IVF */
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#define NV_PMGR_I2C3_CNTL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C3_CNTL_CYCLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C3_CNTL_CYCLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_ADDR 0x0000D064 /* RW-4R */
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#define NV_PMGR_I2C3_ADDR__PRIV_LEVEL_MASK 0x0000D7AC /* */
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#define NV_PMGR_I2C3_ADDR_DAB 9:0 /* RWIVF */
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#define NV_PMGR_I2C3_ADDR_DAB_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C3_ADDR_TEN_BIT 10:10 /* RWIVF */
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#define NV_PMGR_I2C3_ADDR_TEN_BIT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_ADDR_RAB 18:11 /* RWIVF */
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#define NV_PMGR_I2C3_ADDR_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_TIMING 0x0000D068 /* RW-4R */
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#define NV_PMGR_I2C3_TIMING__PRIV_LEVEL_MASK 0x0000D7AC /* */
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#define NV_PMGR_I2C3_TIMING_SCL_PERIOD 11:0 /* RWIVF */
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#define NV_PMGR_I2C3_TIMING_SCL_PERIOD_INIT 0x0000010E /* RWI-V */
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#define NV_PMGR_I2C3_TIMING_IGNORE_ACK 15:15 /* RWIVF */
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#define NV_PMGR_I2C3_TIMING_IGNORE_ACK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_TIMING_TIMEOUT_CLK_CNT 23:16 /* RWIVF */
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#define NV_PMGR_I2C3_TIMING_TIMEOUT_CLK_CNT_INIT 0x00000001 /* R-I-V */
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#define NV_PMGR_I2C3_TIMING_TIMEOUT_CHECK 24:24 /* RWIVF */
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#define NV_PMGR_I2C3_TIMING_TIMEOUT_CHECK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_DATA 0x0000D06C /* RW-4R */
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#define NV_PMGR_I2C3_DATA__PRIV_LEVEL_MASK 0x0000D7AC /* */
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#define NV_PMGR_I2C3_DATA_VALUE 31:0 /* RWIUF */
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#define NV_PMGR_I2C3_DATA_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C3_POLL 0x0000D070 /* RW-4R */
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#define NV_PMGR_I2C3_POLL__PRIV_LEVEL_MASK 0x0000D7AC /* */
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#define NV_PMGR_I2C3_POLL_PERIOD 23:0 /* RWIVF */
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#define NV_PMGR_I2C3_POLL_PERIOD_INIT 0x000F4240 /* R-I-V */
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#define NV_PMGR_I2C3_POLL_INITIAL_DEV_STATUS 25:24 /* RWIVF */
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#define NV_PMGR_I2C3_POLL_INITIAL_DEV_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_POLL_MODE 30:30 /* RWIVF */
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#define NV_PMGR_I2C3_POLL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_POLL_ENABLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C3_POLL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_OVERRIDE 0x0000D074 /* RW-4R */
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#define NV_PMGR_I2C3_OVERRIDE__PRIV_LEVEL_MASK 0x0000D7AC /* */
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#define NV_PMGR_I2C3_OVERRIDE_SCL 0:0 /* RWIVF */
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#define NV_PMGR_I2C3_OVERRIDE_SCL_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C3_OVERRIDE_SDA 1:1 /* RWIVF */
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#define NV_PMGR_I2C3_OVERRIDE_SDA_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C3_OVERRIDE_SIGNALS 2:2 /* RWIVF */
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#define NV_PMGR_I2C3_OVERRIDE_SIGNALS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_OVERRIDE_PMU 3:3 /* RWIVF */
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#define NV_PMGR_I2C3_OVERRIDE_PMU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_OVERRIDE_SCLPAD_IN 4:4 /* R--VF */
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#define NV_PMGR_I2C3_OVERRIDE_SDAPAD_IN 5:5 /* R--VF */
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#define NV_PMGR_I2C3_STEREO 0x0000D078 /* RW-4R */
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#define NV_PMGR_I2C3_STEREO__PRIV_LEVEL_MASK 0x0000D7AC /* */
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#define NV_PMGR_I2C3_STEREO_SDA 2:0 /* RWIVF */
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#define NV_PMGR_I2C3_STEREO_SDA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_STEREO_SCL 3:3 /* RWIVF */
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#define NV_PMGR_I2C3_STEREO_SCL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_STEREO_HEAD0_INV 4:4 /* RWIVF */
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#define NV_PMGR_I2C3_STEREO_HEAD0_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_STEREO_HEAD1_INV 5:5 /* RWIVF */
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#define NV_PMGR_I2C3_STEREO_HEAD1_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_STEREO_HEAD2_INV 6:6 /* RWIVF */
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#define NV_PMGR_I2C3_STEREO_HEAD2_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_STEREO_HEAD3_INV 7:7 /* RWIVF */
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#define NV_PMGR_I2C3_STEREO_HEAD3_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C3_POLL2 0x0000D07C /* RW-4R */
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#define NV_PMGR_I2C3_POLL2__PRIV_LEVEL_MASK 0x0000D7AC /* */
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#define NV_PMGR_I2C3_POLL2_MASK 15:0 /* RWIVF */
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#define NV_PMGR_I2C3_POLL2_MASK_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C3_POLL2_DATA 31:16 /* R-IVF */
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#define NV_PMGR_I2C3_POLL2_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C4_CNTL 0x0000D080 /* RW-4R */
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#define NV_PMGR_I2C4_CNTL__PRIV_LEVEL_MASK 0x0000D7B0 /* */
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#define NV_PMGR_I2C4_CNTL_GEN_START 0:0 /* RWIVF */
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#define NV_PMGR_I2C4_CNTL_GEN_START_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_CNTL_GEN_STOP 1:1 /* RWIVF */
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#define NV_PMGR_I2C4_CNTL_GEN_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_CNTL_CMD 3:2 /* RWIVF */
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#define NV_PMGR_I2C4_CNTL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_CNTL_GEN_RAB 4:4 /* RWIVF */
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#define NV_PMGR_I2C4_CNTL_GEN_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_CNTL_INTR_WHEN_DONE 5:5 /* RWIVF */
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#define NV_PMGR_I2C4_CNTL_INTR_WHEN_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_CNTL_BURST_SIZE 21:6 /* RWIVF */
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#define NV_PMGR_I2C4_CNTL_BURST_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_CNTL_GEN_NACK 28:28 /* RWIVF */
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#define NV_PMGR_I2C4_CNTL_GEN_NACK_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C4_CNTL_STATUS 30:29 /* R-IVF */
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#define NV_PMGR_I2C4_CNTL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C4_CNTL_CYCLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C4_CNTL_CYCLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_ADDR 0x0000D084 /* RW-4R */
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#define NV_PMGR_I2C4_ADDR__PRIV_LEVEL_MASK 0x0000D7B0 /* */
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#define NV_PMGR_I2C4_ADDR_DAB 9:0 /* RWIVF */
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#define NV_PMGR_I2C4_ADDR_DAB_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C4_ADDR_TEN_BIT 10:10 /* RWIVF */
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#define NV_PMGR_I2C4_ADDR_TEN_BIT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_ADDR_RAB 18:11 /* RWIVF */
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#define NV_PMGR_I2C4_ADDR_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_TIMING 0x0000D088 /* RW-4R */
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#define NV_PMGR_I2C4_TIMING__PRIV_LEVEL_MASK 0x0000D7B0 /* */
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#define NV_PMGR_I2C4_TIMING_SCL_PERIOD 11:0 /* RWIVF */
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#define NV_PMGR_I2C4_TIMING_SCL_PERIOD_INIT 0x0000010E /* RWI-V */
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#define NV_PMGR_I2C4_TIMING_IGNORE_ACK 15:15 /* RWIVF */
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#define NV_PMGR_I2C4_TIMING_IGNORE_ACK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_TIMING_TIMEOUT_CLK_CNT 23:16 /* RWIVF */
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#define NV_PMGR_I2C4_TIMING_TIMEOUT_CLK_CNT_INIT 0x00000001 /* R-I-V */
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#define NV_PMGR_I2C4_TIMING_TIMEOUT_CHECK 24:24 /* RWIVF */
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#define NV_PMGR_I2C4_TIMING_TIMEOUT_CHECK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_DATA 0x0000D08C /* RW-4R */
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#define NV_PMGR_I2C4_DATA__PRIV_LEVEL_MASK 0x0000D7B0 /* */
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#define NV_PMGR_I2C4_DATA_VALUE 31:0 /* RWIUF */
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#define NV_PMGR_I2C4_DATA_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C4_POLL 0x0000D090 /* RW-4R */
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#define NV_PMGR_I2C4_POLL__PRIV_LEVEL_MASK 0x0000D7B0 /* */
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#define NV_PMGR_I2C4_POLL_PERIOD 23:0 /* RWIVF */
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#define NV_PMGR_I2C4_POLL_PERIOD_INIT 0x000F4240 /* R-I-V */
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#define NV_PMGR_I2C4_POLL_INITIAL_DEV_STATUS 25:24 /* RWIVF */
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#define NV_PMGR_I2C4_POLL_INITIAL_DEV_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_POLL_MODE 30:30 /* RWIVF */
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#define NV_PMGR_I2C4_POLL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_POLL_ENABLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C4_POLL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_OVERRIDE 0x0000D094 /* RW-4R */
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#define NV_PMGR_I2C4_OVERRIDE__PRIV_LEVEL_MASK 0x0000D7B0 /* */
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#define NV_PMGR_I2C4_OVERRIDE_SCL 0:0 /* RWIVF */
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#define NV_PMGR_I2C4_OVERRIDE_SCL_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C4_OVERRIDE_SDA 1:1 /* RWIVF */
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#define NV_PMGR_I2C4_OVERRIDE_SDA_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C4_OVERRIDE_SIGNALS 2:2 /* RWIVF */
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#define NV_PMGR_I2C4_OVERRIDE_SIGNALS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_OVERRIDE_PMU 3:3 /* RWIVF */
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#define NV_PMGR_I2C4_OVERRIDE_PMU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_OVERRIDE_SCLPAD_IN 4:4 /* R--VF */
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#define NV_PMGR_I2C4_OVERRIDE_SDAPAD_IN 5:5 /* R--VF */
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#define NV_PMGR_I2C4_STEREO 0x0000D098 /* RW-4R */
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#define NV_PMGR_I2C4_STEREO__PRIV_LEVEL_MASK 0x0000D7B0 /* */
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#define NV_PMGR_I2C4_STEREO_SDA 2:0 /* RWIVF */
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#define NV_PMGR_I2C4_STEREO_SDA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_STEREO_SCL 3:3 /* RWIVF */
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#define NV_PMGR_I2C4_STEREO_SCL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_STEREO_HEAD0_INV 4:4 /* RWIVF */
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#define NV_PMGR_I2C4_STEREO_HEAD0_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_STEREO_HEAD1_INV 5:5 /* RWIVF */
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#define NV_PMGR_I2C4_STEREO_HEAD1_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_STEREO_HEAD2_INV 6:6 /* RWIVF */
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#define NV_PMGR_I2C4_STEREO_HEAD2_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_STEREO_HEAD3_INV 7:7 /* RWIVF */
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#define NV_PMGR_I2C4_STEREO_HEAD3_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C4_POLL2 0x0000D09C /* RW-4R */
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#define NV_PMGR_I2C4_POLL2__PRIV_LEVEL_MASK 0x0000D7B0 /* */
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#define NV_PMGR_I2C4_POLL2_MASK 15:0 /* RWIVF */
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#define NV_PMGR_I2C4_POLL2_MASK_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C4_POLL2_DATA 31:16 /* R-IVF */
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#define NV_PMGR_I2C4_POLL2_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C5_CNTL 0x0000D0A0 /* RW-4R */
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#define NV_PMGR_I2C5_CNTL__PRIV_LEVEL_MASK 0x0000D7B4 /* */
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#define NV_PMGR_I2C5_CNTL_GEN_START 0:0 /* RWIVF */
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#define NV_PMGR_I2C5_CNTL_GEN_START_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_CNTL_GEN_STOP 1:1 /* RWIVF */
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#define NV_PMGR_I2C5_CNTL_GEN_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_CNTL_CMD 3:2 /* RWIVF */
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#define NV_PMGR_I2C5_CNTL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_CNTL_GEN_RAB 4:4 /* RWIVF */
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#define NV_PMGR_I2C5_CNTL_GEN_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_CNTL_INTR_WHEN_DONE 5:5 /* RWIVF */
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#define NV_PMGR_I2C5_CNTL_INTR_WHEN_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_CNTL_BURST_SIZE 21:6 /* RWIVF */
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#define NV_PMGR_I2C5_CNTL_BURST_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_CNTL_GEN_NACK 28:28 /* RWIVF */
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#define NV_PMGR_I2C5_CNTL_GEN_NACK_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C5_CNTL_STATUS 30:29 /* R-IVF */
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#define NV_PMGR_I2C5_CNTL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C5_CNTL_CYCLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C5_CNTL_CYCLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_ADDR 0x0000D0A4 /* RW-4R */
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#define NV_PMGR_I2C5_ADDR__PRIV_LEVEL_MASK 0x0000D7B4 /* */
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#define NV_PMGR_I2C5_ADDR_DAB 9:0 /* RWIVF */
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#define NV_PMGR_I2C5_ADDR_DAB_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C5_ADDR_TEN_BIT 10:10 /* RWIVF */
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#define NV_PMGR_I2C5_ADDR_TEN_BIT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_ADDR_RAB 18:11 /* RWIVF */
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#define NV_PMGR_I2C5_ADDR_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_TIMING 0x0000D0A8 /* RW-4R */
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#define NV_PMGR_I2C5_TIMING__PRIV_LEVEL_MASK 0x0000D7B4 /* */
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#define NV_PMGR_I2C5_TIMING_SCL_PERIOD 11:0 /* RWIVF */
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#define NV_PMGR_I2C5_TIMING_SCL_PERIOD_INIT 0x0000010E /* RWI-V */
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#define NV_PMGR_I2C5_TIMING_IGNORE_ACK 15:15 /* RWIVF */
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#define NV_PMGR_I2C5_TIMING_IGNORE_ACK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_TIMING_TIMEOUT_CLK_CNT 23:16 /* RWIVF */
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#define NV_PMGR_I2C5_TIMING_TIMEOUT_CLK_CNT_INIT 0x00000001 /* R-I-V */
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#define NV_PMGR_I2C5_TIMING_TIMEOUT_CHECK 24:24 /* RWIVF */
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#define NV_PMGR_I2C5_TIMING_TIMEOUT_CHECK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_DATA 0x0000D0AC /* RW-4R */
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#define NV_PMGR_I2C5_DATA__PRIV_LEVEL_MASK 0x0000D7B4 /* */
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#define NV_PMGR_I2C5_DATA_VALUE 31:0 /* RWIUF */
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#define NV_PMGR_I2C5_DATA_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C5_POLL 0x0000D0B0 /* RW-4R */
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#define NV_PMGR_I2C5_POLL__PRIV_LEVEL_MASK 0x0000D7B4 /* */
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#define NV_PMGR_I2C5_POLL_PERIOD 23:0 /* RWIVF */
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#define NV_PMGR_I2C5_POLL_PERIOD_INIT 0x000F4240 /* R-I-V */
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#define NV_PMGR_I2C5_POLL_INITIAL_DEV_STATUS 25:24 /* RWIVF */
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#define NV_PMGR_I2C5_POLL_INITIAL_DEV_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_POLL_MODE 30:30 /* RWIVF */
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#define NV_PMGR_I2C5_POLL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_POLL_ENABLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C5_POLL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_OVERRIDE 0x0000D0B4 /* RW-4R */
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#define NV_PMGR_I2C5_OVERRIDE__PRIV_LEVEL_MASK 0x0000D7B4 /* */
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#define NV_PMGR_I2C5_OVERRIDE_SCL 0:0 /* RWIVF */
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#define NV_PMGR_I2C5_OVERRIDE_SCL_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C5_OVERRIDE_SDA 1:1 /* RWIVF */
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#define NV_PMGR_I2C5_OVERRIDE_SDA_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C5_OVERRIDE_SIGNALS 2:2 /* RWIVF */
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#define NV_PMGR_I2C5_OVERRIDE_SIGNALS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_OVERRIDE_PMU 3:3 /* RWIVF */
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#define NV_PMGR_I2C5_OVERRIDE_PMU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_OVERRIDE_SCLPAD_IN 4:4 /* R--VF */
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#define NV_PMGR_I2C5_OVERRIDE_SDAPAD_IN 5:5 /* R--VF */
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#define NV_PMGR_I2C5_STEREO 0x0000D0B8 /* RW-4R */
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#define NV_PMGR_I2C5_STEREO__PRIV_LEVEL_MASK 0x0000D7B4 /* */
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#define NV_PMGR_I2C5_STEREO_SDA 2:0 /* RWIVF */
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#define NV_PMGR_I2C5_STEREO_SDA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_STEREO_SCL 3:3 /* RWIVF */
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#define NV_PMGR_I2C5_STEREO_SCL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_STEREO_HEAD0_INV 4:4 /* RWIVF */
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#define NV_PMGR_I2C5_STEREO_HEAD0_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_STEREO_HEAD1_INV 5:5 /* RWIVF */
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#define NV_PMGR_I2C5_STEREO_HEAD1_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_STEREO_HEAD2_INV 6:6 /* RWIVF */
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#define NV_PMGR_I2C5_STEREO_HEAD2_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_STEREO_HEAD3_INV 7:7 /* RWIVF */
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#define NV_PMGR_I2C5_STEREO_HEAD3_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C5_POLL2 0x0000D0BC /* RW-4R */
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#define NV_PMGR_I2C5_POLL2__PRIV_LEVEL_MASK 0x0000D7B4 /* */
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#define NV_PMGR_I2C5_POLL2_MASK 15:0 /* RWIVF */
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#define NV_PMGR_I2C5_POLL2_MASK_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C5_POLL2_DATA 31:16 /* R-IVF */
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#define NV_PMGR_I2C5_POLL2_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C6_CNTL 0x0000D0C0 /* RW-4R */
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#define NV_PMGR_I2C6_CNTL__PRIV_LEVEL_MASK 0x0000D7B8 /* */
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#define NV_PMGR_I2C6_CNTL_GEN_START 0:0 /* RWIVF */
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#define NV_PMGR_I2C6_CNTL_GEN_START_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_CNTL_GEN_STOP 1:1 /* RWIVF */
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#define NV_PMGR_I2C6_CNTL_GEN_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_CNTL_CMD 3:2 /* RWIVF */
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#define NV_PMGR_I2C6_CNTL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_CNTL_GEN_RAB 4:4 /* RWIVF */
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#define NV_PMGR_I2C6_CNTL_GEN_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_CNTL_INTR_WHEN_DONE 5:5 /* RWIVF */
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#define NV_PMGR_I2C6_CNTL_INTR_WHEN_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_CNTL_BURST_SIZE 21:6 /* RWIVF */
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#define NV_PMGR_I2C6_CNTL_BURST_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_CNTL_GEN_NACK 28:28 /* RWIVF */
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#define NV_PMGR_I2C6_CNTL_GEN_NACK_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C6_CNTL_STATUS 30:29 /* R-IVF */
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#define NV_PMGR_I2C6_CNTL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C6_CNTL_CYCLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C6_CNTL_CYCLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_ADDR 0x0000D0C4 /* RW-4R */
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#define NV_PMGR_I2C6_ADDR__PRIV_LEVEL_MASK 0x0000D7B8 /* */
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#define NV_PMGR_I2C6_ADDR_DAB 9:0 /* RWIVF */
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#define NV_PMGR_I2C6_ADDR_DAB_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C6_ADDR_TEN_BIT 10:10 /* RWIVF */
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#define NV_PMGR_I2C6_ADDR_TEN_BIT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_ADDR_RAB 18:11 /* RWIVF */
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#define NV_PMGR_I2C6_ADDR_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_TIMING 0x0000D0C8 /* RW-4R */
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#define NV_PMGR_I2C6_TIMING__PRIV_LEVEL_MASK 0x0000D7B8 /* */
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#define NV_PMGR_I2C6_TIMING_SCL_PERIOD 11:0 /* RWIVF */
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#define NV_PMGR_I2C6_TIMING_SCL_PERIOD_INIT 0x0000010E /* RWI-V */
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#define NV_PMGR_I2C6_TIMING_IGNORE_ACK 15:15 /* RWIVF */
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#define NV_PMGR_I2C6_TIMING_IGNORE_ACK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_TIMING_TIMEOUT_CLK_CNT 23:16 /* RWIVF */
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#define NV_PMGR_I2C6_TIMING_TIMEOUT_CLK_CNT_INIT 0x00000001 /* R-I-V */
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#define NV_PMGR_I2C6_TIMING_TIMEOUT_CHECK 24:24 /* RWIVF */
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#define NV_PMGR_I2C6_TIMING_TIMEOUT_CHECK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_DATA 0x0000D0CC /* RW-4R */
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#define NV_PMGR_I2C6_DATA__PRIV_LEVEL_MASK 0x0000D7B8 /* */
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#define NV_PMGR_I2C6_DATA_VALUE 31:0 /* RWIUF */
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#define NV_PMGR_I2C6_DATA_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C6_POLL 0x0000D0D0 /* RW-4R */
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#define NV_PMGR_I2C6_POLL__PRIV_LEVEL_MASK 0x0000D7B8 /* */
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#define NV_PMGR_I2C6_POLL_PERIOD 23:0 /* RWIVF */
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#define NV_PMGR_I2C6_POLL_PERIOD_INIT 0x000F4240 /* R-I-V */
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#define NV_PMGR_I2C6_POLL_INITIAL_DEV_STATUS 25:24 /* RWIVF */
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#define NV_PMGR_I2C6_POLL_INITIAL_DEV_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_POLL_MODE 30:30 /* RWIVF */
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#define NV_PMGR_I2C6_POLL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_POLL_ENABLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C6_POLL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_OVERRIDE 0x0000D0D4 /* RW-4R */
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#define NV_PMGR_I2C6_OVERRIDE__PRIV_LEVEL_MASK 0x0000D7B8 /* */
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#define NV_PMGR_I2C6_OVERRIDE_SCL 0:0 /* RWIVF */
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#define NV_PMGR_I2C6_OVERRIDE_SCL_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C6_OVERRIDE_SDA 1:1 /* RWIVF */
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#define NV_PMGR_I2C6_OVERRIDE_SDA_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C6_OVERRIDE_SIGNALS 2:2 /* RWIVF */
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#define NV_PMGR_I2C6_OVERRIDE_SIGNALS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_OVERRIDE_PMU 3:3 /* RWIVF */
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#define NV_PMGR_I2C6_OVERRIDE_PMU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_OVERRIDE_SCLPAD_IN 4:4 /* R--VF */
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#define NV_PMGR_I2C6_OVERRIDE_SDAPAD_IN 5:5 /* R--VF */
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#define NV_PMGR_I2C6_STEREO 0x0000D0D8 /* RW-4R */
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#define NV_PMGR_I2C6_STEREO__PRIV_LEVEL_MASK 0x0000D7B8 /* */
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#define NV_PMGR_I2C6_STEREO_SDA 2:0 /* RWIVF */
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#define NV_PMGR_I2C6_STEREO_SDA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_STEREO_SCL 3:3 /* RWIVF */
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#define NV_PMGR_I2C6_STEREO_SCL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_STEREO_HEAD0_INV 4:4 /* RWIVF */
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#define NV_PMGR_I2C6_STEREO_HEAD0_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_STEREO_HEAD1_INV 5:5 /* RWIVF */
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#define NV_PMGR_I2C6_STEREO_HEAD1_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_STEREO_HEAD2_INV 6:6 /* RWIVF */
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#define NV_PMGR_I2C6_STEREO_HEAD2_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_STEREO_HEAD3_INV 7:7 /* RWIVF */
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#define NV_PMGR_I2C6_STEREO_HEAD3_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C6_POLL2 0x0000D0DC /* RW-4R */
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#define NV_PMGR_I2C6_POLL2__PRIV_LEVEL_MASK 0x0000D7B8 /* */
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#define NV_PMGR_I2C6_POLL2_MASK 15:0 /* RWIVF */
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#define NV_PMGR_I2C6_POLL2_MASK_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C6_POLL2_DATA 31:16 /* R-IVF */
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#define NV_PMGR_I2C6_POLL2_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C7_CNTL 0x0000D0E0 /* RW-4R */
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#define NV_PMGR_I2C7_CNTL__PRIV_LEVEL_MASK 0x0000D7BC /* */
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#define NV_PMGR_I2C7_CNTL_GEN_START 0:0 /* RWIVF */
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#define NV_PMGR_I2C7_CNTL_GEN_START_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_CNTL_GEN_STOP 1:1 /* RWIVF */
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#define NV_PMGR_I2C7_CNTL_GEN_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_CNTL_CMD 3:2 /* RWIVF */
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#define NV_PMGR_I2C7_CNTL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_CNTL_GEN_RAB 4:4 /* RWIVF */
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#define NV_PMGR_I2C7_CNTL_GEN_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_CNTL_INTR_WHEN_DONE 5:5 /* RWIVF */
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#define NV_PMGR_I2C7_CNTL_INTR_WHEN_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_CNTL_BURST_SIZE 21:6 /* RWIVF */
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#define NV_PMGR_I2C7_CNTL_BURST_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_CNTL_GEN_NACK 28:28 /* RWIVF */
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#define NV_PMGR_I2C7_CNTL_GEN_NACK_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C7_CNTL_STATUS 30:29 /* R-IVF */
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#define NV_PMGR_I2C7_CNTL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C7_CNTL_CYCLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C7_CNTL_CYCLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_ADDR 0x0000D0E4 /* RW-4R */
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#define NV_PMGR_I2C7_ADDR__PRIV_LEVEL_MASK 0x0000D7BC /* */
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#define NV_PMGR_I2C7_ADDR_DAB 9:0 /* RWIVF */
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#define NV_PMGR_I2C7_ADDR_DAB_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C7_ADDR_TEN_BIT 10:10 /* RWIVF */
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#define NV_PMGR_I2C7_ADDR_TEN_BIT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_ADDR_RAB 18:11 /* RWIVF */
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#define NV_PMGR_I2C7_ADDR_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_TIMING 0x0000D0E8 /* RW-4R */
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#define NV_PMGR_I2C7_TIMING__PRIV_LEVEL_MASK 0x0000D7BC /* */
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#define NV_PMGR_I2C7_TIMING_SCL_PERIOD 11:0 /* RWIVF */
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#define NV_PMGR_I2C7_TIMING_SCL_PERIOD_INIT 0x0000010E /* RWI-V */
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#define NV_PMGR_I2C7_TIMING_IGNORE_ACK 15:15 /* RWIVF */
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#define NV_PMGR_I2C7_TIMING_IGNORE_ACK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_TIMING_TIMEOUT_CLK_CNT 23:16 /* RWIVF */
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#define NV_PMGR_I2C7_TIMING_TIMEOUT_CLK_CNT_INIT 0x00000001 /* R-I-V */
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#define NV_PMGR_I2C7_TIMING_TIMEOUT_CHECK 24:24 /* RWIVF */
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#define NV_PMGR_I2C7_TIMING_TIMEOUT_CHECK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_DATA 0x0000D0EC /* RW-4R */
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#define NV_PMGR_I2C7_DATA__PRIV_LEVEL_MASK 0x0000D7BC /* */
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#define NV_PMGR_I2C7_DATA_VALUE 31:0 /* RWIUF */
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#define NV_PMGR_I2C7_DATA_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C7_POLL 0x0000D0F0 /* RW-4R */
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#define NV_PMGR_I2C7_POLL__PRIV_LEVEL_MASK 0x0000D7BC /* */
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#define NV_PMGR_I2C7_POLL_PERIOD 23:0 /* RWIVF */
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#define NV_PMGR_I2C7_POLL_PERIOD_INIT 0x000F4240 /* R-I-V */
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#define NV_PMGR_I2C7_POLL_INITIAL_DEV_STATUS 25:24 /* RWIVF */
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#define NV_PMGR_I2C7_POLL_INITIAL_DEV_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_POLL_MODE 30:30 /* RWIVF */
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#define NV_PMGR_I2C7_POLL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_POLL_ENABLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C7_POLL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_OVERRIDE 0x0000D0F4 /* RW-4R */
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#define NV_PMGR_I2C7_OVERRIDE__PRIV_LEVEL_MASK 0x0000D7BC /* */
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#define NV_PMGR_I2C7_OVERRIDE_SCL 0:0 /* RWIVF */
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#define NV_PMGR_I2C7_OVERRIDE_SCL_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C7_OVERRIDE_SDA 1:1 /* RWIVF */
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#define NV_PMGR_I2C7_OVERRIDE_SDA_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C7_OVERRIDE_SIGNALS 2:2 /* RWIVF */
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#define NV_PMGR_I2C7_OVERRIDE_SIGNALS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_OVERRIDE_PMU 3:3 /* RWIVF */
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#define NV_PMGR_I2C7_OVERRIDE_PMU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_OVERRIDE_SCLPAD_IN 4:4 /* R--VF */
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#define NV_PMGR_I2C7_OVERRIDE_SDAPAD_IN 5:5 /* R--VF */
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#define NV_PMGR_I2C7_STEREO 0x0000D0F8 /* RW-4R */
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#define NV_PMGR_I2C7_STEREO__PRIV_LEVEL_MASK 0x0000D7BC /* */
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#define NV_PMGR_I2C7_STEREO_SDA 2:0 /* RWIVF */
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#define NV_PMGR_I2C7_STEREO_SDA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_STEREO_SCL 3:3 /* RWIVF */
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#define NV_PMGR_I2C7_STEREO_SCL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_STEREO_HEAD0_INV 4:4 /* RWIVF */
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#define NV_PMGR_I2C7_STEREO_HEAD0_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_STEREO_HEAD1_INV 5:5 /* RWIVF */
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#define NV_PMGR_I2C7_STEREO_HEAD1_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_STEREO_HEAD2_INV 6:6 /* RWIVF */
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#define NV_PMGR_I2C7_STEREO_HEAD2_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_STEREO_HEAD3_INV 7:7 /* RWIVF */
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#define NV_PMGR_I2C7_STEREO_HEAD3_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C7_POLL2 0x0000D0FC /* RW-4R */
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#define NV_PMGR_I2C7_POLL2__PRIV_LEVEL_MASK 0x0000D7BC /* */
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#define NV_PMGR_I2C7_POLL2_MASK 15:0 /* RWIVF */
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#define NV_PMGR_I2C7_POLL2_MASK_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C7_POLL2_DATA 31:16 /* R-IVF */
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#define NV_PMGR_I2C7_POLL2_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C8_CNTL 0x0000D100 /* RW-4R */
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#define NV_PMGR_I2C8_CNTL__PRIV_LEVEL_MASK 0x0000D7C0 /* */
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#define NV_PMGR_I2C8_CNTL_GEN_START 0:0 /* RWIVF */
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#define NV_PMGR_I2C8_CNTL_GEN_START_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_CNTL_GEN_STOP 1:1 /* RWIVF */
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#define NV_PMGR_I2C8_CNTL_GEN_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_CNTL_CMD 3:2 /* RWIVF */
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#define NV_PMGR_I2C8_CNTL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_CNTL_GEN_RAB 4:4 /* RWIVF */
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#define NV_PMGR_I2C8_CNTL_GEN_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_CNTL_INTR_WHEN_DONE 5:5 /* RWIVF */
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#define NV_PMGR_I2C8_CNTL_INTR_WHEN_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_CNTL_BURST_SIZE 21:6 /* RWIVF */
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#define NV_PMGR_I2C8_CNTL_BURST_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_CNTL_GEN_NACK 28:28 /* RWIVF */
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#define NV_PMGR_I2C8_CNTL_GEN_NACK_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C8_CNTL_STATUS 30:29 /* R-IVF */
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#define NV_PMGR_I2C8_CNTL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C8_CNTL_CYCLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C8_CNTL_CYCLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_ADDR 0x0000D104 /* RW-4R */
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#define NV_PMGR_I2C8_ADDR__PRIV_LEVEL_MASK 0x0000D7C0 /* */
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#define NV_PMGR_I2C8_ADDR_DAB 9:0 /* RWIVF */
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#define NV_PMGR_I2C8_ADDR_DAB_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C8_ADDR_TEN_BIT 10:10 /* RWIVF */
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#define NV_PMGR_I2C8_ADDR_TEN_BIT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_ADDR_RAB 18:11 /* RWIVF */
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#define NV_PMGR_I2C8_ADDR_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_TIMING 0x0000D108 /* RW-4R */
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#define NV_PMGR_I2C8_TIMING__PRIV_LEVEL_MASK 0x0000D7C0 /* */
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#define NV_PMGR_I2C8_TIMING_SCL_PERIOD 11:0 /* RWIVF */
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#define NV_PMGR_I2C8_TIMING_SCL_PERIOD_INIT 0x0000010E /* RWI-V */
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#define NV_PMGR_I2C8_TIMING_IGNORE_ACK 15:15 /* RWIVF */
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#define NV_PMGR_I2C8_TIMING_IGNORE_ACK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_TIMING_TIMEOUT_CLK_CNT 23:16 /* RWIVF */
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#define NV_PMGR_I2C8_TIMING_TIMEOUT_CLK_CNT_INIT 0x00000001 /* R-I-V */
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#define NV_PMGR_I2C8_TIMING_TIMEOUT_CHECK 24:24 /* RWIVF */
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#define NV_PMGR_I2C8_TIMING_TIMEOUT_CHECK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_DATA 0x0000D10C /* RW-4R */
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#define NV_PMGR_I2C8_DATA__PRIV_LEVEL_MASK 0x0000D7C0 /* */
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#define NV_PMGR_I2C8_DATA_VALUE 31:0 /* RWIUF */
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#define NV_PMGR_I2C8_DATA_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C8_POLL 0x0000D110 /* RW-4R */
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#define NV_PMGR_I2C8_POLL__PRIV_LEVEL_MASK 0x0000D7C0 /* */
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#define NV_PMGR_I2C8_POLL_PERIOD 23:0 /* RWIVF */
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#define NV_PMGR_I2C8_POLL_PERIOD_INIT 0x000F4240 /* R-I-V */
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#define NV_PMGR_I2C8_POLL_INITIAL_DEV_STATUS 25:24 /* RWIVF */
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#define NV_PMGR_I2C8_POLL_INITIAL_DEV_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_POLL_MODE 30:30 /* RWIVF */
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#define NV_PMGR_I2C8_POLL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_POLL_ENABLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C8_POLL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_OVERRIDE 0x0000D114 /* RW-4R */
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#define NV_PMGR_I2C8_OVERRIDE__PRIV_LEVEL_MASK 0x0000D7C0 /* */
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#define NV_PMGR_I2C8_OVERRIDE_SCL 0:0 /* RWIVF */
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#define NV_PMGR_I2C8_OVERRIDE_SCL_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C8_OVERRIDE_SDA 1:1 /* RWIVF */
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#define NV_PMGR_I2C8_OVERRIDE_SDA_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C8_OVERRIDE_SIGNALS 2:2 /* RWIVF */
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#define NV_PMGR_I2C8_OVERRIDE_SIGNALS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_OVERRIDE_PMU 3:3 /* RWIVF */
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#define NV_PMGR_I2C8_OVERRIDE_PMU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_OVERRIDE_SCLPAD_IN 4:4 /* R--VF */
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#define NV_PMGR_I2C8_OVERRIDE_SDAPAD_IN 5:5 /* R--VF */
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#define NV_PMGR_I2C8_STEREO 0x0000D118 /* RW-4R */
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#define NV_PMGR_I2C8_STEREO__PRIV_LEVEL_MASK 0x0000D7C0 /* */
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#define NV_PMGR_I2C8_STEREO_SDA 2:0 /* RWIVF */
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#define NV_PMGR_I2C8_STEREO_SDA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_STEREO_SCL 3:3 /* RWIVF */
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#define NV_PMGR_I2C8_STEREO_SCL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_STEREO_HEAD0_INV 4:4 /* RWIVF */
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#define NV_PMGR_I2C8_STEREO_HEAD0_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_STEREO_HEAD1_INV 5:5 /* RWIVF */
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#define NV_PMGR_I2C8_STEREO_HEAD1_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_STEREO_HEAD2_INV 6:6 /* RWIVF */
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#define NV_PMGR_I2C8_STEREO_HEAD2_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_STEREO_HEAD3_INV 7:7 /* RWIVF */
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#define NV_PMGR_I2C8_STEREO_HEAD3_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C8_POLL2 0x0000D11C /* RW-4R */
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#define NV_PMGR_I2C8_POLL2__PRIV_LEVEL_MASK 0x0000D7C0 /* */
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#define NV_PMGR_I2C8_POLL2_MASK 15:0 /* RWIVF */
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#define NV_PMGR_I2C8_POLL2_MASK_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C8_POLL2_DATA 31:16 /* R-IVF */
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#define NV_PMGR_I2C8_POLL2_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C9_CNTL 0x0000D120 /* RW-4R */
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#define NV_PMGR_I2C9_CNTL__PRIV_LEVEL_MASK 0x0000D7C4 /* */
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#define NV_PMGR_I2C9_CNTL_GEN_START 0:0 /* RWIVF */
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#define NV_PMGR_I2C9_CNTL_GEN_START_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_CNTL_GEN_STOP 1:1 /* RWIVF */
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#define NV_PMGR_I2C9_CNTL_GEN_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_CNTL_CMD 3:2 /* RWIVF */
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#define NV_PMGR_I2C9_CNTL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_CNTL_GEN_RAB 4:4 /* RWIVF */
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#define NV_PMGR_I2C9_CNTL_GEN_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_CNTL_INTR_WHEN_DONE 5:5 /* RWIVF */
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#define NV_PMGR_I2C9_CNTL_INTR_WHEN_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_CNTL_BURST_SIZE 21:6 /* RWIVF */
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#define NV_PMGR_I2C9_CNTL_BURST_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_CNTL_GEN_NACK 28:28 /* RWIVF */
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#define NV_PMGR_I2C9_CNTL_GEN_NACK_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C9_CNTL_STATUS 30:29 /* R-IVF */
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#define NV_PMGR_I2C9_CNTL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C9_CNTL_CYCLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C9_CNTL_CYCLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_ADDR 0x0000D124 /* RW-4R */
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#define NV_PMGR_I2C9_ADDR__PRIV_LEVEL_MASK 0x0000D7C4 /* */
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#define NV_PMGR_I2C9_ADDR_DAB 9:0 /* RWIVF */
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#define NV_PMGR_I2C9_ADDR_DAB_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C9_ADDR_TEN_BIT 10:10 /* RWIVF */
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#define NV_PMGR_I2C9_ADDR_TEN_BIT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_ADDR_RAB 18:11 /* RWIVF */
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#define NV_PMGR_I2C9_ADDR_RAB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_TIMING 0x0000D128 /* RW-4R */
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#define NV_PMGR_I2C9_TIMING__PRIV_LEVEL_MASK 0x0000D7C4 /* */
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#define NV_PMGR_I2C9_TIMING_SCL_PERIOD 11:0 /* RWIVF */
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#define NV_PMGR_I2C9_TIMING_SCL_PERIOD_INIT 0x0000010E /* RWI-V */
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#define NV_PMGR_I2C9_TIMING_IGNORE_ACK 15:15 /* RWIVF */
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#define NV_PMGR_I2C9_TIMING_IGNORE_ACK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_TIMING_TIMEOUT_CLK_CNT 23:16 /* RWIVF */
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#define NV_PMGR_I2C9_TIMING_TIMEOUT_CLK_CNT_INIT 0x00000001 /* R-I-V */
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#define NV_PMGR_I2C9_TIMING_TIMEOUT_CHECK 24:24 /* RWIVF */
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#define NV_PMGR_I2C9_TIMING_TIMEOUT_CHECK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_DATA 0x0000D12C /* RW-4R */
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#define NV_PMGR_I2C9_DATA__PRIV_LEVEL_MASK 0x0000D7C4 /* */
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#define NV_PMGR_I2C9_DATA_VALUE 31:0 /* RWIUF */
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#define NV_PMGR_I2C9_DATA_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C9_POLL 0x0000D130 /* RW-4R */
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#define NV_PMGR_I2C9_POLL__PRIV_LEVEL_MASK 0x0000D7C4 /* */
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#define NV_PMGR_I2C9_POLL_PERIOD 23:0 /* RWIVF */
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#define NV_PMGR_I2C9_POLL_PERIOD_INIT 0x000F4240 /* R-I-V */
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#define NV_PMGR_I2C9_POLL_INITIAL_DEV_STATUS 25:24 /* RWIVF */
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#define NV_PMGR_I2C9_POLL_INITIAL_DEV_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_POLL_MODE 30:30 /* RWIVF */
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#define NV_PMGR_I2C9_POLL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_POLL_ENABLE 31:31 /* RWIVF */
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#define NV_PMGR_I2C9_POLL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_OVERRIDE 0x0000D134 /* RW-4R */
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#define NV_PMGR_I2C9_OVERRIDE__PRIV_LEVEL_MASK 0x0000D7C4 /* */
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#define NV_PMGR_I2C9_OVERRIDE_SCL 0:0 /* RWIVF */
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#define NV_PMGR_I2C9_OVERRIDE_SCL_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C9_OVERRIDE_SDA 1:1 /* RWIVF */
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#define NV_PMGR_I2C9_OVERRIDE_SDA_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_I2C9_OVERRIDE_SIGNALS 2:2 /* RWIVF */
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#define NV_PMGR_I2C9_OVERRIDE_SIGNALS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_OVERRIDE_PMU 3:3 /* RWIVF */
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#define NV_PMGR_I2C9_OVERRIDE_PMU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_OVERRIDE_SCLPAD_IN 4:4 /* R--VF */
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#define NV_PMGR_I2C9_OVERRIDE_SDAPAD_IN 5:5 /* R--VF */
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#define NV_PMGR_I2C9_STEREO 0x0000D138 /* RW-4R */
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#define NV_PMGR_I2C9_STEREO__PRIV_LEVEL_MASK 0x0000D7C4 /* */
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#define NV_PMGR_I2C9_STEREO_SDA 2:0 /* RWIVF */
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#define NV_PMGR_I2C9_STEREO_SDA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_STEREO_SCL 3:3 /* RWIVF */
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#define NV_PMGR_I2C9_STEREO_SCL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_STEREO_HEAD0_INV 4:4 /* RWIVF */
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#define NV_PMGR_I2C9_STEREO_HEAD0_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_STEREO_HEAD1_INV 5:5 /* RWIVF */
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#define NV_PMGR_I2C9_STEREO_HEAD1_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_STEREO_HEAD2_INV 6:6 /* RWIVF */
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#define NV_PMGR_I2C9_STEREO_HEAD2_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_STEREO_HEAD3_INV 7:7 /* RWIVF */
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#define NV_PMGR_I2C9_STEREO_HEAD3_INV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_I2C9_POLL2 0x0000D13C /* RW-4R */
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#define NV_PMGR_I2C9_POLL2__PRIV_LEVEL_MASK 0x0000D7C4 /* */
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#define NV_PMGR_I2C9_POLL2_MASK 15:0 /* RWIVF */
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#define NV_PMGR_I2C9_POLL2_MASK_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_I2C9_POLL2_DATA 31:16 /* R-IVF */
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#define NV_PMGR_I2C9_POLL2_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_0 0x00021200 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_0__PRIV_LEVEL_MASK 0x00021000 /* */
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#define NV_GPIO_OUTPUT_CTRL_0_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_0_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_0_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_0_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_0_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_0_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_0_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_0_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_0_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_0_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_0_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_0_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_0_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_0_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_0_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_1 0x00021204 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_1__PRIV_LEVEL_MASK 0x00021004 /* */
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#define NV_GPIO_OUTPUT_CTRL_1_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_1_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_1_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_1_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_1_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_1_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_1_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_1_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_1_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_1_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_1_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_1_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_1_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_1_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_1_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_2 0x00021208 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_2__PRIV_LEVEL_MASK 0x00021008 /* */
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#define NV_GPIO_OUTPUT_CTRL_2_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_2_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_2_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_2_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_2_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_2_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_2_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_2_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_2_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_2_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_2_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_2_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_2_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_2_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_2_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_3 0x0002120C /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_3__PRIV_LEVEL_MASK 0x0002100C /* */
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#define NV_GPIO_OUTPUT_CTRL_3_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_3_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_3_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_3_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_3_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_3_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_3_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_3_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_3_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_3_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_3_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_3_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_3_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_3_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_3_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_4 0x00021210 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_4__PRIV_LEVEL_MASK 0x00021010 /* */
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#define NV_GPIO_OUTPUT_CTRL_4_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_4_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_4_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_4_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_4_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_4_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_4_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_4_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_4_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_4_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_4_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_4_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_4_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_4_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_4_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_5 0x00021214 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_5__PRIV_LEVEL_MASK 0x00021014 /* */
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#define NV_GPIO_OUTPUT_CTRL_5_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_5_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_5_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_5_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_5_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_5_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_5_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_5_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_5_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_5_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_5_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_5_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_5_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_5_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_5_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_6 0x00021218 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_6__PRIV_LEVEL_MASK 0x00021018 /* */
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#define NV_GPIO_OUTPUT_CTRL_6_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_6_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_6_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_6_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_6_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_6_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_6_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_6_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_6_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_6_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_6_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_6_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_6_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_6_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_6_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_7 0x0002121C /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_7__PRIV_LEVEL_MASK 0x0002101C /* */
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#define NV_GPIO_OUTPUT_CTRL_7_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_7_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_7_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_7_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_7_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_7_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_7_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_7_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_7_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_7_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_7_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_7_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_7_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_7_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_7_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_8 0x00021220 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_8__PRIV_LEVEL_MASK 0x00021020 /* */
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#define NV_GPIO_OUTPUT_CTRL_8_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_8_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_8_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_8_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_8_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_8_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_8_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_8_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_8_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_8_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_8_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_8_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_8_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_8_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_8_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_9 0x00021224 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_9__PRIV_LEVEL_MASK 0x00021024 /* */
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#define NV_GPIO_OUTPUT_CTRL_9_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_9_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_9_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_9_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_9_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_9_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_9_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_9_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_9_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_9_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_9_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_9_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_9_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_9_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_9_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_10 0x00021228 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_10__PRIV_LEVEL_MASK 0x00021028 /* */
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#define NV_GPIO_OUTPUT_CTRL_10_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_10_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_10_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_10_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_10_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_10_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_10_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_10_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_10_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_10_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_10_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_10_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_10_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_10_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_10_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_11 0x0002122C /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_11__PRIV_LEVEL_MASK 0x0002102C /* */
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#define NV_GPIO_OUTPUT_CTRL_11_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_11_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_11_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_11_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_11_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_11_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_11_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_11_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_11_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_11_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_11_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_11_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_11_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_11_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_11_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_12 0x00021230 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_12__PRIV_LEVEL_MASK 0x00021030 /* */
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#define NV_GPIO_OUTPUT_CTRL_12_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_12_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_12_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_12_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_12_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_12_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_12_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_12_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_12_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_12_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_12_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_12_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_12_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_12_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_12_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_13 0x00021234 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_13__PRIV_LEVEL_MASK 0x00021034 /* */
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#define NV_GPIO_OUTPUT_CTRL_13_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_13_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_13_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_13_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_13_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_13_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_13_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_13_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_13_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_13_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_13_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_13_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_13_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_13_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_13_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_14 0x00021238 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_14__PRIV_LEVEL_MASK 0x00021038 /* */
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#define NV_GPIO_OUTPUT_CTRL_14_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_14_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_14_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_14_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_14_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_14_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_14_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_14_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_14_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_14_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_14_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_14_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_14_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_14_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_14_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_15 0x0002123C /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_15__PRIV_LEVEL_MASK 0x0002103C /* */
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#define NV_GPIO_OUTPUT_CTRL_15_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_15_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_15_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_15_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_15_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_15_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_15_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_15_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_15_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_15_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_15_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_15_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_15_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_15_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_15_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_16 0x00021240 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_16__PRIV_LEVEL_MASK 0x00021040 /* */
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#define NV_GPIO_OUTPUT_CTRL_16_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_16_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_16_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_16_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_16_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_16_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_16_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_16_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_16_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_16_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_16_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_16_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_16_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_16_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_16_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_17 0x00021244 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_17__PRIV_LEVEL_MASK 0x00021044 /* */
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#define NV_GPIO_OUTPUT_CTRL_17_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_17_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_17_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_17_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_17_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_17_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_17_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_17_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_17_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_17_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_17_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_17_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_17_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_17_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_17_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_18 0x00021248 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_18__PRIV_LEVEL_MASK 0x00021048 /* */
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#define NV_GPIO_OUTPUT_CTRL_18_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_18_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_18_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_18_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_18_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_18_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_18_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_18_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_18_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_18_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_18_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_18_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_18_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_18_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_18_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_19 0x0002124C /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_19__PRIV_LEVEL_MASK 0x0002104C /* */
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#define NV_GPIO_OUTPUT_CTRL_19_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_19_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_19_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_19_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_19_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_19_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_19_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_19_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_19_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_19_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_19_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_19_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_19_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_19_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_19_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_20 0x00021250 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_20__PRIV_LEVEL_MASK 0x00021050 /* */
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#define NV_GPIO_OUTPUT_CTRL_20_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_20_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_20_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_20_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_20_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_20_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_20_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_20_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_20_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_20_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_20_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_20_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_20_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_20_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_20_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_21 0x00021254 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_21__PRIV_LEVEL_MASK 0x00021054 /* */
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#define NV_GPIO_OUTPUT_CTRL_21_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_21_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_21_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_21_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_21_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_21_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_21_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_21_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_21_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_21_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_21_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_21_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_21_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_21_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_21_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_22 0x00021258 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_22__PRIV_LEVEL_MASK 0x00021058 /* */
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#define NV_GPIO_OUTPUT_CTRL_22_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_22_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_22_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_22_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_22_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_22_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_22_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_22_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_22_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_22_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_22_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_22_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_22_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_22_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_22_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_23 0x0002125C /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_23__PRIV_LEVEL_MASK 0x0002105C /* */
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#define NV_GPIO_OUTPUT_CTRL_23_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_23_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_23_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_23_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_23_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_23_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_23_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_23_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_23_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_23_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_23_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_23_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_23_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_23_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_23_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_24 0x00021260 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_24__PRIV_LEVEL_MASK 0x00021060 /* */
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#define NV_GPIO_OUTPUT_CTRL_24_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_24_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_24_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_24_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_24_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_24_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_24_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_24_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_24_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_24_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_24_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_24_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_24_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_24_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_24_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_25 0x00021264 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_25__PRIV_LEVEL_MASK 0x00021064 /* */
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#define NV_GPIO_OUTPUT_CTRL_25_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_25_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_25_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_25_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_25_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_25_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_25_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_25_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_25_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_25_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_25_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_25_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_25_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_25_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_25_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_26 0x00021268 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_26__PRIV_LEVEL_MASK 0x00021068 /* */
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#define NV_GPIO_OUTPUT_CTRL_26_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_26_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_26_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_26_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_26_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_26_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_26_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_26_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_26_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_26_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_26_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_26_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_26_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_26_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_26_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_27 0x0002126C /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_27__PRIV_LEVEL_MASK 0x0002106C /* */
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#define NV_GPIO_OUTPUT_CTRL_27_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_27_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_27_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_27_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_27_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_27_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_27_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_27_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_27_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_27_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_27_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_27_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_27_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_27_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_27_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_28 0x00021270 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_28__PRIV_LEVEL_MASK 0x00021070 /* */
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#define NV_GPIO_OUTPUT_CTRL_28_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_28_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_28_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_28_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_28_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_28_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_28_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_28_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_28_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_28_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_28_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_28_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_28_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_28_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_28_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_29 0x00021274 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_29__PRIV_LEVEL_MASK 0x00021074 /* */
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#define NV_GPIO_OUTPUT_CTRL_29_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_29_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_29_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_29_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_29_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_29_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_29_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_29_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_29_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_29_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_29_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_29_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_29_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_29_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_29_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_30 0x00021278 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_30__PRIV_LEVEL_MASK 0x00021078 /* */
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#define NV_GPIO_OUTPUT_CTRL_30_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_30_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_30_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_30_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_30_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_30_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_30_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_30_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_30_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_30_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_30_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_30_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_30_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_30_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_30_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_31 0x0002127C /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_31__PRIV_LEVEL_MASK 0x0002107C /* */
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#define NV_GPIO_OUTPUT_CTRL_31_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_31_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_31_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_31_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_31_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_31_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_31_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_31_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_31_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_31_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_31_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_31_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_31_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_31_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_31_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_32 0x00021280 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_32__PRIV_LEVEL_MASK 0x00021080 /* */
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#define NV_GPIO_OUTPUT_CTRL_32_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_32_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_32_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_32_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_32_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_32_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_32_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_32_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_32_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_32_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_32_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_32_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_32_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_32_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_32_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_33 0x00021284 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_33__PRIV_LEVEL_MASK 0x00021084 /* */
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#define NV_GPIO_OUTPUT_CTRL_33_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_33_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_33_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_33_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_33_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_33_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_33_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_33_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_33_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_33_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_33_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_33_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_33_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_33_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_33_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_34 0x00021288 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_34__PRIV_LEVEL_MASK 0x00021088 /* */
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#define NV_GPIO_OUTPUT_CTRL_34_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_34_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_34_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_34_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_34_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_34_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_34_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_34_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_34_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_34_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_34_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_34_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_34_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_34_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_34_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_35 0x0002128C /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_35__PRIV_LEVEL_MASK 0x0002108C /* */
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#define NV_GPIO_OUTPUT_CTRL_35_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_35_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_35_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_35_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_35_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_35_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_35_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_35_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_35_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_35_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_35_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_35_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_35_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_35_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_35_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_36 0x00021290 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_36__PRIV_LEVEL_MASK 0x00021090 /* */
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#define NV_GPIO_OUTPUT_CTRL_36_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_36_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_36_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_36_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_36_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_36_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_36_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_36_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_36_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_36_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_36_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_36_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_36_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_36_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_36_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_37 0x00021294 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_37__PRIV_LEVEL_MASK 0x00021094 /* */
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#define NV_GPIO_OUTPUT_CTRL_37_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_37_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_37_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_37_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_37_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_37_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_37_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_37_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_37_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_37_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_37_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_37_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_37_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_37_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_37_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_38 0x00021298 /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_38__PRIV_LEVEL_MASK 0x00021098 /* */
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#define NV_GPIO_OUTPUT_CTRL_38_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_38_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_38_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_38_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_38_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_38_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_38_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_38_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_38_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_38_IO_OUT_INV 15:15 /* RWIVF */
|
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#define NV_GPIO_OUTPUT_CTRL_38_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_38_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_38_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_38_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_38_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_39 0x0002129C /* RW-4R */
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#define NV_GPIO_OUTPUT_CTRL_39__PRIV_LEVEL_MASK 0x0002109C /* */
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#define NV_GPIO_OUTPUT_CTRL_39_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_39_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_39_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_39_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_39_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_39_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_39_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CTRL_39_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_39_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CTRL_39_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_39_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_39_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_39_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CTRL_39_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CTRL_39_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CNTL(i) (0x00021200 +((i) * 0x4)) /* RW-4A */
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#define NV_GPIO_OUTPUT_CNTL__SIZE_1 40 /* */
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#define NV_GPIO_OUTPUT_CNTL_SEL 7:0 /* RWIVF */
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#define NV_GPIO_OUTPUT_CNTL_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_NORMAL 0x00000000 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_RASTER_SYNC_0 0x00000040 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_RASTER_SYNC_1 0x00000041 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_RASTER_SYNC_2 0x00000042 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_RASTER_SYNC_3 0x00000043 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_RASTER_SYNC(i) ((i) + 0x40) /* */
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#define NV_GPIO_OUTPUT_CNTL_SEL_RASTER_SYNC__SIZE_1 4 /* */
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#define NV_GPIO_OUTPUT_CNTL_SEL_STEREO_0 0x00000048 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_STEREO_1 0x00000049 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_STEREO_2 0x0000004A /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_STEREO_3 0x0000004B /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_STEREO(i) ((i) + 0x48) /* */
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#define NV_GPIO_OUTPUT_CNTL_SEL_STEREO__SIZE_1 4 /* */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SWAP_READY_OUT_0 0x00000050 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SWAP_READY_OUT_1 0x00000051 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SWAP_READY_OUT_2 0x00000052 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SWAP_READY_OUT_3 0x00000053 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SWAP_READY_OUT(i) ((i) + 0x50) /* */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SWAP_READY_OUT__SIZE_1 4 /* */
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#define NV_GPIO_OUTPUT_CNTL_SEL_VID_PWM_3 0x00000055 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_VID_PWM_2 0x00000056 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_VID_PWM_1 0x00000057 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_FAN_ALERT 0x00000059 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_ADC_MUX_SEL 0x0000005A /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_BA_METER 0x0000005B /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_PWM_OUTPUT 0x0000005C /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_VID_PWM 0x0000005D /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_THERMAL_PWM 0x0000005E /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_THERMAL_SLOWDOWN 0x0000005F /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_0 0x00000060 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_1 0x00000061 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_2 0x00000062 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_3 0x00000063 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_4 0x00000064 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_5 0x00000065 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_6 0x00000066 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_7 0x00000067 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_8 0x00000068 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_9 0x00000069 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_A 0x0000006A /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_B 0x0000006B /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_C 0x0000006C /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_D 0x0000006D /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_E 0x0000006E /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_DEBUG_PORT_F 0x0000006F /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SPI_CS_1 0x00000071 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SPI_CS_2 0x00000072 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SPI_CS_3 0x00000073 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SPI_CS(i) ((i)+0x70) /* */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SPI_CS__SIZE_1 4 /* */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR0_TMDS_OUT_PWM 0x00000080 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR0_TMDS_OUT_PINA 0x00000081 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR0_TMDS_OUT_PINB 0x00000082 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR1_TMDS_OUT_PWM 0x00000084 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR1_TMDS_OUT_PINA 0x00000085 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR1_TMDS_OUT_PINB 0x00000086 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR2_TMDS_OUT_PWM 0x00000088 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR2_TMDS_OUT_PINA 0x00000089 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR2_TMDS_OUT_PINB 0x0000008A /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR3_TMDS_OUT_PWM 0x0000008C /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR3_TMDS_OUT_PINA 0x0000008D /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR3_TMDS_OUT_PINB 0x0000008E /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR_TMDS_OUT_PWM(i) (((i)*4) + 0x80)/* */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR_TMDS_OUT_PWM__SIZE_1 8 /* */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR_TMDS_OUT_PINA(i) (((i)*4) + 0x81)/* */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR_TMDS_OUT_PINA__SIZE_1 8 /* */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR_TMDS_OUT_PINB(i) (((i)*4) + 0x82)/* */
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#define NV_GPIO_OUTPUT_CNTL_SEL_SOR_TMDS_OUT_PINB__SIZE_1 8 /* */
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#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT 12:12 /* RWIVF */
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#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT_0 0x00000000 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_IO_OUTPUT_1 0x00000001 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_IO_OUT_EN 13:13 /* RWIVF */
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#define NV_GPIO_OUTPUT_CNTL_IO_OUT_EN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CNTL_IO_OUT_EN_NO 0x00000000 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_IO_OUT_EN_YES 0x00000001 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_IO_INPUT 14:14 /* R--VF */
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#define NV_GPIO_OUTPUT_CNTL_IO_INPUT_0 0x00000000 /* R---V */
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#define NV_GPIO_OUTPUT_CNTL_IO_INPUT_1 0x00000001 /* R---V */
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#define NV_GPIO_OUTPUT_CNTL_IO_OUT_INV 15:15 /* RWIVF */
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#define NV_GPIO_OUTPUT_CNTL_IO_OUT_INV_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CNTL_IO_OUT_INV_DISABLE 0x00000000 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_IO_OUT_INV_ENABLE 0x00000001 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_PULLUD 17:16 /* RWIVF */
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#define NV_GPIO_OUTPUT_CNTL_PULLUD_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CNTL_PULLUD_NONE 0x00000000 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_PULLUD_UP 0x00000001 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_PULLUD_DOWN 0x00000002 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_PULLUD_RESERVED 0x00000003 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_OPEN_DRAIN 18:18 /* RWIVF */
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#define NV_GPIO_OUTPUT_CNTL_OPEN_DRAIN_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_OUTPUT_CNTL_OPEN_DRAIN_DISABLE 0x00000000 /* RW--V */
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#define NV_GPIO_OUTPUT_CNTL_OPEN_DRAIN_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_OUTPUT_CNTL_TRIGGER 0x0000D604 /* RWI4R */
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#define NV_PMGR_GPIO_OUTPUT_CNTL_TRIGGER__PRIV_LEVEL_MASK 0x0000D7E0 /* */
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#define NV_PMGR_GPIO_OUTPUT_CNTL_TRIGGER_UPDATE 0:0 /* RWIVF */
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#define NV_PMGR_GPIO_OUTPUT_CNTL_TRIGGER_UPDATE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GPIO_OUTPUT_CNTL_TRIGGER_UPDATE_DONE 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_OUTPUT_CNTL_TRIGGER_UPDATE_TRIGGER 0x00000001 /* -W--T */
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#define NV_PMGR_GPIO_OUTPUT_CNTL_TRIGGER_UPDATE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_0__UNASSIGNED 0x0
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#define NV_PMGR_GPIO_INPUT_FUNC_AUX_HPD(i) ((i)+1)
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#define NV_PMGR_GPIO_INPUT_FUNC_AUX_HPD__SIZE_1 7
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#define NV_PMGR_GPIO_INPUT_FUNC_RASTER_SYNC(i) ((i)+9)
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#define NV_PMGR_GPIO_INPUT_FUNC_RASTER_SYNC__SIZE_1 4
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#define NV_PMGR_GPIO_INPUT_FUNC_SWAP_READY(i) ((i)+17)
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#define NV_PMGR_GPIO_INPUT_FUNC_SWAP_READY__SIZE_1 2
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#define NV_PMGR_GPIO_INPUT_FUNC_THERMAL_PWM 20
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#define NV_PMGR_GPIO_INPUT_FUNC_THERMAL_ALERT 22
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#define NV_PMGR_GPIO_INPUT_FUNC_POWER_ALERT 23
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#define NV_PMGR_GPIO_INPUT_FUNC_TACH_0 24
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#define NV_PMGR_GPIO_INPUT_FUNC_TACH_1 12
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#define NV_PMGR_GPIO_INPUT_FUNC_EXT_ALERT_0 8
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#define NV_PMGR_GPIO_INPUT_FUNC_EXT_ALERT_1 19
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#define NV_PMGR_GPIO_INPUT_FUNC_AUX_0_HPD_PINNUM_INIT 0x00000001
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#define NV_PMGR_GPIO_INPUT_FUNC_AUX_1_HPD_PINNUM_INIT 0x00000013
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#define NV_PMGR_GPIO_INPUT_FUNC_AUX_2_HPD_PINNUM_INIT 0x0000000F
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#define NV_PMGR_GPIO_INPUT_FUNC_AUX_3_HPD_PINNUM_INIT 0x00000015
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#define NV_PMGR_GPIO_INPUT_FUNC_AUX_4_HPD_PINNUM_INIT 0x0000001C
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#define NV_PMGR_GPIO_INPUT_FUNC_AUX_5_HPD_PINNUM_INIT 0x0000000E
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#define NV_PMGR_GPIO_INPUT_FUNC_AUX_6_HPD_PINNUM_INIT 0x0000001B
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#define NV_PMGR_GPIO_INPUT_FUNC_RASTER_SYNC_0_PINNUM_INIT 0x00000003
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#define NV_PMGR_GPIO_INPUT_FUNC_RASTER_SYNC_1_PINNUM_INIT 0x0000000B
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#define NV_PMGR_GPIO_INPUT_FUNC_RASTER_SYNC_2_PINNUM_INIT 0x0000001E
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#define NV_PMGR_GPIO_INPUT_FUNC_SWAP_READY0_PINNUM_INIT 0x00000016
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#define NV_PMGR_GPIO_INPUT_FUNC_SWAP_READY1_PINNUM_INIT 0x00000018
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#define NV_PMGR_GPIO_INPUT_FUNC_THERMAL_PWM_PINNUM_INIT 0x00000010
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#define NV_PMGR_GPIO_INPUT_FUNC_VR_MON_PINNUM_INIT 0x00000008
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#define NV_PMGR_GPIO_INPUT_FUNC_THERMAL_ALERT_PINNUM_INIT 0x00000009
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#define NV_PMGR_GPIO_INPUT_FUNC_POWER_ALERT_PINNUM_INIT 0x0000000C
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#define NV_PMGR_GPIO_INPUT_FUNC_TACH_PINNUM_INIT 0x00000004
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#define NV_PMGR_GPIO_INPUT_FUNC_TACH_0_PINNUM_INIT 0x00000004
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#define NV_PMGR_GPIO_INPUT_FUNC_TACH_1_PINNUM_INIT 0x00000007
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#define NV_PMGR_GPIO_INPUT_CNTL_1 0x0000D740 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_1__PRIV_LEVEL_MASK 0x0000D580 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_1_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_1_PINNUM_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_1_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_1_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_1_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_1_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_1_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_1_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_1_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_2 0x0000D744 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_2__PRIV_LEVEL_MASK 0x0000D584 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_2_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_2_PINNUM_INIT 0x00000013 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_2_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_2_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_2_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_2_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_2_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_2_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_2_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_2_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_2_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_2_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_3 0x0000D748 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_3__PRIV_LEVEL_MASK 0x0000D588 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_3_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_3_PINNUM_INIT 0x0000000F /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_3_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_3_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_3_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_3_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_3_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_3_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_3_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_3_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_3_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_3_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_4 0x0000D74C /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_4__PRIV_LEVEL_MASK 0x0000D58C /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_4_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_4_PINNUM_INIT 0x00000015 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_4_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_4_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_4_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_4_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_4_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_4_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_4_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_4_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_4_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_4_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_5 0x0000D750 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_5__PRIV_LEVEL_MASK 0x0000D590 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_5_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_5_PINNUM_INIT 0x0000001C /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_5_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_5_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_5_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_5_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_5_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_5_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_5_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_5_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_5_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_5_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_6 0x0000D754 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_6__PRIV_LEVEL_MASK 0x0000D594 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_6_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_6_PINNUM_INIT 0x0000000E /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_6_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_6_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_6_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_6_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_6_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_6_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_6_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_6_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_6_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_6_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_7 0x0000D758 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_7__PRIV_LEVEL_MASK 0x0000D598 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_7_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_7_PINNUM_INIT 0x0000001B /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_7_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_7_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_7_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_7_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_7_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_7_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_7_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_7_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_7_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_7_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_8 0x0000D75C /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_8__PRIV_LEVEL_MASK 0x0000D59C /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_8_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_8_PINNUM_INIT 0x000000FF /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_8_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_8_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_8_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_8_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_8_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_8_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_8_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_8_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_8_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_8_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_9 0x0000D760 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_9__PRIV_LEVEL_MASK 0x0000D5A0 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_9_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_9_PINNUM_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_9_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_9_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_9_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_9_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_9_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_9_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_9_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_9_BYPASS_FILTER_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_9_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_9_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_10 0x0000D764 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_10__PRIV_LEVEL_MASK 0x0000D5A4 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_10_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_10_PINNUM_INIT 0x0000000B /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_10_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_10_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_10_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_10_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_10_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_10_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_10_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_10_BYPASS_FILTER_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_10_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_10_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_11 0x0000D768 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_11__PRIV_LEVEL_MASK 0x0000D5A8 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_11_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_11_PINNUM_INIT 0x0000001E /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_11_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_11_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_11_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_11_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_11_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_11_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_11_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_11_BYPASS_FILTER_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_11_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_11_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_12 0x0000D76C /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_12__PRIV_LEVEL_MASK 0x0000D5AC /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_12_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_12_PINNUM_INIT 0x00000007 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_12_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_12_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_12_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_12_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_12_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_12_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_12_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_12_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_12_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_12_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_13 0x0000D770 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_13__PRIV_LEVEL_MASK 0x0000D5B0 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_13_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_13_PINNUM_INIT 0x000000FF /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_13_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_13_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_13_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_13_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_13_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_13_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_13_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_13_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_13_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_13_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_14 0x0000D774 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_14__PRIV_LEVEL_MASK 0x0000D5B4 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_14_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_14_PINNUM_INIT 0x000000FF /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_14_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_14_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_14_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_14_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_14_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_14_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_14_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_14_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_14_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_14_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_15 0x0000D778 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_15__PRIV_LEVEL_MASK 0x0000D5B8 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_15_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_15_PINNUM_INIT 0x000000FF /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_15_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_15_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_15_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_15_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_15_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_15_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_15_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_15_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_15_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_15_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_16 0x0000D77C /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_16__PRIV_LEVEL_MASK 0x0000D5BC /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_16_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_16_PINNUM_INIT 0x000000FF /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_16_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_16_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_16_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_16_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_16_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_16_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_16_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_16_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_16_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_16_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_17 0x0000D780 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_17__PRIV_LEVEL_MASK 0x0000D5C0 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_17_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_17_PINNUM_INIT 0x00000016 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_17_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_17_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_17_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_17_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_17_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_17_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_17_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_17_BYPASS_FILTER_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_17_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_17_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_18 0x0000D784 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_18__PRIV_LEVEL_MASK 0x0000D5C4 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_18_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_18_PINNUM_INIT 0x00000018 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_18_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_18_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_18_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_18_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_18_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_18_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_18_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_18_BYPASS_FILTER_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_18_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_18_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_19 0x0000D788 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_19__PRIV_LEVEL_MASK 0x0000D5C8 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_19_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_19_PINNUM_INIT 0x000000FF /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_19_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_19_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_19_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_19_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_19_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_19_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_19_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_19_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_19_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_19_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_20 0x0000D78C /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_20__PRIV_LEVEL_MASK 0x0000D5CC /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_20_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_20_PINNUM_INIT 0x00000010 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_20_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_20_INV_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_20_INV_YES 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_20_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_20_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_20_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_20_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_20_BYPASS_FILTER_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_20_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_20_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_21 0x0000D790 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_21__PRIV_LEVEL_MASK 0x0000D5D0 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_21_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_21_PINNUM_INIT 0x00000008 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_21_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_21_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_21_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_21_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_21_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_21_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_21_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_21_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_21_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_21_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_22 0x0000D794 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_22__PRIV_LEVEL_MASK 0x0000D5D4 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_22_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_22_PINNUM_INIT 0x00000009 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_22_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_22_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_22_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_22_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_22_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_22_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_22_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_22_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_22_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_22_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_23 0x0000D798 /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_23__PRIV_LEVEL_MASK 0x0000D5D8 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_23_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_23_PINNUM_INIT 0x0000000C /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_23_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_23_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_23_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_23_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_23_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_23_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_23_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_23_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_23_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_23_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_24 0x0000D79C /* RW-4R */
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#define NV_PMGR_GPIO_INPUT_CNTL_24__PRIV_LEVEL_MASK 0x0000D5DC /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_24_PINNUM 7:0 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_24_PINNUM_INIT 0x00000004 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_24_INV 8:8 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_24_INV_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_24_INV_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_24_READ 9:9 /* R--VF */
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#define NV_PMGR_GPIO_INPUT_CNTL_24_READ_0 0x00000000 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_24_READ_1 0x00000001 /* R---V */
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#define NV_PMGR_GPIO_INPUT_CNTL_24_BYPASS_FILTER 10:10 /* RWIVF */
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#define NV_PMGR_GPIO_INPUT_CNTL_24_BYPASS_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GPIO_INPUT_CNTL_24_BYPASS_FILTER_NO 0x00000000 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL_24_BYPASS_FILTER_YES 0x00000001 /* RW--V */
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#define NV_PMGR_GPIO_INPUT_CNTL(i) 0x0000D740 + ((i)-1) * (0x0000D744 - 0x0000D740) /* */
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#define NV_PMGR_GPIO_INPUT_CNTL__SIZE_1 25 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_PINNUM 7:0 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_PINNUM_UNUSED 0x000000FF /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_INV 8:8 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_INV_NO 0x00000000 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_INV_YES 0x00000001 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_READ 9:9 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_READ_0 0x00000000 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_READ_1 0x00000001 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER 10:10 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER_NO 0x00000000 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_BYPASS_FILTER_YES 0x00000001 /* */
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#define NV_PMGR_GPIO_INPUT_CNTL_PINNUM_INIT(i) (i) == 1? 0x00000001 : (i) == 2? 0x00000013 : (i) == 3? 0x0000000F : (i) == 4? 0x00000015 : (i) == 5? 0x0000001C : (i) == 6? 0x0000000E : (i) == 7? 0x0000001B : (i) == 8? 0x000000FF : (i) == 9? 0x00000003 : (i) == 10? 0x0000000B : (i) == 11? 0x0000001E : (i) == 12? 0x00000007 : (i) == 13? 0x000000FF : (i) == 14? 0x000000FF : (i) == 15? 0x000000FF : (i) == 16? 0x000000FF : (i) == 17? 0x00000016 : (i) == 18? 0x00000018 : (i) == 19? 0x000000FF : (i) == 20? 0x00000010 : (i) == 21? 0x00000008 : (i) == 22? 0x00000009 : (i) == 23? 0x0000000C : (i) == 24? 0x00000004 : 0x000000FF
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#define NV_PMGR_GPIO_INPUT_CNTL_PINNUM_INIT__SIZE_1 25
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#define NV_PMGR_IP_VER 0x0000E000 /* R--4R */
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#define NV_PMGR_IP_VER_DEV 7:0 /* R-IVF */
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#define NV_PMGR_IP_VER_DEV_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_IP_VER_ECO 15:8 /* R-IVF */
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#define NV_PMGR_IP_VER_ECO_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_IP_VER_MINOR 23:16 /* R-IVF */
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#define NV_PMGR_IP_VER_MINOR_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_IP_VER_MAJOR 31:24 /* R-IVF */
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#define NV_PMGR_IP_VER_MAJOR_INIT 0x00000004 /* R-I-V */
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#define NV_PMGR_EVENT_DISPATCH 0x0000E040 /* R--4R */
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#define NV_PMGR_EVENT_DISPATCH_I2C 0:0 /* R--VF */
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#define NV_PMGR_EVENT_DISPATCH_I2C_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_DISPATCH_I2C_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_DISPATCH_DAC 1:1 /* R--VF */
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#define NV_PMGR_EVENT_DISPATCH_DAC_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_DISPATCH_DAC_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_DISPATCH_AUX 2:2 /* R--VF */
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#define NV_PMGR_EVENT_DISPATCH_AUX_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_DISPATCH_AUX_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_DISPATCH_GPIO_LIST_1 4:4 /* R--VF */
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#define NV_PMGR_EVENT_DISPATCH_GPIO_LIST_1_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_DISPATCH_GPIO_LIST_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_DISPATCH_GPIO_LIST_2 5:5 /* R--VF */
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#define NV_PMGR_EVENT_DISPATCH_GPIO_LIST_2_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_DISPATCH_GPIO_LIST_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_DISPATCH_SPI 6:6 /* R--VF */
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#define NV_PMGR_EVENT_DISPATCH_SPI_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_DISPATCH_SPI_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_DISPATCH_GPIO_LIST_3 7:7 /* R--VF */
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#define NV_PMGR_EVENT_DISPATCH_GPIO_LIST_3_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_DISPATCH_GPIO_LIST_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH 0x0000E044 /* R--4R */
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#define NV_PMGR_RM_INTR_DISPATCH_I2C 0:0 /* R--VF */
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#define NV_PMGR_RM_INTR_DISPATCH_I2C_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH_I2C_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH_DAC 1:1 /* R--VF */
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#define NV_PMGR_RM_INTR_DISPATCH_DAC_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH_DAC_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH_AUX 2:2 /* R--VF */
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#define NV_PMGR_RM_INTR_DISPATCH_AUX_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH_AUX_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH_GPIO_LIST_1 4:4 /* R--VF */
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#define NV_PMGR_RM_INTR_DISPATCH_GPIO_LIST_1_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH_GPIO_LIST_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH_GPIO_LIST_2 5:5 /* R--VF */
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#define NV_PMGR_RM_INTR_DISPATCH_GPIO_LIST_2_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH_GPIO_LIST_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH_SPI 6:6 /* R--VF */
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#define NV_PMGR_RM_INTR_DISPATCH_SPI_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH_SPI_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH_GPIO_LIST_3 7:7 /* R--VF */
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#define NV_PMGR_RM_INTR_DISPATCH_GPIO_LIST_3_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_DISPATCH_GPIO_LIST_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH 0x0000E048 /* R--4R */
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#define NV_PMGR_PMU_INTR_DISPATCH_I2C 0:0 /* R--VF */
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#define NV_PMGR_PMU_INTR_DISPATCH_I2C_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH_I2C_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH_DAC 1:1 /* R--VF */
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#define NV_PMGR_PMU_INTR_DISPATCH_DAC_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH_DAC_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH_AUX 2:2 /* R--VF */
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#define NV_PMGR_PMU_INTR_DISPATCH_AUX_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH_AUX_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH_GPIO_LIST_1 4:4 /* R--VF */
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#define NV_PMGR_PMU_INTR_DISPATCH_GPIO_LIST_1_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH_GPIO_LIST_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH_GPIO_LIST_2 5:5 /* R--VF */
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#define NV_PMGR_PMU_INTR_DISPATCH_GPIO_LIST_2_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH_GPIO_LIST_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH_SPI 6:6 /* R--VF */
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#define NV_PMGR_PMU_INTR_DISPATCH_SPI_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH_SPI_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH_GPIO_LIST_3 7:7 /* R--VF */
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#define NV_PMGR_PMU_INTR_DISPATCH_GPIO_LIST_3_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_DISPATCH_GPIO_LIST_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH 0x0000E04C /* R--4R */
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#define NV_PMGR_GSP_INTR_DISPATCH_I2C 0:0 /* R--VF */
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#define NV_PMGR_GSP_INTR_DISPATCH_I2C_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH_I2C_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH_DAC 1:1 /* R--VF */
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#define NV_PMGR_GSP_INTR_DISPATCH_DAC_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH_DAC_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH_AUX 2:2 /* R--VF */
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#define NV_PMGR_GSP_INTR_DISPATCH_AUX_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH_AUX_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH_GPIO_LIST_1 4:4 /* R--VF */
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#define NV_PMGR_GSP_INTR_DISPATCH_GPIO_LIST_1_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH_GPIO_LIST_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH_GPIO_LIST_2 5:5 /* R--VF */
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#define NV_PMGR_GSP_INTR_DISPATCH_GPIO_LIST_2_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH_GPIO_LIST_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH_SPI 6:6 /* R--VF */
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#define NV_PMGR_GSP_INTR_DISPATCH_SPI_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH_SPI_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH_GPIO_LIST_3 7:7 /* R--VF */
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#define NV_PMGR_GSP_INTR_DISPATCH_GPIO_LIST_3_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_DISPATCH_GPIO_LIST_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1 0x00021600/* RWI4R */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO0_RISING 0:0 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO0_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO0_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO0_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO1_RISING 1:1 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO1_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO1_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO1_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO2_RISING 2:2 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO2_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO2_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO2_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO3_RISING 3:3 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO3_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO3_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO3_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO4_RISING 4:4 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO4_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO4_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO4_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO5_RISING 5:5 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO5_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO5_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO5_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO6_RISING 6:6 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO6_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO6_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO6_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO7_RISING 7:7 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO7_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO7_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO7_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO8_RISING 8:8 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO8_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO8_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO8_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO9_RISING 9:9 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO9_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO9_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO9_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO10_RISING 10:10 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO10_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO10_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO10_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO11_RISING 11:11 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO11_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO11_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO11_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO12_RISING 12:12 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO12_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO12_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO12_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO13_RISING 13:13 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO13_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO13_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO13_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO14_RISING 14:14 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO14_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO14_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO14_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO15_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO15_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO_RISING(i) (0+(i)):(0+(i)) /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO0_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO0_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO0_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO0_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO1_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO1_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO1_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO1_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO2_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO2_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO2_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO2_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO3_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO3_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO3_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO3_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO4_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO4_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO4_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO4_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO5_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO5_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO5_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO5_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO6_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO6_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO6_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO6_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO7_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO7_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO7_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO7_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO8_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO8_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO8_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO8_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO9_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO9_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO9_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO9_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO10_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO10_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO10_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO10_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO11_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO11_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO11_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO11_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO12_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO12_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO12_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO12_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO13_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO13_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO13_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO13_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO14_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO14_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO14_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO14_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO15_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO15_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO_FALLING(i) (16+(i)):(16+(i))/* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO_FALLING_NOP 0x00000000 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_1_GPIO_FALLING_ASSERT 0x00000001 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_1 0x00021604 /* RW-4R */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO0_RISING 0:0 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO0_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO0_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO0_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO0_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO1_RISING 1:1 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO1_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO1_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO1_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO1_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO2_RISING 2:2 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO2_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO2_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO2_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO2_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO3_RISING 3:3 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO3_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO3_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO3_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO3_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO4_RISING 4:4 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO4_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO4_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO4_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO4_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO5_RISING 5:5 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO5_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO5_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO5_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO5_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO6_RISING 6:6 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO6_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO6_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO6_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO6_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO7_RISING 7:7 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO7_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO7_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO7_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO7_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO8_RISING 8:8 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO8_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO8_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO8_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO8_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO9_RISING 9:9 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO9_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO9_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO9_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO9_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO10_RISING 10:10 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO10_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO10_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO10_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO10_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO11_RISING 11:11 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO11_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO11_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO11_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO11_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO12_RISING 12:12 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO12_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO12_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO12_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO12_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO13_RISING 13:13 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO13_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO13_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO13_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO13_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO14_RISING 14:14 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO14_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO14_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO14_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO14_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO15_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO15_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO15_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO_RISING(i) (0+(i)):(0+(i)) /* */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO_RISING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO_RISING_PENDING 0x00000001 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO_RISING_RESET 0x00000001 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO0_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO0_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO0_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO0_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO0_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO1_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO1_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO1_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO1_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO1_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO2_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO2_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO2_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO2_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO2_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO3_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO3_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO3_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO3_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO3_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO4_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO4_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO4_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO4_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO4_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO5_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO5_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO5_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO5_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO5_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO6_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO6_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO6_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO6_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO6_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO7_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO7_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO7_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO7_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO7_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO8_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO8_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO8_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO8_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO8_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO9_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO9_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO9_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO9_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO9_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO10_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO10_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO10_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO10_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO10_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO11_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO11_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO11_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO11_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO11_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO12_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO12_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO12_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO12_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO12_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO13_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO13_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO13_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO13_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO13_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO14_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO14_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO14_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO14_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO14_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO15_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO15_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO15_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO_FALLING(i) (16+(i)):(16+(i)) /* */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO_FALLING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO_FALLING_PENDING 0x00000001 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_1_GPIO_FALLING_RESET 0x00000001 /* */
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#define NV_PMGR_EVENT_FRC_I2C 0x0000E058 /* RW-4R */
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#define NV_PMGR_EVENT_FRC_I2C_I2C0 0:0 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_I2C_I2C0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C0_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C1 1:1 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_I2C_I2C1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C1_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C1_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C2 2:2 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_I2C_I2C2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C2_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C2_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C3 3:3 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_I2C_I2C3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C3_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C3_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C4 4:4 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_I2C_I2C4_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C4_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C4_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C5 5:5 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_I2C_I2C5_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C5_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C5_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C6 6:6 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_I2C_I2C6_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C6_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C6_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C7 7:7 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_I2C_I2C7_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C7_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C7_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C8 8:8 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_I2C_I2C8_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C8_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C8_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C9 9:9 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_I2C_I2C9_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C9_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C9_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_I2C_I2C(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_EVENT_FRC_I2C_I2C__SIZE_1 10 /* */
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#define NV_PMGR_EVENT_FRC_I2C_I2C_DISABLED 0x00000000 /* */
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#define NV_PMGR_EVENT_FRC_I2C_I2C_ENABLED 0x00000001 /* */
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#define NV_PMGR_EVENT_I2C 0x0000E05C /* RW-4R */
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#define NV_PMGR_EVENT_I2C_I2C0 0:0 /* RWIVF */
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#define NV_PMGR_EVENT_I2C_I2C0_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_I2C_I2C0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C0_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C0_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_I2C_I2C1 1:1 /* RWIVF */
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#define NV_PMGR_EVENT_I2C_I2C1_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_I2C_I2C1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C1_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C1_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_I2C_I2C2 2:2 /* RWIVF */
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#define NV_PMGR_EVENT_I2C_I2C2_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_I2C_I2C2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C2_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C2_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_I2C_I2C3 3:3 /* RWIVF */
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#define NV_PMGR_EVENT_I2C_I2C3_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_I2C_I2C3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C3_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C3_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_I2C_I2C4 4:4 /* RWIVF */
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#define NV_PMGR_EVENT_I2C_I2C4_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_I2C_I2C4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C4_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C4_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_I2C_I2C5 5:5 /* RWIVF */
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#define NV_PMGR_EVENT_I2C_I2C5_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_I2C_I2C5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C5_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C5_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_I2C_I2C6 6:6 /* RWIVF */
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#define NV_PMGR_EVENT_I2C_I2C6_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_I2C_I2C6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C6_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C6_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_I2C_I2C7 7:7 /* RWIVF */
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#define NV_PMGR_EVENT_I2C_I2C7_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_I2C_I2C7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C7_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C7_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_I2C_I2C8 8:8 /* RWIVF */
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#define NV_PMGR_EVENT_I2C_I2C8_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_I2C_I2C8_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C8_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C8_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_I2C_I2C9 9:9 /* RWIVF */
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#define NV_PMGR_EVENT_I2C_I2C9_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_I2C_I2C9_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C9_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_I2C_I2C9_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_I2C_I2C(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_EVENT_I2C_I2C__SIZE_1 10 /* */
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#define NV_PMGR_EVENT_I2C_I2C_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_EVENT_I2C_I2C_PENDING 0x00000001 /* */
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#define NV_PMGR_EVENT_I2C_I2C_RESET 0x00000001 /* */
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#define NV_PMGR_EVENT_FRC_DAC 0x0000E060 /* RW-4R */
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#define NV_PMGR_EVENT_FRC_DAC_DAC0 0:0 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_DAC_DAC0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_DAC_DAC0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_DAC_DAC0_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_DAC_DAC1 1:1 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_DAC_DAC1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_DAC_DAC1_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_DAC_DAC1_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_DAC_DAC2 2:2 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_DAC_DAC2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_DAC_DAC2_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_DAC_DAC2_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_DAC_DAC3 3:3 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_DAC_DAC3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_DAC_DAC3_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_DAC_DAC3_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_DAC_DAC(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_EVENT_FRC_DAC_DAC__SIZE_1 4 /* */
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#define NV_PMGR_EVENT_FRC_DAC_DAC_DISABLED 0x00000000 /* */
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#define NV_PMGR_EVENT_FRC_DAC_DAC_ENABLED 0x00000001 /* */
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#define NV_PMGR_EVENT_DAC 0x0000E064 /* RW-4R */
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#define NV_PMGR_EVENT_DAC_DAC0 0:0 /* RWIVF */
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#define NV_PMGR_EVENT_DAC_DAC0_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_DAC_DAC0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_DAC_DAC0_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_DAC_DAC0_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_DAC_DAC1 1:1 /* RWIVF */
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#define NV_PMGR_EVENT_DAC_DAC1_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_DAC_DAC1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_DAC_DAC1_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_DAC_DAC1_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_DAC_DAC2 2:2 /* RWIVF */
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#define NV_PMGR_EVENT_DAC_DAC2_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_DAC_DAC2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_DAC_DAC2_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_DAC_DAC2_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_DAC_DAC3 3:3 /* RWIVF */
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#define NV_PMGR_EVENT_DAC_DAC3_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_DAC_DAC3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_DAC_DAC3_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_DAC_DAC3_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_DAC_DAC(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_EVENT_DAC_DAC__SIZE_1 4 /* */
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#define NV_PMGR_EVENT_DAC_DAC_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_EVENT_DAC_DAC_PENDING 0x00000001 /* */
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#define NV_PMGR_EVENT_DAC_DAC_RESET 0x00000001 /* */
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#define NV_PMGR_EVENT_FRC_AUX 0x0000E068 /* RW-4R */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_PLUG_EVENT 0:0 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_PLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_UNPLUG_EVENT 1:1 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_UNPLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_IRQ_EVENT 2:2 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_IRQ_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_AUX_DONE 3:3 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX0_AUX_DONE_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_PLUG_EVENT 4:4 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_PLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_UNPLUG_EVENT 5:5 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_UNPLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_IRQ_EVENT 6:6 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_IRQ_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_AUX_DONE 7:7 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX1_AUX_DONE_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_PLUG_EVENT 8:8 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_PLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_UNPLUG_EVENT 9:9 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_UNPLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_IRQ_EVENT 10:10 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_IRQ_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_AUX_DONE 11:11 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX2_AUX_DONE_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_PLUG_EVENT 12:12 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_PLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_UNPLUG_EVENT 13:13 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_UNPLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_IRQ_EVENT 14:14 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_IRQ_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_AUX_DONE 15:15 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX3_AUX_DONE_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_PLUG_EVENT 16:16 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_PLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_UNPLUG_EVENT 17:17 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_UNPLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_IRQ_EVENT 18:18 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_IRQ_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_AUX_DONE 19:19 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX4_AUX_DONE_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_PLUG_EVENT 20:20 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_PLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_UNPLUG_EVENT 21:21 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_UNPLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_IRQ_EVENT 22:22 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_IRQ_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_AUX_DONE 23:23 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX5_AUX_DONE_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_PLUG_EVENT 24:24 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_PLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_UNPLUG_EVENT 25:25 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_UNPLUG_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_IRQ_EVENT 26:26 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_IRQ_EVENT_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_AUX_DONE 27:27 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX6_AUX_DONE_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_PLUG_EVENT(i) (0+(i)*4):(0+(i)*4) /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_PLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_PLUG_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_PLUG_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_UNPLUG_EVENT(i) (1+(i)*4):(1+(i)*4) /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_UNPLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_UNPLUG_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_UNPLUG_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_IRQ_EVENT(i) (2+(i)*4):(2+(i)*4) /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_IRQ_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_IRQ_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_IRQ_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_AUX_DONE(i) (3+(i)*4):(3+(i)*4) /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_AUX_DONE__SIZE_1 7 /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_AUX_DONE_DISABLED 0x00000000 /* */
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#define NV_PMGR_EVENT_FRC_AUX_AUX_AUX_DONE_ENABLED 0x00000001 /* */
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#define NV_PMGR_EVENT_AUX 0x0000E06C /* RW-4R */
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#define NV_PMGR_EVENT_AUX_AUX0_PLUG_EVENT 0:0 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX0_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX0_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX0_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX0_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX0_UNPLUG_EVENT 1:1 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX0_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX0_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX0_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX0_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX0_IRQ_EVENT 2:2 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX0_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX0_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX0_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX0_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX0_AUX_DONE 3:3 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX0_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX0_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX0_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX0_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX1_PLUG_EVENT 4:4 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX1_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX1_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX1_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX1_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX1_UNPLUG_EVENT 5:5 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX1_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX1_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX1_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX1_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX1_IRQ_EVENT 6:6 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX1_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX1_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX1_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX1_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX1_AUX_DONE 7:7 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX1_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX1_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX1_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX1_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX2_PLUG_EVENT 8:8 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX2_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX2_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX2_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX2_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX2_UNPLUG_EVENT 9:9 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX2_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX2_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX2_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX2_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX2_IRQ_EVENT 10:10 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX2_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX2_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX2_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX2_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX2_AUX_DONE 11:11 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX2_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX2_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX2_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX2_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX3_PLUG_EVENT 12:12 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX3_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX3_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX3_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX3_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX3_UNPLUG_EVENT 13:13 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX3_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX3_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX3_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX3_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX3_IRQ_EVENT 14:14 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX3_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX3_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX3_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX3_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX3_AUX_DONE 15:15 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX3_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX3_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX3_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX3_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX4_PLUG_EVENT 16:16 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX4_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX4_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX4_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX4_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX4_UNPLUG_EVENT 17:17 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX4_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX4_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX4_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX4_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX4_IRQ_EVENT 18:18 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX4_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX4_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX4_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX4_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX4_AUX_DONE 19:19 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX4_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX4_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX4_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX4_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX5_PLUG_EVENT 20:20 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX5_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX5_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX5_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX5_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX5_UNPLUG_EVENT 21:21 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX5_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX5_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX5_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX5_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX5_IRQ_EVENT 22:22 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX5_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX5_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX5_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX5_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX5_AUX_DONE 23:23 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX5_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX5_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX5_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX5_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX6_PLUG_EVENT 24:24 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX6_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX6_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX6_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX6_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX6_UNPLUG_EVENT 25:25 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX6_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX6_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX6_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX6_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX6_IRQ_EVENT 26:26 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX6_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX6_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX6_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX6_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX6_AUX_DONE 27:27 /* RWIVF */
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#define NV_PMGR_EVENT_AUX_AUX6_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_AUX_AUX6_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX6_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_AUX_AUX6_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_AUX_AUX_PLUG_EVENT(i) (0+(i)*4):(0+(i)*4) /* */
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#define NV_PMGR_EVENT_AUX_AUX_PLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_EVENT_AUX_AUX_PLUG_EVENT_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_EVENT_AUX_AUX_PLUG_EVENT_PENDING 0x00000001 /* */
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#define NV_PMGR_EVENT_AUX_AUX_PLUG_EVENT_RESET 0x00000001 /* */
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#define NV_PMGR_EVENT_AUX_AUX_UNPLUG_EVENT(i) (1+(i)*4):(1+(i)*4) /* */
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#define NV_PMGR_EVENT_AUX_AUX_UNPLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_EVENT_AUX_AUX_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_EVENT_AUX_AUX_UNPLUG_EVENT_PENDING 0x00000001 /* */
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#define NV_PMGR_EVENT_AUX_AUX_UNPLUG_EVENT_RESET 0x00000001 /* */
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#define NV_PMGR_EVENT_AUX_AUX_IRQ_EVENT(i) (2+(i)*4):(2+(i)*4) /* */
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#define NV_PMGR_EVENT_AUX_AUX_IRQ_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_EVENT_AUX_AUX_IRQ_EVENT_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_EVENT_AUX_AUX_IRQ_EVENT_PENDING 0x00000001 /* */
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#define NV_PMGR_EVENT_AUX_AUX_IRQ_EVENT_RESET 0x00000001 /* */
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#define NV_PMGR_EVENT_AUX_AUX_AUX_DONE(i) (3+(i)*4):(3+(i)*4) /* */
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#define NV_PMGR_EVENT_AUX_AUX_AUX_DONE__SIZE_1 7 /* */
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#define NV_PMGR_EVENT_AUX_AUX_AUX_DONE_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_EVENT_AUX_AUX_AUX_DONE_PENDING 0x00000001 /* */
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#define NV_PMGR_EVENT_AUX_AUX_AUX_DONE_RESET 0x00000001 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2 0x00021608 /* RWI4R */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO16_RISING 0:0 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO16_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO16_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO16_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO17_RISING 1:1 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO17_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO17_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO17_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO18_RISING 2:2 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO18_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO18_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO18_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO19_RISING 3:3 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO19_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO19_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO19_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO20_RISING 4:4 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO20_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO20_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO20_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO21_RISING 5:5 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO21_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO21_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO21_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO22_RISING 6:6 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO22_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO22_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO22_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO23_RISING 7:7 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO23_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO23_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO23_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO24_RISING 8:8 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO24_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO24_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO24_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO25_RISING 9:9 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO25_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO25_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO25_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO26_RISING 10:10 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO26_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO26_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO26_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO27_RISING 11:11 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO27_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO27_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO27_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO28_RISING 12:12 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO28_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO28_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO28_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO29_RISING 13:13 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO29_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO29_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO29_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO30_RISING 14:14 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO30_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO30_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO30_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO31_RISING 15:15 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO31_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO31_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO31_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO16_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO16_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO16_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO16_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO17_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO17_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO17_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO17_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO18_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO18_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO18_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO18_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO19_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO19_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO19_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO19_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO20_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO20_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO20_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO20_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO21_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO21_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO21_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO21_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO22_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO22_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO22_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO22_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO23_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO23_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO23_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO23_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO24_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO24_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO24_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO24_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO25_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO25_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO25_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO25_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO26_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO26_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO26_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO26_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO27_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO27_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO27_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO27_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO28_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO28_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO28_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO28_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO29_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO29_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO29_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO29_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO30_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO30_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO30_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO30_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO31_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO31_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO31_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO31_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_2_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_2 0x0002160C /* RW-4R */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO16_RISING 0:0 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO16_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO16_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO16_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO16_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO17_RISING 1:1 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO17_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO17_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO17_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO17_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO18_RISING 2:2 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO18_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO18_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO18_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO18_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO19_RISING 3:3 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO19_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO19_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO19_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO19_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO20_RISING 4:4 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO20_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO20_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO20_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO20_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO21_RISING 5:5 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO21_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO21_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO21_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO21_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO22_RISING 6:6 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO22_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO22_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO22_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO22_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO23_RISING 7:7 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO23_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO23_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO23_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO23_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO24_RISING 8:8 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO24_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO24_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO24_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO24_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO25_RISING 9:9 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO25_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO25_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO25_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO25_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO26_RISING 10:10 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO26_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO26_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO26_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO26_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO27_RISING 11:11 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO27_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO27_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO27_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO27_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO28_RISING 12:12 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO28_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO28_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO28_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO28_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO29_RISING 13:13 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO29_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO29_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO29_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO29_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO30_RISING 14:14 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO30_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO30_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO30_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO30_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO31_RISING 15:15 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO31_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO31_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO31_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO31_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO_RISING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO_RISING_PENDING 0x00000001 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO_RISING_RESET 0x00000001 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO16_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO16_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO16_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO16_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO16_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO17_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO17_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO17_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO17_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO17_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO18_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO18_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO18_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO18_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO18_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO19_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO19_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO19_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO19_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO19_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO20_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO20_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO20_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO20_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO20_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO21_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO21_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO21_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO21_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO21_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO22_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO22_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO22_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO22_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO22_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO23_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO23_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO23_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO23_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO23_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO24_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO24_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO24_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO24_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO24_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO25_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO25_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO25_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO25_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO25_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO26_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO26_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO26_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO26_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO26_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO27_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO27_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO27_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO27_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO27_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO28_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO28_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO28_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO28_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO28_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO29_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO29_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO29_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO29_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO29_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO30_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO30_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO30_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO30_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO30_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO31_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO31_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO31_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO31_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO31_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO_FALLING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO_FALLING_PENDING 0x00000001 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_2_GPIO_FALLING_RESET 0x00000001 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3 0x00021610 /* RWI4R */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO32_RISING 0:0 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO32_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO32_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO32_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO33_RISING 1:1 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO33_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO33_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO33_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO34_RISING 2:2 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO34_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO34_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO34_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO35_RISING 3:3 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO35_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO35_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO35_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO36_RISING 4:4 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO36_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO36_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO36_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO37_RISING 5:5 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO37_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO37_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO37_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO38_RISING 6:6 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO38_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO38_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO38_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO39_RISING 7:7 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO39_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO39_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO39_RISING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO32_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO32_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO32_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO32_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO33_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO33_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO33_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO33_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO34_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO34_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO34_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO34_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO35_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO35_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO35_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO35_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO36_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO36_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO36_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO36_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO37_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO37_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO37_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO37_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO38_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO38_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO38_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO38_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO39_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO39_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO39_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO39_FALLING_ASSERT 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_3_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST(i) (0x00021600+ (i)*(0x00021608-0x00021600)) /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST__SIZE_1 3 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_RISING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_EVENT_FRC_GPIO_RISING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_RISING_BIT(i) ((i)%16) /* */
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#define NV_GPIO_EVENT_FRC_GPIO_RISING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_FALLING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_EVENT_FRC_GPIO_FALLING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_FALLING_BIT(i) ((i)%16+16) /* */
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#define NV_GPIO_EVENT_FRC_GPIO_FALLING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_EVENT_FRC_GPIO_LIST_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_3 0x00021614 /* RW-4R */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO32_RISING 0:0 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO32_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO32_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO32_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO32_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO33_RISING 1:1 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO33_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO33_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO33_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO33_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO34_RISING 2:2 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO34_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO34_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO34_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO34_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO35_RISING 3:3 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO35_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO35_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO35_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO35_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO36_RISING 4:4 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO36_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO36_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO36_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO36_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO37_RISING 5:5 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO37_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO37_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO37_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO37_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO38_RISING 6:6 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO38_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO38_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO38_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO38_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO39_RISING 7:7 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO39_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO39_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO39_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO39_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO_RISING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO_RISING_PENDING 0x00000001 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO_RISING_RESET 0x00000001 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO32_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO32_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO32_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO32_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO32_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO33_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO33_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO33_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO33_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO33_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO34_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO34_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO34_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO34_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO34_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO35_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO35_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO35_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO35_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO35_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO36_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO36_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO36_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO36_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO36_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO37_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO37_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO37_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO37_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO37_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO38_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO38_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO38_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO38_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO38_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO39_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO39_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO39_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO39_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO39_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO_FALLING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO_FALLING_PENDING 0x00000001 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_3_GPIO_FALLING_RESET 0x00000001 /* */
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#define NV_GPIO_EVENT_GPIO_LIST(i) (0x00021604+ (i)*(0x0002160C-0x00021604)) /* */
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#define NV_GPIO_EVENT_GPIO_LIST__SIZE_1 3 /* */
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#define NV_GPIO_EVENT_GPIO_RISING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_EVENT_GPIO_RISING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_EVENT_GPIO_RISING_BIT(i) ((i)%16) /* */
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#define NV_GPIO_EVENT_GPIO_RISING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_EVENT_GPIO_FALLING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_EVENT_GPIO_FALLING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_EVENT_GPIO_FALLING_BIT(i) ((i)%16+16) /* */
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#define NV_GPIO_EVENT_GPIO_FALLING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_EVENT_GPIO_LIST_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_PMGR_EVENT_FRC_SPI 0x0000E078 /* RW-4R */
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#define NV_PMGR_EVENT_FRC_SPI_SPI0 0:0 /* RWIVF */
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#define NV_PMGR_EVENT_FRC_SPI_SPI0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_EVENT_FRC_SPI_SPI0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_EVENT_FRC_SPI_SPI0_ASSERT 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_FRC_SPI_SPI(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_EVENT_FRC_SPI_SPI__SIZE_1 1 /* */
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#define NV_PMGR_EVENT_FRC_SPI_SPI_DISABLED 0x00000000 /* */
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#define NV_PMGR_EVENT_FRC_SPI_SPI_ENABLED 0x00000001 /* */
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#define NV_PMGR_EVENT_SPI 0x0000E07C /* RW-4R */
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#define NV_PMGR_EVENT_SPI_SPI0 0:0 /* RWIVF */
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#define NV_PMGR_EVENT_SPI_SPI0_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_EVENT_SPI_SPI0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_EVENT_SPI_SPI0_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_EVENT_SPI_SPI0_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_EVENT_SPI_SPI(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_EVENT_SPI_SPI__SIZE_1 1 /* */
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#define NV_PMGR_EVENT_SPI_SPI_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_EVENT_SPI_SPI_PENDING 0x00000001 /* */
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#define NV_PMGR_EVENT_SPI_SPI_RESET 0x00000001 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1 0x00021640 /* RW-4R */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO0_RISING 0:0 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO0_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO0_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO0_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO0_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO1_RISING 1:1 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO1_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO1_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO1_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO1_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO2_RISING 2:2 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO2_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO2_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO2_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO2_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO3_RISING 3:3 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO3_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO3_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO3_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO3_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO4_RISING 4:4 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO4_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO4_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO4_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO4_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO5_RISING 5:5 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO5_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO5_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO5_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO5_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO6_RISING 6:6 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO6_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO6_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO6_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO6_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO7_RISING 7:7 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO7_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO7_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO7_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO7_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO8_RISING 8:8 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO8_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO8_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO8_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO8_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO9_RISING 9:9 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO9_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO9_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO9_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO9_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO10_RISING 10:10 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO10_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO10_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO10_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO10_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO11_RISING 11:11 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO11_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO11_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO11_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO11_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO12_RISING 12:12 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO12_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO12_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO12_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO12_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO13_RISING 13:13 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO13_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO13_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO13_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO13_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO14_RISING 14:14 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO14_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO14_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO14_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO14_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO15_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO15_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO15_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO_RISING(i) (0+(i)):(0+(i)) /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO_RISING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO_RISING_PENDING 0x00000001 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO_RISING_RESET 0x00000001 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO0_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO0_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO0_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO0_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO0_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO1_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO1_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO1_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO1_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO1_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO2_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO2_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO2_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO2_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO2_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO3_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO3_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO3_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO3_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO3_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO4_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO4_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO4_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO4_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO4_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO5_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO5_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO5_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO5_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO5_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO6_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO6_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO6_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO6_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO6_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO7_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO7_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO7_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO7_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO7_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO8_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO8_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO8_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO8_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO8_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO9_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO9_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO9_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO9_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO9_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO10_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO10_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO10_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO10_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO10_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO11_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO11_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO11_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO11_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO11_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO12_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO12_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO12_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO12_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO12_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO13_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO13_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO13_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO13_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO13_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO14_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO14_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO14_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO14_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO14_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO15_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO15_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO15_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO_FALLING(i) (16+(i)):(16+(i)) /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO_FALLING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO_FALLING_PENDING 0x00000001 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_1_GPIO_FALLING_RESET 0x00000001 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1 0x00021644 /* RWI4R */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO0_RISING 0:0 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO0_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO0_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO0_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO1_RISING 1:1 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO1_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO1_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO1_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO2_RISING 2:2 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO2_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO2_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO2_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO3_RISING 3:3 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO3_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO3_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO3_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO4_RISING 4:4 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO4_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO4_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO4_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO5_RISING 5:5 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO5_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO5_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO5_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO6_RISING 6:6 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO6_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO6_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO6_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO7_RISING 7:7 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO7_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO7_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO7_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO8_RISING 8:8 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO8_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO8_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO8_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO9_RISING 9:9 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO9_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO9_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO9_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO10_RISING 10:10 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO10_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO10_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO10_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO11_RISING 11:11 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO11_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO11_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO11_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO12_RISING 12:12 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO12_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO12_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO12_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO13_RISING 13:13 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO13_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO13_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO13_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO14_RISING 14:14 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO14_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO14_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO14_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO_RISING(i) (0+(i)):(0+(i)) /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO0_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO0_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO0_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO0_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO1_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO1_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO1_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO1_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO2_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO2_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO2_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO2_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO3_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO3_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO3_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO3_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO4_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO4_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO4_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO4_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO5_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO5_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO5_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO5_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO6_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO6_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO6_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO6_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO7_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO7_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO7_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO7_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO8_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO8_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO8_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO8_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO9_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO9_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO9_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO9_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO10_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO10_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO10_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO10_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO11_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO11_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO11_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO11_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO12_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO12_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO12_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO12_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO13_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO13_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO13_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO13_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO14_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO14_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO14_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO14_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO_FALLING(i) (16+(i)):(16+(i)) /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_1_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1 0x00021648 /* RWI4R */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO0_RISING 0:0 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO0_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO0_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO0_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO1_RISING 1:1 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO1_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO1_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO1_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO2_RISING 2:2 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO2_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO2_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO2_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO3_RISING 3:3 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO3_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO3_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO3_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO4_RISING 4:4 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO4_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO4_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO4_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO5_RISING 5:5 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO5_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO5_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO5_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO6_RISING 6:6 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO6_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO6_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO6_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO7_RISING 7:7 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO7_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO7_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO7_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO8_RISING 8:8 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO8_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO8_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO8_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO9_RISING 9:9 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO9_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO9_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO9_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO10_RISING 10:10 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO10_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO10_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO10_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO11_RISING 11:11 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO11_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO11_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO11_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO12_RISING 12:12 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO12_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO12_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO12_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO13_RISING 13:13 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO13_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO13_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO13_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO14_RISING 14:14 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO14_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO14_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO14_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO15_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO15_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO_RISING(i) (0+(i)):(0+(i)) /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO0_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO0_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO0_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO0_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO1_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO1_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO1_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO1_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO2_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO2_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO2_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO2_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO3_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO3_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO3_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO3_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO4_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO4_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO4_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO4_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO5_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO5_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO5_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO5_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO6_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO6_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO6_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO6_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO7_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO7_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO7_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO7_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO8_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO8_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO8_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO8_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO9_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO9_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO9_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO9_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO10_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO10_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO10_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO10_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO11_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO11_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO11_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO11_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO12_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO12_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO12_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO12_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO13_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO13_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO13_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO13_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO14_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO14_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO14_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO14_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO15_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO15_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO_FALLING(i) (16+(i)):(16+(i)) /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_1_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_I2C 0x0000DC20 /* RW-4R */
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#define NV_PMGR_RM_INTR_I2C_I2C0 0:0 /* RWIVF */
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#define NV_PMGR_RM_INTR_I2C_I2C0_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_I2C_I2C0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C0_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C0_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_I2C_I2C1 1:1 /* RWIVF */
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#define NV_PMGR_RM_INTR_I2C_I2C1_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_I2C_I2C1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C1_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C1_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_I2C_I2C2 2:2 /* RWIVF */
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#define NV_PMGR_RM_INTR_I2C_I2C2_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_I2C_I2C2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C2_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C2_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_I2C_I2C3 3:3 /* RWIVF */
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#define NV_PMGR_RM_INTR_I2C_I2C3_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_I2C_I2C3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C3_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C3_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_I2C_I2C4 4:4 /* RWIVF */
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#define NV_PMGR_RM_INTR_I2C_I2C4_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_I2C_I2C4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C4_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C4_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_I2C_I2C5 5:5 /* RWIVF */
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#define NV_PMGR_RM_INTR_I2C_I2C5_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_I2C_I2C5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C5_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C5_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_I2C_I2C6 6:6 /* RWIVF */
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#define NV_PMGR_RM_INTR_I2C_I2C6_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_I2C_I2C6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C6_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C6_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_I2C_I2C7 7:7 /* RWIVF */
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#define NV_PMGR_RM_INTR_I2C_I2C7_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_I2C_I2C7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C7_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C7_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_I2C_I2C8 8:8 /* RWIVF */
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#define NV_PMGR_RM_INTR_I2C_I2C8_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_I2C_I2C8_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C8_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C8_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_I2C_I2C9 9:9 /* RWIVF */
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#define NV_PMGR_RM_INTR_I2C_I2C9_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_I2C_I2C9_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C9_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_I2C_I2C9_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_I2C_I2C(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_RM_INTR_I2C_I2C__SIZE_1 10 /* */
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#define NV_PMGR_RM_INTR_I2C_I2C_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_RM_INTR_I2C_I2C_PENDING 0x00000001 /* */
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#define NV_PMGR_RM_INTR_I2C_I2C_RESET 0x00000001 /* */
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#define NV_PMGR_RM_INTR_MSK_I2C 0x0000DC24 /* RW-4R */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C0 0:0 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C0_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C0_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C0_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C1 1:1 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C1_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C1_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C1_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C2 2:2 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C2_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C2_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C2_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C3 3:3 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C3_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C3_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C3_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C4 4:4 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C4_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C4_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C4_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C5 5:5 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C5_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C5_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C5_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C6 6:6 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C6_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C6_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C6_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C7 7:7 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C7_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C7_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C7_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C8 8:8 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C8_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C8_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C8_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C9 9:9 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C9_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C9_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C9_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C__SIZE_1 10 /* */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_MSK_I2C_I2C_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_EN_I2C 0x0000DC28 /* RW-4R */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C0 0:0 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C0_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C0_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C1 1:1 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C1_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C1_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C2 2:2 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C2_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C2_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C3 3:3 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C3_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C3_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C4 4:4 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C4_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C4_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C4_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C5 5:5 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C5_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C5_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C5_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C6 6:6 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C6_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C6_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C6_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C7 7:7 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C7_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C7_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C7_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C8 8:8 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C8_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C8_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C8_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C9 9:9 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C9_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C9_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C9_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C__SIZE_1 10 /* */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_EN_I2C_I2C_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_DAC 0x0000DC40 /* RW-4R */
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#define NV_PMGR_RM_INTR_DAC_DAC0 0:0 /* RWIVF */
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#define NV_PMGR_RM_INTR_DAC_DAC0_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_DAC_DAC0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_DAC_DAC0_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_DAC_DAC0_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_DAC_DAC1 1:1 /* RWIVF */
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#define NV_PMGR_RM_INTR_DAC_DAC1_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_DAC_DAC1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_DAC_DAC1_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_DAC_DAC1_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_DAC_DAC2 2:2 /* RWIVF */
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#define NV_PMGR_RM_INTR_DAC_DAC2_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_DAC_DAC2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_DAC_DAC2_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_DAC_DAC2_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_DAC_DAC3 3:3 /* RWIVF */
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#define NV_PMGR_RM_INTR_DAC_DAC3_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_DAC_DAC3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_DAC_DAC3_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_DAC_DAC3_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_DAC_DAC(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_RM_INTR_DAC_DAC__SIZE_1 4 /* */
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#define NV_PMGR_RM_INTR_DAC_DAC_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_RM_INTR_DAC_DAC_PENDING 0x00000001 /* */
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#define NV_PMGR_RM_INTR_DAC_DAC_RESET 0x00000001 /* */
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#define NV_PMGR_RM_INTR_MSK_DAC 0x0000DC44 /* RW-4R */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC0 0:0 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC0_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC0_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC0_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC1 1:1 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC1_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC1_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC1_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC2 2:2 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC2_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC2_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC2_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC3 3:3 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC3_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC3_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC3_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC__SIZE_1 4 /* */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_MSK_DAC_DAC_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_EN_DAC 0x0000DC48 /* RW-4R */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC0 0:0 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC0_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC0_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC1 1:1 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC1_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC1_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC2 2:2 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC2_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC2_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC3 3:3 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC3_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC3_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC__SIZE_1 4 /* */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_EN_DAC_DAC_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_AUX 0x0000DC60 /* RW-4R */
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#define NV_PMGR_RM_INTR_AUX_AUX0_PLUG_EVENT 0:0 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX0_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_UNPLUG_EVENT 1:1 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX0_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_IRQ_EVENT 2:2 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX0_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_AUX_DONE 3:3 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX0_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX0_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_PLUG_EVENT 4:4 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX1_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_UNPLUG_EVENT 5:5 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX1_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_IRQ_EVENT 6:6 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX1_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_AUX_DONE 7:7 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX1_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX1_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_PLUG_EVENT 8:8 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX2_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_UNPLUG_EVENT 9:9 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX2_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_IRQ_EVENT 10:10 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX2_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_AUX_DONE 11:11 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX2_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX2_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_PLUG_EVENT 12:12 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX3_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_UNPLUG_EVENT 13:13 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX3_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_IRQ_EVENT 14:14 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX3_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_AUX_DONE 15:15 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX3_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX3_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_PLUG_EVENT 16:16 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX4_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_UNPLUG_EVENT 17:17 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX4_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_IRQ_EVENT 18:18 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX4_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_AUX_DONE 19:19 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX4_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX4_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_PLUG_EVENT 20:20 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX5_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_UNPLUG_EVENT 21:21 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX5_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_IRQ_EVENT 22:22 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX5_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_AUX_DONE 23:23 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX5_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX5_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_PLUG_EVENT 24:24 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX6_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_UNPLUG_EVENT 25:25 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX6_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_IRQ_EVENT 26:26 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX6_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_AUX_DONE 27:27 /* RWIVF */
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#define NV_PMGR_RM_INTR_AUX_AUX6_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_AUX_AUX6_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_AUX_AUX_PLUG_EVENT(i) (0+(i)*4):(0+(i)*4) /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_PLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_PLUG_EVENT_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_PLUG_EVENT_PENDING 0x00000001 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_PLUG_EVENT_RESET 0x00000001 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_UNPLUG_EVENT(i) (1+(i)*4):(1+(i)*4) /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_UNPLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_UNPLUG_EVENT_PENDING 0x00000001 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_UNPLUG_EVENT_RESET 0x00000001 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_IRQ_EVENT(i) (2+(i)*4):(2+(i)*4) /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_IRQ_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_IRQ_EVENT_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_IRQ_EVENT_PENDING 0x00000001 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_IRQ_EVENT_RESET 0x00000001 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_AUX_DONE(i) (3+(i)*4):(3+(i)*4) /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_AUX_DONE__SIZE_1 7 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_AUX_DONE_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_AUX_DONE_PENDING 0x00000001 /* */
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#define NV_PMGR_RM_INTR_AUX_AUX_AUX_DONE_RESET 0x00000001 /* */
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#define NV_PMGR_RM_INTR_MSK_AUX 0x0000DC64 /* RW-4R */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_PLUG_EVENT 0:0 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_PLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_UNPLUG_EVENT 1:1 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_UNPLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_IRQ_EVENT 2:2 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_IRQ_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_AUX_DONE 3:3 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_AUX_DONE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX0_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_PLUG_EVENT 4:4 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_PLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_UNPLUG_EVENT 5:5 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_UNPLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_IRQ_EVENT 6:6 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_IRQ_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_AUX_DONE 7:7 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_AUX_DONE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX1_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_PLUG_EVENT 8:8 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_PLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_UNPLUG_EVENT 9:9 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_UNPLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_IRQ_EVENT 10:10 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_IRQ_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_AUX_DONE 11:11 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_AUX_DONE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX2_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_PLUG_EVENT 12:12 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_PLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_UNPLUG_EVENT 13:13 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_UNPLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_IRQ_EVENT 14:14 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_IRQ_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_AUX_DONE 15:15 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_AUX_DONE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX3_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_PLUG_EVENT 16:16 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_PLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_UNPLUG_EVENT 17:17 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_UNPLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_IRQ_EVENT 18:18 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_IRQ_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_AUX_DONE 19:19 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_AUX_DONE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX4_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_PLUG_EVENT 20:20 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_PLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_UNPLUG_EVENT 21:21 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_UNPLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_IRQ_EVENT 22:22 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_IRQ_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_AUX_DONE 23:23 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_AUX_DONE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX5_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_PLUG_EVENT 24:24 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_PLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_UNPLUG_EVENT 25:25 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_UNPLUG_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_IRQ_EVENT 26:26 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_IRQ_EVENT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_AUX_DONE 27:27 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_AUX_DONE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX6_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_PLUG_EVENT(i) (0+(i)*4):(0+(i)*4) /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_PLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_PLUG_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_PLUG_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_UNPLUG_EVENT(i) (1+(i)*4):(1+(i)*4) /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_UNPLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_UNPLUG_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_UNPLUG_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_IRQ_EVENT(i) (2+(i)*4):(2+(i)*4) /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_IRQ_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_IRQ_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_IRQ_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_AUX_DONE(i) (3+(i)*4):(3+(i)*4) /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_AUX_DONE__SIZE_1 7 /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_AUX_DONE_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_MSK_AUX_AUX_AUX_DONE_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_EN_AUX 0x0000DC68 /* RW-4R */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_PLUG_EVENT 0:0 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_UNPLUG_EVENT 1:1 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_IRQ_EVENT 2:2 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_AUX_DONE 3:3 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX0_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_PLUG_EVENT 4:4 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_UNPLUG_EVENT 5:5 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_IRQ_EVENT 6:6 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_AUX_DONE 7:7 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX1_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_PLUG_EVENT 8:8 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_UNPLUG_EVENT 9:9 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_IRQ_EVENT 10:10 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_AUX_DONE 11:11 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX2_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_PLUG_EVENT 12:12 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_UNPLUG_EVENT 13:13 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_IRQ_EVENT 14:14 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_AUX_DONE 15:15 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX3_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_PLUG_EVENT 16:16 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_UNPLUG_EVENT 17:17 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_IRQ_EVENT 18:18 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_AUX_DONE 19:19 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX4_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_PLUG_EVENT 20:20 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_UNPLUG_EVENT 21:21 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_IRQ_EVENT 22:22 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_AUX_DONE 23:23 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX5_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_PLUG_EVENT 24:24 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_UNPLUG_EVENT 25:25 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_IRQ_EVENT 26:26 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_AUX_DONE 27:27 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX6_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_PLUG_EVENT(i) (0+(i)*4):(0+(i)*4) /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_PLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_PLUG_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_PLUG_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_UNPLUG_EVENT(i) (1+(i)*4):(1+(i)*4) /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_UNPLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_UNPLUG_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_UNPLUG_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_IRQ_EVENT(i) (2+(i)*4):(2+(i)*4) /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_IRQ_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_IRQ_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_IRQ_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_AUX_DONE(i) (3+(i)*4):(3+(i)*4) /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_AUX_DONE__SIZE_1 7 /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_AUX_DONE_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_EN_AUX_AUX_AUX_DONE_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2 0x0002164C /* RW-4R */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO16_RISING 0:0 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO16_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO16_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO16_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO16_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO17_RISING 1:1 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO17_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO17_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO17_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO17_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO18_RISING 2:2 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO18_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO18_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO18_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO18_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO19_RISING 3:3 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO19_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO19_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO19_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO19_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO20_RISING 4:4 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO20_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO20_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO20_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO20_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO21_RISING 5:5 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO21_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO21_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO21_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO21_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO22_RISING 6:6 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO22_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO22_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO22_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO22_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO23_RISING 7:7 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO23_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO23_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO23_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO23_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO24_RISING 8:8 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO24_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO24_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO24_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO24_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO25_RISING 9:9 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO25_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO25_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO25_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO25_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO26_RISING 10:10 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO26_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO26_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO26_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO26_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO27_RISING 11:11 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO27_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO27_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO27_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO27_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO28_RISING 12:12 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO28_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO28_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO28_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO28_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO29_RISING 13:13 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO29_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO29_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO29_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO29_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO30_RISING 14:14 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO30_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO30_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO30_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO30_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO31_RISING 15:15 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO31_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO31_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO31_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO31_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO_RISING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO_RISING_PENDING 0x00000001 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO_RISING_RESET 0x00000001 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO16_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO16_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO16_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO16_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO16_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO17_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO17_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO17_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO17_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO17_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO18_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO18_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO18_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO18_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO18_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO19_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO19_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO19_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO19_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO19_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO20_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO20_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO20_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO20_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO20_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO21_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO21_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO21_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO21_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO21_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO22_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO22_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO22_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO22_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO22_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO23_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO23_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO23_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO23_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO23_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO24_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO24_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO24_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO24_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO24_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO25_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO25_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO25_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO25_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO25_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO26_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO26_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO26_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO26_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO26_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO27_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO27_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO27_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO27_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO27_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO28_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO28_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO28_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO28_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO28_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO29_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO29_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO29_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO29_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO29_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO30_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO30_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO30_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO30_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO30_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO31_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO31_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO31_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO31_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO31_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO_FALLING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO_FALLING_PENDING 0x00000001 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_2_GPIO_FALLING_RESET 0x00000001 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2 0x00021650 /* RWI4R */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO16_RISING 0:0 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO16_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO16_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO16_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO17_RISING 1:1 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO17_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO17_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO17_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO18_RISING 2:2 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO18_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO18_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO18_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO19_RISING 3:3 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO19_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO19_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO19_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO20_RISING 4:4 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO20_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO20_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO20_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO21_RISING 5:5 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO21_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO21_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO21_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO22_RISING 6:6 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO22_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO22_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO22_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO23_RISING 7:7 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO23_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO23_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO23_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO24_RISING 8:8 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO24_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO24_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO24_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO25_RISING 9:9 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO25_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO25_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO25_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO26_RISING 10:10 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO26_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO26_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO26_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO27_RISING 11:11 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO27_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO27_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO27_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO28_RISING 12:12 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO28_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO28_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO28_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO29_RISING 13:13 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO29_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO29_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO29_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO30_RISING 14:14 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO30_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO30_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO30_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO31_RISING 15:15 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO31_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO31_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO31_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO16_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO16_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO16_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO16_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO17_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO17_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO17_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO17_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO18_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO18_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO18_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO18_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO19_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO19_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO19_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO19_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO20_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO20_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO20_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO20_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO21_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO21_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO21_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO21_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO22_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO22_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO22_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO22_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO23_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO23_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO23_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO23_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO24_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO24_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO24_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO24_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO25_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO25_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO25_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO25_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO26_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO26_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO26_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO26_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO27_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO27_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO27_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO27_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO28_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO28_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO28_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO28_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO29_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO29_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO29_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO29_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO30_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO30_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO30_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO30_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO31_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO31_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO31_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO31_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_2_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2 0x00021654 /* RWI4R */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO16_RISING 0:0 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO16_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO16_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO16_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO17_RISING 1:1 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO17_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO17_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO17_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO18_RISING 2:2 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO18_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO18_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO18_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO19_RISING 3:3 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO19_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO19_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO19_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO20_RISING 4:4 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO20_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO20_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO20_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO21_RISING 5:5 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO21_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO21_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO21_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO22_RISING 6:6 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO22_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO22_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO22_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO23_RISING 7:7 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO23_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO23_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO23_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO24_RISING 8:8 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO24_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO24_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO24_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO25_RISING 9:9 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO25_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO25_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO25_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO26_RISING 10:10 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO26_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO26_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO26_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO27_RISING 11:11 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO27_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO27_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO27_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO28_RISING 12:12 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO28_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO28_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO28_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO29_RISING 13:13 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO29_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO29_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO29_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO30_RISING 14:14 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO30_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO30_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO30_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO31_RISING 15:15 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO31_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO31_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO31_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO16_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO16_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO16_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO16_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO17_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO17_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO17_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO17_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO18_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO18_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO18_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO18_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO19_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO19_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO19_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO19_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO20_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO20_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO20_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO20_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO21_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO21_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO21_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO21_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO22_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO22_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO22_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO22_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO23_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO23_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO23_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO23_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO24_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO24_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO24_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO24_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO25_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO25_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO25_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO25_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO26_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO26_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO26_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO26_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO27_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO27_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO27_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO27_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO28_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO28_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO28_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO28_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO29_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO29_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO29_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO29_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO30_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO30_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO30_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO30_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO31_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO31_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO31_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO31_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3 0x00021658 /* RW-4R */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO32_RISING 0:0 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO32_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO32_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO32_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO32_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO33_RISING 1:1 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO33_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO33_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO33_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO33_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO34_RISING 2:2 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO34_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO34_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO34_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO34_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO35_RISING 3:3 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO35_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO35_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO35_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO35_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO36_RISING 4:4 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO36_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO36_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO36_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO36_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO37_RISING 5:5 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO37_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO37_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO37_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO37_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO38_RISING 6:6 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO38_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO38_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO38_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO38_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO39_RISING 7:7 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO39_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO39_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO39_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO39_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO_RISING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO_RISING_PENDING 0x00000001 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO_RISING_RESET 0x00000001 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO32_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO32_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO32_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO32_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO32_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO33_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO33_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO33_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO33_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO33_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO34_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO34_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO34_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO34_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO34_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO35_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO35_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO35_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO35_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO35_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO36_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO36_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO36_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO36_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO36_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO37_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO37_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO37_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO37_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO37_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO38_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO38_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO38_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO38_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO38_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO39_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO39_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO39_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO39_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO39_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO_FALLING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO_FALLING_PENDING 0x00000001 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_3_GPIO_FALLING_RESET 0x00000001 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST(i) (0x00021640+ (i)*(0x0002164C-0x00021640)) /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST__SIZE_1 3 /* */
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#define NV_GPIO_RM_INTR_GPIO_RISING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_RM_INTR_GPIO_RISING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_RM_INTR_GPIO_RISING_BIT(i) ((i)%16) /* */
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#define NV_GPIO_RM_INTR_GPIO_RISING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_RM_INTR_GPIO_FALLING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_RM_INTR_GPIO_FALLING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_RM_INTR_GPIO_FALLING_BIT(i) ((i)%16+16) /* */
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#define NV_GPIO_RM_INTR_GPIO_FALLING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_GPIO_LIST_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3 0x0002165C /* RWI4R */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO32_RISING 0:0 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO32_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO32_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO32_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO33_RISING 1:1 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO33_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO33_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO33_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO34_RISING 2:2 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO34_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO34_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO34_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO35_RISING 3:3 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO35_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO35_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO35_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO36_RISING 4:4 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO36_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO36_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO36_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO37_RISING 5:5 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO37_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO37_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO37_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO38_RISING 6:6 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO38_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO38_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO38_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO39_RISING 7:7 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO39_RISING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO39_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO39_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO32_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO32_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO32_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO32_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO33_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO33_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO33_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO33_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO34_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO34_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO34_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO34_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO35_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO35_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO35_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO35_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO36_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO36_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO36_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO36_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO37_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO37_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO37_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO37_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO38_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO38_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO38_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO38_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO39_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO39_FALLING_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO39_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO39_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_3_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST(i) (0x00021644+ (i)*(0x00021650-0x00021644)) /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST__SIZE_1 3 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_RISING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_RISING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_RISING_BIT(i) ((i)%16) /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_RISING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_FALLING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_FALLING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_FALLING_BIT(i) ((i)%16+16) /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_FALLING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_MSK_GPIO_LIST_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3 0x00021660 /* RWI4R */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO32_RISING 0:0 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO32_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO32_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO32_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO33_RISING 1:1 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO33_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO33_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO33_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO34_RISING 2:2 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO34_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO34_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO34_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO35_RISING 3:3 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO35_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO35_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO35_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO36_RISING 4:4 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO36_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO36_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO36_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO37_RISING 5:5 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO37_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO37_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO37_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO38_RISING 6:6 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO38_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO38_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO38_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO39_RISING 7:7 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO39_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO39_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO39_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO32_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO32_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO32_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO32_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO33_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO33_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO33_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO33_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO34_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO34_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO34_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO34_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO35_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO35_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO35_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO35_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO36_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO36_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO36_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO36_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO37_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO37_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO37_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO37_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO38_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO38_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO38_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO38_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO39_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO39_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO39_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO39_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_3_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST(i) (0x00021648+ (i)*(0x00021654-0x00021648)) /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST__SIZE_1 3 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_RISING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_RISING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_RISING_BIT(i) ((i)%16) /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_RISING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_FALLING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_FALLING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_FALLING_BIT(i) ((i)%16+16) /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_FALLING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_RM_INTR_EN_GPIO_LIST_2_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_SPI 0x0000DCA0 /* RW-4R */
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#define NV_PMGR_RM_INTR_SPI_SPI0 0:0 /* RWIVF */
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#define NV_PMGR_RM_INTR_SPI_SPI0_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_RM_INTR_SPI_SPI0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_RM_INTR_SPI_SPI0_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_RM_INTR_SPI_SPI0_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_RM_INTR_SPI_SPI(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_RM_INTR_SPI_SPI__SIZE_1 1 /* */
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#define NV_PMGR_RM_INTR_SPI_SPI_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_RM_INTR_SPI_SPI_PENDING 0x00000001 /* */
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#define NV_PMGR_RM_INTR_SPI_SPI_RESET 0x00000001 /* */
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#define NV_PMGR_RM_INTR_MSK_SPI 0x0000DCA4 /* RW-4R */
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#define NV_PMGR_RM_INTR_MSK_SPI_SPI0 0:0 /* RWIVF */
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#define NV_PMGR_RM_INTR_MSK_SPI_SPI0_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RM_INTR_MSK_SPI_SPI0_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_SPI_SPI0_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_MSK_SPI_SPI(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_RM_INTR_MSK_SPI_SPI__SIZE_1 1 /* */
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#define NV_PMGR_RM_INTR_MSK_SPI_SPI_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_MSK_SPI_SPI_ENABLED 0x00000001 /* */
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#define NV_PMGR_RM_INTR_EN_SPI 0x0000DCA8 /* RW-4R */
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#define NV_PMGR_RM_INTR_EN_SPI_SPI0 0:0 /* RWIVF */
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#define NV_PMGR_RM_INTR_EN_SPI_SPI0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RM_INTR_EN_SPI_SPI0_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_SPI_SPI0_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_RM_INTR_EN_SPI_SPI(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_RM_INTR_EN_SPI_SPI__SIZE_1 1 /* */
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#define NV_PMGR_RM_INTR_EN_SPI_SPI_DISABLED 0x00000000 /* */
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#define NV_PMGR_RM_INTR_EN_SPI_SPI_ENABLED 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1 0x000216A0 /* RW-4R */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO0_RISING 0:0 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO0_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO0_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO0_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO0_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO1_RISING 1:1 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO1_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO1_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO1_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO1_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO2_RISING 2:2 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO2_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO2_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO2_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO2_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO3_RISING 3:3 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO3_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO3_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO3_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO3_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO4_RISING 4:4 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO4_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO4_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO4_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO4_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO5_RISING 5:5 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO5_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO5_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO5_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO5_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO6_RISING 6:6 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO6_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO6_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO6_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO6_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO7_RISING 7:7 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO7_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO7_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO7_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO7_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO8_RISING 8:8 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO8_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO8_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO8_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO8_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO9_RISING 9:9 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO9_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO9_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO9_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO9_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO10_RISING 10:10 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO10_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO10_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO10_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO10_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO11_RISING 11:11 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO11_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO11_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO11_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO11_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO12_RISING 12:12 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO12_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO12_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO12_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO12_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO13_RISING 13:13 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO13_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO13_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO13_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO13_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO14_RISING 14:14 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO14_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO14_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO14_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO14_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO15_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO15_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO15_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO_RISING(i) (0+(i)):(0+(i)) /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO_RISING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO_RISING_PENDING 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO_RISING_RESET 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO0_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO0_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO0_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO0_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO0_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO1_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO1_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO1_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO1_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO1_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO2_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO2_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO2_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO2_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO2_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO3_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO3_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO3_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO3_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO3_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO4_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO4_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO4_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO4_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO4_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO5_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO5_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO5_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO5_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO5_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO6_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO6_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO6_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO6_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO6_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO7_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO7_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO7_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO7_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO7_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO8_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO8_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO8_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO8_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO8_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO9_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO9_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO9_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO9_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO9_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO10_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO10_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO10_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO10_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO10_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO11_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO11_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO11_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO11_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO11_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO12_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO12_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO12_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO12_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO12_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO13_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO13_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO13_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO13_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO13_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO14_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO14_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO14_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO14_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO14_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO15_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO15_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO15_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO_FALLING(i) (16+(i)):(16+(i)) /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO_FALLING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO_FALLING_PENDING 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_1_GPIO_FALLING_RESET 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1 0x000216A4 /* RWI4R */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO0_RISING 0:0 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO0_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO0_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO0_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO1_RISING 1:1 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO1_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO1_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO1_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO2_RISING 2:2 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO2_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO2_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO2_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO3_RISING 3:3 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO3_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO3_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO3_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO4_RISING 4:4 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO4_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO4_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO4_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO5_RISING 5:5 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO5_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO5_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO5_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO6_RISING 6:6 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO6_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO6_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO6_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO7_RISING 7:7 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO7_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO7_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO7_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO8_RISING 8:8 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO8_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO8_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO8_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO9_RISING 9:9 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO9_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO9_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO9_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO10_RISING 10:10 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO10_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO10_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO10_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO11_RISING 11:11 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO11_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO11_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO11_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO12_RISING 12:12 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO12_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO12_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO12_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO13_RISING 13:13 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO13_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO13_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO13_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO14_RISING 14:14 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO14_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO14_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO14_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO_RISING(i) (0+(i)):(0+(i)) /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO0_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO0_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO0_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO0_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO1_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO1_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO1_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO1_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO2_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO2_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO2_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO2_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO3_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO3_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO3_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO3_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO4_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO4_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO4_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO4_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO5_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO5_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO5_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO5_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO6_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO6_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO6_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO6_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO7_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO7_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO7_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO7_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO8_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO8_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO8_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO8_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO9_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO9_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO9_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO9_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO10_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO10_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO10_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO10_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO11_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO11_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO11_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO11_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO12_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO12_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO12_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO12_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO13_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO13_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO13_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO13_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO14_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO14_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO14_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO14_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO_FALLING(i) (16+(i)):(16+(i)) /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_1_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1 0x000216A8 /* RW-4R */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO0_RISING 0:0 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO0_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO0_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO0_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO1_RISING 1:1 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO1_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO1_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO1_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO2_RISING 2:2 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO2_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO2_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO2_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO3_RISING 3:3 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO3_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO3_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO3_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO4_RISING 4:4 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO4_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO4_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO4_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO5_RISING 5:5 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO5_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO5_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO5_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO6_RISING 6:6 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO6_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO6_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO6_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO7_RISING 7:7 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO7_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO7_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO7_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO8_RISING 8:8 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO8_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO8_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO8_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO9_RISING 9:9 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO9_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO9_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO9_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO10_RISING 10:10 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO10_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO10_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO10_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO11_RISING 11:11 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO11_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO11_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO11_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO12_RISING 12:12 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO12_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO12_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO12_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO13_RISING 13:13 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO13_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO13_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO13_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO14_RISING 14:14 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO14_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO14_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO14_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO15_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO15_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO_RISING(i) (0+(i)):(0+(i)) /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO_RISING_NOP 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO_RISING_FORWARD 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO0_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO0_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO0_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO0_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO1_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO1_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO1_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO1_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO2_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO2_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO2_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO2_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO3_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO3_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO3_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO3_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO4_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO4_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO4_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO4_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO5_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO5_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO5_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO5_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO6_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO6_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO6_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO6_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO7_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO7_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO7_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO7_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO8_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO8_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO8_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO8_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO9_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO9_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO9_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO9_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO10_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO10_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO10_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO10_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO11_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO11_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO11_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO11_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO12_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO12_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO12_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO12_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO13_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO13_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO13_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO13_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO14_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO14_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO14_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO14_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO15_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO15_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO_FALLING(i) (16+(i)):(16+(i)) /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO_FALLING_NOP 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_1_GPIO_FALLING_FORWARD 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1 0x000216AC /* RWI4R */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO0_RISING 0:0 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO0_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO0_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO0_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO1_RISING 1:1 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO1_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO1_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO1_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO2_RISING 2:2 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO2_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO2_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO2_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO3_RISING 3:3 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO3_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO3_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO3_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO4_RISING 4:4 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO4_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO4_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO4_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO5_RISING 5:5 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO5_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO5_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO5_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO6_RISING 6:6 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO6_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO6_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO6_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO7_RISING 7:7 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO7_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO7_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO7_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO8_RISING 8:8 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO8_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO8_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO8_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO9_RISING 9:9 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO9_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO9_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO9_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO10_RISING 10:10 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO10_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO10_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO10_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO11_RISING 11:11 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO11_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO11_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO11_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO12_RISING 12:12 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO12_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO12_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO12_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO13_RISING 13:13 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO13_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO13_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO13_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO14_RISING 14:14 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO14_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO14_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO14_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO15_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO15_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO_RISING(i) (0+(i)):(0+(i)) /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO_RISING_NOP 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO_RISING_FORWARD 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO0_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO0_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO0_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO0_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO1_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO1_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO1_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO1_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO2_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO2_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO2_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO2_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO3_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO3_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO3_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO3_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO4_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO4_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO4_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO4_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO5_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO5_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO5_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO5_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO6_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO6_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO6_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO6_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO7_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO7_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO7_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO7_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO8_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO8_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO8_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO8_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO9_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO9_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO9_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO9_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO10_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO10_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO10_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO10_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO11_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO11_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO11_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO11_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO12_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO12_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO12_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO12_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO13_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO13_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO13_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO13_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO14_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO14_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO14_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO14_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO15_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO15_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO_FALLING(i) (16+(i)):(16+(i)) /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO_FALLING_NOP 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_1_GPIO_FALLING_FORWARD 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_I2C 0x0000DD20 /* RW-4R */
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#define NV_PMGR_PMU_INTR_I2C_I2C0 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_I2C_I2C0_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_I2C_I2C0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C0_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C0_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_I2C_I2C1 1:1 /* RWIVF */
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#define NV_PMGR_PMU_INTR_I2C_I2C1_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_I2C_I2C1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C1_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C1_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_I2C_I2C2 2:2 /* RWIVF */
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#define NV_PMGR_PMU_INTR_I2C_I2C2_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_I2C_I2C2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C2_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C2_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_I2C_I2C3 3:3 /* RWIVF */
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#define NV_PMGR_PMU_INTR_I2C_I2C3_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_I2C_I2C3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C3_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C3_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_I2C_I2C4 4:4 /* RWIVF */
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#define NV_PMGR_PMU_INTR_I2C_I2C4_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_I2C_I2C4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C4_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C4_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_I2C_I2C5 5:5 /* RWIVF */
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#define NV_PMGR_PMU_INTR_I2C_I2C5_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_I2C_I2C5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C5_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C5_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_I2C_I2C6 6:6 /* RWIVF */
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#define NV_PMGR_PMU_INTR_I2C_I2C6_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_I2C_I2C6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C6_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C6_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_I2C_I2C7 7:7 /* RWIVF */
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#define NV_PMGR_PMU_INTR_I2C_I2C7_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_I2C_I2C7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C7_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C7_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_I2C_I2C8 8:8 /* RWIVF */
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#define NV_PMGR_PMU_INTR_I2C_I2C8_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_I2C_I2C8_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C8_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C8_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_I2C_I2C9 9:9 /* RWIVF */
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#define NV_PMGR_PMU_INTR_I2C_I2C9_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_I2C_I2C9_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C9_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_I2C_I2C9_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_I2C_I2C(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_PMU_INTR_I2C_I2C__SIZE_1 10 /* */
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#define NV_PMGR_PMU_INTR_I2C_I2C_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_I2C_I2C_PENDING 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_I2C_I2C_RESET 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_MSK_I2C 0x0000DD24 /* RW-4R */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C0 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C0_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C0_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C1 1:1 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C1_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C1_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C2 2:2 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C2_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C2_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C3 3:3 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C3_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C3_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C4 4:4 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C4_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C4_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C4_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C5 5:5 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C5_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C5_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C5_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C6 6:6 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C6_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C6_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C6_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C7 7:7 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C7_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C7_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C7_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C8 8:8 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C8_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C8_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C8_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C9 9:9 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C9_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C9_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C9_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C__SIZE_1 10 /* */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C_DISABLED 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_MSK_I2C_I2C_ENABLED 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C 0x0000DD28 /* RW-4R */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C0 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C0_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C1 1:1 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C1_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C1_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C2 2:2 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C2_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C2_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C3 3:3 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C3_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C3_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C4 4:4 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C4_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C4_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C4_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C5 5:5 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C5_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C5_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C5_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C6 6:6 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C6_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C6_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C6_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C7 7:7 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C7_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C7_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C7_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C8 8:8 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C8_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C8_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C8_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C9 9:9 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C9_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C9_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C9_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C__SIZE_1 10 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_I2C_I2C_FORWARD 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C 0x0000DD2C /* RW-4R */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C0 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C0_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C1 1:1 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C1_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C1_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C2 2:2 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C2_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C2_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C3 3:3 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C3_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C3_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C4 4:4 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C4_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C4_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C4_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C5 5:5 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C5_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C5_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C5_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C6 6:6 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C6_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C6_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C6_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C7 7:7 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C7_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C7_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C7_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C8 8:8 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C8_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C8_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C8_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C9 9:9 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C9_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C9_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C9_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C__SIZE_1 10 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_I2C_I2C_FORWARD 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_DAC 0x0000DD40 /* RW-4R */
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#define NV_PMGR_PMU_INTR_DAC_DAC0 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_DAC_DAC0_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_DAC_DAC0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_DAC_DAC0_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_DAC_DAC0_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_DAC_DAC1 1:1 /* RWIVF */
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#define NV_PMGR_PMU_INTR_DAC_DAC1_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_DAC_DAC1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_DAC_DAC1_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_DAC_DAC1_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_DAC_DAC2 2:2 /* RWIVF */
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#define NV_PMGR_PMU_INTR_DAC_DAC2_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_DAC_DAC2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_DAC_DAC2_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_DAC_DAC2_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_DAC_DAC3 3:3 /* RWIVF */
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#define NV_PMGR_PMU_INTR_DAC_DAC3_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_DAC_DAC3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_DAC_DAC3_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_DAC_DAC3_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_DAC_DAC(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_PMU_INTR_DAC_DAC__SIZE_1 4 /* */
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#define NV_PMGR_PMU_INTR_DAC_DAC_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_DAC_DAC_PENDING 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_DAC_DAC_RESET 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_MSK_DAC 0x0000DD44 /* RW-4R */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC0 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC0_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC0_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC1 1:1 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC1_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC1_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC2 2:2 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC2_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC2_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC3 3:3 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC3_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC3_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC__SIZE_1 4 /* */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC_DISABLED 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_MSK_DAC_DAC_ENABLED 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC 0x0000DD48 /* RW-4R */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC0 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC0_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC1 1:1 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC1_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC1_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC2 2:2 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC2_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC2_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC3 3:3 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC3_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC3_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC__SIZE_1 4 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_DAC_DAC_FORWARD 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC 0x0000DD4C /* RW-4R */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC0 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC0_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC1 1:1 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC1_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC1_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC2 2:2 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC2_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC2_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC3 3:3 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC3_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC3_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC__SIZE_1 4 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_DAC_DAC_FORWARD 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_AUX 0x0000DD60 /* RW-4R */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_PLUG_EVENT 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_UNPLUG_EVENT 1:1 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_IRQ_EVENT 2:2 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_AUX_DONE 3:3 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX0_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_PLUG_EVENT 4:4 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_UNPLUG_EVENT 5:5 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_IRQ_EVENT 6:6 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_AUX_DONE 7:7 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX1_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_PLUG_EVENT 8:8 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_UNPLUG_EVENT 9:9 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_IRQ_EVENT 10:10 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_AUX_DONE 11:11 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX2_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_PLUG_EVENT 12:12 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_UNPLUG_EVENT 13:13 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_IRQ_EVENT 14:14 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_AUX_DONE 15:15 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX3_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_PLUG_EVENT 16:16 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_UNPLUG_EVENT 17:17 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_IRQ_EVENT 18:18 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_AUX_DONE 19:19 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX4_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_PLUG_EVENT 20:20 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_UNPLUG_EVENT 21:21 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_IRQ_EVENT 22:22 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_AUX_DONE 23:23 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX5_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_PLUG_EVENT 24:24 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_UNPLUG_EVENT 25:25 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_IRQ_EVENT 26:26 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_AUX_DONE 27:27 /* RWIVF */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_AUX_AUX6_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_AUX_AUX_PLUG_EVENT(i) (0+(i)*4):(0+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_PLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_PLUG_EVENT_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_PLUG_EVENT_PENDING 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_PLUG_EVENT_RESET 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_UNPLUG_EVENT(i) (1+(i)*4):(1+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_UNPLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_UNPLUG_EVENT_PENDING 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_UNPLUG_EVENT_RESET 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_IRQ_EVENT(i) (2+(i)*4):(2+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_IRQ_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_IRQ_EVENT_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_IRQ_EVENT_PENDING 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_IRQ_EVENT_RESET 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_AUX_DONE(i) (3+(i)*4):(3+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_AUX_DONE__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_AUX_DONE_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_AUX_DONE_PENDING 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_AUX_AUX_AUX_DONE_RESET 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX 0x0000DD64 /* RW-4R */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_PLUG_EVENT 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_UNPLUG_EVENT 1:1 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_IRQ_EVENT 2:2 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_AUX_DONE 3:3 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX0_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_PLUG_EVENT 4:4 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_UNPLUG_EVENT 5:5 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_IRQ_EVENT 6:6 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_AUX_DONE 7:7 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX1_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_PLUG_EVENT 8:8 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_UNPLUG_EVENT 9:9 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_IRQ_EVENT 10:10 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_AUX_DONE 11:11 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX2_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_PLUG_EVENT 12:12 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_UNPLUG_EVENT 13:13 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_IRQ_EVENT 14:14 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_AUX_DONE 15:15 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX3_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_PLUG_EVENT 16:16 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_UNPLUG_EVENT 17:17 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_IRQ_EVENT 18:18 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_AUX_DONE 19:19 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX4_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_PLUG_EVENT 20:20 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_UNPLUG_EVENT 21:21 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_IRQ_EVENT 22:22 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_AUX_DONE 23:23 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX5_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_PLUG_EVENT 24:24 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_UNPLUG_EVENT 25:25 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_IRQ_EVENT 26:26 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_AUX_DONE 27:27 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX6_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_PLUG_EVENT(i) (0+(i)*4):(0+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_PLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_PLUG_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_PLUG_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_UNPLUG_EVENT(i) (1+(i)*4):(1+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_UNPLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_UNPLUG_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_UNPLUG_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_IRQ_EVENT(i) (2+(i)*4):(2+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_IRQ_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_IRQ_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_IRQ_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_AUX_DONE(i) (3+(i)*4):(3+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_AUX_DONE__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_AUX_DONE_DISABLED 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_MSK_AUX_AUX_AUX_DONE_ENABLED 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX 0x0000DD68 /* RW-4R */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_PLUG_EVENT 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_UNPLUG_EVENT 1:1 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_IRQ_EVENT 2:2 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_AUX_DONE 3:3 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX0_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_PLUG_EVENT 4:4 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_UNPLUG_EVENT 5:5 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_IRQ_EVENT 6:6 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_AUX_DONE 7:7 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX1_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_PLUG_EVENT 8:8 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_UNPLUG_EVENT 9:9 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_IRQ_EVENT 10:10 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_AUX_DONE 11:11 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX2_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_PLUG_EVENT 12:12 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_UNPLUG_EVENT 13:13 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_IRQ_EVENT 14:14 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_AUX_DONE 15:15 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX3_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_PLUG_EVENT 16:16 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_UNPLUG_EVENT 17:17 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_IRQ_EVENT 18:18 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_AUX_DONE 19:19 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX4_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_PLUG_EVENT 20:20 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_UNPLUG_EVENT 21:21 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_IRQ_EVENT 22:22 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_AUX_DONE 23:23 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX5_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_PLUG_EVENT 24:24 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_UNPLUG_EVENT 25:25 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_IRQ_EVENT 26:26 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_AUX_DONE 27:27 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX6_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_PLUG_EVENT(i) (0+(i)*4):(0+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_PLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_PLUG_EVENT_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_PLUG_EVENT_FORWARD 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_UNPLUG_EVENT(i) (1+(i)*4):(1+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_UNPLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_UNPLUG_EVENT_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_UNPLUG_EVENT_FORWARD 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_IRQ_EVENT(i) (2+(i)*4):(2+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_IRQ_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_IRQ_EVENT_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_IRQ_EVENT_FORWARD 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_AUX_DONE(i) (3+(i)*4):(3+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_AUX_DONE__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_AUX_DONE_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_AUX_AUX_AUX_DONE_FORWARD 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX 0x0000DD6C /* RW-4R */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_PLUG_EVENT 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_UNPLUG_EVENT 1:1 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_IRQ_EVENT 2:2 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_AUX_DONE 3:3 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX0_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_PLUG_EVENT 4:4 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_UNPLUG_EVENT 5:5 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_IRQ_EVENT 6:6 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_AUX_DONE 7:7 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX1_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_PLUG_EVENT 8:8 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_UNPLUG_EVENT 9:9 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_IRQ_EVENT 10:10 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_AUX_DONE 11:11 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX2_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_PLUG_EVENT 12:12 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_UNPLUG_EVENT 13:13 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_IRQ_EVENT 14:14 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_AUX_DONE 15:15 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX3_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_PLUG_EVENT 16:16 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_UNPLUG_EVENT 17:17 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_IRQ_EVENT 18:18 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_AUX_DONE 19:19 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX4_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_PLUG_EVENT 20:20 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_UNPLUG_EVENT 21:21 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_IRQ_EVENT 22:22 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_AUX_DONE 23:23 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX5_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_PLUG_EVENT 24:24 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_UNPLUG_EVENT 25:25 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_IRQ_EVENT 26:26 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_AUX_DONE 27:27 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX6_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_PLUG_EVENT(i) (0+(i)*4):(0+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_PLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_PLUG_EVENT_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_PLUG_EVENT_FORWARD 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_UNPLUG_EVENT(i) (1+(i)*4):(1+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_UNPLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_UNPLUG_EVENT_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_UNPLUG_EVENT_FORWARD 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_IRQ_EVENT(i) (2+(i)*4):(2+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_IRQ_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_IRQ_EVENT_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_IRQ_EVENT_FORWARD 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_AUX_DONE(i) (3+(i)*4):(3+(i)*4) /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_AUX_DONE__SIZE_1 7 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_AUX_DONE_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_AUX_AUX_AUX_DONE_FORWARD 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2 0x000216B0 /* RW-4R */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO16_RISING 0:0 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO16_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO16_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO16_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO16_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO17_RISING 1:1 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO17_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO17_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO17_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO17_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO18_RISING 2:2 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO18_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO18_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO18_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO18_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO19_RISING 3:3 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO19_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO19_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO19_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO19_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO20_RISING 4:4 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO20_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO20_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO20_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO20_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO21_RISING 5:5 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO21_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO21_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO21_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO21_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO22_RISING 6:6 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO22_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO22_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO22_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO22_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO23_RISING 7:7 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO23_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO23_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO23_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO23_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO24_RISING 8:8 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO24_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO24_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO24_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO24_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO25_RISING 9:9 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO25_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO25_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO25_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO25_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO26_RISING 10:10 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO26_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO26_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO26_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO26_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO27_RISING 11:11 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO27_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO27_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO27_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO27_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO28_RISING 12:12 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO28_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO28_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO28_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO28_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO29_RISING 13:13 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO29_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO29_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO29_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO29_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO30_RISING 14:14 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO30_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO30_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO30_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO30_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO31_RISING 15:15 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO31_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO31_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO31_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO31_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO_RISING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO_RISING_PENDING 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO_RISING_RESET 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO16_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO16_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO16_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO16_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO16_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO17_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO17_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO17_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO17_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO17_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO18_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO18_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO18_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO18_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO18_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO19_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO19_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO19_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO19_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO19_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO20_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO20_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO20_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO20_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO20_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO21_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO21_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO21_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO21_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO21_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO22_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO22_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO22_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO22_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO22_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO23_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO23_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO23_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO23_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO23_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO24_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO24_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO24_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO24_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO24_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO25_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO25_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO25_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO25_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO25_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO26_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO26_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO26_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO26_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO26_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO27_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO27_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO27_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO27_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO27_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO28_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO28_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO28_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO28_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO28_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO29_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO29_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO29_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO29_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO29_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO30_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO30_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO30_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO30_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO30_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO31_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO31_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO31_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO31_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO31_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO_FALLING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO_FALLING_PENDING 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_2_GPIO_FALLING_RESET 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2 0x000216B4 /* RWI4R */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO16_RISING 0:0 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO16_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO16_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO16_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO17_RISING 1:1 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO17_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO17_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO17_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO18_RISING 2:2 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO18_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO18_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO18_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO19_RISING 3:3 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO19_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO19_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO19_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO20_RISING 4:4 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO20_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO20_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO20_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO21_RISING 5:5 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO21_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO21_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO21_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO22_RISING 6:6 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO22_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO22_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO22_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO23_RISING 7:7 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO23_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO23_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO23_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO24_RISING 8:8 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO24_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO24_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO24_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO25_RISING 9:9 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO25_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO25_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO25_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO26_RISING 10:10 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO26_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO26_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO26_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO27_RISING 11:11 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO27_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO27_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO27_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO28_RISING 12:12 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO28_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO28_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO28_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO29_RISING 13:13 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO29_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO29_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO29_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO30_RISING 14:14 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO30_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO30_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO30_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO31_RISING 15:15 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO31_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO31_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO31_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO16_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO16_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO16_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO16_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO17_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO17_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO17_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO17_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO18_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO18_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO18_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO18_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO19_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO19_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO19_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO19_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO20_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO20_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO20_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO20_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO21_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO21_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO21_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO21_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO22_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO22_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO22_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO22_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO23_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO23_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO23_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO23_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO24_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO24_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO24_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO24_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO25_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO25_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO25_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO25_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO26_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO26_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO26_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO26_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO27_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO27_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO27_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO27_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO28_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO28_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO28_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO28_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO29_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO29_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO29_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO29_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO30_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO30_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO30_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO30_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO31_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO31_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO31_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO31_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_2_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2 0x000216B8 /* RWI4R */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO16_RISING 0:0 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO16_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO16_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO16_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO17_RISING 1:1 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO17_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO17_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO17_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO18_RISING 2:2 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO18_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO18_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO18_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO19_RISING 3:3 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO19_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO19_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO19_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO20_RISING 4:4 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO20_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO20_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO20_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO21_RISING 5:5 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO21_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO21_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO21_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO22_RISING 6:6 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO22_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO22_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO22_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO23_RISING 7:7 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO23_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO23_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO23_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO24_RISING 8:8 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO24_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO24_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO24_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO25_RISING 9:9 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO25_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO25_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO25_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO26_RISING 10:10 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO26_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO26_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO26_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO27_RISING 11:11 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO27_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO27_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO27_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO28_RISING 12:12 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO28_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO28_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO28_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO29_RISING 13:13 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO29_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO29_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO29_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO30_RISING 14:14 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO30_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO30_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO30_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO31_RISING 15:15 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO31_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO31_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO31_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO_RISING_NOP 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO_RISING_FORWARD 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO16_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO16_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO16_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO16_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO17_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO17_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO17_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO17_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO18_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO18_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO18_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO18_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO19_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO19_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO19_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO19_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO20_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO20_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO20_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO20_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO21_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO21_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO21_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO21_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO22_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO22_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO22_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO22_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO23_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO23_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO23_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO23_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO24_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO24_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO24_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO24_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO25_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO25_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO25_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO25_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO26_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO26_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO26_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO26_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO27_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO27_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO27_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO27_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO28_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO28_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO28_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO28_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO29_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO29_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO29_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO29_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO30_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO30_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO30_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO30_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO31_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO31_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO31_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO31_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO_FALLING_NOP 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_2_GPIO_FALLING_FORWARD 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2 0x000216BC /* RWI4R */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO16_RISING 0:0 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO16_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO16_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO16_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO17_RISING 1:1 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO17_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO17_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO17_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO18_RISING 2:2 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO18_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO18_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO18_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO19_RISING 3:3 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO19_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO19_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO19_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO20_RISING 4:4 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO20_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO20_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO20_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO21_RISING 5:5 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO21_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO21_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO21_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO22_RISING 6:6 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO22_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO22_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO22_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO23_RISING 7:7 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO23_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO23_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO23_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO24_RISING 8:8 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO24_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO24_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO24_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO25_RISING 9:9 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO25_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO25_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO25_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO26_RISING 10:10 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO26_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO26_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO26_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO27_RISING 11:11 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO27_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO27_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO27_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO28_RISING 12:12 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO28_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO28_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO28_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO29_RISING 13:13 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO29_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO29_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO29_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO30_RISING 14:14 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO30_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO30_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO30_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO31_RISING 15:15 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO31_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO31_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO31_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO_RISING_NOP 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO_RISING_FORWARD 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO16_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO16_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO16_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO16_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO17_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO17_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO17_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO17_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO18_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO18_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO18_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO18_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO19_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO19_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO19_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO19_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO20_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO20_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO20_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO20_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO21_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO21_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO21_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO21_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO22_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO22_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO22_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO22_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO23_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO23_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO23_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO23_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO24_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO24_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO24_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO24_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO25_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO25_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO25_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO25_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO26_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO26_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO26_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO26_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO27_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO27_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO27_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO27_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO28_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO28_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO28_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO28_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO29_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO29_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO29_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO29_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO30_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO30_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO30_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO30_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO31_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO31_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO31_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO31_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO_FALLING_NOP 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_2_GPIO_FALLING_FORWARD 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3 0x000216C0 /* RW-4R */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO32_RISING 0:0 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO32_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO32_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO32_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO32_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO33_RISING 1:1 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO33_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO33_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO33_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO33_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO34_RISING 2:2 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO34_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO34_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO34_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO34_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO35_RISING 3:3 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO35_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO35_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO35_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO35_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO36_RISING 4:4 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO36_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO36_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO36_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO36_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO37_RISING 5:5 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO37_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO37_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO37_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO37_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO38_RISING 6:6 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO38_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO38_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO38_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO38_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO39_RISING 7:7 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO39_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO39_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO39_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO39_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO_RISING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO_RISING_PENDING 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO_RISING_RESET 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO32_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO32_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO32_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO32_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO32_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO33_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO33_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO33_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO33_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO33_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO34_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO34_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO34_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO34_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO34_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO35_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO35_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO35_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO35_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO35_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO36_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO36_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO36_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO36_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO36_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO37_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO37_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO37_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO37_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO37_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO38_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO38_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO38_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO38_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO38_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO39_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO39_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO39_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO39_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO39_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO_FALLING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO_FALLING_PENDING 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_3_GPIO_FALLING_RESET 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST(i) (0x000216A0+ (i)*(0x000216B0-0x000216A0)) /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST__SIZE_1 3 /* */
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#define NV_GPIO_PMU_INTR_GPIO_RISING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_PMU_INTR_GPIO_RISING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_GPIO_RISING_BIT(i) ((i)%16) /* */
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#define NV_GPIO_PMU_INTR_GPIO_RISING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_GPIO_FALLING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_PMU_INTR_GPIO_FALLING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_GPIO_FALLING_BIT(i) ((i)%16+16) /* */
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#define NV_GPIO_PMU_INTR_GPIO_FALLING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_GPIO_LIST_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3 0x000216C4 /* RWI4R */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO32_RISING 0:0 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO32_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO32_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO32_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO33_RISING 1:1 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO33_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO33_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO33_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO34_RISING 2:2 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO34_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO34_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO34_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO35_RISING 3:3 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO35_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO35_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO35_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO36_RISING 4:4 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO36_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO36_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO36_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO37_RISING 5:5 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO37_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO37_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO37_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO38_RISING 6:6 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO38_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO38_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO38_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO39_RISING 7:7 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO39_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO39_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO39_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO32_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO32_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO32_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO32_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO33_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO33_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO33_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO33_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO34_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO34_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO34_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO34_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO35_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO35_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO35_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO35_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO36_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO36_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO36_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO36_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO37_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO37_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO37_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO37_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO38_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO38_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO38_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO38_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO39_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO39_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO39_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO39_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_3_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST(i) (0x000216A4+ (i)*(0x000216B4-0x000216A4)) /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST__SIZE_1 3 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_RISING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_RISING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_RISING_BIT(i) ((i)%16) /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_RISING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_FALLING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_FALLING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_FALLING_BIT(i) ((i)%16+16) /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_FALLING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_MSK_GPIO_LIST_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3 0x000216C8 /* RWI4R */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO32_RISING 0:0 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO32_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO32_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO32_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO33_RISING 1:1 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO33_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO33_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO33_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO34_RISING 2:2 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO34_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO34_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO34_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO35_RISING 3:3 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO35_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO35_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO35_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO36_RISING 4:4 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO36_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO36_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO36_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO37_RISING 5:5 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO37_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO37_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO37_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO38_RISING 6:6 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO38_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO38_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO38_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO39_RISING 7:7 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO39_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO39_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO39_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO_RISING_NOP 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO_RISING_FORWARD 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO32_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO32_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO32_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO32_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO33_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO33_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO33_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO33_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO34_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO34_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO34_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO34_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO35_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO35_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO35_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO35_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO36_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO36_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO36_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO36_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO37_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO37_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO37_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO37_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO38_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO38_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO38_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO38_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO39_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO39_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO39_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO39_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO_FALLING_NOP 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_3_GPIO_FALLING_FORWARD 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST(i) (0x000216A8+ (i)*(0x000216B8-0x000216A8)) /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST__SIZE_1 3 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_RISING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_RISING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_RISING_BIT(i) ((i)%16) /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_RISING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_FALLING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_FALLING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_FALLING_BIT(i) ((i)%16+16) /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_FALLING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2RM_GPIO_LIST_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3 0x000216CC /* RWI4R */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO32_RISING 0:0 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO32_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO32_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO32_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO33_RISING 1:1 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO33_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO33_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO33_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO34_RISING 2:2 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO34_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO34_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO34_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO35_RISING 3:3 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO35_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO35_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO35_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO36_RISING 4:4 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO36_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO36_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO36_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO37_RISING 5:5 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO37_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO37_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO37_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO38_RISING 6:6 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO38_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO38_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO38_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO39_RISING 7:7 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO39_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO39_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO39_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO_RISING_NOP 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO_RISING_FORWARD 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO32_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO32_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO32_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO32_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO33_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO33_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO33_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO33_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO34_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO34_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO34_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO34_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO35_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO35_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO35_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO35_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO36_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO36_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO36_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO36_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO37_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO37_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO37_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO37_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO38_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO38_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO38_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO38_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO39_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO39_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO39_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO39_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO_FALLING_NOP 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_3_GPIO_FALLING_FORWARD 0x00000001 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST(i) (0x000216AC+ (i)*(0x000216BC-0x000216AC)) /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST__SIZE_1 3 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_RISING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_RISING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_RISING_BIT(i) ((i)%16) /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_RISING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_FALLING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_FALLING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_FALLING_BIT(i) ((i)%16+16) /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_FALLING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_PMU_INTR_FWD2GSP_GPIO_LIST_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_SPI 0x0000DDA0 /* RW-4R */
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#define NV_PMGR_PMU_INTR_SPI_SPI0 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_SPI_SPI0_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PMU_INTR_SPI_SPI0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_PMU_INTR_SPI_SPI0_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_PMU_INTR_SPI_SPI0_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_SPI_SPI(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_PMU_INTR_SPI_SPI__SIZE_1 1 /* */
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#define NV_PMGR_PMU_INTR_SPI_SPI_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_SPI_SPI_PENDING 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_SPI_SPI_RESET 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_MSK_SPI 0x0000DDA4 /* RW-4R */
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#define NV_PMGR_PMU_INTR_MSK_SPI_SPI0 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_MSK_SPI_SPI0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_MSK_SPI_SPI0_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_SPI_SPI0_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_PMU_INTR_MSK_SPI_SPI(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_PMU_INTR_MSK_SPI_SPI__SIZE_1 1 /* */
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#define NV_PMGR_PMU_INTR_MSK_SPI_SPI_DISABLED 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_MSK_SPI_SPI_ENABLED 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_SPI 0x0000DDA8 /* RW-4R */
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#define NV_PMGR_PMU_INTR_FWD2RM_SPI_SPI0 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2RM_SPI_SPI0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2RM_SPI_SPI0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_SPI_SPI0_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2RM_SPI_SPI(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_SPI_SPI__SIZE_1 1 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_SPI_SPI_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2RM_SPI_SPI_FORWARD 0x00000001 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_SPI 0x0000DDAC /* RW-4R */
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#define NV_PMGR_PMU_INTR_FWD2GSP_SPI_SPI0 0:0 /* RWIVF */
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#define NV_PMGR_PMU_INTR_FWD2GSP_SPI_SPI0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_SPI_SPI0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_SPI_SPI0_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_PMU_INTR_FWD2GSP_SPI_SPI(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_SPI_SPI__SIZE_1 1 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_SPI_SPI_NOP 0x00000000 /* */
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#define NV_PMGR_PMU_INTR_FWD2GSP_SPI_SPI_FORWARD 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1 0x00021720 /* RW-4R */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO0_RISING 0:0 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO0_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO0_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO0_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO0_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO1_RISING 1:1 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO1_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO1_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO1_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO1_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO2_RISING 2:2 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO2_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO2_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO2_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO2_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO3_RISING 3:3 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO3_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO3_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO3_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO3_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO4_RISING 4:4 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO4_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO4_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO4_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO4_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO5_RISING 5:5 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO5_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO5_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO5_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO5_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO6_RISING 6:6 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO6_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO6_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO6_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO6_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO7_RISING 7:7 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO7_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO7_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO7_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO7_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO8_RISING 8:8 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO8_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO8_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO8_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO8_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO9_RISING 9:9 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO9_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO9_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO9_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO9_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO10_RISING 10:10 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO10_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO10_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO10_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO10_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO11_RISING 11:11 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO11_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO11_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO11_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO11_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO12_RISING 12:12 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO12_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO12_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO12_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO12_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO13_RISING 13:13 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO13_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO13_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO13_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO13_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO14_RISING 14:14 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO14_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO14_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO14_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO14_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO15_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO15_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO15_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO_RISING(i) (0+(i)):(0+(i)) /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO_RISING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO_RISING_PENDING 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO_RISING_RESET 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO0_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO0_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO0_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO0_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO0_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO1_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO1_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO1_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO1_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO1_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO2_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO2_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO2_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO2_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO2_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO3_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO3_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO3_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO3_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO3_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO4_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO4_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO4_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO4_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO4_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO5_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO5_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO5_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO5_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO5_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO6_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO6_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO6_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO6_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO6_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO7_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO7_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO7_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO7_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO7_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO8_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO8_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO8_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO8_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO8_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO9_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO9_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO9_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO9_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO9_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO10_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO10_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO10_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO10_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO10_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO11_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO11_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO11_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO11_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO11_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO12_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO12_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO12_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO12_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO12_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO13_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO13_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO13_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO13_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO13_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO14_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO14_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO14_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO14_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO14_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO15_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO15_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO15_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO_FALLING(i) (16+(i)):(16+(i)) /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO_FALLING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO_FALLING_PENDING 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_1_GPIO_FALLING_RESET 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1 0x00021724 /* RWI4R */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO0_RISING 0:0 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO0_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO0_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO0_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO1_RISING 1:1 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO1_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO1_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO1_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO2_RISING 2:2 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO2_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO2_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO2_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO3_RISING 3:3 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO3_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO3_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO3_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO4_RISING 4:4 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO4_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO4_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO4_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO5_RISING 5:5 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO5_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO5_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO5_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO6_RISING 6:6 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO6_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO6_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO6_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO7_RISING 7:7 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO7_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO7_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO7_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO8_RISING 8:8 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO8_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO8_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO8_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO9_RISING 9:9 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO9_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO9_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO9_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO10_RISING 10:10 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO10_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO10_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO10_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO11_RISING 11:11 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO11_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO11_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO11_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO12_RISING 12:12 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO12_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO12_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO12_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO13_RISING 13:13 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO13_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO13_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO13_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO14_RISING 14:14 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO14_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO14_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO14_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO15_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO_RISING(i) (0+(i)):(0+(i)) /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO0_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO0_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO0_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO0_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO1_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO1_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO1_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO1_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO2_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO2_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO2_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO2_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO3_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO3_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO3_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO3_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO4_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO4_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO4_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO4_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO5_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO5_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO5_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO5_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO6_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO6_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO6_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO6_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO7_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO7_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO7_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO7_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO8_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO8_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO8_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO8_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO9_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO9_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO9_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO9_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO10_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO10_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO10_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO10_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO11_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO11_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO11_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO11_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO12_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO12_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO12_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO12_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO13_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO13_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO13_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO13_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO14_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO14_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO14_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO14_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO15_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO_FALLING(i) (16+(i)):(16+(i)) /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_1_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1 0x00021728 /* RWI4R */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO0_RISING 0:0 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO0_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO0_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO0_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO1_RISING 1:1 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO1_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO1_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO1_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO2_RISING 2:2 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO2_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO2_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO2_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO3_RISING 3:3 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO3_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO3_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO3_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO4_RISING 4:4 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO4_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO4_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO4_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO5_RISING 5:5 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO5_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO5_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO5_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO6_RISING 6:6 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO6_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO6_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO6_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO7_RISING 7:7 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO7_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO7_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO7_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO8_RISING 8:8 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO8_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO8_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO8_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO9_RISING 9:9 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO9_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO9_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO9_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO10_RISING 10:10 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO10_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO10_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO10_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO11_RISING 11:11 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO11_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO11_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO11_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO12_RISING 12:12 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO12_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO12_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO12_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO13_RISING 13:13 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO13_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO13_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO13_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO14_RISING 14:14 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO14_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO14_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO14_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO15_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO15_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO_RISING(i) (0+(i)):(0+(i)) /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO_RISING_NOP 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO_RISING_FORWARD 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO0_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO0_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO0_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO0_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO1_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO1_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO1_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO1_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO2_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO2_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO2_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO2_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO3_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO3_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO3_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO3_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO4_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO4_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO4_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO4_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO5_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO5_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO5_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO5_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO6_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO6_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO6_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO6_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO7_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO7_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO7_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO7_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO8_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO8_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO8_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO8_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO9_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO9_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO9_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO9_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO10_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO10_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO10_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO10_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO11_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO11_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO11_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO11_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO12_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO12_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO12_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO12_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO13_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO13_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO13_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO13_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO14_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO14_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO14_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO14_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO15_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO15_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO_FALLING(i) (16+(i)):(16+(i)) /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO_FALLING_NOP 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_1_GPIO_FALLING_FORWARD 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1 0x0002172C /* RWI4R */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO0_RISING 0:0 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO0_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO0_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO0_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO1_RISING 1:1 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO1_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO1_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO1_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO2_RISING 2:2 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO2_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO2_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO2_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO3_RISING 3:3 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO3_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO3_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO3_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO4_RISING 4:4 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO4_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO4_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO4_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO5_RISING 5:5 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO5_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO5_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO5_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO6_RISING 6:6 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO6_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO6_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO6_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO7_RISING 7:7 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO7_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO7_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO7_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO8_RISING 8:8 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO8_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO8_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO8_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO9_RISING 9:9 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO9_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO9_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO9_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO10_RISING 10:10 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO10_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO10_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO10_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO11_RISING 11:11 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO11_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO11_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO11_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO12_RISING 12:12 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO12_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO12_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO12_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO13_RISING 13:13 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO13_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO13_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO13_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO14_RISING 14:14 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO14_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO14_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO14_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO15_RISING 15:15 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO15_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO15_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO15_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO_RISING(i) (0+(i)):(0+(i)) /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO_RISING_NOP 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO_RISING_FORWARD 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO0_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO0_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO0_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO0_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO1_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO1_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO1_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO1_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO2_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO2_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO2_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO2_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO3_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO3_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO3_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO3_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO4_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO4_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO4_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO4_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO5_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO5_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO5_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO5_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO6_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO6_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO6_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO6_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO7_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO7_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO7_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO7_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO8_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO8_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO8_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO8_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO9_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO9_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO9_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO9_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO10_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO10_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO10_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO10_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO11_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO11_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO11_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO11_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO12_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO12_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO12_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO12_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO13_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO13_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO13_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO13_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO14_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO14_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO14_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO14_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO15_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO15_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO15_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO15_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO_FALLING(i) (16+(i)):(16+(i)) /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO_FALLING_NOP 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_1_GPIO_FALLING_FORWARD 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_I2C 0x0000DE20 /* RW-4R */
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#define NV_PMGR_GSP_INTR_I2C_I2C0 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_I2C_I2C0_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_I2C_I2C0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C0_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C0_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_I2C_I2C1 1:1 /* RWIVF */
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#define NV_PMGR_GSP_INTR_I2C_I2C1_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_I2C_I2C1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C1_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C1_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_I2C_I2C2 2:2 /* RWIVF */
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#define NV_PMGR_GSP_INTR_I2C_I2C2_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_I2C_I2C2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C2_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C2_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_I2C_I2C3 3:3 /* RWIVF */
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#define NV_PMGR_GSP_INTR_I2C_I2C3_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_I2C_I2C3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C3_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C3_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_I2C_I2C4 4:4 /* RWIVF */
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#define NV_PMGR_GSP_INTR_I2C_I2C4_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_I2C_I2C4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C4_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C4_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_I2C_I2C5 5:5 /* RWIVF */
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#define NV_PMGR_GSP_INTR_I2C_I2C5_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_I2C_I2C5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C5_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C5_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_I2C_I2C6 6:6 /* RWIVF */
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#define NV_PMGR_GSP_INTR_I2C_I2C6_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_I2C_I2C6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C6_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C6_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_I2C_I2C7 7:7 /* RWIVF */
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#define NV_PMGR_GSP_INTR_I2C_I2C7_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_I2C_I2C7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C7_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C7_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_I2C_I2C8 8:8 /* RWIVF */
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#define NV_PMGR_GSP_INTR_I2C_I2C8_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_I2C_I2C8_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C8_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C8_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_I2C_I2C9 9:9 /* RWIVF */
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#define NV_PMGR_GSP_INTR_I2C_I2C9_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_I2C_I2C9_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C9_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_I2C_I2C9_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_I2C_I2C(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_GSP_INTR_I2C_I2C__SIZE_1 10 /* */
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#define NV_PMGR_GSP_INTR_I2C_I2C_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_I2C_I2C_PENDING 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_I2C_I2C_RESET 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_MSK_I2C 0x0000DE24 /* RW-4R */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C0 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C0_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C0_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C1 1:1 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C1_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C1_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C2 2:2 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C2_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C2_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C3 3:3 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C3_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C3_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C4 4:4 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C4_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C4_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C4_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C5 5:5 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C5_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C5_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C5_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C6 6:6 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C6_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C6_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C6_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C7 7:7 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C7_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C7_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C7_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C8 8:8 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C8_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C8_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C8_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C9 9:9 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C9_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C9_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C9_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C__SIZE_1 10 /* */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C_DISABLED 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_MSK_I2C_I2C_ENABLED 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C 0x0000DE28 /* RW-4R */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C0 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C0_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C1 1:1 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C1_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C1_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C2 2:2 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C2_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C2_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C3 3:3 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C3_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C3_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C4 4:4 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C4_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C4_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C4_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C5 5:5 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C5_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C5_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C5_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C6 6:6 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C6_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C6_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C6_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C7 7:7 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C7_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C7_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C7_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C8 8:8 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C8_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C8_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C8_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C9 9:9 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C9_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C9_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C9_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C__SIZE_1 10 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_I2C_I2C_FORWARD 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C 0x0000DE2C /* RW-4R */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C0 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C0_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C1 1:1 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C1_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C1_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C2 2:2 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C2_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C2_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C3 3:3 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C3_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C3_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C4 4:4 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C4_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C4_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C4_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C5 5:5 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C5_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C5_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C5_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C6 6:6 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C6_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C6_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C6_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C7 7:7 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C7_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C7_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C7_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C8 8:8 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C8_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C8_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C8_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C9 9:9 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C9_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C9_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C9_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C__SIZE_1 10 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_I2C_I2C_FORWARD 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_DAC 0x0000DE40 /* RW-4R */
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#define NV_PMGR_GSP_INTR_DAC_DAC0 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_DAC_DAC0_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_DAC_DAC0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_DAC_DAC0_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_DAC_DAC0_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_DAC_DAC1 1:1 /* RWIVF */
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#define NV_PMGR_GSP_INTR_DAC_DAC1_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_DAC_DAC1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_DAC_DAC1_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_DAC_DAC1_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_DAC_DAC2 2:2 /* RWIVF */
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#define NV_PMGR_GSP_INTR_DAC_DAC2_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_DAC_DAC2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_DAC_DAC2_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_DAC_DAC2_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_DAC_DAC3 3:3 /* RWIVF */
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#define NV_PMGR_GSP_INTR_DAC_DAC3_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_DAC_DAC3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_DAC_DAC3_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_DAC_DAC3_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_DAC_DAC(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_GSP_INTR_DAC_DAC__SIZE_1 4 /* */
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#define NV_PMGR_GSP_INTR_DAC_DAC_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_DAC_DAC_PENDING 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_DAC_DAC_RESET 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_MSK_DAC 0x0000DE44 /* RW-4R */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC0 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC0_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC0_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC1 1:1 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC1_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC1_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC2 2:2 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC2_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC2_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC3 3:3 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC3_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC3_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC__SIZE_1 4 /* */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC_DISABLED 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_MSK_DAC_DAC_ENABLED 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC 0x0000DE48 /* RW-4R */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC0 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC0_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC1 1:1 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC1_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC1_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC2 2:2 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC2_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC2_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC3 3:3 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC3_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC3_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC__SIZE_1 4 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_DAC_DAC_FORWARD 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC 0x0000DE4C /* RW-4R */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC0 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC0_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC1 1:1 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC1_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC1_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC1_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC2 2:2 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC2_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC2_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC2_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC3 3:3 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC3_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC3_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC__SIZE_1 4 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_DAC_DAC_FORWARD 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_AUX 0x0000DE60 /* RW-4R */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_PLUG_EVENT 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_UNPLUG_EVENT 1:1 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_IRQ_EVENT 2:2 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_AUX_DONE 3:3 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX0_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_PLUG_EVENT 4:4 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_UNPLUG_EVENT 5:5 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_IRQ_EVENT 6:6 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_AUX_DONE 7:7 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX1_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_PLUG_EVENT 8:8 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_UNPLUG_EVENT 9:9 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_IRQ_EVENT 10:10 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_AUX_DONE 11:11 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX2_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_PLUG_EVENT 12:12 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_UNPLUG_EVENT 13:13 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_IRQ_EVENT 14:14 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_AUX_DONE 15:15 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX3_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_PLUG_EVENT 16:16 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_UNPLUG_EVENT 17:17 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_IRQ_EVENT 18:18 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_AUX_DONE 19:19 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX4_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_PLUG_EVENT 20:20 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_UNPLUG_EVENT 21:21 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_IRQ_EVENT 22:22 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_AUX_DONE 23:23 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX5_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_PLUG_EVENT 24:24 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_PLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_PLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_PLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_PLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_UNPLUG_EVENT 25:25 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_UNPLUG_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_UNPLUG_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_UNPLUG_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_IRQ_EVENT 26:26 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_IRQ_EVENT_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_IRQ_EVENT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_IRQ_EVENT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_IRQ_EVENT_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_AUX_DONE 27:27 /* RWIVF */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_AUX_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_AUX_DONE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_AUX_DONE_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_AUX_AUX6_AUX_DONE_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_AUX_AUX_PLUG_EVENT(i) (0+(i)*4):(0+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_PLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_PLUG_EVENT_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_PLUG_EVENT_PENDING 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_PLUG_EVENT_RESET 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_UNPLUG_EVENT(i) (1+(i)*4):(1+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_UNPLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_UNPLUG_EVENT_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_UNPLUG_EVENT_PENDING 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_UNPLUG_EVENT_RESET 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_IRQ_EVENT(i) (2+(i)*4):(2+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_IRQ_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_IRQ_EVENT_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_IRQ_EVENT_PENDING 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_IRQ_EVENT_RESET 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_AUX_DONE(i) (3+(i)*4):(3+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_AUX_DONE__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_AUX_DONE_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_AUX_DONE_PENDING 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_AUX_AUX_AUX_DONE_RESET 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX 0x0000DE64 /* RW-4R */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_PLUG_EVENT 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_UNPLUG_EVENT 1:1 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_IRQ_EVENT 2:2 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_AUX_DONE 3:3 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX0_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_PLUG_EVENT 4:4 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_UNPLUG_EVENT 5:5 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_IRQ_EVENT 6:6 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_AUX_DONE 7:7 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX1_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_PLUG_EVENT 8:8 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_UNPLUG_EVENT 9:9 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_IRQ_EVENT 10:10 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_AUX_DONE 11:11 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX2_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_PLUG_EVENT 12:12 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_UNPLUG_EVENT 13:13 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_IRQ_EVENT 14:14 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_AUX_DONE 15:15 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX3_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_PLUG_EVENT 16:16 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_UNPLUG_EVENT 17:17 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_IRQ_EVENT 18:18 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_AUX_DONE 19:19 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX4_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_PLUG_EVENT 20:20 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_UNPLUG_EVENT 21:21 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_IRQ_EVENT 22:22 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_AUX_DONE 23:23 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX5_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_PLUG_EVENT 24:24 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_PLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_PLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_UNPLUG_EVENT 25:25 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_UNPLUG_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_UNPLUG_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_IRQ_EVENT 26:26 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_IRQ_EVENT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_IRQ_EVENT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_AUX_DONE 27:27 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_AUX_DONE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX6_AUX_DONE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_PLUG_EVENT(i) (0+(i)*4):(0+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_PLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_PLUG_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_PLUG_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_UNPLUG_EVENT(i) (1+(i)*4):(1+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_UNPLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_UNPLUG_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_UNPLUG_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_IRQ_EVENT(i) (2+(i)*4):(2+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_IRQ_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_IRQ_EVENT_DISABLED 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_IRQ_EVENT_ENABLED 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_AUX_DONE(i) (3+(i)*4):(3+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_AUX_DONE__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_AUX_DONE_DISABLED 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_MSK_AUX_AUX_AUX_DONE_ENABLED 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX 0x0000DE68 /* RW-4R */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_PLUG_EVENT 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_UNPLUG_EVENT 1:1 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_IRQ_EVENT 2:2 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_AUX_DONE 3:3 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX0_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_PLUG_EVENT 4:4 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_UNPLUG_EVENT 5:5 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_IRQ_EVENT 6:6 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_AUX_DONE 7:7 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX1_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_PLUG_EVENT 8:8 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_UNPLUG_EVENT 9:9 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_IRQ_EVENT 10:10 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_AUX_DONE 11:11 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX2_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_PLUG_EVENT 12:12 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_UNPLUG_EVENT 13:13 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_IRQ_EVENT 14:14 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_AUX_DONE 15:15 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX3_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_PLUG_EVENT 16:16 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_UNPLUG_EVENT 17:17 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_IRQ_EVENT 18:18 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_AUX_DONE 19:19 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX4_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_PLUG_EVENT 20:20 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_UNPLUG_EVENT 21:21 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_IRQ_EVENT 22:22 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_AUX_DONE 23:23 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX5_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_PLUG_EVENT 24:24 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_UNPLUG_EVENT 25:25 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_IRQ_EVENT 26:26 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_AUX_DONE 27:27 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX6_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_PLUG_EVENT(i) (0+(i)*4):(0+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_PLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_PLUG_EVENT_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_PLUG_EVENT_FORWARD 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_UNPLUG_EVENT(i) (1+(i)*4):(1+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_UNPLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_UNPLUG_EVENT_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_UNPLUG_EVENT_FORWARD 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_IRQ_EVENT(i) (2+(i)*4):(2+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_IRQ_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_IRQ_EVENT_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_IRQ_EVENT_FORWARD 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_AUX_DONE(i) (3+(i)*4):(3+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_AUX_DONE__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_AUX_DONE_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_AUX_AUX_AUX_DONE_FORWARD 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX 0x0000DE6C /* RW-4R */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_PLUG_EVENT 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_UNPLUG_EVENT 1:1 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_IRQ_EVENT 2:2 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_AUX_DONE 3:3 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX0_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_PLUG_EVENT 4:4 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_UNPLUG_EVENT 5:5 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_IRQ_EVENT 6:6 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_AUX_DONE 7:7 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX1_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_PLUG_EVENT 8:8 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_UNPLUG_EVENT 9:9 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_IRQ_EVENT 10:10 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_AUX_DONE 11:11 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX2_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_PLUG_EVENT 12:12 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_UNPLUG_EVENT 13:13 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_IRQ_EVENT 14:14 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_AUX_DONE 15:15 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX3_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_PLUG_EVENT 16:16 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_UNPLUG_EVENT 17:17 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_IRQ_EVENT 18:18 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_AUX_DONE 19:19 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX4_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_PLUG_EVENT 20:20 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_UNPLUG_EVENT 21:21 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_IRQ_EVENT 22:22 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_AUX_DONE 23:23 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX5_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_PLUG_EVENT 24:24 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_PLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_PLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_PLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_UNPLUG_EVENT 25:25 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_UNPLUG_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_UNPLUG_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_UNPLUG_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_IRQ_EVENT 26:26 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_IRQ_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_IRQ_EVENT_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_IRQ_EVENT_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_AUX_DONE 27:27 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_AUX_DONE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_AUX_DONE_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX6_AUX_DONE_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_PLUG_EVENT(i) (0+(i)*4):(0+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_PLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_PLUG_EVENT_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_PLUG_EVENT_FORWARD 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_UNPLUG_EVENT(i) (1+(i)*4):(1+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_UNPLUG_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_UNPLUG_EVENT_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_UNPLUG_EVENT_FORWARD 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_IRQ_EVENT(i) (2+(i)*4):(2+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_IRQ_EVENT__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_IRQ_EVENT_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_IRQ_EVENT_FORWARD 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_AUX_DONE(i) (3+(i)*4):(3+(i)*4) /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_AUX_DONE__SIZE_1 7 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_AUX_DONE_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_AUX_AUX_AUX_DONE_FORWARD 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2 0x00021730 /* RW-4R */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO16_RISING 0:0 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO16_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO16_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO16_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO16_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO17_RISING 1:1 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO17_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO17_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO17_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO17_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO18_RISING 2:2 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO18_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO18_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO18_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO18_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO19_RISING 3:3 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO19_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO19_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO19_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO19_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO20_RISING 4:4 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO20_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO20_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO20_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO20_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO21_RISING 5:5 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO21_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO21_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO21_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO21_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO22_RISING 6:6 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO22_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO22_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO22_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO22_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO23_RISING 7:7 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO23_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO23_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO23_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO23_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO24_RISING 8:8 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO24_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO24_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO24_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO24_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO25_RISING 9:9 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO25_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO25_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO25_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO25_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO26_RISING 10:10 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO26_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO26_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO26_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO26_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO27_RISING 11:11 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO27_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO27_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO27_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO27_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO28_RISING 12:12 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO28_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO28_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO28_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO28_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO29_RISING 13:13 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO29_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO29_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO29_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO29_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO30_RISING 14:14 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO30_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO30_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO30_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO30_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO31_RISING 15:15 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO31_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO31_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO31_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO31_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO_RISING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO_RISING_PENDING 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO_RISING_RESET 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO16_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO16_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO16_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO16_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO16_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO17_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO17_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO17_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO17_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO17_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO18_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO18_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO18_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO18_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO18_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO19_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO19_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO19_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO19_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO19_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO20_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO20_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO20_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO20_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO20_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO21_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO21_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO21_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO21_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO21_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO22_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO22_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO22_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO22_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO22_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO23_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO23_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO23_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO23_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO23_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO24_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO24_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO24_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO24_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO24_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO25_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO25_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO25_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO25_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO25_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO26_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO26_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO26_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO26_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO26_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO27_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO27_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO27_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO27_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO27_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO28_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO28_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO28_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO28_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO28_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO29_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO29_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO29_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO29_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO29_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO30_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO30_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO30_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO30_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO30_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO31_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO31_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO31_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO31_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO31_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO_FALLING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO_FALLING_PENDING 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_2_GPIO_FALLING_RESET 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2 0x00021734 /* RWI4R */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO16_RISING 0:0 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO16_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO16_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO16_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO17_RISING 1:1 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO17_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO17_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO17_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO18_RISING 2:2 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO18_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO18_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO18_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO19_RISING 3:3 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO19_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO19_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO19_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO20_RISING 4:4 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO20_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO20_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO20_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO21_RISING 5:5 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO21_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO21_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO21_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO22_RISING 6:6 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO22_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO22_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO22_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO23_RISING 7:7 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO23_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO23_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO23_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO24_RISING 8:8 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO24_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO24_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO24_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO25_RISING 9:9 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO25_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO25_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO25_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO26_RISING 10:10 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO26_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO26_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO26_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO27_RISING 11:11 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO27_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO27_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO27_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO28_RISING 12:12 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO28_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO28_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO28_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO29_RISING 13:13 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO29_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO29_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO29_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO30_RISING 14:14 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO30_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO30_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO30_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO31_RISING 15:15 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO31_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO31_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO31_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO16_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO16_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO16_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO16_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO17_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO17_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO17_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO17_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO18_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO18_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO18_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO18_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO19_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO19_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO19_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO19_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO20_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO20_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO20_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO20_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO21_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO21_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO21_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO21_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO22_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO22_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO22_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO22_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO23_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO23_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO23_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO23_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO24_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO24_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO24_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO24_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO25_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO25_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO25_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO25_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO26_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO26_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO26_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO26_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO27_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO27_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO27_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO27_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO28_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO28_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO28_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO28_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO29_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO29_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO29_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO29_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO30_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO30_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO30_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO30_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO31_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO31_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO31_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO31_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_2_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2 0x00021738 /* RWI4R */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO16_RISING 0:0 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO16_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO16_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO16_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO17_RISING 1:1 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO17_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO17_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO17_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO18_RISING 2:2 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO18_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO18_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO18_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO19_RISING 3:3 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO19_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO19_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO19_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO20_RISING 4:4 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO20_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO20_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO20_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO21_RISING 5:5 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO21_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO21_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO21_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO22_RISING 6:6 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO22_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO22_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO22_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO23_RISING 7:7 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO23_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO23_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO23_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO24_RISING 8:8 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO24_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO24_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO24_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO25_RISING 9:9 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO25_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO25_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO25_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO26_RISING 10:10 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO26_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO26_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO26_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO27_RISING 11:11 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO27_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO27_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO27_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO28_RISING 12:12 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO28_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO28_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO28_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO29_RISING 13:13 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO29_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO29_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO29_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO30_RISING 14:14 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO30_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO30_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO30_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO31_RISING 15:15 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO31_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO31_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO31_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO_RISING_NOP 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO_RISING_FORWARD 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO16_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO16_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO16_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO16_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO17_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO17_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO17_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO17_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO18_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO18_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO18_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO18_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO19_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO19_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO19_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO19_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO20_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO20_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO20_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO20_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO21_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO21_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO21_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO21_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO22_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO22_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO22_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO22_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO23_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO23_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO23_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO23_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO24_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO24_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO24_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO24_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO25_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO25_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO25_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO25_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO26_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO26_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO26_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO26_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO27_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO27_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO27_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO27_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO28_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO28_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO28_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO28_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO29_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO29_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO29_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO29_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO30_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO30_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO30_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO30_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO31_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO31_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO31_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO31_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO_FALLING_NOP 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_2_GPIO_FALLING_FORWARD 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2 0x0002173C /* RWI4R */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO16_RISING 0:0 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO16_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO16_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO16_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO17_RISING 1:1 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO17_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO17_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO17_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO18_RISING 2:2 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO18_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO18_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO18_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO19_RISING 3:3 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO19_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO19_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO19_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO20_RISING 4:4 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO20_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO20_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO20_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO21_RISING 5:5 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO21_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO21_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO21_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO22_RISING 6:6 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO22_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO22_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO22_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO23_RISING 7:7 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO23_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO23_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO23_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO24_RISING 8:8 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO24_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO24_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO24_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO25_RISING 9:9 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO25_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO25_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO25_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO26_RISING 10:10 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO26_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO26_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO26_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO27_RISING 11:11 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO27_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO27_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO27_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO28_RISING 12:12 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO28_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO28_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO28_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO29_RISING 13:13 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO29_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO29_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO29_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO30_RISING 14:14 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO30_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO30_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO30_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO31_RISING 15:15 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO31_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO31_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO31_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO_RISING_NOP 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO_RISING_FORWARD 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO16_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO16_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO16_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO16_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO17_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO17_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO17_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO17_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO18_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO18_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO18_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO18_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO19_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO19_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO19_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO19_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO20_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO20_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO20_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO20_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO21_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO21_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO21_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO21_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO22_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO22_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO22_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO22_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO23_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO23_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO23_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO23_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO24_FALLING 24:24 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO24_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO24_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO24_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO25_FALLING 25:25 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO25_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO25_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO25_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO26_FALLING 26:26 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO26_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO26_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO26_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO27_FALLING 27:27 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO27_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO27_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO27_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO28_FALLING 28:28 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO28_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO28_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO28_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO29_FALLING 29:29 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO29_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO29_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO29_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO30_FALLING 30:30 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO30_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO30_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO30_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO31_FALLING 31:31 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO31_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO31_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO31_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO_FALLING_NOP 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_2_GPIO_FALLING_FORWARD 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3 0x00021740 /* RW-4R */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO32_RISING 0:0 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO32_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO32_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO32_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO32_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO33_RISING 1:1 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO33_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO33_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO33_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO33_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO34_RISING 2:2 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO34_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO34_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO34_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO34_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO35_RISING 3:3 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO35_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO35_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO35_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO35_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO36_RISING 4:4 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO36_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO36_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO36_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO36_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO37_RISING 5:5 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO37_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO37_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO37_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO37_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO38_RISING 6:6 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO38_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO38_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO38_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO38_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO39_RISING 7:7 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO39_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO39_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO39_RISING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO39_RISING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO_RISING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO_RISING_PENDING 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO_RISING_RESET 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO32_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO32_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO32_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO32_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO32_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO33_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO33_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO33_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO33_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO33_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO34_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO34_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO34_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO34_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO34_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO35_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO35_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO35_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO35_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO35_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO36_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO36_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO36_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO36_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO36_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO37_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO37_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO37_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO37_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO37_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO38_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO38_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO38_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO38_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO38_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO39_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO39_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO39_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO39_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO39_FALLING_RESET 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO_FALLING_NOT_PENDING 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO_FALLING_PENDING 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_3_GPIO_FALLING_RESET 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST(i) (0x00021720+ (i)*(0x00021730-0x00021720)) /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST__SIZE_1 3 /* */
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#define NV_GPIO_GSP_INTR_GPIO_RISING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_GSP_INTR_GPIO_RISING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_GPIO_RISING_BIT(i) ((i)%16) /* */
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#define NV_GPIO_GSP_INTR_GPIO_RISING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_GPIO_FALLING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_GSP_INTR_GPIO_FALLING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_GPIO_FALLING_BIT(i) ((i)%16+16) /* */
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#define NV_GPIO_GSP_INTR_GPIO_FALLING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_GPIO_LIST_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3 0x00021744 /* RWI4R */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO32_RISING 0:0 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO32_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO32_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO32_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO33_RISING 1:1 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO33_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO33_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO33_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO34_RISING 2:2 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO34_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO34_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO34_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO35_RISING 3:3 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO35_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO35_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO35_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO36_RISING 4:4 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO36_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO36_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO36_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO37_RISING 5:5 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO37_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO37_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO37_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO38_RISING 6:6 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO38_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO38_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO38_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO39_RISING 7:7 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO39_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO39_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO39_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO32_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO32_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO32_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO32_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO33_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO33_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO33_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO33_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO34_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO34_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO34_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO34_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO35_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO35_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO35_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO35_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO36_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO36_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO36_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO36_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO37_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO37_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO37_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO37_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO38_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO38_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO38_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO38_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO39_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO39_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO39_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO39_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO_FALLING_DISABLED 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_3_GPIO_FALLING_ENABLED 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST(i) (0x00021724+ (i)*(0x00021734-0x00021724)) /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST__SIZE_1 3 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_RISING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_RISING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_RISING_BIT(i) ((i)%16) /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_RISING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_FALLING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_FALLING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_FALLING_BIT(i) ((i)%16+16) /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_FALLING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_MSK_GPIO_LIST_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3 0x00021748 /* RWI4R */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO32_RISING 0:0 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO32_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO32_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO32_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO33_RISING 1:1 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO33_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO33_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO33_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO34_RISING 2:2 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO34_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO34_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO34_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO35_RISING 3:3 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO35_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO35_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO35_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO36_RISING 4:4 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO36_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO36_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO36_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO37_RISING 5:5 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO37_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO37_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO37_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO38_RISING 6:6 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO38_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO38_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO38_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO39_RISING 7:7 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO39_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO39_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO39_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO_RISING_NOP 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO_RISING_FORWARD 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO32_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO32_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO32_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO32_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO33_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO33_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO33_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO33_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO34_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO34_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO34_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO34_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO35_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO35_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO35_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO35_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO36_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO36_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO36_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO36_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO37_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO37_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO37_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO37_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO38_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO38_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO38_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO38_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO39_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO39_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO39_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO39_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO_FALLING_NOP 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_3_GPIO_FALLING_FORWARD 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST(i) (0x00021728+ (i)*(0x00021738-0x00021728)) /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST__SIZE_1 3 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_RISING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_RISING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_RISING_BIT(i) ((i)%16) /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_RISING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_FALLING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_FALLING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_FALLING_BIT(i) ((i)%16+16) /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_FALLING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2RM_GPIO_LIST_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3 0x0002174C /* RWI4R */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO32_RISING 0:0 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO32_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO32_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO32_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO33_RISING 1:1 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO33_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO33_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO33_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO34_RISING 2:2 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO34_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO34_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO34_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO35_RISING 3:3 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO35_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO35_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO35_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO36_RISING 4:4 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO36_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO36_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO36_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO37_RISING 5:5 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO37_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO37_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO37_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO38_RISING 6:6 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO38_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO38_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO38_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO39_RISING 7:7 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO39_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO39_RISING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO39_RISING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO_RISING(i) ((i)-16):((i)-16) /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO_RISING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO_RISING_NOP 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO_RISING_FORWARD 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO32_FALLING 16:16 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO32_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO32_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO32_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO33_FALLING 17:17 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO33_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO33_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO33_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO34_FALLING 18:18 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO34_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO34_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO34_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO35_FALLING 19:19 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO35_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO35_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO35_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO36_FALLING 20:20 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO36_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO36_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO36_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO37_FALLING 21:21 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO37_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO37_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO37_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO38_FALLING 22:22 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO38_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO38_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO38_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO39_FALLING 23:23 /* RWIVF */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO39_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO39_FALLING_NOP 0x00000000 /* RW--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO39_FALLING_FORWARD 0x00000001 /* -W--V */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO_FALLING(i) ((i)):((i)) /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO_FALLING__SIZE_1 16 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO_FALLING_NOP 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_3_GPIO_FALLING_FORWARD 0x00000001 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST(i) (0x0002172C+ (i)*(0x0002173C-0x0002172C)) /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST__SIZE_1 3 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_RISING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_RISING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_RISING_BIT(i) ((i)%16) /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_RISING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_FALLING_LIST(i) ((i)/16+1) /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_FALLING_LIST__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_FALLING_BIT(i) ((i)%16+16) /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_FALLING_BIT__SIZE_1 40 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_GPIO_RISING_DISABLED 0x00000000 /* */
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#define NV_GPIO_GSP_INTR_FWD2PMU_GPIO_LIST_GPIO_RISING_ENABLED 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_SPI 0x0000DEA0 /* RW-4R */
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#define NV_PMGR_GSP_INTR_SPI_SPI0 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_SPI_SPI0_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_GSP_INTR_SPI_SPI0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PMGR_GSP_INTR_SPI_SPI0_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_GSP_INTR_SPI_SPI0_RESET 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_SPI_SPI(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_GSP_INTR_SPI_SPI__SIZE_1 1 /* */
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#define NV_PMGR_GSP_INTR_SPI_SPI_NOT_PENDING 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_SPI_SPI_PENDING 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_SPI_SPI_RESET 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_MSK_SPI 0x0000DEA4 /* RW-4R */
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#define NV_PMGR_GSP_INTR_MSK_SPI_SPI0 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_MSK_SPI_SPI0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_MSK_SPI_SPI0_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_SPI_SPI0_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_GSP_INTR_MSK_SPI_SPI(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_GSP_INTR_MSK_SPI_SPI__SIZE_1 1 /* */
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#define NV_PMGR_GSP_INTR_MSK_SPI_SPI_DISABLED 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_MSK_SPI_SPI_ENABLED 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_SPI 0x0000DEA8 /* RW-4R */
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#define NV_PMGR_GSP_INTR_FWD2RM_SPI_SPI0 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2RM_SPI_SPI0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2RM_SPI_SPI0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_SPI_SPI0_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2RM_SPI_SPI(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_SPI_SPI__SIZE_1 1 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_SPI_SPI_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2RM_SPI_SPI_FORWARD 0x00000001 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_SPI 0x0000DEAC /* RW-4R */
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#define NV_PMGR_GSP_INTR_FWD2PMU_SPI_SPI0 0:0 /* RWIVF */
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#define NV_PMGR_GSP_INTR_FWD2PMU_SPI_SPI0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_SPI_SPI0_NOP 0x00000000 /* RW--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_SPI_SPI0_FORWARD 0x00000001 /* -W--V */
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#define NV_PMGR_GSP_INTR_FWD2PMU_SPI_SPI(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_SPI_SPI__SIZE_1 1 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_SPI_SPI_NOP 0x00000000 /* */
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#define NV_PMGR_GSP_INTR_FWD2PMU_SPI_SPI_FORWARD 0x00000001 /* */
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#define NV_PMGR_PWM0 0x0000E114 /* RW-4R */
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#define NV_PMGR_PWM0__PRIV_LEVEL_MASK 0x0000D7D4 /* */
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#define NV_PMGR_PWM0_PERIOD 23:0 /* RWIVF */
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#define NV_PMGR_PWM0_PERIOD_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PWM0_PERIOD_ZERO 0x00000001 /* RW--V */
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#define NV_PMGR_PWM0_PERIOD_MAX 0x00FFFFFF /* RW--V */
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#define NV_PMGR_PWM1 0x0000E118 /* RW-4R */
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#define NV_PMGR_PWM1__PRIV_LEVEL_MASK 0x0000D7D4 /* */
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#define NV_PMGR_PWM1_HI 23:0 /* RWIVF */
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#define NV_PMGR_PWM1_HI_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PWM1_HI_ZERO 0x00000000 /* RW--V */
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#define NV_PMGR_PWM1_NEW_REQUEST 30:30 /* RWIVF */
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#define NV_PMGR_PWM1_NEW_REQUEST_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_PWM1_NEW_REQUEST_TRIGGER 0x00000001 /* -W--V */
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#define NV_PMGR_PWM1_NEW_REQUEST_TRIGGER_DONE 0x00000000 /* R---V */
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#define NV_PMGR_PWM1_SETTING_NEW 31:31 /* R-IVF */
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#define NV_PMGR_PWM1_SETTING_NEW_DONE 0x00000000 /* R-I-V */
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#define NV_PMGR_PWM1_SETTING_NEW_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_FAN0 0x0000E11C /* RW-4R */
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#define NV_PMGR_FAN0__PRIV_LEVEL_MASK 0x0000D7DC /* */
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#define NV_PMGR_FAN0_PERIOD 23:0 /* RWIVF */
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#define NV_PMGR_FAN0_PERIOD_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_FAN0_PERIOD_ZERO 0x00000001 /* RW--V */
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#define NV_PMGR_FAN0_PERIOD_MAX 0x00FFFFFF /* RW--V */
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#define NV_PMGR_FAN1 0x0000E120 /* RW-4R */
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#define NV_PMGR_FAN1__PRIV_LEVEL_MASK 0x0000D7DC /* */
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#define NV_PMGR_FAN1_HI 23:0 /* RWIVF */
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#define NV_PMGR_FAN1_HI_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_FAN1_HI_ZERO 0x00000000 /* RW--V */
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#define NV_PMGR_FAN1_ALERT_OUTPUT_OVERRIDE 24:24 /* RWIVF */
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#define NV_PMGR_FAN1_ALERT_OUTPUT_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_FAN1_ALERT_OUTPUT_OVERRIDE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_FAN1_ALERT_OUTPUT_OVERRIDE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_FAN1_ALERT_OUTPUT_POLARITY 25:25 /* RWIVF */
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#define NV_PMGR_FAN1_ALERT_OUTPUT_POLARITY_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_FAN1_ALERT_OUTPUT_POLARITY_LO 0x00000000 /* RW--V */
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#define NV_PMGR_FAN1_ALERT_OUTPUT_POLARITY_HI 0x00000001 /* RW--V */
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#define NV_PMGR_FAN1_NEW_REQUEST 30:30 /* RWIVF */
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#define NV_PMGR_FAN1_NEW_REQUEST_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_FAN1_NEW_REQUEST_TRIGGER 0x00000001 /* -W--V */
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#define NV_PMGR_FAN1_NEW_REQUEST_TRIGGER_DONE 0x00000000 /* R---V */
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#define NV_PMGR_FAN1_SETTING_NEW 31:31 /* R-IVF */
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#define NV_PMGR_FAN1_SETTING_NEW_DONE 0x00000000 /* R-I-V */
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#define NV_PMGR_FAN1_SETTING_NEW_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_LDT_BIAS_CTRL 0x0000E184 /* RW-4R */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_UPDATE 29:29 /* RWIVF */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_UPDATE_DEFAULT 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_UPDATE_EN 0x00000001 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_UPDATE_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_OVERRIDE 28:28 /* RWIVF */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_OVERRIDE_DEFAULT 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_OVERRIDE_ON 0x00000001 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_OVERRIDE_OFF 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_UPDATE 27:27 /* RWIVF */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_UPDATE_DEFAULT 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_UPDATE_EN 0x00000001 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_UPDATE_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_OVERRIDE 26:26 /* RWIVF */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_OVERRIDE_DEFAULT 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_OVERRIDE_ON 0x00000001 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_OVERRIDE_OFF 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_UPDATE 25:25 /* RWIVF */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_UPDATE_DEFAULT 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_UPDATE_EN 0x00000001 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_UPDATE_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_OVERRIDE 24:24 /* RWIVF */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_OVERRIDE_DEFAULT 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_OVERRIDE_ON 0x00000001 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_OVERRIDE_OFF 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_OVERRIDE_VAL 23:20 /* RWIVF */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_OVERRIDE_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_OVERRIDE_VAL_DEFAULT 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RNBIAS_OVERRIDE_VAL_0 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_OVERRIDE_VAL 19:16 /* RWIVF */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_OVERRIDE_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_OVERRIDE_VAL_DEFAULT 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RPBIAS_OVERRIDE_VAL_0 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_OVERRIDE_VAL 15:12 /* RWIVF */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_OVERRIDE_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_OVERRIDE_VAL_DEFAULT 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_RBBIAS_OVERRIDE_VAL_0 0x00000000 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_BIAS_PERIOD 11:0 /* RWIVF */
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#define NV_PMGR_LDT_BIAS_CTRL_BIAS_PERIOD_INIT 0x00000012 /* RWI-V */
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#define NV_PMGR_LDT_BIAS_CTRL_BIAS_PERIOD_DEFAULT 0x00000012 /* RW--V */
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#define NV_PMGR_LDT_BIAS_CTRL_BIAS_PERIOD_18US 0x00000012 /* RW--V */
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#define NV_PMGR_LDT_BIAS_STATUS 0x0000E188 /* R--4R */
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#define NV_PMGR_LDT_BIAS_STATUS_RNBIAS_STATUS 11:8 /* R--VF */
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#define NV_PMGR_LDT_BIAS_STATUS_RNBIAS_STATUS_0 0x00000000 /* R---V */
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#define NV_PMGR_LDT_BIAS_STATUS_RPBIAS_STATUS 7:4 /* R--VF */
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#define NV_PMGR_LDT_BIAS_STATUS_RPBIAS_STATUS_0 0x00000000 /* R---V */
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#define NV_PMGR_LDT_BIAS_STATUS_RBBIAS_STATUS 3:0 /* R--VF */
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#define NV_PMGR_LDT_BIAS_STATUS_RBBIAS_STATUS_0 0x00000000 /* R---V */
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#define NV_PMGR_CLK_SELECTS 0x0000E18C /* RW-4R */
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#define NV_PMGR_CLK_SELECTS_XTAL_OUT_E_DIFF 20:20 /* RWEVF */
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#define NV_PMGR_CLK_SELECTS_XTAL_OUT_E_DIFF_INIT 0x00000000 /* RWE-V */
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#define NV_PMGR_CLK_SELECTS_XTAL_OUT_E_DIFF_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_CLK_SELECTS_XTAL_OUT_E_DIFF_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_CLK_DEBUG 0x0000E190 /* RW-4R */
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#define NV_PMGR_CLK_DEBUG_PREVENT_FLATLINE 0:0 /* RWIVF */
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#define NV_PMGR_CLK_DEBUG_PREVENT_FLATLINE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CLK_DEBUG_PREVENT_FLATLINE_NO 0x00000000 /* RW--V */
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#define NV_PMGR_CLK_DEBUG_PREVENT_FLATLINE_YES 0x00000001 /* RW--V */
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#define NV_PMGR_DEBUG_CTL 0x0000E194 /* RW-4R */
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#define NV_PMGR_DEBUG_CTL_MODE 0:0 /* RWIVF */
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#define NV_PMGR_DEBUG_CTL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DEBUG_CTL_MODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DEBUG_CTL_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DEBUG_READ 0x0000E198 /* R--4R */
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#define NV_PMGR_DEBUG_READ_DATA 15:0 /* R-XUF */
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#define NV_PMGR_DEBUG_SEL_0 0x0000E19C /* RW-4R */
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#define NV_PMGR_DEBUG_SEL_0_X 3:0 /* RWXUF */
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#define NV_PMGR_DEBUG_SEL_1 0x0000E1A0 /* RW-4R */
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#define NV_PMGR_DEBUG_SEL_1_X 3:0 /* RWXUF */
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#define NV_PMGR_DEBUG_SEL_2 0x0000E1A4 /* RW-4R */
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#define NV_PMGR_DEBUG_SEL_2_X 3:0 /* RWXUF */
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#define NV_PMGR_DEBUG_SEL_3 0x0000E1A8 /* RW-4R */
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#define NV_PMGR_DEBUG_SEL_3_SWAP 0:0 /* */
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#define NV_PMGR_DEBUG_SEL_3_SWAP_NORMAL 0x00000000 /* */
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#define NV_PMGR_DEBUG_SEL_3_SWAP_7_0_15_8 0x00000001 /* */
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#define NV_PMGR_DEBUG_SEL_3_X 3:0 /* RWXUF */
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#define NV_PMGR_TESTCLK_BYPCTRL 0x0000E1AC /* RW-4R */
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#define NV_PMGR_TESTCLK_BYPCTRL_CAPCLK 0:0 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_CAPCLK_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_CAPCLK_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_CAPCLK_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_DAC0CLK 1:1 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_DAC0CLK_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_DAC0CLK_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_DAC0CLK_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_DISPCLK 2:2 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_DISPCLK_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_DISPCLK_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_DISPCLK_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SPPLL0 3:3 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_SPPLL0_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SPPLL0_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SPPLL0_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SPPLL1 4:4 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_SPPLL1_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SPPLL1_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_GVCLK 5:5 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_GVCLK_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_GVCLK_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_GVCLK_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_ORCLK 6:6 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_ORCLK_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_ORCLK_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_ORCLK_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_RG0CLK 7:7 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_RG0CLK_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_RG0CLK_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_RG0CLK_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_RG1CLK 8:8 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_RG1CLK_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_RG1CLK_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_RG1CLK_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SOR_SCLK 9:9 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_SOR_SCLK_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SOR_SCLK_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SOR_SCLK_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SORCLK 10:10 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_SORCLK_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SORCLK_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SORCLK_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SYNC 11:11 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_SYNC_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SYNC_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SYNC_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_VPLL0 12:12 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_VPLL0_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_VPLL0_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_VPLL0_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_VPLL1 13:13 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_VPLL1_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_VPLL1_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_VPLL1_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_GVPLL 14:14 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_GVPLL_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_GVPLL_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_GVPLL_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_GVRXCLK 15:15 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_GVRXCLK_BYP_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_GVRXCLK_BYP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_GVRXCLK_BYP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_MODE 17:16 /* RWIUF */
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#define NV_PMGR_TESTCLK_BYPCTRL_MODE_INIT 0x00000002 /* RWI-V */
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#define NV_PMGR_TESTCLK_BYPCTRL_MODE_NOBYPASS 0x00000002 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_MODE_BYPASS 0x00000000 /* RW--V */
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#define NV_PMGR_TESTCLK_BYPCTRL_SPARE 21:18 /* RW-UF */
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#define NV_PMGR_POWERCTRL_0 0x0000E1B0 /* RW-4R */
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#define NV_PMGR_POWERCTRL_0_FULLP_IDDQ 0:0 /* RWIUF */
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#define NV_PMGR_POWERCTRL_0_FULLP_IDDQ_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_POWERCTRL_0_FULLP_IDDQ_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_FULLP_IDDQ_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_FULLP_PULLDOWN 1:1 /* RWIUF */
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#define NV_PMGR_POWERCTRL_0_FULLP_PULLDOWN_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_POWERCTRL_0_FULLP_PULLDOWN_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_FULLP_PULLDOWN_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_FULLP_STPULLDOWN 2:2 /* RWIUF */
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#define NV_PMGR_POWERCTRL_0_FULLP_STPULLDOWN_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_POWERCTRL_0_FULLP_STPULLDOWN_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_FULLP_STPULLDOWN_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_FULLP_DPULLDOWN 3:3 /* RWIUF */
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#define NV_PMGR_POWERCTRL_0_FULLP_DPULLDOWN_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_POWERCTRL_0_FULLP_DPULLDOWN_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_FULLP_DPULLDOWN_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_SUSP_IDDQ 4:4 /* RWIUF */
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#define NV_PMGR_POWERCTRL_0_SUSP_IDDQ_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_POWERCTRL_0_SUSP_IDDQ_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_SUSP_IDDQ_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_SUSP_PULLDOWN 5:5 /* RWIUF */
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#define NV_PMGR_POWERCTRL_0_SUSP_PULLDOWN_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_POWERCTRL_0_SUSP_PULLDOWN_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_SUSP_PULLDOWN_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_SUSP_STPULLDOWN 6:6 /* RWIUF */
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#define NV_PMGR_POWERCTRL_0_SUSP_STPULLDOWN_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_POWERCTRL_0_SUSP_STPULLDOWN_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_SUSP_STPULLDOWN_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_SUSP_VREF 17:17 /* RWIUF */
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#define NV_PMGR_POWERCTRL_0_SUSP_VREF_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_POWERCTRL_0_SUSP_VREF_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_0_SUSP_VREF_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_2 0x0000E1B4 /* RW-4R */
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#define NV_PMGR_POWERCTRL_2_ENGINESTATE_DISP 1:0 /* RWIUF */
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#define NV_PMGR_POWERCTRL_2_ENGINESTATE_DISP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_POWERCTRL_2_ENGINESTATE_DISP_FULLPOWER 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_2_ENGINESTATE_DISP_AUTOMATIC 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_2_ENGINESTATE_DISP_DISABLED 0x00000003 /* RW--V */
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#define NV_PMGR_POWERCTRL_2_ENGINESTATE_CAP 3:2 /* RWIUF */
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#define NV_PMGR_POWERCTRL_2_ENGINESTATE_CAP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_POWERCTRL_2_ENGINESTATE_CAP_FULLPOWER 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_2_ENGINESTATE_CAP_AUTOMATIC 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_2_ENGINESTATE_CAP_DISABLED 0x00000003 /* RW--V */
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#define NV_PMGR_POWERCTRL_5 0x0000E1B8 /* RW-4R */
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#define NV_PMGR_POWERCTRL_5__PRIV_LEVEL_MASK 0x0000D7CC /* */
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#define NV_PMGR_POWERCTRL_5_I2C0_PAD_INPUT_RCV 16:16 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_I2C0_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_I2C0_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2C0_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2C1_PAD_INPUT_RCV 17:17 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_I2C1_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_I2C1_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2C1_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2C2_PAD_INPUT_RCV 18:18 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_I2C2_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_I2C2_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2C2_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2C3_PAD_INPUT_RCV 19:19 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_I2C3_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_I2C3_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2C3_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2C_0_PAD_INP_RCVR(i) (16+(i)):(16+(i)) /* */
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#define NV_PMGR_POWERCTRL_5_I2C_0_PAD_INP_RCVR__SIZE_1 4 /* */
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#define NV_PMGR_POWERCTRL_5_I2C_0_PAD_INP_RCVR_DIS 0x00000000 /* */
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#define NV_PMGR_POWERCTRL_5_I2C_0_PAD_INP_RCVR_EN 0x00000001 /* */
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#define NV_PMGR_POWERCTRL_5_HDCP_I2C_PAD_INPUT_RCV 20:20 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_HDCP_I2C_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_HDCP_I2C_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_HDCP_I2C_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2S0_PAD_INPUT_RCV 21:21 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_I2S0_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_I2S0_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2S0_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2S1_PAD_INPUT_RCV 22:22 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_I2S1_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_I2S1_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2S1_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_MIOA_PAD_INPUT_RCV 23:23 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_MIOA_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_MIOA_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_MIOA_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_MIOB_PAD_INPUT_RCV 24:24 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_MIOB_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_MIOB_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_MIOB_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_MIO_PAD_INPUT_RCV(i) (23+(i)):(23+(i)) /* */
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#define NV_PMGR_POWERCTRL_5_MIO_PAD_INPUT_RCV__SIZE_1 2 /* */
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#define NV_PMGR_POWERCTRL_5_MIO_PAD_INPUT_RCV_DIS 0x00000000 /* */
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#define NV_PMGR_POWERCTRL_5_MIO_PAD_INPUT_RCV_EN 0x00000001 /* */
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#define NV_PMGR_POWERCTRL_5_DRA_PAD_INPUT_RCV 25:25 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_DRA_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_DRA_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_DRA_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_DRB_PAD_INPUT_RCV 26:26 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_DRB_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_DRB_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_DRB_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_DR_PAD_INPUT_RCV(i) (25+(i)):(25+(i)) /* */
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#define NV_PMGR_POWERCTRL_5_DR_PAD_INPUT_RCV__SIZE_1 2 /* */
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#define NV_PMGR_POWERCTRL_5_DR_PAD_INPUT_RCV_DIS 0x00000000 /* */
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#define NV_PMGR_POWERCTRL_5_DR_PAD_INPUT_RCV_EN 0x00000001 /* */
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#define NV_PMGR_POWERCTRL_5_SWAPRDYA_PAD_INPUT_RCV 27:27 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_SWAPRDYA_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_SWAPRDYA_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_SWAPRDYA_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_SWAPRDYB_PAD_INPUT_RCV 28:28 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_SWAPRDYB_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_SWAPRDYB_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_SWAPRDYB_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_SWAPRDY_PAD_INPUT_RCV(i) (27+(i)):(27+(i)) /* */
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#define NV_PMGR_POWERCTRL_5_SWAPRDY_PAD_INPUT_RCV__SIZE_1 2 /* */
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#define NV_PMGR_POWERCTRL_5_SWAPRDY_PAD_INPUT_RCV_DIS 0x00000000 /* */
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#define NV_PMGR_POWERCTRL_5_SWAPRDY_PAD_INPUT_RCV_EN 0x00000001 /* */
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#define NV_PMGR_POWERCTRL_5_I2C4_PAD_INPUT_RCV 29:29 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_I2C4_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_I2C4_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2C4_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2C5_PAD_INPUT_RCV 30:30 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_I2C5_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_I2C5_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2C5_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_DBG_DATA_PAD_INPUT_RCV 31:31 /* RWIVF */
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#define NV_PMGR_POWERCTRL_5_DBG_DATA_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_POWERCTRL_5_DBG_DATA_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_DBG_DATA_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_POWERCTRL_5_I2C_1_PAD_INP_RCVR(i) (29+(i)):(29+(i)) /* */
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#define NV_PMGR_POWERCTRL_5_I2C_1_PAD_INP_RCVR__SIZE_1 2 /* */
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#define NV_PMGR_POWERCTRL_5_I2C_1_PAD_INP_RCVR_DIS 0x00000000 /* */
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#define NV_PMGR_POWERCTRL_5_I2C_1_PAD_INP_RCVR_EN 0x00000001 /* */
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#define NV_GPIO_FILTER_COUNT 0x00021808 /* RWI4R */
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#define NV_GPIO_FILTER_COUNT__PRIV_LEVEL_MASK 0x00021800 /* */
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#define NV_GPIO_FILTER_COUNT_LIMIT 5:0 /* RWIVF */
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#define NV_GPIO_FILTER_COUNT_LIMIT_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_FILTER_COUNT_LIMIT_DEFAULT 0x00000001 /* RW--V */
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#define NV_PMGR_GV_UPSTREAM_CREDIT_CYCLE 0x0000E1C0 /* RW-4R */
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#define NV_PMGR_GV_UPSTREAM_CREDIT_CYCLE_COUNT 5:0 /* RWIUF */
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#define NV_PMGR_GV_UPSTREAM_CREDIT_CYCLE_COUNT_INIT 0x00000002 /* RWI-V */
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#define NV_PMGR_JTAG_ACCESS_CTRL 0x0000E1C4 /* RW-4R */
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#define NV_PMGR_JTAG_ACCESS_CTRL_INSTR_ID 7:0 /* RW-UF */
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#define NV_PMGR_JTAG_ACCESS_CTRL_REG_LENGTH 17:8 /* RW-UF */
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#define NV_PMGR_JTAG_ACCESS_CTRL_DWORD_EN 22:18 /* RW-UF */
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#define NV_PMGR_JTAG_ACCESS_CTRL_CTRL_STATUS 30:30 /* RW-UF */
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#define NV_PMGR_JTAG_ACCESS_CTRL_REQ_CTRL 31:31 /* RW-UF */
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#define NV_PMGR_JTAG_ACCESS_DATA 0x0000E1C8 /* RW-4R */
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#define NV_PMGR_JTAG_ACCESS_DATA_VALUE 31:0 /* RW-VF */
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#define NV_PMGR_GV_PRI_TIMEOUT 0x0000E1D8 /* RW-4R */
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#define NV_PMGR_GV_PRI_TIMEOUT_CYCLES 3:0 /* RWIVF */
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#define NV_PMGR_GV_PRI_TIMEOUT_CYCLES_INIT 0x0000000f /* RWI-V */
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#define NV_PMGR_GV_PRI_TIMEOUT_CYCLES_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_GV_PRI_TIMEOUT_CYCLES_MAX 0x0000000f /* RW--V */
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#define NV_PMGR_GV_PRI_TIMEOUT_EN 4:4 /* RWIVF */
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#define NV_PMGR_GV_PRI_TIMEOUT_EN_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_GV_PRI_TIMEOUT_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_GV_PRI_TIMEOUT_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_EXT_RESET 0x0000E1DC /* RW-4R */
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#define NV_PMGR_EXT_RESET_EXT_DEVICES 0:0 /* RWIVF */
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#define NV_PMGR_EXT_RESET_EXT_DEVICES_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_EXT_RESET_EXT_DEVICES_ASSERT 0x00000000 /* RW--V */
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#define NV_PMGR_EXT_RESET_EXT_DEVICES_DEASSERT 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_IN 0x0000E1E0 /* R--4R */
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#define NV_PMGR_CYA_SPARE_IN_BIT0 0:0 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT0_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT0_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT1 1:1 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT1_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT1_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT2 2:2 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT2_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT2_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT3 3:3 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT3_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT3_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT4 4:4 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT4_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT4_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT5 5:5 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT5_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT5_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT6 6:6 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT6_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT6_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT7 7:7 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT7_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT7_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT8 8:8 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT8_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT8_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT9 9:9 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT9_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT9_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT10 10:10 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT10_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT10_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT11 11:11 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT11_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT11_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT12 12:12 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT12_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT12_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT13 13:13 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT13_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT13_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT14 14:14 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT14_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT14_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT15 15:15 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT15_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT15_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT16 16:16 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT16_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT16_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT17 17:17 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT17_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT17_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT18 18:18 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT18_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT18_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT19 19:19 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT19_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT19_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT20 20:20 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT20_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT20_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT21 21:21 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT21_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT21_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT22 22:22 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT22_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT22_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT23 23:23 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT23_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT23_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT24 24:24 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT24_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT24_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT25 25:25 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT25_0 0x00000000 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT25_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT26 26:26 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT26_0 0x00000000 /* R---V */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT26_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT27 27:27 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT27_0 0x00000000 /* R---V */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT27_1 0x00000001 /* R---V */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT28 28:28 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT28_0 0x00000000 /* R---V */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT28_1 0x00000001 /* R---V */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT29 29:29 /* R--VF */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT29_0 0x00000000 /* R---V */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT29_1 0x00000001 /* R---V */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT30 30:30 /* R--VF */
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#define NV_PMGR_CYA_SPARE_IN_BIT30_0 0x00000000 /* R---V */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT30_1 0x00000001 /* R---V */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT31 31:31 /* R--VF */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT31_0 0x00000000 /* R---V */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT31_1 0x00000001 /* R---V */
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#define NV_PMGR_CYA_SPARE_IN_BIT(i) (0+(i)):(0+(i)) /* */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT__SIZE_1 32 /* */
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#define NV_PMGR_CYA_SPARE_IN_BIT_0 0x00000000 /* */
|
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#define NV_PMGR_CYA_SPARE_IN_BIT_1 0x00000001 /* */
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#define NV_PMGR_CYA_SPARE_OUT 0x0000E1E4 /* RW-4R */
|
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#define NV_PMGR_CYA_SPARE_OUT_BIT0 0:0 /* RWIVF */
|
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#define NV_PMGR_CYA_SPARE_OUT_BIT0_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT0_0 0x00000000 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT0_1 0x00000001 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT1 1:1 /* RWIVF */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT1_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT1_0 0x00000000 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT1_1 0x00000001 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT2 2:2 /* RWIVF */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT2_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT2_0 0x00000000 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT2_1 0x00000001 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT3 3:3 /* RWIVF */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT3_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT3_0 0x00000000 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT3_1 0x00000001 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT4 4:4 /* RWIVF */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT4_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT4_0 0x00000000 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT4_1 0x00000001 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT5 5:5 /* RWIVF */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT5_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT5_0 0x00000000 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT5_1 0x00000001 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT6 6:6 /* RWIVF */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT6_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT6_0 0x00000000 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT6_1 0x00000001 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT7 7:7 /* RWIVF */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT7_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT7_0 0x00000000 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT7_1 0x00000001 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT8 8:8 /* RWIVF */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT8_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT8_0 0x00000000 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT8_1 0x00000001 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT9 9:9 /* RWIVF */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT9_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT9_0 0x00000000 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT9_1 0x00000001 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT10 10:10 /* RWIVF */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT10_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT10_0 0x00000000 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT10_1 0x00000001 /* RW--V */
|
|
#define NV_PMGR_CYA_SPARE_OUT_BIT11 11:11 /* RWIVF */
|
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#define NV_PMGR_CYA_SPARE_OUT_BIT11_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT11_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT11_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT12 12:12 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT12_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT12_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT12_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT13 13:13 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT13_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT13_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT13_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT14 14:14 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT14_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT14_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT14_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT15 15:15 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT15_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT15_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT15_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT16 16:16 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT16_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT16_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT16_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT17 17:17 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT17_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT17_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT17_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT18 18:18 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT18_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT18_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT18_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT19 19:19 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT19_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT19_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT19_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT20 20:20 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT20_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT20_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT20_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT21 21:21 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT21_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT21_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT21_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT22 22:22 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT22_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT22_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT22_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT23 23:23 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT23_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT23_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT23_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT24 24:24 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT24_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT24_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT24_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT25 25:25 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT25_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT25_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT25_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT26 26:26 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT26_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT26_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT26_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT27 27:27 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT27_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT27_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT27_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT28 28:28 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT28_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT28_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT28_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT29 29:29 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT29_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT29_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT29_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT30 30:30 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT30_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT30_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT30_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT31 31:31 /* RWIVF */
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#define NV_PMGR_CYA_SPARE_OUT_BIT31_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT31_0 0x00000000 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT31_1 0x00000001 /* RW--V */
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#define NV_PMGR_CYA_SPARE_OUT_BIT(i) (0+(i)):(0+(i)) /* */
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#define NV_PMGR_CYA_SPARE_OUT_BIT__SIZE_1 32 /* */
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#define NV_PMGR_CYA_SPARE_OUT_BIT_0 0x00000000 /* */
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#define NV_PMGR_CYA_SPARE_OUT_BIT_1 0x00000001 /* */
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#define NV_PMGR_CAP_AFE_CTRL 0x0000E1E8 /* RW-4R */
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#define NV_PMGR_CAP_AFE_CTRL_POWERDOWN 0:0 /* RWIVF */
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#define NV_PMGR_CAP_AFE_CTRL_POWERDOWN_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_CAP_AFE_CTRL_POWERDOWN_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_CAP_AFE_CTRL_POWERDOWN_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_VCLK0_DIV 0x0000E1EC /* RW-4R */
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#define NV_PMGR_VCLK0_DIV_SEL 2:0 /* RWIVF */
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#define NV_PMGR_VCLK0_DIV_SEL_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_VCLK0_DIV_SEL_DIV1 0x00000000 /* RW--V */
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#define NV_PMGR_VCLK0_DIV_SEL_DIV2 0x00000001 /* RW--V */
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#define NV_PMGR_VCLK0_DIV_SEL_DIV4 0x00000002 /* RW--V */
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#define NV_PMGR_VCLK0_DIV_SEL_DIV8 0x00000003 /* RW--V */
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#define NV_PMGR_VCLK1_DIV 0x0000E1F0 /* RW-4R */
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#define NV_PMGR_VCLK1_DIV_SEL 2:0 /* RWIVF */
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#define NV_PMGR_VCLK1_DIV_SEL_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_VCLK1_DIV_SEL_DIV1 0x00000000 /* RW--V */
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#define NV_PMGR_VCLK1_DIV_SEL_DIV2 0x00000001 /* RW--V */
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#define NV_PMGR_VCLK1_DIV_SEL_DIV4 0x00000002 /* RW--V */
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#define NV_PMGR_VCLK1_DIV_SEL_DIV8 0x00000003 /* RW--V */
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#define NV_PMGR_VCLK2_DIV 0x0000E238 /* RW-4R */
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#define NV_PMGR_VCLK2_DIV_SEL 2:0 /* RWIVF */
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#define NV_PMGR_VCLK2_DIV_SEL_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_VCLK2_DIV_SEL_DIV1 0x00000000 /* RW--V */
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#define NV_PMGR_VCLK2_DIV_SEL_DIV2 0x00000001 /* RW--V */
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#define NV_PMGR_VCLK2_DIV_SEL_DIV4 0x00000002 /* RW--V */
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#define NV_PMGR_VCLK2_DIV_SEL_DIV8 0x00000003 /* RW--V */
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#define NV_PMGR_VCLK3_DIV 0x0000E23C /* RW-4R */
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#define NV_PMGR_VCLK3_DIV_SEL 2:0 /* RWIVF */
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#define NV_PMGR_VCLK3_DIV_SEL_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_VCLK3_DIV_SEL_DIV1 0x00000000 /* RW--V */
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#define NV_PMGR_VCLK3_DIV_SEL_DIV2 0x00000001 /* RW--V */
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#define NV_PMGR_VCLK3_DIV_SEL_DIV4 0x00000002 /* RW--V */
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#define NV_PMGR_VCLK3_DIV_SEL_DIV8 0x00000003 /* RW--V */
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#define NV_PMGR_SPPLL0_2GVPLL_DIVSEL 0x0000E1F8 /* RW-4R */
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#define NV_PMGR_SPPLL0_2GVPLL_DIVSEL_DIV 2:0 /* RWIVF */
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#define NV_PMGR_SPPLL0_2GVPLL_DIVSEL_DIV_INIT 0x00000002 /* RWI-V */
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#define NV_PMGR_SPPLL0_2GVPLL_DIVSEL_DIV_DIVBY1 0x00000000 /* RW--V */
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#define NV_PMGR_SPPLL0_2GVPLL_DIVSEL_DIV_DIVBY2 0x00000001 /* RW--V */
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#define NV_PMGR_SPPLL0_2GVPLL_DIVSEL_DIV_DIVBY4 0x00000002 /* RW--V */
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#define NV_PMGR_SPPLL0_2GVPLL_DIVSEL_DIV_DIVBY8 0x00000003 /* RW--V */
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#define NV_PMGR_SPPLL1_2GVPLL_DIVSEL 0x0000E1FC /* RW-4R */
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#define NV_PMGR_SPPLL1_2GVPLL_DIVSEL_DIV 2:0 /* RWIVF */
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#define NV_PMGR_SPPLL1_2GVPLL_DIVSEL_DIV_INIT 0x00000002 /* RWI-V */
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#define NV_PMGR_SPPLL_2GVPLL_DIVSEL(i) 0x0000E1F8 +(i)* 4 /* */
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#define NV_PMGR_SPPLL_2GVPLL_DIVSEL__SIZE_1 2 /* */
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#define NV_PMGR_MIOIO_PADCTL 0x0000E600 /* RW-4R */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_PULLDOWN 4:0 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_PULLDOWN_INIT 0x00000019 /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_PULLDOWN_3V 0x00000019 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_PULLDOWN_1X2XAGP2 0x0000001f /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_TERM 5:5 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_TERM_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_TERM_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_TERM_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_EPREAMP 6:6 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_EPREAMP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_EPREAMP_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_EPREAMP_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_ECTT 7:7 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_ECTT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_ECTT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_ECTT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_PULLUP 12:8 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_PULLUP_INIT 0x0000000f /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_PULLUP_3V 0x0000000f /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_PULLUP_1X2XAGP2 0x00000013 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_E33V 13:13 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_E33V_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_E33V_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_E33V_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_SEL_E33V 14:14 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_SEL_E33V_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_SEL_E33V_STRAP 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_SEL_E33V_SW 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_VREF 15:15 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_VREF_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_VREF_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOA_VREF_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_PULLDOWN 20:16 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_PULLDOWN_INIT 0x00000019 /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_PULLDOWN_3V 0x00000019 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_PULLDOWN_1X2XAGP2 0x0000001f /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_TERM 21:21 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_TERM_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_TERM_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_TERM_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_EPREAMP 22:22 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_EPREAMP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_EPREAMP_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_EPREAMP_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_ECTT 23:23 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_ECTT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_ECTT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_ECTT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_PULLUP 28:24 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_PULLUP_INIT 0x0000000f /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_PULLUP_3V 0x0000000f /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_PULLUP_1X2XAGP2 0x00000013 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_E33V 29:29 /* RWIVF */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_E33V_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_E33V_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_PADCTL_MIOB_E33V_ENABLED 0x00000001 /* RW--V */
|
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#define NV_PMGR_MIOIO_PADCTL_MIOB_SEL_E33V 30:30 /* RWIVF */
|
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#define NV_PMGR_MIOIO_PADCTL_MIOB_SEL_E33V_INIT 0x00000000 /* RWI-V */
|
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#define NV_PMGR_MIOIO_PADCTL_MIOB_SEL_E33V_STRAP 0x00000000 /* RW--V */
|
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#define NV_PMGR_MIOIO_PADCTL_MIOB_SEL_E33V_SW 0x00000001 /* RW--V */
|
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#define NV_PMGR_MIOIO_PADCTL_MIOB_VREF 31:31 /* RWIVF */
|
|
#define NV_PMGR_MIOIO_PADCTL_MIOB_VREF_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_MIOIO_PADCTL_MIOB_VREF_DISABLED 0x00000000 /* RW--V */
|
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#define NV_PMGR_MIOIO_PADCTL_MIOB_VREF_ENABLED 0x00000001 /* RW--V */
|
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#define NV_PMGR_MIOIO_PADCTL_PULLDOWN(i) 4+(16*(i)):0+(16*(i)) /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_PULLDOWN__SIZE_1 2 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_PULLDOWN_3V 0x00000019 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_PULLDOWN_1X2XAGP2 0x0000001f /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_TERM(i) 5+(16*(i)):5+(16*(i)) /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_TERM__SIZE_1 2 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_TERM_DISABLED 0x00000000 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_TERM_ENABLED 0x00000001 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_EPREAMP(i) 6+(16*(i)):6+(16*(i)) /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_EPREAMP__SIZE_1 2 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_EPREAMP_DISABLED 0x00000000 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_EPREAMP_ENABLED 0x00000001 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_ECTT(i) 7+(16*(i)):7+(16*(i)) /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_ECTT__SIZE_1 2 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_ECTT_DISABLED 0x00000000 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_ECTT_ENABLED 0x00000001 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_PULLUP(i) 12+(16*(i)):8+(16*(i)) /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_PULLUP__SIZE_1 2 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_PULLUP_3V 0x0000000f /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_PULLUP_1X2XAGP2 0x00000013 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_E33V(i) 13+(16*(i)):13+(16*(i)) /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_E33V__SIZE_1 2 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_E33V_DISABLED 0x00000000 /* */
|
|
#define NV_PMGR_MIOIO_PADCTL_E33V_ENABLED 0x00000001 /* */
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#define NV_PMGR_MIOIO_PADCTL_SEL_E33V(i) 14+(16*(i)):14+(16*(i)) /* */
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#define NV_PMGR_MIOIO_PADCTL_SEL_E33V__SIZE_1 2 /* */
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#define NV_PMGR_MIOIO_PADCTL_SEL_E33V_STRAP 0x00000000 /* */
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#define NV_PMGR_MIOIO_PADCTL_SEL_E33V_SW 0x00000001 /* */
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#define NV_PMGR_MIOIO_PADCTL_VREF(i) 15+(16*(i)):15+(16*(i)) /* */
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#define NV_PMGR_MIOIO_PADCTL_VREF__SIZE_1 2 /* */
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#define NV_PMGR_MIOIO_PADCTL_VREF_DISABLED 0x00000000 /* */
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#define NV_PMGR_MIOIO_PADCTL_VREF_ENABLED 0x00000001 /* */
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#define NV_PMGR_MIOIO_A(i) (0x0000E60C+(i)*12) /* RW-4A */
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#define NV_PMGR_MIOIO_A__SIZE_1 2 /* */
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#define NV_PMGR_MIOIO_A_SLEW_FALL 4:0 /* RWIVF */
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#define NV_PMGR_MIOIO_A_SLEW_FALL_INIT 0x0000000A /* RWI-V */
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#define NV_PMGR_MIOIO_A_SLEW_FALL_FORCE_BYP_OR_CAL 6:6 /* RWIVF */
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#define NV_PMGR_MIOIO_A_SLEW_FALL_FORCE_BYP_OR_CAL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_A_SLEW_FALL_FORCE_BYP_OR_CAL_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_A_SLEW_FALL_FORCE_BYP_OR_CAL_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_A_SLEW_FALL_BYP 7:7 /* RWIVF */
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#define NV_PMGR_MIOIO_A_SLEW_FALL_BYP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_A_SLEW_FALL_BYP_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_A_SLEW_FALL_BYP_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_A_SLEW_RISE 12:8 /* RWIVF */
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#define NV_PMGR_MIOIO_A_SLEW_RISE_INIT 0x0000000A /* RWI-V */
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#define NV_PMGR_MIOIO_A_SLEW_RISE_FORCE_BYP_OR_CAL 14:14 /* RWIVF */
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#define NV_PMGR_MIOIO_A_SLEW_RISE_FORCE_BYP_OR_CAL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_A_SLEW_RISE_FORCE_BYP_OR_CAL_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_A_SLEW_RISE_FORCE_BYP_OR_CAL_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_A_SLEW_RISE_BYP 15:15 /* RWIVF */
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#define NV_PMGR_MIOIO_A_SLEW_RISE_BYP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_A_SLEW_RISE_BYP_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_A_SLEW_RISE_BYP_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_A_VDDQ 31:31 /* RWIVF */
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#define NV_PMGR_MIOIO_A_VDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_MIOIO_A_VDDQ_33 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_A_VDDQ_18 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_B(i) (0x0000E610+(i)*12) /* RW-4A */
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#define NV_PMGR_MIOIO_B__SIZE_1 2 /* */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD 3:0 /* RWIVF */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD_INIT 0x00000009 /* RWI-V */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD_0MS 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD_1MS 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD_2MS 0x00000002 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD_4MS 0x00000003 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD_8MS 0x00000004 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD_16MS 0x00000005 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD_32MS 0x00000006 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD_64MS 0x00000007 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD_128MS 0x00000008 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD_256MS 0x00000009 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD_512MS 0x0000000a /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_PERIOD_DISABLED 0x0000000f /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_FIXED_PD 8:4 /* RWIVF */
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#define NV_PMGR_MIOIO_B_MIOCAL_FIXED_PD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_B_MIOCAL_FIXED_PD_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_FIXED_PD_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_FIXED_PU 14:10 /* RWIVF */
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#define NV_PMGR_MIOIO_B_MIOCAL_FIXED_PU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_B_MIOCAL_FIXED_PU_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_FIXED_PU_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_USE_FIXED 16:16 /* RWIVF */
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#define NV_PMGR_MIOIO_B_MIOCAL_USE_FIXED_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_B_MIOCAL_USE_FIXED_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_USE_FIXED_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_FORCE_BYP_OR_CAL 17:17 /* RWIVF */
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#define NV_PMGR_MIOIO_B_MIOCAL_FORCE_BYP_OR_CAL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_B_MIOCAL_FORCE_BYP_OR_CAL_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_FORCE_BYP_OR_CAL_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_ON_RESUME 18:18 /* RWIVF */
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#define NV_PMGR_MIOIO_B_MIOCAL_ON_RESUME_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_B_MIOCAL_ON_RESUME_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_ON_RESUME_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_COMP 19:19 /* RWIVF */
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#define NV_PMGR_MIOIO_B_MIOCAL_COMP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_B_MIOCAL_COMP_INVALID 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_COMP_VALID 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_B_MIOCAL_COMPUTED_PD 24:20 /* R--VF */
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#define NV_PMGR_MIOIO_B_MIOCAL_COMPUTED_PD_MIN 0x00000000 /* R---V */
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#define NV_PMGR_MIOIO_B_MIOCAL_COMPUTED_PD_MAX 0x0000001f /* R---V */
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#define NV_PMGR_MIOIO_B_MIOCAL_COMPUTED_PU 30:26 /* R--VF */
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#define NV_PMGR_MIOIO_B_MIOCAL_COMPUTED_PU_MIN 0x00000000 /* R---V */
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#define NV_PMGR_MIOIO_B_MIOCAL_COMPUTED_PU_MAX 0x0000001f /* R---V */
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#define NV_PMGR_MIOIO_C(i) (0x0000E614+(i)*12) /* RW-4A */
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#define NV_PMGR_MIOIO_C__SIZE_1 2 /* */
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#define NV_PMGR_MIOIO_C_MIOCAL_STRENGTH 4:0 /* RWIVF */
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#define NV_PMGR_MIOIO_C_MIOCAL_STRENGTH_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_C_MIOCAL_STRENGTH_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_C_MIOCAL_STRENGTH_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_MIOIO_C_MIOCAL_TESTMODE 8:8 /* RWIVF */
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#define NV_PMGR_MIOIO_C_MIOCAL_TESTMODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_C_MIOCAL_TESTMODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_C_MIOCAL_TESTMODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_MIOIO_C_MIOCAL_PD_STATUS 10:10 /* R--VF */
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#define NV_PMGR_MIOIO_C_MIOCAL_PD_STATUS_READY 0x00000000 /* R---V */
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#define NV_PMGR_MIOIO_C_MIOCAL_PD_STATUS_NOT_READY 0x00000001 /* R---V */
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#define NV_PMGR_MIOIO_C_MIOCAL_PU_STATUS 11:11 /* R--VF */
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#define NV_PMGR_MIOIO_C_MIOCAL_PU_STATUS_NOT_READY 0x00000000 /* R---V */
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#define NV_PMGR_MIOIO_C_MIOCAL_PU_STATUS_READY 0x00000001 /* R---V */
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#define NV_PMGR_MIOIO_C_MIOCAL_MINCAL_PD 16:12 /* RWIVF */
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#define NV_PMGR_MIOIO_C_MIOCAL_MINCAL_PD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_C_MIOCAL_MINCAL_PD_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_C_MIOCAL_MINCAL_PD_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_MIOIO_C_MIOCAL_MAXCAL_PD 21:17 /* RWIVF */
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#define NV_PMGR_MIOIO_C_MIOCAL_MAXCAL_PD_INIT 0x0000001f /* RWI-V */
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#define NV_PMGR_MIOIO_C_MIOCAL_MAXCAL_PD_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_C_MIOCAL_MAXCAL_PD_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_MIOIO_C_MIOCAL_MINCAL_PU 26:22 /* RWIVF */
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#define NV_PMGR_MIOIO_C_MIOCAL_MINCAL_PU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOIO_C_MIOCAL_MINCAL_PU_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_C_MIOCAL_MINCAL_PU_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_MIOIO_C_MIOCAL_MAXCAL_PU 31:27 /* RWIVF */
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#define NV_PMGR_MIOIO_C_MIOCAL_MAXCAL_PU_INIT 0x0000001f /* RWI-V */
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#define NV_PMGR_MIOIO_C_MIOCAL_MAXCAL_PU_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_MIOIO_C_MIOCAL_MAXCAL_PU_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_MIO_FREQ 0x0000E624 /* RW-4R */
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#define NV_PMGR_MIO_FREQ_DIV 6:0 /* RWIVF */
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#define NV_PMGR_MIO_FREQ_DIV_INIT 0x0000001A /* RWI-V */
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#define NV_PMGR_MIO_FREQ_DIV_DEFAULT 0x0000001A /* RW--V */
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#define NV_PMGR_VIP_CNTL 0x0000E630 /* RW-4R */
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#define NV_PMGR_VIP_CNTL_PIN_SET 1:0 /* RWIVF */
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#define NV_PMGR_VIP_CNTL_PIN_SET_NEITHER 0x00000000 /* RWI-V */
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#define NV_PMGR_VIP_CNTL_PIN_SET_A 0x00000001 /* RW--V */
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#define NV_PMGR_VIP_CNTL_PIN_SET_B 0x00000002 /* RW--V */
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#define NV_PMGR_MIOA_PADCTL 0x0000E638 /* RW-4R */
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#define NV_PMGR_MIOA_PADCTL_REG_LEVEL 1:0 /* RWIVF */
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#define NV_PMGR_MIOA_PADCTL_REG_LEVEL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOA_PADCTL_REG_LEVEL_DEFAULT 0x00000000 /* RW--V */
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#define NV_PMGR_MIOA_PADCTL_VREF_STD 2:2 /* RWIVF */
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#define NV_PMGR_MIOA_PADCTL_VREF_STD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOA_PADCTL_VREF_STD_DEFAULT 0x00000000 /* RW--V */
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#define NV_PMGR_MIOB_PADCTL 0x0000E63C /* RW-4R */
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#define NV_PMGR_MIOB_PADCTL_REG_LEVEL 1:0 /* RWIVF */
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#define NV_PMGR_MIOB_PADCTL_REG_LEVEL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOB_PADCTL_REG_LEVEL_DEFAULT 0x00000000 /* RW--V */
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#define NV_PMGR_MIOB_PADCTL_VREF_STD 2:2 /* RWIVF */
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#define NV_PMGR_MIOB_PADCTL_VREF_STD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MIOB_PADCTL_VREF_STD_DEFAULT 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL 0x0000E640 /* RW-4R */
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#define NV_PMGR_DRIO_PADCTL_DRA_PULLDOWN 4:0 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_DRA_PULLDOWN_INIT 0x00000019 /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_DRA_PULLDOWN_3V 0x00000019 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_PULLDOWN_1X2XAGP2 0x0000001f /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_TERM 5:5 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_DRA_TERM_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_DRA_TERM_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_TERM_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_EMCI 6:6 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_DRA_EMCI_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_DRA_EMCI_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_EMCI_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_ECTT 7:7 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_DRA_ECTT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_DRA_ECTT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_ECTT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_PULLUP 12:8 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_DRA_PULLUP_INIT 0x0000000f /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_DRA_PULLUP_3V 0x0000000f /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_PULLUP_1X2XAGP2 0x00000013 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_E25V 13:13 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_DRA_E25V_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_DRA_E25V_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_E25V_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_ESCH 14:14 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_DRA_ESCH_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_DRA_ESCH_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_ESCH_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_VREF 15:15 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_DRA_VREF_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_DRA_VREF_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRA_VREF_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRB_PULLDOWN 20:16 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_DRB_PULLDOWN_INIT 0x00000019 /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_DRB_PULLDOWN_3V 0x00000019 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRB_PULLDOWN_1X2XAGP2 0x0000001f /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRB_TERM 21:21 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_DRB_TERM_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_DRB_TERM_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRB_TERM_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRB_EMCI 22:22 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_DRB_EMCI_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_DRB_EMCI_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRB_EMCI_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRB_ECTT 23:23 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_DRB_ECTT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_DRB_ECTT_DISABLED 0x00000000 /* RW--V */
|
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#define NV_PMGR_DRIO_PADCTL_DRB_ECTT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRB_PULLUP 28:24 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_DRB_PULLUP_INIT 0x0000000f /* RWI-V */
|
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#define NV_PMGR_DRIO_PADCTL_DRB_PULLUP_3V 0x0000000f /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_DRB_PULLUP_1X2XAGP2 0x00000013 /* RW--V */
|
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#define NV_PMGR_DRIO_PADCTL_DRB_E25V 29:29 /* RWIVF */
|
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#define NV_PMGR_DRIO_PADCTL_DRB_E25V_INIT 0x00000000 /* RWI-V */
|
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#define NV_PMGR_DRIO_PADCTL_DRB_E25V_DISABLED 0x00000000 /* RW--V */
|
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#define NV_PMGR_DRIO_PADCTL_DRB_E25V_ENABLED 0x00000001 /* RW--V */
|
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#define NV_PMGR_DRIO_PADCTL_DRB_ESCH 30:30 /* RWIVF */
|
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#define NV_PMGR_DRIO_PADCTL_DRB_ESCH_INIT 0x00000000 /* RWI-V */
|
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#define NV_PMGR_DRIO_PADCTL_DRB_ESCH_DISABLED 0x00000000 /* RW--V */
|
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#define NV_PMGR_DRIO_PADCTL_DRB_ESCH_ENABLED 0x00000001 /* RW--V */
|
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#define NV_PMGR_DRIO_PADCTL_DRB_VREF 31:31 /* RWIVF */
|
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#define NV_PMGR_DRIO_PADCTL_DRB_VREF_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_DRIO_PADCTL_DRB_VREF_DISABLED 0x00000000 /* RW--V */
|
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#define NV_PMGR_DRIO_PADCTL_DRB_VREF_ENABLED 0x00000001 /* RW--V */
|
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#define NV_PMGR_DRIO_PADCTL_PULLDOWN(i) 4+(16*(i)):0+(16*(i)) /* */
|
|
#define NV_PMGR_DRIO_PADCTL_PULLDOWN__SIZE_1 2 /* */
|
|
#define NV_PMGR_DRIO_PADCTL_PULLDOWN_3V 0x00000019 /* */
|
|
#define NV_PMGR_DRIO_PADCTL_PULLDOWN_1X2XAGP2 0x0000001f /* */
|
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#define NV_PMGR_DRIO_PADCTL_TERM(i) 5+(16*(i)):5+(16*(i)) /* */
|
|
#define NV_PMGR_DRIO_PADCTL_TERM__SIZE_1 2 /* */
|
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#define NV_PMGR_DRIO_PADCTL_TERM_DISABLED 0x00000000 /* */
|
|
#define NV_PMGR_DRIO_PADCTL_TERM_ENABLED 0x00000001 /* */
|
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#define NV_PMGR_DRIO_PADCTL_EMCI(i) 6+(16*(i)):6+(16*(i)) /* */
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#define NV_PMGR_DRIO_PADCTL_EMCI__SIZE_1 2 /* */
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#define NV_PMGR_DRIO_PADCTL_EMCI_DISABLED 0x00000000 /* */
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#define NV_PMGR_DRIO_PADCTL_EMCI_ENABLED 0x00000001 /* */
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#define NV_PMGR_DRIO_PADCTL_ECTT(i) 7+(16*(i)):7+(16*(i)) /* */
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#define NV_PMGR_DRIO_PADCTL_ECTT__SIZE_1 2 /* */
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#define NV_PMGR_DRIO_PADCTL_ECTT_DISABLED 0x00000000 /* */
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#define NV_PMGR_DRIO_PADCTL_ECTT_ENABLED 0x00000001 /* */
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#define NV_PMGR_DRIO_PADCTL_PULLUP(i) 12+(16*(i)):8+(16*(i)) /* */
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#define NV_PMGR_DRIO_PADCTL_PULLUP__SIZE_1 2 /* */
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#define NV_PMGR_DRIO_PADCTL_PULLUP_3V 0x0000000f /* */
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#define NV_PMGR_DRIO_PADCTL_PULLUP_1X2XAGP2 0x00000013 /* */
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#define NV_PMGR_DRIO_PADCTL_E25V(i) 13+(16*(i)):13+(16*(i)) /* */
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#define NV_PMGR_DRIO_PADCTL_E25V__SIZE_1 2 /* */
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#define NV_PMGR_DRIO_PADCTL_E25V_DISABLED 0x00000000 /* */
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#define NV_PMGR_DRIO_PADCTL_E25V_ENABLED 0x00000001 /* */
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#define NV_PMGR_DRIO_PADCTL_ESCH(i) 14+(16*(i)):14+(16*(i)) /* */
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#define NV_PMGR_DRIO_PADCTL_ESCH__SIZE_1 2 /* */
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#define NV_PMGR_DRIO_PADCTL_ESCH_DISABLED 0x00000000 /* */
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#define NV_PMGR_DRIO_PADCTL_ESCH_ENABLED 0x00000001 /* */
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#define NV_PMGR_DRIO_PADCTL_VREF(i) 15+(16*(i)):15+(16*(i)) /* */
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#define NV_PMGR_DRIO_PADCTL_VREF__SIZE_1 2 /* */
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#define NV_PMGR_DRIO_PADCTL_VREF_DISABLED 0x00000000 /* */
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#define NV_PMGR_DRIO_PADCTL_VREF_ENABLED 0x00000001 /* */
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#define NV_PMGR_DRIO_PADCTL_B 0x0000E648 /* RW-4R */
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#define NV_PMGR_DRIO_PADCTL_B_SLEW_FALL 4:0 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_B_SLEW_FALL_INIT 0x0000000A /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_B_SLEW_RISE 12:8 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_B_SLEW_RISE_INIT 0x0000000A /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_B_DRIVE_FALL 20:16 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_B_DRIVE_FALL_INIT 0x0000000A /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_B_DRIVE_RISE 28:24 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_B_DRIVE_RISE_INIT 0x0000000A /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_B_VDDQ 31:31 /* RWIVF */
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#define NV_PMGR_DRIO_PADCTL_B_VDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_DRIO_PADCTL_B_VDDQ_33 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_PADCTL_B_VDDQ_18 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_A(i) (0x0000E64C+(i)*16) /* RW-4A */
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#define NV_PMGR_DRIO_A__SIZE_1 1 /* */
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#define NV_PMGR_DRIO_A_SLEW_FALL 4:0 /* RWIVF */
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#define NV_PMGR_DRIO_A_SLEW_FALL_INIT 0x0000000A /* RWI-V */
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#define NV_PMGR_DRIO_A_SLEW_FALL_FORCE_BYP_OR_CAL 6:6 /* RWIVF */
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#define NV_PMGR_DRIO_A_SLEW_FALL_FORCE_BYP_OR_CAL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_A_SLEW_FALL_FORCE_BYP_OR_CAL_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_A_SLEW_FALL_FORCE_BYP_OR_CAL_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_A_SLEW_FALL_BYP 7:7 /* RWIVF */
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#define NV_PMGR_DRIO_A_SLEW_FALL_BYP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_A_SLEW_FALL_BYP_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_A_SLEW_FALL_BYP_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_A_SLEW_RISE 12:8 /* RWIVF */
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#define NV_PMGR_DRIO_A_SLEW_RISE_INIT 0x0000000A /* RWI-V */
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#define NV_PMGR_DRIO_A_SLEW_RISE_FORCE_BYP_OR_CAL 14:14 /* RWIVF */
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#define NV_PMGR_DRIO_A_SLEW_RISE_FORCE_BYP_OR_CAL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_A_SLEW_RISE_FORCE_BYP_OR_CAL_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_A_SLEW_RISE_FORCE_BYP_OR_CAL_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_A_SLEW_RISE_BYP 15:15 /* RWIVF */
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#define NV_PMGR_DRIO_A_SLEW_RISE_BYP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_A_SLEW_RISE_BYP_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_A_SLEW_RISE_BYP_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_A_VDDQ 31:31 /* RWIVF */
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#define NV_PMGR_DRIO_A_VDDQ_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_DRIO_A_VDDQ_33 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_A_VDDQ_18 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_B(i) (0x0000E650+(i)*16) /* RW-4A */
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|
#define NV_PMGR_DRIO_B__SIZE_1 1 /* */
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|
#define NV_PMGR_DRIO_B_DRCAL_PERIOD 3:0 /* RWIVF */
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#define NV_PMGR_DRIO_B_DRCAL_PERIOD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_B_DRCAL_PERIOD_0MS 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_PERIOD_1MS 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_PERIOD_2MS 0x00000002 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_PERIOD_4MS 0x00000003 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_PERIOD_8MS 0x00000004 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_PERIOD_16MS 0x00000005 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_PERIOD_32MS 0x00000006 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_PERIOD_64MS 0x00000007 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_PERIOD_128MS 0x00000008 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_PERIOD_256MS 0x00000009 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_PERIOD_512MS 0x0000000a /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_PERIOD_DISABLED 0x0000000f /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_FIXED_PD 8:4 /* RWIVF */
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#define NV_PMGR_DRIO_B_DRCAL_FIXED_PD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_B_DRCAL_FIXED_PD_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_FIXED_PD_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_FIXED_PU 14:10 /* RWIVF */
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#define NV_PMGR_DRIO_B_DRCAL_FIXED_PU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_B_DRCAL_FIXED_PU_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_FIXED_PU_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_USE_FIXED 16:16 /* RWIVF */
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#define NV_PMGR_DRIO_B_DRCAL_USE_FIXED_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_B_DRCAL_USE_FIXED_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_USE_FIXED_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_FORCE_BYP_OR_CAL 17:17 /* RWIVF */
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#define NV_PMGR_DRIO_B_DRCAL_FORCE_BYP_OR_CAL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_B_DRCAL_FORCE_BYP_OR_CAL_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_FORCE_BYP_OR_CAL_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_ON_RESUME 18:18 /* RWIVF */
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#define NV_PMGR_DRIO_B_DRCAL_ON_RESUME_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_B_DRCAL_ON_RESUME_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_ON_RESUME_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_COMP 19:19 /* RW-VF */
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#define NV_PMGR_DRIO_B_DRCAL_COMP_INVALID 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_COMP_VALID 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_B_DRCAL_COMPUTED_PD 24:20 /* R--VF */
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#define NV_PMGR_DRIO_B_DRCAL_COMPUTED_PD_MIN 0x00000000 /* R---V */
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#define NV_PMGR_DRIO_B_DRCAL_COMPUTED_PD_MAX 0x0000001f /* R---V */
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#define NV_PMGR_DRIO_B_DRCAL_COMPUTED_PU 30:26 /* R--VF */
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#define NV_PMGR_DRIO_B_DRCAL_COMPUTED_PU_MIN 0x00000000 /* R---V */
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#define NV_PMGR_DRIO_B_DRCAL_COMPUTED_PU_MAX 0x0000001f /* R---V */
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#define NV_PMGR_DRIO_C(i) (0x0000E654+(i)*16) /* RW-4A */
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#define NV_PMGR_DRIO_C__SIZE_1 1 /* */
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#define NV_PMGR_DRIO_C_DRCAL_STRENGTH 4:0 /* RWIVF */
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#define NV_PMGR_DRIO_C_DRCAL_STRENGTH_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_C_DRCAL_STRENGTH_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_C_DRCAL_STRENGTH_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_DRIO_C_DRCAL_TESTMODE 8:8 /* RWIVF */
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#define NV_PMGR_DRIO_C_DRCAL_TESTMODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_C_DRCAL_TESTMODE_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_C_DRCAL_TESTMODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DRIO_C_DRCAL_PD_STATUS 10:10 /* R--VF */
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#define NV_PMGR_DRIO_C_DRCAL_PD_STATUS_READY 0x00000000 /* R---V */
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#define NV_PMGR_DRIO_C_DRCAL_PD_STATUS_NOT_READY 0x00000001 /* R---V */
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#define NV_PMGR_DRIO_C_DRCAL_PU_STATUS 11:11 /* R--VF */
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#define NV_PMGR_DRIO_C_DRCAL_PU_STATUS_NOT_READY 0x00000000 /* R---V */
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#define NV_PMGR_DRIO_C_DRCAL_PU_STATUS_READY 0x00000001 /* R---V */
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#define NV_PMGR_DRIO_C_DRCAL_MINCAL_PD 16:12 /* RWIVF */
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#define NV_PMGR_DRIO_C_DRCAL_MINCAL_PD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_C_DRCAL_MINCAL_PD_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_C_DRCAL_MINCAL_PD_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_DRIO_C_DRCAL_MAXCAL_PD 21:17 /* RWIVF */
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#define NV_PMGR_DRIO_C_DRCAL_MAXCAL_PD_INIT 0x0000001f /* RWI-V */
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#define NV_PMGR_DRIO_C_DRCAL_MAXCAL_PD_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_C_DRCAL_MAXCAL_PD_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_DRIO_C_DRCAL_MINCAL_PU 26:22 /* RWIVF */
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#define NV_PMGR_DRIO_C_DRCAL_MINCAL_PU_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DRIO_C_DRCAL_MINCAL_PU_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_C_DRCAL_MINCAL_PU_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_DRIO_C_DRCAL_MAXCAL_PU 31:27 /* RWIVF */
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#define NV_PMGR_DRIO_C_DRCAL_MAXCAL_PU_INIT 0x0000001f /* RWI-V */
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#define NV_PMGR_DRIO_C_DRCAL_MAXCAL_PU_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_DRIO_C_DRCAL_MAXCAL_PU_MAX 0x0000001f /* RW--V */
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#define NV_PMGR_DR_FREQ 0x0000E658 /* RW-4R */
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#define NV_PMGR_DR_FREQ_DIV 6:0 /* RWIVF */
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#define NV_PMGR_DR_FREQ_DIV_INIT 0x0000001A /* RWI-V */
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#define NV_PMGR_DVI_PADCTL 0x0000E680 /* RW-4R */
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#define NV_PMGR_DVI_PADCTL_ECTT 0:0 /* RWIVF */
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#define NV_PMGR_DVI_PADCTL_ECTT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DVI_PADCTL_ECTT_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DVI_PADCTL_ECTT_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DVI_PADCTL_EMCI 1:1 /* RWIVF */
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#define NV_PMGR_DVI_PADCTL_EMCI_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DVI_PADCTL_EMCI_DISABLED 0x00000000 /* RW--V */
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#define NV_PMGR_DVI_PADCTL_EMCI_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_DVI_PADCTL_TERM 2:2 /* RWIVF */
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#define NV_PMGR_DVI_PADCTL_TERM_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_DVI_PADCTL_TERM_DISABLED 0x00000000 /* RW--V */
|
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#define NV_PMGR_DVI_PADCTL_TERM_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_VTTGEN_CTRL 0x0000E690 /* RW-4R */
|
|
#define NV_PMGR_VTTGEN_CTRL_FBDN 4:0 /* RWIVF */
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|
#define NV_PMGR_VTTGEN_CTRL_FBDN_INIT 0x00000004 /* RWI-V */
|
|
#define NV_PMGR_VTTGEN_CTRL_FBUP 12:8 /* RWIVF */
|
|
#define NV_PMGR_VTTGEN_CTRL_FBUP_INIT 0x00000002 /* RWI-V */
|
|
#define NV_PMGR_VTTGEN_CTRL_DRVDN 18:16 /* RWIVF */
|
|
#define NV_PMGR_VTTGEN_CTRL_DRVDN_INIT 0x00000007 /* RWI-V */
|
|
#define NV_PMGR_VTTGEN_CTRL_DRVUP 22:20 /* RWIVF */
|
|
#define NV_PMGR_VTTGEN_CTRL_DRVUP_INIT 0x00000007 /* RWI-V */
|
|
#define NV_PMGR_VTTGEN_CTRL_BW 26:24 /* RWIVF */
|
|
#define NV_PMGR_VTTGEN_CTRL_BW_INIT 0x00000004 /* RWI-V */
|
|
#define NV_PMGR_VTTGEN_CTRL_E_PWRD_A 28:28 /* RWIVF */
|
|
#define NV_PMGR_VTTGEN_CTRL_E_PWRD_A_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PMGR_VTTGEN_CTRL_E_PWRD_B 29:29 /* RWIVF */
|
|
#define NV_PMGR_VTTGEN_CTRL_E_PWRD_B_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PMGR_VTTGEN_CTRL_E_PWRD_C 30:30 /* RWIVF */
|
|
#define NV_PMGR_VTTGEN_CTRL_E_PWRD_C_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PMGR_VTTGEN_CTRL_E_PWRD_D 31:31 /* RWIVF */
|
|
#define NV_PMGR_VTTGEN_CTRL_E_PWRD_D_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PMGR_ROM_CONFIG 0x0000E200 /* RWI4R */
|
|
#define NV_PMGR_ROM_CONFIG__PRIV_LEVEL_MASK 0x0000D7D0 /* */
|
|
#define NV_PMGR_ROM_CONFIG_TW1 5:0 /* RWIVF */
|
|
#define NV_PMGR_ROM_CONFIG_TW1_INIT 0x00000020 /* RWI-V */
|
|
#define NV_PMGR_ROM_CONFIG_TW1_66MHZ 0x0000003F /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW1_100MHZ 0x00000020 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW1_266MHZ 0x0000003C /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW1_DEFAULT 0x00000020 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW0 7:6 /* RWIVF */
|
|
#define NV_PMGR_ROM_CONFIG_TW0_INIT 0x00000003 /* RWI-V */
|
|
#define NV_PMGR_ROM_CONFIG_TW0_66MHZ 0x00000003 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW0_100MHZ 0x00000002 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW0_266MHZ 0x00000000 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW0_DEFAULT 0x00000003 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_SCKDIV 15:8 /* RWIVF */
|
|
#define NV_PMGR_ROM_CONFIG_SCKDIV_INIT 0x00000008 /* RWI-V */
|
|
#define NV_PMGR_ROM_CONFIG_SCKDIV_66MHZ 0x00000004 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_SCKDIV_133MHZ 0x00000008 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_SCKDIV_266MHZ 0x00000010 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_SCKDIV_DEFAULT 0x00000008 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW1_EXT 18:16 /* RWIVF */
|
|
#define NV_PMGR_ROM_CONFIG_TW1_EXT_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PMGR_ROM_CONFIG_TW1_EXT_66MHZ 0x00000000 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW1_EXT_100MHZ 0x00000001 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW1_EXT_266MHZ 0x00000003 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW1_EXT_DEFAULT 0x00000001 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW0_EXT 26:24 /* RWIVF */
|
|
#define NV_PMGR_ROM_CONFIG_TW0_EXT_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PMGR_ROM_CONFIG_TW0_EXT_66MHZ 0x00000000 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW0_EXT_100MHZ 0x00000001 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW0_EXT_266MHZ 0x00000003 /* RW--V */
|
|
#define NV_PMGR_ROM_CONFIG_TW0_EXT_DEFAULT 0x00000001 /* RW--V */
|
|
#define NV_PMGR_ROM_SERIAL_BYPASS 0x0000E204 /* RW-4R */
|
|
#define NV_PMGR_ROM_SERIAL_BYPASS__PRIV_LEVEL_MASK 0x0000D7D8 /* */
|
|
#define NV_PMGR_ROM_SERIAL_BYPASS_BYPASS 0:0 /* RWIVF */
|
|
#define NV_PMGR_ROM_SERIAL_BYPASS_BYPASS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_ROM_SERIAL_BYPASS_BYPASS_DISABLED 0x00000000 /* RW--V */
|
|
#define NV_PMGR_ROM_SERIAL_BYPASS_BYPASS_ENABLED 0x00000001 /* RW--V */
|
|
#define NV_PMGR_ROM_SERIAL_BYPASS_CS 1:1 /* RWIVF */
|
|
#define NV_PMGR_ROM_SERIAL_BYPASS_CS_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PMGR_ROM_SERIAL_BYPASS_CS_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_PMGR_ROM_SERIAL_BYPASS_CS_DISABLED 0x00000001 /* RW--V */
|
|
#define NV_PMGR_ROM_SERIAL_BYPASS_SCK 2:2 /* RWIVF */
|
|
#define NV_PMGR_ROM_SERIAL_BYPASS_SCK_INIT 0x00000000 /* RWI-V */
|
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#define NV_PMGR_ROM_SERIAL_BYPASS_SCK_LOW 0x00000000 /* RW--V */
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#define NV_PMGR_ROM_SERIAL_BYPASS_SCK_HI 0x00000001 /* RW--V */
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#define NV_PMGR_ROM_SERIAL_BYPASS_SI 3:3 /* RWIVF */
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#define NV_PMGR_ROM_SERIAL_BYPASS_SI_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_ROM_SERIAL_BYPASS_SI_LOW 0x00000000 /* RW--V */
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#define NV_PMGR_ROM_SERIAL_BYPASS_SI_HI 0x00000001 /* RW--V */
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#define NV_PMGR_ROM_SERIAL_BYPASS_SO 4:4 /* R--VF */
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#define NV_PMGR_ROM_SERIAL_BYPASS_SO_LOW 0x00000000 /* R---V */
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#define NV_PMGR_ROM_SERIAL_BYPASS_SO_HI 0x00000001 /* R---V */
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#define NV_PMGR_ROM_ADDR_OFFSET 0x0000E208 /* RW-4R */
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#define NV_PMGR_ROM_ADDR_OFFSET__PRIV_LEVEL_MASK 0x0000D7D0 /* */
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#define NV_PMGR_ROM_ADDR_OFFSET_EN 0:0 /* RWIUF */
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#define NV_PMGR_ROM_ADDR_OFFSET_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_PMGR_ROM_ADDR_OFFSET_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_ROM_ADDR_OFFSET_AMOUNT 23:2 /* RWIUF */
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#define NV_PMGR_ROM_ADDR_OFFSET_AMOUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL 0x0000E20C /* RW-4R */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL__PRIV_LEVEL_MASK 0x0000D7D8 /* */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_STATUS 0:0 /* R--VF */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_STATUS_UNACTIVATED 0x00000000 /* R---V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_STATUS_ACTIVATED 0x00000001 /* R---V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_OVERRIDE 1:1 /* RWIVF */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_OVERRIDE_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_FEEDBACK_MODE_CYA 2:2 /* RWIVF */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_FEEDBACK_MODE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_FEEDBACK_CLK_CYA 4:3 /* RWIVF */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_FEEDBACK_CLK_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_FEEDBACK_MODE_FUSE_STATUS 5:5 /* R--VF */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_FEEDBACK_MODE_FUSE_STATUS_AFIFO_MODE 0x00000000 /* R---V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_FEEDBACK_MODE_FUSE_STATUS_AFIFO_BYPASS_MODE 0x00000001 /* R---V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_FEEDBACK_CLK_ADJ_FUSE_STATUS 7:6 /* R--VF */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_FEEDBACK_CLK_ADJ_FUSE_STATUS_NO_ADDITIONAL_DELAY 0x00000000 /* R---V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_FEEDBACK_CLK_ADJ_FUSE_STATUS_WITH_ADDITIONAL_DELAY 0x00000001 /* R---V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_RBI_LEGACY_MODE_CYA 8:8 /* RWIVF */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_RBI_LEGACY_MODE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_SPI_LEGACY_MODE_CYA 9:9 /* RWIVF */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_SPI_LEGACY_MODE_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_RBI_LEGACY_MODE_FUSE_STATUS 10:10 /* R--VF */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_RBI_LEGACY_MODE_FUSE_STATUS_OFF 0x00000000 /* R---V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_RBI_LEGACY_MODE_FUSE_STATUS_ON 0x00000001 /* R---V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_SPI_LEGACY_MODE_FUSE_STATUS 11:11 /* R--VF */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_SPI_LEGACY_MODE_FUSE_STATUS_OFF 0x00000000 /* R---V */
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#define NV_PMGR_ROM_SERIAL_HW_CONTROL_SPI_LEGACY_MODE_FUSE_STATUS_ON 0x00000001 /* R---V */
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#define NV_PMGR_ROM_SERIAL_MODE 0x0000E210 /* RW-4R */
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#define NV_PMGR_ROM_SERIAL_MODE__PRIV_LEVEL_MASK 0x0000D7D8 /* */
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#define NV_PMGR_ROM_SERIAL_MODE_FASTREAD 0:0 /* RWIVF */
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#define NV_PMGR_ROM_SERIAL_MODE_FASTREAD_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_ROM_SERIAL_MODE_FASTREAD_ENABLE 0x00000001 /* RWI-V */
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#define NV_PMGR_ROM_SERIAL_MODE_1 0x0000E214 /* RW-4R */
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#define NV_PMGR_ROM_SERIAL_MODE_1__PRIV_LEVEL_MASK 0x0000D7D0 /* */
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#define NV_PMGR_ROM_SERIAL_MODE_1_DRVSTR 15:14 /* RWIVF */
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#define NV_PMGR_ROM_SERIAL_MODE_1_DRVSTR_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_ROM_WINDOW_XVE 0x0000E218 /* RW-4R */
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#define NV_PMGR_ROM_WINDOW_XVE_OFFSET 11:0 /* RWHVF */
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#define NV_PMGR_ROM_WINDOW_XVE_OFFSET_MIN 0x00000000 /* RWH-V */
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#define NV_PMGR_ROM_WINDOW_XVE_OFFSET_MAX 0x00000FFF /* RW--V */
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#define NV_PMGR_ROM_WINDOW_XVE_LIMIT 27:16 /* RWHVF */
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#define NV_PMGR_ROM_WINDOW_XVE_LIMIT_MIN 0x00000000 /* RW--V */
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#define NV_PMGR_ROM_WINDOW_XVE_LIMIT_MAX 0x00000FFF /* RWH-V */
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#define NV_PMGR_ROM_ADDR_OFFSET_2 0x0000E21C /* RW-4R */
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#define NV_PMGR_ROM_ADDR_OFFSET_2__PRIV_LEVEL_MASK 0x0000D7D0 /* */
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#define NV_PMGR_ROM_ADDR_OFFSET_2_EN 0:0 /* RWIUF */
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#define NV_PMGR_ROM_ADDR_OFFSET_2_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_PMGR_ROM_ADDR_OFFSET_2_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PMGR_ROM_ADDR_OFFSET_2_AMOUNT 23:2 /* RWIUF */
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#define NV_PMGR_ROM_ADDR_OFFSET_2_AMOUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_DATA_ARRAY(i) (0x0000E4A0+(i)*4) /* RW-4A */
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#define NV_PMGR_SPI_DATA_ARRAY__SIZE_1 64 /* */
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#define NV_PMGR_SPI_DATA_ARRAY__PRIV_LEVEL_MASK 0x0000D7D8 /* */
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#define NV_PMGR_SPI_DATA_ARRAY_BYTE_0 7:0 /* RW-VF */
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#define NV_PMGR_SPI_DATA_ARRAY_BYTE_1 15:8 /* RW-VF */
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#define NV_PMGR_SPI_DATA_ARRAY_BYTE_2 23:16 /* RW-VF */
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#define NV_PMGR_SPI_DATA_ARRAY_BYTE_3 31:24 /* RW-VF */
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#define NV_PMGR_SPI_CTRL 0x0000E5A0 /* RW-4R */
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#define NV_PMGR_SPI_CTRL__PRIV_LEVEL_MASK 0x0000D7D8 /* */
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#define NV_PMGR_SPI_CTRL_TRANSFER_SIZE 7:0 /* RWIVF */
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#define NV_PMGR_SPI_CTRL_TRANSFER_SIZE_1 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_CTRL_TRANSFER_SIZE_256 0x000000FF /* RW--V */
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#define NV_PMGR_SPI_CTRL_TRANSMIT_SIZE 15:8 /* RWIVF */
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#define NV_PMGR_SPI_CTRL_TRANSMIT_SIZE_1 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_CTRL_TRANSMIT_SIZE_256 0x000000FF /* RW--V */
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#define NV_PMGR_SPI_CTRL_TRANSMIT 16:16 /* RWIVF */
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#define NV_PMGR_SPI_CTRL_TRANSMIT_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_CTRL_TRANSMIT_YES 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_CTRL_RECEIVE 17:17 /* RWIVF */
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#define NV_PMGR_SPI_CTRL_RECEIVE_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_CTRL_RECEIVE_YES 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_CTRL_CSID 19:18 /* RWIVF */
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#define NV_PMGR_SPI_CTRL_CSID_0 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_CTRL_CSID_1 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_CTRL_CSID_2 0x00000002 /* RW--V */
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#define NV_PMGR_SPI_CTRL_CSID_3 0x00000003 /* RW--V */
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#define NV_PMGR_SPI_CTRL_DESELECT 27:27 /* RWIVF */
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#define NV_PMGR_SPI_CTRL_DESELECT_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_CTRL_DESELECT_YES 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_CTRL_INTERRUPT 28:28 /* RWIVF */
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#define NV_PMGR_SPI_CTRL_INTERRUPT_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_CTRL_INTERRUPT_YES 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_CTRL_REVERSE 29:29 /* RWIVF */
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#define NV_PMGR_SPI_CTRL_REVERSE_NO 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_CTRL_REVERSE_YES 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_CTRL_TRANSFER 31:31 /* RWIVF */
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#define NV_PMGR_SPI_CTRL_TRANSFER_DONE 0x00000000 /* R-I-V */
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#define NV_PMGR_SPI_CTRL_TRANSFER_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_SPI_CTRL_TRANSFER_TRIGGER 0x00000001 /* -W--V */
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#define NV_PMGR_SPI_CONFIG(i) (0x0000E5A4+(i)*4) /* RW-4A */
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#define NV_PMGR_SPI_CONFIG__SIZE_1 4 /* */
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#define NV_PMGR_SPI_CONFIG__PRIV_LEVEL_MASK 0x0000D7D8 /* */
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#define NV_PMGR_SPI_CONFIG_CPOL 0:0 /* RWIVF */
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#define NV_PMGR_SPI_CONFIG_CPOL_ACTIVE_HIGH 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_CONFIG_CPOL_ACTIVE_LOW 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_CPHA 1:1 /* RWIVF */
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#define NV_PMGR_SPI_CONFIG_CPHA_FIRST 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_CONFIG_CPHA_SECOND 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_PERIOD 3:2 /* RWIVF */
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#define NV_PMGR_SPI_CONFIG_PERIOD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_CONFIG_PERIOD_1X 0x00000000 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_PERIOD_2X 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_PERIOD_3X 0x00000002 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_PERIOD_4X 0x00000003 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_PERIOD_50P0MHZ 0x00000000 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_PERIOD_25P0MHZ 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_PERIOD_16P6MHZ 0x00000002 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_PERIOD_12P5MHZ 0x00000003 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_READLATENCY 7:4 /* RWIVF */
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#define NV_PMGR_SPI_CONFIG_READLATENCY_INIT 0x00000008 /* RWI-V */
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#define NV_PMGR_SPI_CONFIG_READLATENCY_DIS 0x00000004 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_READLATENCY_0 0x00000000 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_READLATENCY_1 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_READLATENCY_2 0x00000002 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_READLATENCY_3 0x00000003 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_READLATENCY_4 0x00000004 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_READLATENCY_5 0x00000005 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_READLATENCY_6 0x00000006 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_READLATENCY_7 0x00000007 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_REFCLK 8:8 /* RWIVF */
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#define NV_PMGR_SPI_CONFIG_REFCLK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_CONFIG_REFCLK_PEX_REFCLK 0x00000000 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_REFCLK_XTAL4X 0x00000000 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_REFCLK_XTAL 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_SCKDIV 16:9 /* RWIVF */
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#define NV_PMGR_SPI_CONFIG_SCKDIV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_CONFIG_SCKDIV_2 0x00000000 /* RW--V */
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#define NV_PMGR_SPI_CONFIG_SCKDIV_512 0x000000FF /* RW--V */
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#define NV_PMGR_SPI_CONFIG_CS_SETUP 20:17 /* RWIVF */
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#define NV_PMGR_SPI_CONFIG_CS_SETUP_INIT 0x00000008 /* RWI-V */
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#define NV_PMGR_SPI_CONFIG_CS_HOLD 24:21 /* RWIVF */
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#define NV_PMGR_SPI_CONFIG_CS_HOLD_INIT 0x00000008 /* RWI-V */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK 0x0000E5B4 /* RW-4R */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RWI-V */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_SPI_ARBITER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_SPI_ARBITER_CTRL0 0x0000E5B8 /* RW-4R */
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#define NV_PMGR_SPI_ARBITER_CTRL0__PRIV_LEVEL_MASK 0x0000E5B4 /* */
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#define NV_PMGR_SPI_ARBITER_CTRL0_BLOCK_BIT 0:0 /* RWEVF */
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#define NV_PMGR_SPI_ARBITER_CTRL0_BLOCK_BIT_INIT 0x00000000 /* RWE-V */
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#define NV_PMGR_SPI_ARBITER_CTRL0_BLOCK_BIT_XUSB_ALLOWED 0x00000000 /* RW--V */
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#define NV_PMGR_SPI_ARBITER_CTRL0_BLOCK_BIT_XUSB_BLOCKED 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_ARBITER_CTRL1 0x0000E5BC /* RW-4R */
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#define NV_PMGR_SPI_ARBITER_CTRL1__PRIV_LEVEL_MASK 0x0000E5B4 /* */
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#define NV_PMGR_SPI_ARBITER_CTRL1_HIGH_PRIORITY 0:0 /* RWIVF */
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#define NV_PMGR_SPI_ARBITER_CTRL1_HIGH_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_ARBITER_CTRL1_HIGH_PRIORITY_NO 0x00000000 /* RW--V */
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#define NV_PMGR_SPI_ARBITER_CTRL1_HIGH_PRIORITY_YES 0x00000001 /* RW--V */
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#define NV_PMGR_SPI_ARBITER_CTRL1_SPARE 31:1 /* RWIVF */
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#define NV_PMGR_SPI_ARBITER_CTRL1_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_ARBITER_CONFIG 0x0000E5C0 /* RW-4R */
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#define NV_PMGR_SPI_ARBITER_CONFIG__PRIV_LEVEL_MASK 0x0000E5B4 /* */
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#define NV_PMGR_SPI_ARBITER_CONFIG_REQCOUNT_HOST 7:0 /* RWIVF */
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#define NV_PMGR_SPI_ARBITER_CONFIG_REQCOUNT_HOST_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_SPI_ARBITER_CONFIG_REQCOUNT_XUSB 15:8 /* RWIVF */
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#define NV_PMGR_SPI_ARBITER_CONFIG_REQCOUNT_XUSB_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_SPI_ARBITER_CONFIG_TIMEOUT_HOST 23:16 /* RWIVF */
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#define NV_PMGR_SPI_ARBITER_CONFIG_TIMEOUT_HOST_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_SPI_ARBITER_CONFIG_TIMEOUT_XUSB 31:24 /* RWIVF */
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#define NV_PMGR_SPI_ARBITER_CONFIG_TIMEOUT_XUSB_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK 0x0000E5C4 /* RW-4R */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RWI-V */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_PAD_SHARE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_PAD_SHARE 0x0000E5C8 /* RW-4R */
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#define NV_PMGR_PAD_SHARE__PRIV_LEVEL_MASK 0x0000E5C4 /* */
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#define NV_PMGR_PAD_SHARE_IFPB_AUX_PAD_SEL 0:0 /* RWIVF */
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#define NV_PMGR_PAD_SHARE_IFPB_AUX_PAD_SEL_PMGR 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_SHARE_IFPB_AUX_PAD_SEL_XUSB 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR 0x0000E480 /* RW-4R */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR_VALUE 11:0 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR_INST 15:12 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR_INST_ZERO 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR_INST_ONE 0x00000001 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR_INST_TWO 0x00000002 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR_INST_THREE 0x00000003 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR_INST_ZERO_HDCP2_SEC 0x00000004 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR_INST_ONE_HDCP2_SEC 0x00000005 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR_INST_TWO_HDCP2_SEC 0x00000006 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR_INST_THREE_HDCP2_SEC 0x00000007 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR_MSB_VALUE 19:16 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_ADDR_MSB_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_DATA 0x0000E484 /* RW-4R */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_DATA_VALUE 31:0 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_DATA_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD 0x0000E490 /* RW-4R */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_ENABLE_MON 0:0 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_ENABLE_MON_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_ENABLE_MON_NO 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_ENABLE_MON_YES 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_RESERVED0 1:1 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_RESERVED0_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_HSYNC_NOVBLANK 2:2 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_HSYNC_NOVBLANK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_HSYNC_NOVBLANK_NO 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_HSYNC_NOVBLANK_YES 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_HEAD 6:3 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_HEAD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_HEAD_0 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_HEAD_1 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_HEAD_2 0x00000002 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_HEAD_3 0x00000003 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_SNOOZE 7:7 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_SNOOZE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_SNOOZE_NO 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_SNOOZE_YES 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_ASLEEP_SV3 8:8 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_ASLEEP_SV3_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_ASLEEP_SV3_NO 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_ASLEEP_SV3_YES 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_ASLEEP_RGSTALL 9:9 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_ASLEEP_RGSTALL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_ASLEEP_RGSTALL_NO 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_ASLEEP_RGSTALL_YES 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_AWAKE_ACTIVE 10:10 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_AWAKE_ACTIVE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_AWAKE_ACTIVE_NO 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_AWAKE_ACTIVE_YES 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_AWAKE_VBLANK 11:11 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_AWAKE_VBLANK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_AWAKE_VBLANK_NO 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_AWAKE_VBLANK_YES 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_AWAKE_RGSTALL 12:12 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_AWAKE_RGSTALL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_AWAKE_RGSTALL_NO 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_AWAKE_RGSTALL_YES 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_SNOOZE_RGSTALL 13:13 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_SNOOZE_RGSTALL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_SNOOZE_RGSTALL_NO 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_SNOOZE_RGSTALL_YES 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_MODE 14:14 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_MODE_CONTINUOUS 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_MODE_ONE_SHOT 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_STEREO_MODE 15:15 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_STEREO_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_STEREO_MODE_NO 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_STEREO_MODE_YES 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_ODD_MODE 16:16 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_ODD_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_ODD_MODE_NO 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_ODD_MODE_YES 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_USE_PROG_DELAY 17:17 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_USE_PROG_DELAY_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_USE_PROG_DELAY_NO 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_USE_PROG_DELAY_YES 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_PROG_DELAY 30:18 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_PROG_DELAY_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_PROG_DELAY_0 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_PROG_DELAY_4095 0x00000fff /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_PROG_DELAY_8191 0x00001fff /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_SNOOZE_ERROR 31:31 /* RWIVF */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_SNOOZE_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_SNOOZE_ERROR_PENDING 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_SNOOZE_ERROR_NOT_PENDING 0x00000000 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_STALL_MON_CMD_UNSTALL_SNOOZE_ERROR_CLEAR 0x00000001 /* RW--V */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_REPLY_CMD 1:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_REPLY_CMD_NO_FORCE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_REPLY_CMD_NACK 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_REPLY_CMD_DEFER 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_REPLY_PREAMBLE_NUM 2:2 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_REPLY_PREAMBLE_NUM_DOWN_LMT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_REPLY_PREAMBLE_NUM_UP_LMT 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_INCOMPLETE_NUM 6:3 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_INCOMPLETE_NUM_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_REPLY_TIMEOUT 7:7 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_REPLY_TIMEOUT_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_REPLY_TIMEOUT_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_NOISE 12:12 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_NOISE_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_AUX_NOISE_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_MAX_LINK_SPEED 20:19 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_MAX_LINK_SPEED_RBR 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_MAX_LINK_SPEED_HBR 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_MAX_LINK_SPEED_HBR2 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_MAX_LANE_COUNT 23:21 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_MAX_LANE_COUNT_ONE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_MAX_LANE_COUNT_TWO 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_MAX_LANE_COUNT_FOUR 0x00000004 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_ENHANCED_FRAME_CAP 24:24 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_ENHANCED_FRAME_CAP_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_ENHANCED_FRAME_CAP_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_SIDEBAND_MSG_CAP 25:25 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_SIDEBAND_MSG_CAP_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_SIDEBAND_MSG_CAP_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_DP_VERSION 31:26 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_DP_VERSION_11 0x00000011 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_0_DP_VERSION_12 0x00000012 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_1 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_1_HDCP_CAPABLE 0:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_1_HDCP_CAPABLE_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_1_HDCP_CAPABLE_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_1_HDCP_BKSV_SEL 4:1 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_1_HDCP_BKSV_SEL_B1 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_1_HDCP_BKSV_SEL_B2 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_1_HDCP_TOPO_SEL 8:5 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_1_HDCP_TOPO_SEL_0 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_1_HDCP_TOPO_SEL_1 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_1_HDCP_REPEATER 9:9 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_1_HDCP_REPEATER_FALSE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_1_HDCP_REPEATER_TRUE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN 0:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_DONE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_PENDING 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TRIGGER 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_LOOP_COUNT 3:1 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_LOOP_COUNT_MIN 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_LOOP_COUNT_MAX 0x00000007 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_VOLT 5:4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_VOLT_LEVEL0 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_VOLT_LEVEL1 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_VOLT_LEVEL2 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_VOLT_LEVEL3 0x00000003 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_PREE 7:6 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_PREE_LEVEL0 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_PREE_LEVEL1 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_PREE_LEVEL2 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_PREE_LEVEL3 0x00000003 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_CR_BW 9:8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_CR_BW_RBR 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_CR_BW_HBR 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_CR_BW_HBR2 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_EQ_BW 11:10 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_EQ_BW_RBR 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_EQ_BW_HBR 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_EQ_BW_HBR2 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_CR_TRAIN 12:12 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_CR_TRAIN_INIT 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_CR_TRAIN_ENABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_CR_TRAIN_DISABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_EQ_TRAIN 13:13 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_EQ_TRAIN_INIT 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_EQ_TRAIN_ENABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_EQ_TRAIN_DISABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_POSTCURSOR2 15:14 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_POSTCURSOR2_LEVEL0 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_POSTCURSOR2_LEVEL1 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_POSTCURSOR2_LEVEL2 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_2_TRAIN_TARGET_POSTCURSOR2_LEVEL3 0x00000003 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3 0x00000003 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3_HPD_START 0:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3_HPD_START_DONE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3_HPD_START_PENDING 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3_HPD_START_TRIGGER 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3_HPD_INIT_VALUE 1:1 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3_HPD_INIT_VALUE_LOW 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3_HPD_INIT_VALUE_HIGH 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3_HPD_END_VALUE 2:2 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3_HPD_END_VALUE_LOW 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3_HPD_END_VALUE_HIGH 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3_HPD_PULSE_WIDTH 18:3 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3_HPD_PULSE_WIDTH_MIN 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_3_HPD_PULSE_WIDTH_MAX 0x0000FFFF /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_4 0x00000004 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_4_VBID 5:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_4_VBID2 21:16 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5 0x00000005 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_HEAD_PARITY_ERROR 0:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_DATA_PARITY_ERROR 1:1 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_PADDED_ERROR 2:2 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_HEAD_BYTE_ERROR 3:3 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_AUDIO_MUTE_ASSERT 4:4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_AUDIO_STREAM_EXCESS_MAX_NUM_ERROR 5:5 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_AUDIO_TIMESTAMP_BYTE_COUNT_ERROR 6:6 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_AUDIO_TIMESTAMP_PADDED_ERROR 7:7 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_MAUD_INCONSISTENT_ERROR 8:8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_NAUD_INCONSISTENT_ERROR 9:9 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_INFO_FRAME_BYTE_COUNT_ERROR 10:10 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_INFO_FRAME_AUDIO_RESERVED_ERROR 11:11 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_INFO_FRAME_PACKET_TYPE_ERROR 12:12 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_5_SDP_TYPE_ERROR 13:13 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_6 0x00000006 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_6_PIX_CNT 31:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_6_PIX_CNT_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_7 0x00000007 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_7_PIX_ERR_CNT 31:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_7_PIX_ERR_CNT_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_VC_ALC(i) (0x00000008+(i)*1) /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_VC_ALC__SIZE_1 63 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_VC_ALC_VALUE 6:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_VC_ALC_PBN 31:16 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_ALC_VLD 0x00000047 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_ALC_VLD_VALUE 0:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_ALC_VLD_VALUE_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_ALC_VLD_VALUE_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_ALC_VLD_VALUE_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72 0x00000048 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_SL_LINK_ENABLE 0:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_SL_LINK_ENABLE_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_SL_LINK_ENABLE_NO 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_SL_LINK_ENABLE_YES 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_DUAL_DP_COL_INTERLEAVE_MODE 1:1 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_DUAL_DP_COL_INTERLEAVE_MODE_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_DUAL_DP_COL_INTERLEAVE_MODE_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_DUAL_DP_COL_INTERLEAVE_MODE_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_DUAL_DP_PIX_SBS_MODE 2:2 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_DUAL_DP_PIX_SBS_MODE_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_DUAL_DP_PIX_SBS_MODE_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_DUAL_DP_PIX_SBS_MODE_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_SL_AUX_HPD_ENABLE 3:3 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_SL_AUX_HPD_ENABLE_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_SL_AUX_HPD_ENABLE_NO 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_SL_AUX_HPD_ENABLE_YES 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_DUAL_DP_COL_WIDTH 31:16 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_72_DUAL_DP_COL_WIDTH_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73 0x00000049 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN 0:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_DONE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_PENDING 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TRIGGER 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_LOOP_COUNT 3:1 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_LOOP_COUNT_MIN 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_LOOP_COUNT_MAX 0x00000007 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_VOLT 5:4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_VOLT_LEVEL0 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_VOLT_LEVEL1 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_VOLT_LEVEL2 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_VOLT_LEVEL3 0x00000003 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_PREE 7:6 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_PREE_LEVEL0 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_PREE_LEVEL1 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_PREE_LEVEL2 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_PREE_LEVEL3 0x00000003 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_CR_BW 9:8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_CR_BW_RBR 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_CR_BW_HBR 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_CR_BW_HBR2 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_EQ_BW 11:10 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_EQ_BW_RBR 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_EQ_BW_HBR 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_EQ_BW_HBR2 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_CR_TRAIN 12:12 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_CR_TRAIN_INIT 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_CR_TRAIN_ENABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_CR_TRAIN_DISABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_EQ_TRAIN 13:13 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_EQ_TRAIN_INIT 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_EQ_TRAIN_ENABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_EQ_TRAIN_DISABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_POSTCURSOR2 15:14 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_POSTCURSOR2_LEVEL0 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_POSTCURSOR2_LEVEL1 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_POSTCURSOR2_LEVEL2 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_73_TRAIN_TARGET_POSTCURSOR2_LEVEL3 0x00000003 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74 0x0000004A /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_REPLY_CMD 1:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_REPLY_CMD_NO_FORCE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_REPLY_CMD_NACK 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_REPLY_CMD_DEFER 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_REPLY_PREAMBLE_NUM 2:2 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_REPLY_PREAMBLE_NUM_DOWN_LMT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_REPLY_PREAMBLE_NUM_UP_LMT 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_INCOMPLETE_NUM 6:3 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_INCOMPLETE_NUM_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_REPLY_TIMEOUT 7:7 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_REPLY_TIMEOUT_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_REPLY_TIMEOUT_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_NOISE 12:12 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_NOISE_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_74_AUX_NOISE_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75 0x0000004B /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75_HPD_START 0:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75_HPD_START_DONE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75_HPD_START_PENDING 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75_HPD_START_TRIGGER 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75_HPD_INIT_VALUE 1:1 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75_HPD_INIT_VALUE_LOW 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75_HPD_INIT_VALUE_HIGH 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75_HPD_END_VALUE 2:2 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75_HPD_END_VALUE_LOW 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75_HPD_END_VALUE_HIGH 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75_HPD_PULSE_WIDTH 18:3 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75_HPD_PULSE_WIDTH_MIN 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_75_HPD_PULSE_WIDTH_MAX 0x0000FFFF /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_76 0x0000004C /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_76_GUID_DATA_0 31:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_76_GUID_DATA_0_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_77 0x0000004D /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_77_GUID_DATA_0 31:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_77_GUID_DATA_0_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_78 0x0000004E /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_78_GUID_DATA_0 31:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_78_GUID_DATA_0_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_79 0x0000004F /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_79_GUID_DATA_0 31:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_79_GUID_DATA_0_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_80 0x00000050 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_80_GUID_OVERRIDE_ENABLE 5:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_80_GUID_OVERRIDE_ENABLE_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_80_GUID_OVERRIDE_ENABLE_BRANCH_1 0x00000020 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_80_GUID_OVERRIDE_ENABLE_BRANCH_2 0x00000010 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_80_GUID_OVERRIDE_ENABLE_SINK_1 0x00000008 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_80_GUID_OVERRIDE_ENABLE_SINK_2 0x00000004 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_80_GUID_OVERRIDE_ENABLE_SINK_3 0x00000002 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_80_GUID_OVERRIDE_ENABLE_SINK_4 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81 0x00000051 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_1 4:4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_1_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_1_DISCONNECT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_1_CONNECT 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_2 3:3 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_2_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_2_DISCONNECT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_2_CONNECT 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_3 2:2 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_3_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_3_DISCONNECT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_3_CONNECT 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_4 1:1 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_4_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_4_DISCONNECT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_4_CONNECT 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_5 0:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_5_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_5_DISCONNECT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_81_LINK_CONNECT_STAT_LINK_5_CONNECT 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_83 0x00000053 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_83_HDCP1x_CRYPT_COUNT 7:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_83_HDCP1x_CRYPT_COUNT_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_83_HDCP1x_AUTH_COUNT 15:8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_83_HDCP1x_AUTH_COUNT_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_83_HDCP2x_CRYPT_COUNT 23:16 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_83_HDCP2x_CRYPT_COUNT_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_83_HDCP2x_AUTH_COUNT 31:23 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_83_HDCP2x_AUTH_COUNT_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_84 0x00000054 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_84_HDCP1x_CRYPT_COUNT 7:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_84_HDCP1x_CRYPT_COUNT_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_84_HDCP1x_AUTH_COUNT 15:8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_84_HDCP1x_AUTH_COUNT_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_84_HDCP2x_CRYPT_COUNT 23:16 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_84_HDCP2x_CRYPT_COUNT_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_84_HDCP2x_AUTH_COUNT 31:23 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_84_HDCP2x_AUTH_COUNT_INIT 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RTX_MSB 0x00009000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RTX_LSB 0x00009004 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_TXCAPS 0x00009008 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_TXCAPS_TRANSMITTER_CAPABILITY_MASK 15:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_TXCAPS_VERSION 23:16 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CERTRX(i) (0x0000900B+(i)*4) /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CERTRX__SIZE_1 131 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RRX_MSB 0x00009215 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RRX_LSB 0x00009219 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXCAPS 0x00000921D /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXCAPS_REPEATER 0:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXCAPS_HDCP_CAPABLE 1:1 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXCAPS_RECEIVER_CAPABILITY_MASK 15:2 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXCAPS_VERSION 23:16 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EKPUB_KM(i) (0x0009220+(i)*4) /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EKPUB_KM__SIZE_1 32 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EKH_KM_MSB 0x000092A0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EKH_KM_LSB3 0x000092A4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EKH_KM_LSB2 0x000092A8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EKH_KM_LSB1 0x000092AC /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_M_MSB 0x000092B0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_M_LSB3 0x000092B4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_M_LSB2 0x000092B8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_M_LSB1 0x000092BC /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_HPRIME_MSB 0x00092C0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_HPRIME_LSB7 0x00092C4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_HPRIME_LSB6 0x00092C8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_HPRIME_LSB5 0x00092CC /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_HPRIME_LSB4 0x00092D0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_HPRIME_LSB3 0x00092D4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_HPRIME_LSB2 0x00092D8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_HPRIME_LSB1 0x00092DC /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EKH_KM_READ_MSB 0x000092E0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EKH_KM_READ_LSB3 0x000092E4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EKH_KM_READ_LSB2 0x000092E8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EKH_KM_READ_LSB1 0x000092EC /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RM_MSB 0x000092F0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RM_LSB 0x000092F4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_LPRIME_MSB 0x00092F8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_LPRIME_LSB7 0x00092FC /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_LPRIME_LSB6 0x0009300 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_LPRIME_LSB5 0x0009304 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_LPRIME_LSB4 0x0009308 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_LPRIME_LSB3 0x000930C /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_LPRIME_LSB2 0x0009310 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_LPRIME_LSB1 0x0009314 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EDKEY_KS_MSB 0x0009318 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EDKEY_KS_LSB3 0x000931C /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EDKEY_KS_LSB2 0x0009320 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_EDKEY_KS_LSB1 0x0009324 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RIV_MSB 0x00009328 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RIV_LSB 0x0000932C /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXINFO 0x00009330 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXINFO_HDCP1_DEVICE_DOWNSTREAM 0:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXINFO_HDCP2_0_REPEATER_DOWNSTREAM 1:1 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXINFO_MAX_CASCADE_EXCEEDED 2:2 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXINFO_MAX_DEVS_EXCEEDED 3:3 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXINFO_DEVICE_COUNT 8:4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXINFO_DEPTH 11:9 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_SEQ_NUM_V 0x00009332 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_VPRIME_MSB 0x0009335 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_VPRIME_LSB3 0x0009339 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_VPRIME_LSB2 0x000933D /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_VPRIME_LSB1 0x0009341 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RCVR_ID_LST(i) (0x0009345+(i)*4) /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RCVR_ID_LST__SIZE_1 39 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_V_MSB 0x000093E0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_V_LSB3 0x000093E4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_V_LSB2 0x000093E8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_V_LSB1 0x000093EC /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_SEQ_NUM_M 0x000093F0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_K 0x000093F3 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_STREAMID_TYPE(i) (0x00093F5+(i)*4) /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_STREAMID_TYPE__SIZE_1 32 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_MPRIME_MSB 0x00009473 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_MPRIME_LSB7 0x00009477 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_MPRIME_LSB6 0x0000947B /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_MPRIME_LSB5 0x0000947F /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_MPRIME_LSB4 0x00009483 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_MPRIME_LSB3 0x00009487 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_MPRIME_LSB2 0x0000948B /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_MPRIME_LSB1 0x0000948F /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXSTATUS 0x00009493 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXSTATUS_READY 0:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXSTATUS_HPRIME_AVAILABLE 1:1 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXSTATUS_PAIRING_AVAILABLE 2:2 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXSTATUS_REAUTH_REQ 3:3 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RXSTATUS_LINK_INTEGRITY_FAILURE 4:4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_TYPE 0x0009494 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RSVD(i) (0x0009495+(i)*4) /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_RSVD__SIZE_1 33 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_DBG(i) (0x0009518+(i)*4) /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_DBG__SIZE_1 16 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_KS_MSB 0x00009558 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_KS_LSB3 0x0000955C /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_KS_LSB2 0x00009560 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_KS_LSB1 0x00009564 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_KM_MSB 0x000009568 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_KM_LSB3 0x00000956C /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_KM_LSB2 0x000009570 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_KM_LSB1 0x000009574 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_KD_MSB 0x000009578 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_KD_LSB3 0x00000957C /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_KD_LSB2 0x000009580 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_KD_LSB1 0x000009584 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_LC_MSB 0x000009598 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_LC_LSB3 0x00000959C /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_LC_LSB2 0x000009590 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_LC_LSB1 0x000009594 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL 0x000095A8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_ENABLE_HDCP_2_2 0:0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_ENABLE_HDCP_2_2_NO 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_ENABLE_HDCP_2_2_YES 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_BYPASS_AKE 1:1 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_BYPASS_AKE_NO 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_BYPASS_AKE_YES 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_READY_ASSERT 2:2 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_READY_ASSERT_NO 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_READY_ASSERT_YES 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_REPEATER 3:3 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_REPEATER_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_REPEATER_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_REAUTH_REQUEST 4:4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_REAUTH_REQUEST_CLEAR 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_REAUTH_REQUEST_SET 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_LINK_INTEGRITY_FAIL 5:5 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_LINK_INTEGRITY_FAIL_CLEAR 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_LINK_INTEGRITY_FAIL_SET 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_CERT_RX_TIMEOUT 6:6 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_CERT_RX_TIMEOUT_ENABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_CERT_RX_TIMEOUT_DISABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_HPRIME_TIMEOUT 7:7 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_HPRIME_TIMEOUT_ENABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_HPRIME_TIMEOUT_DISABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_PAIRING_TIMEOUT 8:8 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_PAIRING_TIMEOUT_ENABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_PAIRING_TIMEOUT_DISABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_LPRIME_TIMEOUT 9:9 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_LPRIME_TIMEOUT_ENABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_LPRIME_TIMEOUT_DISABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_VPRIME_TIMEOUT 10:10 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_VPRIME_TIMEOUT_ENABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_VPRIME_TIMEOUT_DISABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_MPRIME_TIMEOUT 11:11 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_MPRIME_TIMEOUT_ENABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_MPRIME_TIMEOUT_DISABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_CERT_RX_INVALID 12:12 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_CERT_RX_INVALID_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_CERT_RX_INVALID_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_HPRIME_INVALID 13:13 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_HPRIME_INVALID_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_HPRIME_INVALID_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_PAIRING_INVALID 14:14 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_PAIRING_INVALID_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_PAIRING_INVALID_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_LPRIME_INVALID 15:15 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_LPRIME_INVALID_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_LPRIME_INVALID_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_VPRIME_INVALID 16:16 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_VPRIME_INVALID_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_VPRIME_INVALID_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_MPRIME_INVALID 17:17 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_MPRIME_INVALID_DISABLE 0x00000000 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_CTRL_MPRIME_INVALID_ENABLE 0x00000001 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_INPUTCTR_MSB 0x0000095AC /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_INPUTCTR_LSB3 0x0000095B0 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_INPUTCTR_LSB2 0x0000095B4 /* */
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#define NV_PMGR_NON_SILICON_VERIF_DP_BFM_REG_HDCP22_INPUTCTR_LSB1 0x0000095B8 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W0(i) (0x0000D930+(i)*80) /* RW-4A */
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#define NV_PMGR_DP_AUXDATA_WRITE_W0__SIZE_1 7 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W0_REG 31:0 /* RWIUF */
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#define NV_PMGR_DP_AUXDATA_WRITE_W0_REG_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DP_AUXDATA_WRITE_W0_BYTE0 7:0 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W0_BYTE1 15:8 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W0_BYTE2 23:16 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W0_BYTE3 31:24 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W0_BYTE(i) (8*(i)+7):(8*(i)) /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W0_BYTE__SIZE_1 4 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W1(i) (0x0000D934+(i)*80) /* RW-4A */
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#define NV_PMGR_DP_AUXDATA_WRITE_W1__SIZE_1 7 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W1_REG 31:0 /* RWIUF */
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#define NV_PMGR_DP_AUXDATA_WRITE_W1_REG_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DP_AUXDATA_WRITE_W1_BYTE0 7:0 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W1_BYTE1 15:8 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W1_BYTE2 23:16 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W1_BYTE3 31:24 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W1_BYTE(i) (8*(i)+7):(8*(i)) /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W1_BYTE__SIZE_1 4 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W2(i) (0x0000D938+(i)*80) /* RW-4A */
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#define NV_PMGR_DP_AUXDATA_WRITE_W2__SIZE_1 7 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W2_REG 31:0 /* RWIUF */
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#define NV_PMGR_DP_AUXDATA_WRITE_W2_REG_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DP_AUXDATA_WRITE_W2_BYTE0 7:0 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W2_BYTE1 15:8 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W2_BYTE2 23:16 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W2_BYTE3 31:24 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W2_BYTE(i) (8*(i)+7):(8*(i)) /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W2_BYTE__SIZE_1 4 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W3(i) (0x0000D93C+(i)*80) /* RW-4A */
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#define NV_PMGR_DP_AUXDATA_WRITE_W3__SIZE_1 7 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W3_REG 31:0 /* RWIUF */
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#define NV_PMGR_DP_AUXDATA_WRITE_W3_REG_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DP_AUXDATA_WRITE_W3_BYTE0 7:0 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W3_BYTE1 15:8 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W3_BYTE2 23:16 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W3_BYTE3 31:24 /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W3_BYTE(i) (8*(i)+7):(8*(i)) /* */
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#define NV_PMGR_DP_AUXDATA_WRITE_W3_BYTE__SIZE_1 4 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W0(i) (0x0000D940+(i)*80) /* R--4A */
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#define NV_PMGR_DP_AUXDATA_READ_W0__SIZE_1 7 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W0_REG 31:0 /* R--UF */
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#define NV_PMGR_DP_AUXDATA_READ_W0_BYTE0 7:0 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W0_BYTE1 15:8 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W0_BYTE2 23:16 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W0_BYTE3 31:24 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W0_BYTE(i) (8*(i)+7):(8*(i)) /* */
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#define NV_PMGR_DP_AUXDATA_READ_W0_BYTE__SIZE_1 4 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W1(i) (0x0000D944+(i)*80) /* R--4A */
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#define NV_PMGR_DP_AUXDATA_READ_W1__SIZE_1 7 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W1_REG 31:0 /* R--UF */
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#define NV_PMGR_DP_AUXDATA_READ_W1_BYTE0 7:0 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W1_BYTE1 15:8 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W1_BYTE2 23:16 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W1_BYTE3 31:24 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W1_BYTE(i) (8*(i)+7):(8*(i)) /* */
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#define NV_PMGR_DP_AUXDATA_READ_W1_BYTE__SIZE_1 4 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W2(i) (0x0000D948+(i)*80) /* R--4A */
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#define NV_PMGR_DP_AUXDATA_READ_W2__SIZE_1 7 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W2_REG 31:0 /* R--UF */
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#define NV_PMGR_DP_AUXDATA_READ_W2_BYTE0 7:0 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W2_BYTE1 15:8 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W2_BYTE2 23:16 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W2_BYTE3 31:24 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W2_BYTE(i) (8*(i)+7):(8*(i)) /* */
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#define NV_PMGR_DP_AUXDATA_READ_W2_BYTE__SIZE_1 4 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W3(i) (0x0000D94C+(i)*80) /* R--4A */
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#define NV_PMGR_DP_AUXDATA_READ_W3__SIZE_1 7 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W3_REG 31:0 /* R--UF */
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#define NV_PMGR_DP_AUXDATA_READ_W3_BYTE0 7:0 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W3_BYTE1 15:8 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W3_BYTE2 23:16 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W3_BYTE3 31:24 /* */
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#define NV_PMGR_DP_AUXDATA_READ_W3_BYTE(i) (8*(i)+7):(8*(i)) /* */
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#define NV_PMGR_DP_AUXDATA_READ_W3_BYTE__SIZE_1 4 /* */
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#define NV_PMGR_DP_AUXADDR(i) (0x0000D950+(i)*80) /* RW-4A */
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#define NV_PMGR_DP_AUXADDR__SIZE_1 7 /* */
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#define NV_PMGR_DP_AUXADDR_REG 19:0 /* RWIVF */
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#define NV_PMGR_DP_AUXADDR_REG_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DP_AUXCTL(i) (0x0000D954+(i)*80) /* RW-4A */
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#define NV_PMGR_DP_AUXCTL__SIZE_1 7 /* */
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#define NV_PMGR_DP_AUXCTL_CMDLEN 7:0 /* RWIVF */
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#define NV_PMGR_DP_AUXCTL_CMDLEN_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DP_AUXCTL_ADDRESS_ONLY 8:8 /* RWIVF */
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#define NV_PMGR_DP_AUXCTL_ADDRESS_ONLY_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DP_AUXCTL_ADDRESS_ONLY_NO 0x00000000 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_ADDRESS_ONLY_YES 0x00000001 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_CMD 15:12 /* RWIVF */
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#define NV_PMGR_DP_AUXCTL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DP_AUXCTL_CMD_I2CWR 0x00000000 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_CMD_I2CRD 0x00000001 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_CMD_I2CREQWSTAT 0x00000002 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_CMD_MOTWR 0x00000004 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_CMD_MOTRD 0x00000005 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_CMD_MOTREQWSTAT 0x00000006 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_CMD_AUXWR 0x00000008 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_CMD_AUXRD 0x00000009 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_TRANSACTREQ 16:16 /* RWIVF */
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#define NV_PMGR_DP_AUXCTL_TRANSACTREQ_DONE 0x00000000 /* R-I-V */
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#define NV_PMGR_DP_AUXCTL_TRANSACTREQ_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_DP_AUXCTL_TRANSACTREQ_TRIGGER 0x00000001 /* -W--T */
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#define NV_PMGR_DP_AUXCTL_SEMA_REQUEST 22:20 /* RWIVF */
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#define NV_PMGR_DP_AUXCTL_SEMA_REQUEST_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DP_AUXCTL_SEMA_REQUEST_RELEASE 0x00000000 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_SEMA_REQUEST_RM 0x00000001 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_SEMA_REQUEST_VBIOS 0x00000002 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_SEMA_REQUEST_PMU 0x00000003 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_SEMA_REQUEST_GSP 0x00000004 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_SEMA_REQUEST_SEC2 0x00000005 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_SEMA_GRANT 26:24 /* R--VF */
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#define NV_PMGR_DP_AUXCTL_SEMA_GRANT_INIT 0x00000000 /* R---V */
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#define NV_PMGR_DP_AUXCTL_SEMA_GRANT_NONE 0x00000000 /* R---V */
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#define NV_PMGR_DP_AUXCTL_SEMA_GRANT_RM 0x00000001 /* R---V */
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#define NV_PMGR_DP_AUXCTL_SEMA_GRANT_VBIOS 0x00000002 /* R---V */
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#define NV_PMGR_DP_AUXCTL_SEMA_GRANT_PMU 0x00000003 /* R---V */
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#define NV_PMGR_DP_AUXCTL_SEMA_GRANT_GSP 0x00000004 /* R---V */
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#define NV_PMGR_DP_AUXCTL_SEMA_GRANT_SEC2 0x00000005 /* R---V */
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#define NV_PMGR_DP_AUXCTL_RESET 31:31 /* RWIVF */
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#define NV_PMGR_DP_AUXCTL_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_DP_AUXCTL_RESET_ASSERT 0x00000001 /* RW--V */
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#define NV_PMGR_DP_AUXCTL_RESET_DEASSERT 0x00000000 /* RW--V */
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#define NV_PMGR_DP_AUXSTAT(i) (0x0000D958+(i)*80) /* RW-4A */
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#define NV_PMGR_DP_AUXSTAT__SIZE_1 7 /* */
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#define NV_PMGR_DP_AUXSTAT_REPLY_M 7:0 /* R--UF */
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#define NV_PMGR_DP_AUXSTAT_TIMEOUT 8:8 /* RWIVF */
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#define NV_PMGR_DP_AUXSTAT_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PMGR_DP_AUXSTAT_TIMEOUT_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_TIMEOUT_RESET 0x00000001 /* -W--C */
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#define NV_PMGR_DP_AUXSTAT_RX_ERROR 9:9 /* RWIVF */
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#define NV_PMGR_DP_AUXSTAT_RX_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PMGR_DP_AUXSTAT_RX_ERROR_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_RX_ERROR_RESET 0x00000001 /* -W--C */
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#define NV_PMGR_DP_AUXSTAT_SINKSTAT_ERROR 10:10 /* RWIVF */
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#define NV_PMGR_DP_AUXSTAT_SINKSTAT_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PMGR_DP_AUXSTAT_SINKSTAT_ERROR_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_SINKSTAT_ERROR_RESET 0x00000001 /* -W--C */
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#define NV_PMGR_DP_AUXSTAT_NO_STOP_ERROR 11:11 /* RWIVF */
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#define NV_PMGR_DP_AUXSTAT_NO_STOP_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PMGR_DP_AUXSTAT_NO_STOP_ERROR_PENDING 0x00000001 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_NO_STOP_ERROR_RESET 0x00000001 /* -W--C */
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#define NV_PMGR_DP_AUXSTAT_REPLYTYPE 19:16 /* R--VF */
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#define NV_PMGR_DP_AUXSTAT_REPLYTYPE_ACK 0x00000000 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_REPLYTYPE_NACK 0x00000001 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_REPLYTYPE_DEFER 0x00000002 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_REPLYTYPE_I2CNACK 0x00000004 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_REPLYTYPE_I2CDEFER 0x00000008 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE 23:20 /* R-IVF */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_SYNC 0x00000001 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_START1 0x00000002 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_COMMAND 0x00000003 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_ADDRESS 0x00000004 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_LENGTH 0x00000005 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_WRITE1 0x00000006 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_READ1 0x00000007 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_GET_M 0x00000008 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_STOP1 0x00000009 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_STOP2 0x0000000A /* R---V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_REPLY 0x0000000B /* R---V */
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#define NV_PMGR_DP_AUXSTAT_AUXCTL_STATE_CLEANUP 0x0000000C /* R---V */
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#define NV_PMGR_DP_AUXSTAT_HPD_STATUS 28:28 /* R--VF */
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#define NV_PMGR_DP_AUXSTAT_HPD_STATUS_UNPLUG 0x00000000 /* R---V */
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#define NV_PMGR_DP_AUXSTAT_HPD_STATUS_PLUGGED 0x00000001 /* R---V */
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#define NV_PMGR_DP_AUX_SINKSTATLO(i) (0x0000D95C+(i)*80) /* R--4A */
|
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#define NV_PMGR_DP_AUX_SINKSTATLO__SIZE_1 7 /* */
|
|
#define NV_PMGR_DP_AUX_SINKSTATLO_REG 31:0 /* R--UF */
|
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#define NV_PMGR_DP_AUX_SINKSTATLO_BYTE0 7:0 /* */
|
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#define NV_PMGR_DP_AUX_SINKSTATLO_BYTE1 15:8 /* */
|
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#define NV_PMGR_DP_AUX_SINKSTATLO_BYTE2 23:16 /* */
|
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#define NV_PMGR_DP_AUX_SINKSTATLO_BYTE3 31:24 /* */
|
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#define NV_PMGR_DP_AUX_SINKSTATHI(i) (0x0000D960+(i)*80) /* R--4A */
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|
#define NV_PMGR_DP_AUX_SINKSTATHI__SIZE_1 7 /* */
|
|
#define NV_PMGR_DP_AUX_SINKSTATHI_REG 15:0 /* R--UF */
|
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#define NV_PMGR_DP_AUX_SINKSTATHI_BYTE0 7:0 /* */
|
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#define NV_PMGR_DP_AUX_SINKSTATHI_BYTE1 15:8 /* */
|
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#define NV_PMGR_HPD_CONFIG(i) (0x0000D964+(i)*80) /* RW-4A */
|
|
#define NV_PMGR_HPD_CONFIG__SIZE_1 7 /* */
|
|
#define NV_PMGR_HPD_CONFIG_PLUG_MIN_TIME 15:0 /* RWIVF */
|
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#define NV_PMGR_HPD_CONFIG_PLUG_MIN_TIME_INIT 0x000000FA /* RWI-V */
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#define NV_PMGR_HPD_CONFIG_UNPLUG_MIN_TIME 31:16 /* RWIVF */
|
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#define NV_PMGR_HPD_CONFIG_UNPLUG_MIN_TIME_INIT 0x000007D0 /* RWI-V */
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#define NV_PMGR_HPD_IRQ_CONFIG(i) (0x0000D968+(i)*80) /* RW-4A */
|
|
#define NV_PMGR_HPD_IRQ_CONFIG__SIZE_1 7 /* */
|
|
#define NV_PMGR_HPD_IRQ_CONFIG_MIN_LOW_TIME 15:0 /* RWIVF */
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#define NV_PMGR_HPD_IRQ_CONFIG_MIN_LOW_TIME_INIT 0x000000FA /* RWI-V */
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#define NV_PMGR_HPD_IRQ_CONFIG_AUTO_DPCD_READ 16:16 /* RWIVF */
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#define NV_PMGR_HPD_IRQ_CONFIG_AUTO_DPCD_READ_INIT 0x00000001 /* R-I-V */
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#define NV_PMGR_HPD_IRQ_CONFIG_AUTO_DPCD_READ_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_HPD_IRQ_CONFIG_AUTO_DPCD_READ_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_DP_AUX_CONFIG(i) (0x0000D96C+(i)*80) /* RW-4A */
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#define NV_PMGR_DP_AUX_CONFIG__SIZE_1 7 /* */
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#define NV_PMGR_DP_AUX_CONFIG_TIMEOUT 15:0 /* RWIVF */
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#define NV_PMGR_DP_AUX_CONFIG_TIMEOUT_INIT 0x00000C80 /* RWI-V */
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#define NV_PMGR_DP_AUX_CONFIG_IDLETIME 19:16 /* RWIVF */
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#define NV_PMGR_DP_AUX_CONFIG_IDLETIME_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_HYBRID_PADCTL(i) (0x0000D970+(i)*80) /* RW-4A */
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#define NV_PMGR_HYBRID_PADCTL__SIZE_1 7 /* */
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#define NV_PMGR_HYBRID_PADCTL_MODE 0:0 /* RWIVF */
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#define NV_PMGR_HYBRID_PADCTL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_HYBRID_PADCTL_MODE_AUX 0x00000000 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_MODE_I2C 0x00000001 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_INPUT_RCV 1:1 /* RWIVF */
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#define NV_PMGR_HYBRID_PADCTL_AUX_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_INPUT_RCV_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_INPUT_RCV_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_DRVI 7:2 /* RWIVF */
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#define NV_PMGR_HYBRID_PADCTL_AUX_DRVI_INIT 0x00000028 /* RWI-V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_DRVZ 10:8 /* RWIVF */
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#define NV_PMGR_HYBRID_PADCTL_AUX_DRVZ_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_DRVZ_78_OHM 0x00000000 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_DRVZ_60_OHM 0x00000001 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_DRVZ_54_OHM 0x00000002 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_DRVZ_45_OHM 0x00000003 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_DRVZ_50_OHM 0x00000004 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_DRVZ_42_OHM 0x00000005 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_DRVZ_39_OHM 0x00000006 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_DRVZ_34_OHM 0x00000007 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_CMH 13:12 /* RWIVF */
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#define NV_PMGR_HYBRID_PADCTL_AUX_CMH_INIT 0x00000002 /* RWI-V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_CMH_0_60V 0x00000000 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_CMH_0_64V 0x00000001 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_CMH_0_70V 0x00000002 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_AUX_CMH_0_56V 0x00000003 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_I2C_SCL_INPUT_RCV 14:14 /* RWIVF */
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#define NV_PMGR_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_I2C_SCL_INPUT_RCV_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_I2C_SDA_INPUT_RCV 15:15 /* RWIVF */
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#define NV_PMGR_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_HYBRID_PADCTL_I2C_SDA_INPUT_RCV_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_HYBRID_SPARE(i) (0x0000D97C+(i)*80) /* RW-4A */
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#define NV_PMGR_HYBRID_SPARE__SIZE_1 7 /* */
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#define NV_PMGR_HYBRID_SPARE_PAD_PWR 0:0 /* RWIVF */
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#define NV_PMGR_HYBRID_SPARE_PAD_PWR_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_HYBRID_SPARE_PAD_PWR_POWERDOWN 0x00000001 /* RW--V */
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#define NV_PMGR_HYBRID_SPARE_PAD_PWR_POWERUP 0x00000000 /* RW--V */
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#define NV_PMGR_HYBRID_SPARE_REG 31:1 /* RWIVF */
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#define NV_PMGR_HYBRID_SPARE_REG_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_FPGA_DEBUG_CMD 0x0000E734 /* RW-4R */
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#define NV_PMGR_FPGA_DEBUG_CMD_OFFSET 15:0 /* RWIVF */
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#define NV_PMGR_FPGA_DEBUG_CMD_OFFSET_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_FPGA_DEBUG_CMD_OP 23:16 /* RWIVF */
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#define NV_PMGR_FPGA_DEBUG_CMD_OP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_FPGA_DEBUG_CMD_OP_SERDES 0x00000000 /* RW--V */
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#define NV_PMGR_FPGA_DEBUG_CMD_RW 31:31 /* RWIVF */
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#define NV_PMGR_FPGA_DEBUG_CMD_RW_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_FPGA_DEBUG_CMD_RW_READ 0x00000000 /* RW--V */
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#define NV_PMGR_FPGA_DEBUG_CMD_RW_WRITE 0x00000001 /* RW--V */
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#define NV_PMGR_FPGA_DEBUG_DATA 0x0000E738 /* R--4R */
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#define NV_PMGR_FPGA_DEBUG_DATA_REG 31:0 /* R-IVF */
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#define NV_PMGR_FPGA_DEBUG_DATA_REG_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_MUTEX_ID_ACQUIRE 0x0000DF00 /* R--4R */
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#define NV_PMGR_MUTEX_ID_ACQUIRE_VALUE 7:0 /* R-IUF */
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#define NV_PMGR_MUTEX_ID_ACQUIRE_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PMGR_MUTEX_ID_ACQUIRE_VALUE_NOT_AVAIL 0x000000ff /* R---V */
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#define NV_PMGR_MUTEX_ID_RELEASE 0x0000DF04 /* RW-4R */
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#define NV_PMGR_MUTEX_ID_RELEASE_VALUE 7:0 /* RWIUF */
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#define NV_PMGR_MUTEX_ID_RELEASE_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_MUTEX_REG(i) (0x0000DF08+(i)*4) /* RW-4A */
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#define NV_PMGR_MUTEX_REG__SIZE_1 32 /* */
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#define NV_PMGR_MUTEX_REG_VALUE 7:0 /* RWIVF */
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#define NV_PMGR_MUTEX_REG_VALUE_INITIAL_LOCK 0x00000000 /* RWI-V */
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#define NV_PMGR_SCRATCH(i) (0x0000DFE0+(i)*4) /* RW-4A */
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#define NV_PMGR_SCRATCH__SIZE_1 4 /* */
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#define NV_PMGR_SCRATCH_REG 31:0 /* RWIVF */
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#define NV_PMGR_SCRATCH_REG_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK 0x0000E2B0 /* RW-4R */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION__LEVEL2_ENABLE 0x0000000C /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION__LEVEL2_ENABLE 0x0000000C /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK 0x0000E2B4 /* RW-4R */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION__LEVEL2_ENABLE 0x0000000C /* RWI-V */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_SECURE_WR_SCRATCH_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH(i) (0x0000E290 + (i)*4) /* RW-4A */
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|
#define NV_PMGR_SECURE_SCRATCH__SIZE_1 4 /* */
|
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#define NV_PMGR_SECURE_SCRATCH__PRIV_LEVEL_MASK 0x0000E2B0 /* */
|
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#define NV_PMGR_SECURE_SCRATCH_VAL 31:0 /* RWIUF */
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#define NV_PMGR_SECURE_SCRATCH_VAL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_SECURE_WR_SCRATCH(i) (0x0000E2A0 + (i)*4) /* RW-4A */
|
|
#define NV_PMGR_SECURE_WR_SCRATCH__SIZE_1 4 /* */
|
|
#define NV_PMGR_SECURE_WR_SCRATCH__PRIV_LEVEL_MASK 0x0000E2B4 /* */
|
|
#define NV_PMGR_SECURE_WR_SCRATCH_VAL 31:0 /* RWIUF */
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|
#define NV_PMGR_SECURE_WR_SCRATCH_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_I2C 0x0000E2C4 /* RW-4R */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C__PRIV_LEVEL_MASK 0x0000D7CC /* */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C0_SCL 0:0 /* RWIVF */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C0_SCL_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C0_SCL_SEL_18 0x00000000 /* RW--V */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C0_SCL_SEL_33 0x00000001 /* RW--V */
|
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2C0_SDA 1:1 /* RWIVF */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C0_SDA_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C0_SDA_SEL_18 0x00000000 /* RW--V */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C0_SDA_SEL_33 0x00000001 /* RW--V */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C1_SCL 2:2 /* RWIVF */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C1_SCL_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C1_SCL_SEL_18 0x00000000 /* RW--V */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C1_SCL_SEL_33 0x00000001 /* RW--V */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C1_SDA 3:3 /* RWIVF */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C1_SDA_INIT 0x00000001 /* RWI-V */
|
|
#define NV_PMGR_RCV_33_18_SEL_I2C_I2C1_SDA_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2C1_SDA_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2C2_SCL 4:4 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2C2_SCL_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2C2_SCL_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2C2_SCL_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2C2_SDA 5:5 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2C2_SDA_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2C2_SDA_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2C2_SDA_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2CS_SCL 6:6 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2CS_SCL_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2CS_SCL_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2CS_SCL_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2CS_SDA 7:7 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2CS_SDA_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2CS_SDA_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_I2C_I2CS_SDA_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX 0x0000E2C8 /* RW-4R */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX__PRIV_LEVEL_MASK 0x0000D7CC /* */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPA 0:0 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPA_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPA_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPA_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPB 1:1 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPB_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPB_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPB_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPC 2:2 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPC_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPC_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPC_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPD 3:3 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPD_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPD_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPD_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPE 4:4 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPE_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPE_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPF 5:5 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPF_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPF_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPF_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPG 6:6 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPG_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPG_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_DPAUX_IFPG_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_ROM 0x0000E2CC /* RW-4R */
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#define NV_PMGR_RCV_33_18_SEL_ROM__PRIV_LEVEL_MASK 0x0000D7CC /* */
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|
#define NV_PMGR_RCV_33_18_SEL_ROM_CS 0:0 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_ROM_CS_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_ROM_CS_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_ROM_CS_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_ROM_SCK 1:1 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_ROM_SCK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_ROM_SCK_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_ROM_SCK_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_ROM_SI 2:2 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_ROM_SI_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_ROM_SI_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_ROM_SI_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_ROM_SO 3:3 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_ROM_SO_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_ROM_SO_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_ROM_SO_SEL_33 0x00000001 /* RW--V */
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#define NV_GPIO_PAD_CONFIG(i) ( 0x00021400+(i) * 0x4) /* RW-4A */
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#define NV_GPIO_PAD_CONFIG__SIZE_1 40 /* */
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#define NV_GPIO_PAD_CONFIG__PRIV_LEVEL_MASK 0x00021800 /* */
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#define NV_GPIO_PAD_CONFIG_PAD_INPUT_RCV 0:0 /* RWIVF */
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#define NV_GPIO_PAD_CONFIG_PAD_INPUT_RCV_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_PAD_CONFIG_PAD_INPUT_RCV_DIS 0x00000000 /* RW--V */
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#define NV_GPIO_PAD_CONFIG_PAD_INPUT_RCV_EN 0x00000001 /* RW--V */
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#define NV_GPIO_PAD_CONFIG_RCV_33_18_SEL 1:1 /* RWIVF */
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#define NV_GPIO_PAD_CONFIG_RCV_33_18_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_GPIO_PAD_CONFIG_RCV_33_18_SEL_SEL_18 0x00000000 /* RW--V */
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#define NV_GPIO_PAD_CONFIG_RCV_33_18_SEL_SEL_33 0x00000001 /* RW--V */
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#define NV_GPIO_PAD_CONFIG_E_ONE 2:2 /* RWIVF */
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#define NV_GPIO_PAD_CONFIG_E_ONE_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_PAD_CONFIG_E_TWO 3:3 /* RWIVF */
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#define NV_GPIO_PAD_CONFIG_E_TWO_INIT 0x00000001 /* RWI-V */
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#define NV_GPIO_PAD_CONFIG_SCHMITT 5:4 /* RWIVF */
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#define NV_GPIO_PAD_CONFIG_SCHMITT_INIT 0x00000003 /* RWI-V */
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#define NV_GPIO_PAD_CONFIG_SCHMITT_DIS 0x00000000 /* RW--V */
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#define NV_GPIO_PAD_CONFIG_SCHMITT_0075V 0x00000001 /* RW--V */
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#define NV_GPIO_PAD_CONFIG_SCHMITT_015V 0x00000002 /* RW--V */
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#define NV_GPIO_PAD_CONFIG_SCHMITT_024V 0x00000003 /* RW--V */
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#define NV_GPIO_PAD_CONFIG_SPARE 7:6 /* RWIVF */
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#define NV_GPIO_PAD_CONFIG_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_I2C 0x0000E2E8 /* RW-4R */
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#define NV_PMGR_PAD_I2C__PRIV_LEVEL_MASK 0x0000D7CC /* */
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#define NV_PMGR_PAD_I2C_I2C0_SPARE 1:0 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2C0_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2C0_SCHMITT 3:2 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2C0_SCHMITT_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2C0_SCHMITT_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C0_SCHMITT_0075V 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C0_SCHMITT_015V 0x00000002 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C0_SCHMITT_024V 0x00000003 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C0_E_ONE 4:4 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2C0_E_ONE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2C0_E_ONE_OFF 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C0_E_ONE_ON 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C0_E_TWO 5:5 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2C0_E_TWO_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2C0_E_TWO_OFF 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C0_E_TWO_ON 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C1_SPARE 9:8 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2C1_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2C1_SCHMITT 11:10 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2C1_SCHMITT_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2C1_SCHMITT_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C1_SCHMITT_0075V 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C1_SCHMITT_015V 0x00000002 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C1_SCHMITT_024V 0x00000003 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C1_E_ONE 12:12 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2C1_E_ONE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2C1_E_ONE_OFF 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C1_E_ONE_ON 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C1_E_TWO 13:13 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2C1_E_TWO_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2C1_E_TWO_OFF 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C1_E_TWO_ON 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C2_SPARE 17:16 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2C2_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2C2_SCHMITT 19:18 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2C2_SCHMITT_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2C2_SCHMITT_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C2_SCHMITT_0075V 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C2_SCHMITT_015V 0x00000002 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C2_SCHMITT_024V 0x00000003 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C2_E_ONE 20:20 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2C2_E_ONE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2C2_E_ONE_OFF 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C2_E_ONE_ON 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C2_E_TWO 21:21 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2C2_E_TWO_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2C2_E_TWO_OFF 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2C2_E_TWO_ON 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2CS_SPARE 25:24 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2CS_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2CS_SCHMITT 27:26 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2CS_SCHMITT_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2CS_SCHMITT_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2CS_SCHMITT_0075V 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2CS_SCHMITT_015V 0x00000002 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2CS_SCHMITT_024V 0x00000003 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2CS_E_ONE 28:28 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2CS_E_ONE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2CS_E_ONE_OFF 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2CS_E_ONE_ON 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2CS_E_TWO 29:29 /* RWIVF */
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#define NV_PMGR_PAD_I2C_I2CS_E_TWO_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_I2C_I2CS_E_TWO_OFF 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_I2C_I2CS_E_TWO_ON 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_SROM 0x0000E2EC /* RW-4R */
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#define NV_PMGR_PAD_SROM__PRIV_LEVEL_MASK 0x0000D7CC /* */
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#define NV_PMGR_PAD_SROM_ROM_SPARE 1:0 /* RWIVF */
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#define NV_PMGR_PAD_SROM_ROM_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_SROM_ROM_SCHMITT 3:2 /* RWIVF */
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#define NV_PMGR_PAD_SROM_ROM_SCHMITT_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_PAD_SROM_ROM_SCHMITT_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_SROM_ROM_SCHMITT_0075V 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_SROM_ROM_SCHMITT_015V 0x00000002 /* RW--V */
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#define NV_PMGR_PAD_SROM_ROM_SCHMITT_024V 0x00000003 /* RW--V */
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#define NV_PMGR_PAD_ASRC 0x0000E314 /* RW-4R */
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#define NV_PMGR_PAD_ASRC__PRIV_LEVEL_MASK 0x0000D7CC /* */
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#define NV_PMGR_PAD_ASRC_MISC0_OUTER 6:0 /* RWIUF */
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#define NV_PMGR_PAD_ASRC_MISC0_OUTER_INIT 0x00000040 /* RWI-V */
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#define NV_PMGR_PAD_ASRC_MISC1_OUTER 14:8 /* RWIUF */
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#define NV_PMGR_PAD_ASRC_MISC1_OUTER_INIT 0x00000040 /* RWI-V */
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#define NV_PMGR_PAD_ASRC_ROM_XTAL 22:16 /* RWIUF */
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#define NV_PMGR_PAD_ASRC_ROM_XTAL_INIT 0x00000040 /* RWI-V */
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#define NV_PMGR_PAD_ASRC_XTAL 30:24 /* RWIUF */
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#define NV_PMGR_PAD_ASRC_XTAL_INIT 0x00000040 /* RWI-V */
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#define NV_PMGR_PAD_MIOA 0x0000E2F0 /* RW-4R */
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#define NV_PMGR_PAD_MIOA__PRIV_LEVEL_MASK 0x0000D7CC /* */
|
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#define NV_PMGR_PAD_MIOA_SPARE 3:0 /* RWIVF */
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#define NV_PMGR_PAD_MIOA_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_MIOA_SCHMITT 5:4 /* RWIVF */
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#define NV_PMGR_PAD_MIOA_SCHMITT_INIT 0x00000002 /* RWI-V */
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#define NV_PMGR_PAD_MIOA_SCHMITT_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_MIOA_SCHMITT_0075V 0x00000001 /* RW--V */
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|
#define NV_PMGR_PAD_MIOA_SCHMITT_015V 0x00000002 /* RW--V */
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|
#define NV_PMGR_PAD_MIOA_SCHMITT_024V 0x00000003 /* RW--V */
|
|
#define NV_PMGR_PAD_MIOA_PWR 6:6 /* RWIVF */
|
|
#define NV_PMGR_PAD_MIOA_PWR_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_MIOA_PWR_POWERDOWN 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_MIOA_PWR_POWERUP 0x00000000 /* RW--V */
|
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#define NV_PMGR_PAD_MIOA_PWR__PROD 0x00000001 /* RW--V */
|
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#define NV_PMGR_PAD_MIOA_PREAMP 10:7 /* RWIVF */
|
|
#define NV_PMGR_PAD_MIOA_PREAMP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_PAD_MIOA_E_DEEMP 17:17 /* RWIVF */
|
|
#define NV_PMGR_PAD_MIOA_E_DEEMP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_PAD_MIOA_E_DEEMP_DIS 0x00000000 /* RW--V */
|
|
#define NV_PMGR_PAD_MIOA_E_DEEMP_EN 0x00000001 /* RW--V */
|
|
#define NV_PMGR_PAD_MIOA_DEEMP 21:18 /* RWIVF */
|
|
#define NV_PMGR_PAD_MIOA_DEEMP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_PAD_MIOA_E_SHALLOW_LPBK 22:22 /* RWIVF */
|
|
#define NV_PMGR_PAD_MIOA_E_SHALLOW_LPBK_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_PAD_MIOA_E_SHALLOW_LPBK_DIS 0x00000000 /* RW--V */
|
|
#define NV_PMGR_PAD_MIOA_E_SHALLOW_LPBK_EN 0x00000001 /* RW--V */
|
|
#define NV_PMGR_PAD_MIOA_E_INT_VREF 23:23 /* RWIVF */
|
|
#define NV_PMGR_PAD_MIOA_E_INT_VREF_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_PAD_MIOA_E_INT_VREF_DIS 0x00000000 /* RW--V */
|
|
#define NV_PMGR_PAD_MIOA_E_INT_VREF_EN 0x00000001 /* RW--V */
|
|
#define NV_PMGR_PAD_MIOA_VREF_SEL 26:24 /* RWIVF */
|
|
#define NV_PMGR_PAD_MIOA_VREF_SEL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_PAD_MIOA_E_WEAKPULL 27:27 /* RWIVF */
|
|
#define NV_PMGR_PAD_MIOA_E_WEAKPULL_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PMGR_PAD_MIOA_E_WEAKPULL_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_PMGR_PAD_MIOA_E_WEAKPULL_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_PMGR_PAD_MIOB 0x0000E2F4 /* RW-4R */
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#define NV_PMGR_PAD_MIOB__PRIV_LEVEL_MASK 0x0000D7CC /* */
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#define NV_PMGR_PAD_MIOB_SPARE 3:0 /* RWIVF */
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#define NV_PMGR_PAD_MIOB_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_MIOB_SCHMITT 5:4 /* RWIVF */
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#define NV_PMGR_PAD_MIOB_SCHMITT_INIT 0x00000002 /* RWI-V */
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#define NV_PMGR_PAD_MIOB_SCHMITT_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_MIOB_SCHMITT_0075V 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_MIOB_SCHMITT_015V 0x00000002 /* RW--V */
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#define NV_PMGR_PAD_MIOB_SCHMITT_024V 0x00000003 /* RW--V */
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#define NV_PMGR_PAD_MIOB_PWR 6:6 /* RWIVF */
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#define NV_PMGR_PAD_MIOB_PWR_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_MIOB_PWR_POWERDOWN 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_MIOB_PWR_POWERUP 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_MIOB_PWR__PROD 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_MIOB_PREAMP 10:7 /* RWIVF */
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#define NV_PMGR_PAD_MIOB_PREAMP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_MIOB_E_DEEMP 17:17 /* RWIVF */
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#define NV_PMGR_PAD_MIOB_E_DEEMP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_MIOB_E_DEEMP_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_MIOB_E_DEEMP_EN 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_MIOB_DEEMP 21:18 /* RWIVF */
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#define NV_PMGR_PAD_MIOB_DEEMP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_MIOB_E_SHALLOW_LPBK 22:22 /* RWIVF */
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#define NV_PMGR_PAD_MIOB_E_SHALLOW_LPBK_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_MIOB_E_SHALLOW_LPBK_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_MIOB_E_SHALLOW_LPBK_EN 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_MIOB_E_INT_VREF 23:23 /* RWIVF */
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#define NV_PMGR_PAD_MIOB_E_INT_VREF_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_MIOB_E_INT_VREF_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_MIOB_E_INT_VREF_EN 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_MIOB_VREF_SEL 26:24 /* RWIVF */
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#define NV_PMGR_PAD_MIOB_VREF_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_MIOB_E_WEAKPULL 27:27 /* RWIVF */
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#define NV_PMGR_PAD_MIOB_E_WEAKPULL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_MIOB_E_WEAKPULL_ENABLE 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_MIOB_E_WEAKPULL_DISABLE 0x00000000 /* RW--V */
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#define NV_PMGR_VPLL_EXT_REF_CONFIG(i) (0x0000E2F8+(i)*4) /* RW-4A */
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#define NV_PMGR_VPLL_EXT_REF_CONFIG__SIZE_1 4 /* */
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#define NV_PMGR_VPLL_EXT_REF_CONFIG_QUAL_DIV 5:0 /* RWIUF */
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#define NV_PMGR_VPLL_EXT_REF_CONFIG_QUAL_DIV_INIT 0x0000000E /* RWI-V */
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#define NV_PMGR_VPLL_EXT_REF_CONFIG_QUAL_TEST_PER 12:6 /* RWIUF */
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#define NV_PMGR_VPLL_EXT_REF_CONFIG_QUAL_TEST_PER_INIT 0x00000063 /* RWI-V */
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#define NV_PMGR_VPLL_EXT_REF_CONFIG_QUAL_STATUS 13:13 /* R--VF */
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#define NV_PMGR_VPLL_EXT_REF_CONFIG_QUAL_STATUS_INACTIVE 0x00000000 /* R---V */
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#define NV_PMGR_VPLL_EXT_REF_CONFIG_QUAL_STATUS_ACTIVE 0x00000001 /* R---V */
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#define NV_PMGR_RCV_33_18_SEL_EXT_REFCLK 0x0000E308 /* RW-4R */
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#define NV_PMGR_RCV_33_18_SEL_EXT_REFCLK_A 0:0 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_EXT_REFCLK_A_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_EXT_REFCLK_A_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_EXT_REFCLK_A_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_EXT_REFCLK_B 1:1 /* RWIVF */
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#define NV_PMGR_RCV_33_18_SEL_EXT_REFCLK_B_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_RCV_33_18_SEL_EXT_REFCLK_B_SEL_18 0x00000000 /* RW--V */
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#define NV_PMGR_RCV_33_18_SEL_EXT_REFCLK_B_SEL_33 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKA 0x0000E30C /* RW-4R */
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#define NV_PMGR_PAD_EXT_REFCLKA_SPARE 1:0 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKA_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKA_SCHMITT 3:2 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKA_SCHMITT_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKA_SCHMITT_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKA_SCHMITT_0075V 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKA_SCHMITT_015V 0x00000002 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKA_SCHMITT_024V 0x00000003 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_ONE 4:4 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_ONE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_TWO 5:5 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_TWO_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKA_EN 6:6 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKA_EN_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKA_EN_ACTIVE 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKA_EN_TRISTATE 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_INPUT 7:7 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_INPUT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_INPUT_LOW 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_INPUT_ACTIVE 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_PULLDN 8:8 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_PULLDN_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_PULLUP 9:9 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_PULLUP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_SCH 10:10 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKA_E_SCH_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKB 0x0000E310 /* RW-4R */
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#define NV_PMGR_PAD_EXT_REFCLKB_SPARE 1:0 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKB_SPARE_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKB_SCHMITT 3:2 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKB_SCHMITT_INIT 0x00000003 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKB_SCHMITT_DIS 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKB_SCHMITT_0075V 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKB_SCHMITT_015V 0x00000002 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKB_SCHMITT_024V 0x00000003 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_ONE 4:4 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_ONE_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_TWO 5:5 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_TWO_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKB_EN 6:6 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKB_EN_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKB_EN_ACTIVE 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKB_EN_TRISTATE 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_INPUT 7:7 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_INPUT_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_INPUT_LOW 0x00000000 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_INPUT_ACTIVE 0x00000001 /* RW--V */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_PULLDN 8:8 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_PULLDN_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_PULLUP 9:9 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_PULLUP_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_SCH 10:10 /* RWIVF */
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#define NV_PMGR_PAD_EXT_REFCLKB_E_SCH_INIT 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK(i) (0x0000E380 + (i)*4) /* RW-4A */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK__SIZE_1 8 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_EANBLED 0x0000000C /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_EANBLED 0x0000000C /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH0(i) (0x0000E3A0 + (i)*4) /* RW-4A */
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#define NV_PMGR_SECURE_SCRATCH0__SIZE_1 8 /* */
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#define NV_PMGR_SECURE_SCRATCH0__PRIV_LEVEL_MASK "NV_PMGR_SECURE_SCRATCH0_PRIV_LEVEL_MASK" /* */
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#define NV_PMGR_SECURE_SCRATCH0_VAL 31:0 /* RWIUF */
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#define NV_PMGR_SECURE_SCRATCH0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK(i) (0x0000E3C0 + (i)*4) /* RW-4A */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK__SIZE_1 8 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_EANBLED 0x0000000F /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_EANBLED 0x0000000C /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PMGR_SECURE_SCRATCH1(i) (0x0000E3E0 + (i)*4) /* RW-4A */
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#define NV_PMGR_SECURE_SCRATCH1__SIZE_1 8 /* */
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#define NV_PMGR_SECURE_SCRATCH1__PRIV_LEVEL_MASK "NV_PMGR_SECURE_SCRATCH1_PRIV_LEVEL_MASK" /* */
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#define NV_PMGR_SECURE_SCRATCH1_VAL 31:0 /* RWIUF */
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#define NV_PMGR_SECURE_SCRATCH1_VAL_INIT 0x00000000 /* RWI-V */
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#endif // __ga102_dev_pmgr_h__
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