6476 lines
594 KiB
C
6476 lines
594 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_nvltlc_ip_h__
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#define __ga102_dev_nvltlc_ip_h__
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/* This file is autogenerated. Do not edit */
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#define NV_NVLTLC_TX_SYS 0x000007FF:0x00000000 /* RW--D */
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#define NV_NVLTLC_RX_SYS 0x00000FFF:0x00000800 /* RW--D */
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#define NV_NVLTLC_TX_LNK 0x000017FF:0x00001000 /* RW--D */
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#define NV_NVLTLC_RX_LNK 0x00001FFF:0x00001800 /* RW--D */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0 0x00000000 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1 0x00000004 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2 0x00000008 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask2" /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK2_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3 0x0000000c /* RW-4R */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask3" /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK3_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4 0x00000010 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask4" /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK4_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5 0x00000014 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask5" /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK5_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6 0x00000018 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK6_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7 0x0000001c /* RW-4R */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask7" /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_SYS_PRIV_LEVEL_MASK7_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_SCRATCH_WARM 0x000007c0 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_SCRATCH_WARM_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_SYS_SCRATCH_COLD 0x000007c4 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_SCRATCH_COLD_DATA 31:0 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_SCRATCH_COLD_DATA_INIT 0xdeadbaad /* RWI-V */
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#define NV_NVLTLC_TX_SYS_SCRATCH_COLD_AND_DEBUG 0x000007c8 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_SCRATCH_COLD_AND_DEBUG_DATA 31:0 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_SCRATCH_COLD_AND_DEBUG_DATA_INIT 0xdeadbaad /* RWD-V */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK0 0x000007d0 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK0__PRIV_LEVEL_MASK 0x00000000 /* */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK0_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK0_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK1 0x000007d4 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK1__PRIV_LEVEL_MASK 0x00000004 /* */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK1_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK1_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK2 0x000007d8 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK2__PRIV_LEVEL_MASK 0x00000008 /* */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK2_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK2_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK3 0x000007dc /* RW-4R */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK3__PRIV_LEVEL_MASK 0x0000000c /* */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK3_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK3_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK4 0x000007e0 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK4__PRIV_LEVEL_MASK 0x00000010 /* */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK4_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK4_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK5 0x000007e4 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK5__PRIV_LEVEL_MASK 0x00000014 /* */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK5_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK5_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK6 0x000007e8 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK6__PRIV_LEVEL_MASK 0x00000018 /* */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK6_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK6_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK7 0x000007ec /* RW-4R */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK7__PRIV_LEVEL_MASK 0x0000001c /* */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK7_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_SCRATCH_PRIVMASK7_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG 0x00000080 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG__PRIV_LEVEL_MASK 0x00000008 /* */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_TIMEOUT 17:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_TIMEOUT_INIT 0x00001000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_SETUP_CLOCKS 22:20 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_SETUP_CLOCKS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_WAIT_CLOCKS 26:24 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_WAIT_CLOCKS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_HOLD_CLOCKS 29:27 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_HOLD_CLOCKS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_FS_ACTION 30:30 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_FS_ACTION_ERROR 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_FS_ACTION_SOLDIER_ON 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_RESET_ACTION 31:31 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_RESET_ACTION_ERROR 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_MASTER_SMCONFIG_RESET_ACTION_SOLDIER_ON 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_CLOCK_GATING 0x00000084 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_CLOCK_GATING__PRIV_LEVEL_MASK 0x00000008 /* */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_CLOCK_GATING_CG1_SLCG 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_CLOCK_GATING_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_CTRL_PRI_CLOCK_GATING_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_LINK_CONFIG 0x00000100 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_CTRL_LINK_CONFIG__PRIV_LEVEL_MASK 0x0000001c /* */
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#define NV_NVLTLC_TX_SYS_CTRL_LINK_CONFIG_NCISOC_EMBEDDED_DATA_OPTIMIZATION_ENABLE 8:8 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_LINK_CONFIG_NCISOC_EMBEDDED_DATA_OPTIMIZATION_ENABLE_ENABLED 0x00000001 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_LINK_CONFIG_NCISOC_EMBEDDED_DATA_OPTIMIZATION_ENABLE_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_SYS_CTRL_LINK_CONFIG_FORCE_BYTE_ENABLE_FLIT 16:16 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_LINK_CONFIG_FORCE_BYTE_ENABLE_FLIT_FORCE_BE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_CTRL_LINK_CONFIG_FORCE_BYTE_ENABLE_FLIT_DO_NOT_FORCE_BE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC0 0x00000104 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC0__PRIV_LEVEL_MASK 0x00000004 /* */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC0_CREDITS 11:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC0_CREDITS_INIT 0x000000a0 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC1 0x00000108 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC1__PRIV_LEVEL_MASK 0x00000004 /* */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC1_CREDITS 11:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC1_CREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC2 0x0000010c /* RW-4R */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC2__PRIV_LEVEL_MASK 0x00000004 /* */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC2_CREDITS 11:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC2_CREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC3 0x00000110 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC3__PRIV_LEVEL_MASK 0x00000004 /* */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC3_CREDITS 11:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC3_CREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC4 0x00000114 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC4__PRIV_LEVEL_MASK 0x00000004 /* */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC4_CREDITS 11:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC4_CREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC5 0x00000118 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC5__PRIV_LEVEL_MASK 0x00000004 /* */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC5_CREDITS 11:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC5_CREDITS_INIT 0x000000a0 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC6 0x0000011c /* RW-4R */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC6__PRIV_LEVEL_MASK 0x00000004 /* */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC6_CREDITS 11:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC6_CREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC7 0x00000120 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC7__PRIV_LEVEL_MASK 0x00000004 /* */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC7_CREDITS 11:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_CREDITS_VC7_CREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY 0x00000124 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY_BUFFERRDY 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY_BUFFERRDY_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_CTRL_BUFFER_READY_BUFFERRDY_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_CREDIT_CLEAR 0x00000128 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_CTRL_CREDIT_CLEAR__PRIV_LEVEL_MASK 0x0000000c /* */
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#define NV_NVLTLC_TX_SYS_CTRL_CREDIT_CLEAR_CREDIT_CLEAR_REQ 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_CTRL_CREDIT_CLEAR_CREDIT_CLEAR_REQ_START_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_CTRL_CREDIT_CLEAR_CREDIT_CLEAR_REQ_END_CLEAR 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_CTRL_CREDIT_CLEAR_CREDIT_CLEAR_ACK 1:1 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_CTRL_CREDIT_CLEAR_CREDIT_CLEAR_ACK_COMPLETE 0x00000001 /* R---V */
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#define NV_NVLTLC_TX_SYS_CTRL_CREDIT_CLEAR_CREDIT_CLEAR_ACK_NOT_COMPLETE 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_CTRL_CREDIT_CLEAR_CREDIT_CLEAR_STATE 9:8 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_CTRL_CREDIT_CLEAR_CREDIT_CLEAR_STATE_GOTO_CLEAR 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_CTRL_CREDIT_CLEAR_CREDIT_CLEAR_STATE_CLEAR 0x00000001 /* R---V */
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#define NV_NVLTLC_TX_SYS_CTRL_CREDIT_CLEAR_CREDIT_CLEAR_STATE_GOTO_ACTIVE 0x00000002 /* R---V */
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#define NV_NVLTLC_TX_SYS_CTRL_CREDIT_CLEAR_CREDIT_CLEAR_STATE_ACTIVE 0x00000003 /* R---V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_CTRL 0x00000200 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_CTRL__PRIV_LEVEL_MASK 0x00000018 /* */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE 1:1 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT 0x00000204 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT__PRIV_LEVEL_MASK 0x00000018 /* */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_NCISOC_ECC_CTL3_PARITY 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_NCISOC_ECC_CTL3_PARITY_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_NCISOC_ECC_CTL3_PARITY_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_CREQ_RAM_ECC_SBE 1:1 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_CREQ_RAM_ECC_SBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_CREQ_RAM_ECC_SBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_CREQ_RAM_ECC_DBE 2:2 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_CREQ_RAM_ECC_DBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_CREQ_RAM_ECC_DBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_RSP_RAM_ECC_SBE 3:3 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_RSP_RAM_ECC_SBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_RSP_RAM_ECC_SBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_RSP_RAM_ECC_DBE 4:4 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_RSP_RAM_ECC_DBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_RSP_RAM_ECC_DBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_COM_RAM_ECC_SBE 5:5 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_COM_RAM_ECC_SBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_COM_RAM_ECC_SBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_COM_RAM_ECC_DBE 6:6 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_COM_RAM_ECC_DBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_COM_RAM_ECC_DBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_RSP1_RAM_ECC_SBE 7:7 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_RSP1_RAM_ECC_SBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_RSP1_RAM_ECC_SBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_RSP1_RAM_ECC_DBE 8:8 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_RSP1_RAM_ECC_DBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_ECC_INJECT_RSP1_RAM_ECC_DBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_NCISOC_ECC_ERROR_COUNTER 0x00000208 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_ERR_NCISOC_ECC_ERROR_COUNTER__PRIV_LEVEL_MASK 0x00000018 /* */
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#define NV_NVLTLC_TX_SYS_ERR_NCISOC_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_NCISOC_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_NCISOC_ECC_ERROR_COUNTER_LIMIT 0x0000020c /* RW-4R */
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#define NV_NVLTLC_TX_SYS_ERR_NCISOC_ECC_ERROR_COUNTER_LIMIT__PRIV_LEVEL_MASK 0x00000018 /* */
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#define NV_NVLTLC_TX_SYS_ERR_NCISOC_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_NCISOC_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0 0x00000280 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_NCISOC_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXPOISONDET 23:23 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXPOISONDET_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXPOISONDET_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_HW_ERR 24:24 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_HW_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_HW_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_UR_ERR 25:25 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_UR_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_UR_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_PRIV_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_STATUS_0_TXRSPSTATUS_PRIV_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0 0x00000284 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0__PRIV_LEVEL_MASK 0x0000001c /* */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_NCISOC_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_NCISOC_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_NCISOC_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_NCISOC_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_TXPOISONDET 23:23 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_TXPOISONDET_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_TXPOISONDET_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_TXRSPSTATUS_HW_ERR 24:24 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_TXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_TXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_TXRSPSTATUS_UR_ERR 25:25 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_TXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_TXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_TXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_LOG_EN_0_TXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0 0x00000288 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXPOISONDET 23:23 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXPOISONDET_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXPOISONDET_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR 24:24 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR 25:25 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0 0x0000028c /* RW-4R */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXPOISONDET 23:23 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXPOISONDET_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXPOISONDET_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR 24:24 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR 25:25 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_NON_FATAL_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0 0x00000290 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_TXPOISONDET 23:23 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_TXPOISONDET_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_TXPOISONDET_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_TXRSPSTATUS_HW_ERR 24:24 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_TXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_TXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_TXRSPSTATUS_UR_ERR 25:25 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_TXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_TXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CORRECTABLE_REPORT_EN_0_TXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0 0x00000294 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0__PRIV_LEVEL_MASK 0x0000001c /* */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_NCISOC_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_NCISOC_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_NCISOC_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_NCISOC_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_NCISOC_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_TXPOISONDET 23:23 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_TXPOISONDET_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_TXPOISONDET_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_TXRSPSTATUS_HW_ERR 24:24 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_TXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_TXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_TXRSPSTATUS_UR_ERR 25:25 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_TXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_TXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWEVF */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_TXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_SYS_ERR_CONTAIN_EN_0_TXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0 0x00000298 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0__PRIV_LEVEL_MASK 0x00000010 /* */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_NCISOC_PARITY_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_NCISOC_PARITY_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_NCISOC_HDR_ECC_DBE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_NCISOC_HDR_ECC_DBE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_NCISOC_DAT_ECC_DBE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_NCISOC_DAT_ECC_DBE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_NCISOC_ECC_LIMIT_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_NCISOC_ECC_LIMIT_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_TXPOISONDET 23:23 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_TXPOISONDET_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_TXPOISONDET_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_TXRSPSTATUS_HW_ERR 24:24 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_TXRSPSTATUS_HW_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_TXRSPSTATUS_HW_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_TXRSPSTATUS_UR_ERR 25:25 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_TXRSPSTATUS_UR_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_TXRSPSTATUS_UR_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_TXRSPSTATUS_PRIV_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_REPORT_INJECT_0_TXRSPSTATUS_PRIV_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0 0x0000029c /* RW-4R */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR 8:8 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_DAT_ECC_DBE_ERR 9:9 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_ECC_LIMIT_ERR 10:10 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_NCISOC_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXPOISONDET 23:23 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXPOISONDET_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXPOISONDET_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_HW_ERR 24:24 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_HW_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_HW_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_UR_ERR 25:25 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_UR_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_UR_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_PRIV_ERR 26:26 /* RWDVF */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_PRIV_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_SYS_ERR_FIRST_0_TXRSPSTATUS_PRIV_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_0 0x000002a0 /* R--4R */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_0_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_0_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_1 0x000002a4 /* R--4R */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_1_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_1_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_2 0x000002a8 /* R--4R */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_2_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_2_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_3 0x000002ac /* R--4R */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_3_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_3_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_4 0x000002b0 /* R--4R */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_4_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_4_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_5 0x000002b4 /* R--4R */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_5_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_5_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_VALID 0x000002b8 /* R--4R */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_VALID_VALID 0:0 /* R-IVF */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_VALID_VALID_INVALID 0x00000000 /* R-I-V */
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#define NV_NVLTLC_TX_SYS_ERR_HEADER_LOG_VALID_VALID_VALID 0x00000001 /* R---V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_CTRL 0x00000500 /* RW-4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_CTRL__PRIV_LEVEL_MASK 0x00000010 /* */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_CTRL_ENABLE 0:0 /* RWIVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_0 0x00000504 /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_0_PARSE_ENTRY0 15:0 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_0_PARSE_ENTRY0_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_0_PARSE_ENTRY1 31:16 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_0_PARSE_ENTRY1_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_1 0x00000508 /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_1_PARSE_ENTRY2 15:0 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_1_PARSE_ENTRY2_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_1_PARSE_ENTRY3 31:16 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_1_PARSE_ENTRY3_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_2 0x0000050c /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_2_PARSE_ENTRY4 15:0 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_2_PARSE_ENTRY4_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_2_PARSE_ENTRY5 31:16 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_2_PARSE_ENTRY5_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_3 0x00000510 /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_3_PARSE_ENTRY6 15:0 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_3_PARSE_ENTRY6_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_3_PARSE_ENTRY7 31:16 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_3_PARSE_ENTRY7_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_4 0x00000514 /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_4_TX_DBG_PARSE_IDX 2:0 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_4_TX_DBG_PARSE_IDX_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC0 0x00000518 /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC0_TX_RAM_LOWER_LIMIT 8:0 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC0_TX_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC0_TX_RAM_UPPER_LIMIT 24:16 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC0_TX_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC1 0x0000051c /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC1_TX_RAM_LOWER_LIMIT 8:0 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC1_TX_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC1_TX_RAM_UPPER_LIMIT 24:16 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC1_TX_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC2 0x00000520 /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC2_TX_RAM_LOWER_LIMIT 8:0 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC2_TX_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC2_TX_RAM_UPPER_LIMIT 24:16 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC2_TX_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC3 0x00000524 /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC3_TX_RAM_LOWER_LIMIT 8:0 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC3_TX_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC3_TX_RAM_UPPER_LIMIT 24:16 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC3_TX_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC4 0x00000528 /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC4_TX_RAM_LOWER_LIMIT 8:0 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC4_TX_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC4_TX_RAM_UPPER_LIMIT 24:16 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC4_TX_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC5 0x0000052c /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC5_TX_RAM_LOWER_LIMIT 8:0 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC5_TX_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC5_TX_RAM_UPPER_LIMIT 24:16 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC5_TX_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC6 0x00000530 /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC6_TX_RAM_LOWER_LIMIT 8:0 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC6_TX_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC6_TX_RAM_UPPER_LIMIT 24:16 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC6_TX_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC7 0x00000534 /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC7_TX_RAM_LOWER_LIMIT 8:0 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC7_TX_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC7_TX_RAM_UPPER_LIMIT 24:16 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_VC7_TX_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_16 0x00000538 /* R--4R */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_16_STALL 16:16 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_16_STALL_INIT 0x00000001 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_16_STALL_ACK 17:17 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_16_STALL_ACK_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_16_CREDIT_CLEAR 18:18 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_16_CREDIT_CLEAR_INIT 0x00000001 /* R-E-V */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_16_CREDIT_CLEAR_ACK 19:19 /* R-EVF */
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#define NV_NVLTLC_TX_SYS_DEBUG_MISC_16_CREDIT_CLEAR_ACK_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0 0x00000800 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1 0x00000804 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2 0x00000808 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask2" /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK2_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3 0x0000080c /* RW-4R */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask3" /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK3_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4 0x00000810 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask4" /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK4_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5 0x00000814 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask5" /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK5_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6 0x00000818 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK6_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7 0x0000081c /* RW-4R */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask7" /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_SYS_PRIV_LEVEL_MASK7_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_SCRATCH_WARM 0x00000fc0 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_SCRATCH_WARM_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_SYS_SCRATCH_COLD 0x00000fc4 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_SCRATCH_COLD_DATA 31:0 /* RWIVF */
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#define NV_NVLTLC_RX_SYS_SCRATCH_COLD_DATA_INIT 0xdeadbaad /* RWI-V */
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#define NV_NVLTLC_RX_SYS_SCRATCH_COLD_AND_DEBUG 0x00000fc8 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_SCRATCH_COLD_AND_DEBUG_DATA 31:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_SCRATCH_COLD_AND_DEBUG_DATA_INIT 0xdeadbaad /* RWD-V */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK0 0x00000fd0 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK0__PRIV_LEVEL_MASK 0x00000800 /* */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK0_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK0_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK1 0x00000fd4 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK1__PRIV_LEVEL_MASK 0x00000804 /* */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK1_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK1_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK2 0x00000fd8 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK2__PRIV_LEVEL_MASK 0x00000808 /* */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK2_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK2_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK3 0x00000fdc /* RW-4R */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK3__PRIV_LEVEL_MASK 0x0000080c /* */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK3_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK3_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK4 0x00000fe0 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK4__PRIV_LEVEL_MASK 0x00000810 /* */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK4_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK4_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK5 0x00000fe4 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK5__PRIV_LEVEL_MASK 0x00000814 /* */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK5_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK5_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK6 0x00000fe8 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK6__PRIV_LEVEL_MASK 0x00000818 /* */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK6_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK6_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK7 0x00000fec /* RW-4R */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK7__PRIV_LEVEL_MASK 0x0000081c /* */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK7_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_SCRATCH_PRIVMASK7_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG 0x00000880 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG__PRIV_LEVEL_MASK 0x00000808 /* */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_TIMEOUT 17:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_TIMEOUT_INIT 0x00001000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_SETUP_CLOCKS 22:20 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_SETUP_CLOCKS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_WAIT_CLOCKS 26:24 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_WAIT_CLOCKS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_HOLD_CLOCKS 29:27 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_HOLD_CLOCKS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_FS_ACTION 30:30 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_FS_ACTION_ERROR 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_FS_ACTION_SOLDIER_ON 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_RESET_ACTION 31:31 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_RESET_ACTION_ERROR 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_MASTER_SMCONFIG_RESET_ACTION_SOLDIER_ON 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_CLOCK_GATING 0x00000884 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_CLOCK_GATING__PRIV_LEVEL_MASK 0x00000808 /* */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_CLOCK_GATING_CG1_SLCG 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_CLOCK_GATING_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_CTRL_PRI_CLOCK_GATING_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_LINK_CONFIG 0x00000900 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_CTRL_LINK_CONFIG__PRIV_LEVEL_MASK 0x0000081c /* */
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#define NV_NVLTLC_RX_SYS_CTRL_LINK_CONFIG_DBI_ENABLE 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_LINK_CONFIG_DBI_ENABLE_ENABLED 0x00000001 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_LINK_CONFIG_DBI_ENABLE_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_CTRL_LINK_CONFIG_NCISOC_EMBEDDED_DATA_ENABLE 8:8 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_LINK_CONFIG_NCISOC_EMBEDDED_DATA_ENABLE_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_CTRL_LINK_CONFIG_NCISOC_EMBEDDED_DATA_ENABLE_DISABLED 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_LINK_CONFIG_SEND_POISON_ON_UC_RAM_ERROR 9:9 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_LINK_CONFIG_SEND_POISON_ON_UC_RAM_ERROR_ENABLED 0x00000001 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_LINK_CONFIG_SEND_POISON_ON_UC_RAM_ERROR_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC0 0x00000904 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC0__PRIV_LEVEL_MASK 0x00000804 /* */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC0_HDRCREDITS 9:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC0_HDRCREDITS_INIT 0x00000140 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC0_DATACREDITS 25:16 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC0_DATACREDITS_INIT 0x00000140 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC1 0x00000908 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC1__PRIV_LEVEL_MASK 0x00000804 /* */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC1_HDRCREDITS 9:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC1_HDRCREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC1_DATACREDITS 25:16 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC1_DATACREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC2 0x0000090c /* RW-4R */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC2__PRIV_LEVEL_MASK 0x00000804 /* */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC2_HDRCREDITS 9:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC2_HDRCREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC2_DATACREDITS 25:16 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC2_DATACREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC3 0x00000910 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC3__PRIV_LEVEL_MASK 0x00000804 /* */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC3_HDRCREDITS 9:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC3_HDRCREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC3_DATACREDITS 25:16 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC3_DATACREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC4 0x00000914 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC4__PRIV_LEVEL_MASK 0x00000804 /* */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC4_HDRCREDITS 9:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC4_HDRCREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC4_DATACREDITS 25:16 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC4_DATACREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC5 0x00000918 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC5__PRIV_LEVEL_MASK 0x00000804 /* */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC5_HDRCREDITS 9:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC5_HDRCREDITS_INIT 0x00000140 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC5_DATACREDITS 25:16 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC5_DATACREDITS_INIT 0x00000140 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC6 0x0000091c /* RW-4R */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC6__PRIV_LEVEL_MASK 0x00000804 /* */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC6_HDRCREDITS 9:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC6_HDRCREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC6_DATACREDITS 25:16 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC6_DATACREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC7 0x00000920 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC7__PRIV_LEVEL_MASK 0x00000804 /* */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC7_HDRCREDITS 9:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC7_HDRCREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC7_DATACREDITS 25:16 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_CREDITS_VC7_DATACREDITS_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY 0x00000924 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY_BUFFERRDY 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY_BUFFERRDY_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_CTRL_BUFFER_READY_BUFFERRDY_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL 0x00000a00 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL__PRIV_LEVEL_MASK 0x00000818 /* */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_NCISOC_ECC_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_NCISOC_PARITY_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_HDR_RAM_ECC_ENABLE 8:8 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_HDR_RAM_ECC_ENABLE_ENABLE 0x00000001 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_HDR_RAM_ECC_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_DAT0_RAM_ECC_ENABLE 9:9 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_DAT0_RAM_ECC_ENABLE_ENABLE 0x00000001 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_DAT0_RAM_ECC_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_DAT1_RAM_ECC_ENABLE 10:10 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_DAT1_RAM_ECC_ENABLE_ENABLE 0x00000001 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_CTRL_DAT1_RAM_ECC_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT 0x00000a04 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT__PRIV_LEVEL_MASK 0x00000818 /* */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT_NCISOC_ECC_SBE 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT_NCISOC_ECC_SBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT_NCISOC_ECC_SBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT_NCISOC_ECC_DBE 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT_NCISOC_ECC_DBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT_NCISOC_ECC_DBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT_NCISOC_ECC_PDCTL_PARITY 2:2 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT_NCISOC_ECC_PDCTL_PARITY_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT_NCISOC_ECC_PDCTL_PARITY_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT_NCISOC_ECC_CTL2_PARITY 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT_NCISOC_ECC_CTL2_PARITY_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_INJECT_NCISOC_ECC_CTL2_PARITY_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_COUNTER 0x00000a08 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_COUNTER__PRIV_LEVEL_MASK 0x00000818 /* */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_COUNTER_LIMIT 0x00000a0c /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_COUNTER_LIMIT__PRIV_LEVEL_MASK 0x00000818 /* */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_ADDRESS 0x00000a10 /* R--4R */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_ADDRESS_VALID 0x00000a14 /* R--4R */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_ERR_HDR_RAM_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_COUNTER 0x00000a18 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_COUNTER__PRIV_LEVEL_MASK 0x00000818 /* */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_COUNTER_LIMIT 0x00000a1c /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_COUNTER_LIMIT__PRIV_LEVEL_MASK 0x00000818 /* */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_ADDRESS 0x00000a20 /* R--4R */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_ADDRESS_VALID 0x00000a24 /* R--4R */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_ERR_DAT0_RAM_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_COUNTER 0x00000a28 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_COUNTER__PRIV_LEVEL_MASK 0x00000818 /* */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_COUNTER_LIMIT 0x00000a2c /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_COUNTER_LIMIT__PRIV_LEVEL_MASK 0x00000818 /* */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_ADDRESS 0x00000a30 /* R--4R */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_ADDRESS_VALID 0x00000a34 /* R--4R */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_ERR_DAT1_RAM_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT 0x00000a38 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT__PRIV_LEVEL_MASK 0x00000818 /* */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_REQUEST 2:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_REQUEST_NOP 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_REQUEST_SBE_HDR_SBE_INJECT_ARM 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_REQUEST_DBE_HDR_DBE_INJECT_ARM 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_REQUEST_SBE_DATA_SBE_INJECT_ARM 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_REQUEST_DBE_DATA_DBE_INJECT_ARM 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_REQUEST_INJECT_DISARM 0x00000007 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_VC 10:8 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_VC_CREQ 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_VC_DGD 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_VC_ATR 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_VC_ATSD 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_VC_PRB 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_VC_RSP 0x00000005 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_VC_CREQ_VCSET1 0x00000006 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_VC_RSP_VCSET1 0x00000007 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_PKT_DEBUG_TRIGGER_ENABLE 16:16 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_PKT_DEBUG_TRIGGER_ENABLE_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_READY 31:31 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_ERR_ECC_PRECISE_INJECT_READY_INIT 0x00000001 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0 0x00000a80 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_HDR_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT0_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_STATUS_0_DAT1_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0 0x00000a84 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0__PRIV_LEVEL_MASK 0x0000081c /* */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_HDR_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_HDR_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_HDR_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_HDR_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_DAT0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_DAT0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_DAT0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_DAT0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_DAT1_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_DAT1_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_DAT1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_LOG_EN_0_DAT1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0 0x00000a88 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0 0x00000a8c /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_NON_FATAL_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0 0x00000a90 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_HDR_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_HDR_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_DAT0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_DAT0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_DAT1_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CORRECTABLE_REPORT_EN_0_DAT1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0 0x00000a94 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0__PRIV_LEVEL_MASK 0x0000081c /* */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_NCISOC_PARITY_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_HDR_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_HDR_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_HDR_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_HDR_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_DAT0_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_DAT0_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_DAT0_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_DAT0_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_DAT1_RAM_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_DAT1_RAM_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWEVF */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_DAT1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_SYS_ERR_CONTAIN_EN_0_DAT1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0 0x00000a98 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0__PRIV_LEVEL_MASK 0x00000810 /* */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_NCISOC_PARITY_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_NCISOC_PARITY_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_HDR_RAM_ECC_DBE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_HDR_RAM_ECC_DBE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_HDR_RAM_ECC_LIMIT_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_HDR_RAM_ECC_LIMIT_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_DAT0_RAM_ECC_DBE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_DAT0_RAM_ECC_DBE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_DAT0_RAM_ECC_LIMIT_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_DAT0_RAM_ECC_LIMIT_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_DAT1_RAM_ECC_DBE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_DAT1_RAM_ECC_DBE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_DAT1_RAM_ECC_LIMIT_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_REPORT_INJECT_0_DAT1_RAM_ECC_LIMIT_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0 0x00000a9c /* RW-4R */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_NCISOC_PARITY_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_DBE_ERR 1:1 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_LIMIT_ERR 2:2 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_HDR_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_DBE_ERR 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_LIMIT_ERR 4:4 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT0_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_DBE_ERR 5:5 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_LIMIT_ERR 6:6 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_ERR_FIRST_0_DAT1_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_CTRL 0x00000d00 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_CTRL_GROUP252 3:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_CTRL_GROUP252_INIT 0x0000000b /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_CTRL_GROUP253 7:4 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_CTRL_GROUP253_INIT 0x00000004 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_CTRL_GROUP254 11:8 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_CTRL_GROUP254_INIT 0x0000000a /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_CTRL_GROUP255 15:12 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_CTRL_GROUP255_INIT 0x00000005 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_CTRL_WATCHBUSENABLE 31:31 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_CTRL_WATCHBUSENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT 0x00000d04 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0 7:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP0 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP1 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP2 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP3 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP4 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP5 0x00000005 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP6 0x00000006 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP7 0x00000007 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP8 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP9 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP10 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP11 0x0000000b /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP12 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP13 0x0000000d /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP14 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP15 0x0000000f /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP16 0x00000010 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP17 0x00000011 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP18 0x00000012 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP19 0x00000013 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP20 0x00000014 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP21 0x00000015 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP22 0x00000016 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP23 0x00000017 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP24 0x00000018 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP25 0x00000019 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP26 0x0000001a /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP27 0x0000001b /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP28 0x0000001c /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP29 0x0000001d /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP30 0x0000001e /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP31 0x0000001f /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP32 0x00000020 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP33 0x00000021 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP34 0x00000022 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP35 0x00000023 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP36 0x00000024 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP37 0x00000025 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP38 0x00000026 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP39 0x00000027 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP40 0x00000028 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP41 0x00000029 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP42 0x0000002a /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP43 0x0000002b /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP44 0x0000002c /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP45 0x0000002d /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP46 0x0000002e /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP47 0x0000002f /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP48 0x00000030 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP49 0x00000031 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP50 0x00000032 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP51 0x00000033 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP52 0x00000034 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP53 0x00000035 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP54 0x00000036 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP55 0x00000037 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP56 0x00000038 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP57 0x00000039 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP58 0x0000003a /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP59 0x0000003b /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP60 0x0000003c /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP61 0x0000003d /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP62 0x0000003e /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP63 0x0000003f /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP64 0x00000040 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP65 0x00000041 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP66 0x00000042 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP67 0x00000043 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP68 0x00000044 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP69 0x00000045 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP70 0x00000046 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP71 0x00000047 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP72 0x00000048 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP73 0x00000049 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP74 0x0000004a /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP75 0x0000004b /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP76 0x0000004c /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP77 0x0000004d /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP78 0x0000004e /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP79 0x0000004f /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP80 0x00000050 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP81 0x00000051 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP82 0x00000052 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP83 0x00000053 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP84 0x00000054 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP85 0x00000055 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP86 0x00000056 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP87 0x00000057 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP88 0x00000058 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP89 0x00000059 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP90 0x0000005a /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP91 0x0000005b /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP92 0x0000005c /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP93 0x0000005d /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP94 0x0000005e /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP95 0x0000005f /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP96 0x00000060 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP97 0x00000061 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP98 0x00000062 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP99 0x00000063 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP100 0x00000064 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP101 0x00000065 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP102 0x00000066 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP103 0x00000067 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP104 0x00000068 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP105 0x00000069 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP106 0x0000006a /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP107 0x0000006b /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP108 0x0000006c /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP109 0x0000006d /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP110 0x0000006e /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP111 0x0000006f /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP112 0x00000070 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP113 0x00000071 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP114 0x00000072 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP115 0x00000073 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP116 0x00000074 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP117 0x00000075 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP118 0x00000076 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP119 0x00000077 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP120 0x00000078 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP121 0x00000079 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP122 0x0000007a /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP123 0x0000007b /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP124 0x0000007c /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP125 0x0000007d /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP126 0x0000007e /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP127 0x0000007f /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP128 0x00000080 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP129 0x00000081 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP130 0x00000082 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP131 0x00000083 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP132 0x00000084 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP133 0x00000085 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP134 0x00000086 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP135 0x00000087 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP136 0x00000088 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP137 0x00000089 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP138 0x0000008a /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP139 0x0000008b /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP140 0x0000008c /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP141 0x0000008d /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP142 0x0000008e /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP143 0x0000008f /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP144 0x00000090 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP145 0x00000091 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP146 0x00000092 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP147 0x00000093 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP148 0x00000094 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP149 0x00000095 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP150 0x00000096 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP151 0x00000097 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP152 0x00000098 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP153 0x00000099 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP154 0x0000009a /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP155 0x0000009b /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP156 0x0000009c /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP157 0x0000009d /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP158 0x0000009e /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP159 0x0000009f /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP160 0x000000a0 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP161 0x000000a1 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP162 0x000000a2 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP163 0x000000a3 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP164 0x000000a4 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP165 0x000000a5 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP166 0x000000a6 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP167 0x000000a7 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP168 0x000000a8 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP169 0x000000a9 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP170 0x000000aa /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP171 0x000000ab /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP172 0x000000ac /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP173 0x000000ad /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP174 0x000000ae /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP175 0x000000af /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP176 0x000000b0 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP177 0x000000b1 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP178 0x000000b2 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP179 0x000000b3 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP180 0x000000b4 /* RW--V */
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|
#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP181 0x000000b5 /* RW--V */
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|
#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP182 0x000000b6 /* RW--V */
|
|
#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP183 0x000000b7 /* RW--V */
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|
#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP184 0x000000b8 /* RW--V */
|
|
#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP185 0x000000b9 /* RW--V */
|
|
#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP186 0x000000ba /* RW--V */
|
|
#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP187 0x000000bb /* RW--V */
|
|
#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP188 0x000000bc /* RW--V */
|
|
#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP189 0x000000bd /* RW--V */
|
|
#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP190 0x000000be /* RW--V */
|
|
#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP191 0x000000bf /* RW--V */
|
|
#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP192 0x000000c0 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP193 0x000000c1 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP194 0x000000c2 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP195 0x000000c3 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP196 0x000000c4 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP197 0x000000c5 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP198 0x000000c6 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP199 0x000000c7 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP200 0x000000c8 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP201 0x000000c9 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP202 0x000000ca /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP203 0x000000cb /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP204 0x000000cc /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP205 0x000000cd /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP206 0x000000ce /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP207 0x000000cf /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP208 0x000000d0 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP209 0x000000d1 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP210 0x000000d2 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP211 0x000000d3 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP212 0x000000d4 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP213 0x000000d5 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP214 0x000000d6 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP215 0x000000d7 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP216 0x000000d8 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP217 0x000000d9 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP218 0x000000da /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP219 0x000000db /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP220 0x000000dc /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP221 0x000000dd /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP222 0x000000de /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP223 0x000000df /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP224 0x000000e0 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP225 0x000000e1 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP226 0x000000e2 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP227 0x000000e3 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP228 0x000000e4 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP229 0x000000e5 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP230 0x000000e6 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP231 0x000000e7 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP232 0x000000e8 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP233 0x000000e9 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP234 0x000000ea /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP235 0x000000eb /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP236 0x000000ec /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP237 0x000000ed /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP238 0x000000ee /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP239 0x000000ef /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP240 0x000000f0 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP241 0x000000f1 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP242 0x000000f2 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP243 0x000000f3 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP244 0x000000f4 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP245 0x000000f5 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP246 0x000000f6 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP247 0x000000f7 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP248 0x000000f8 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP249 0x000000f9 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP250 0x000000fa /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP251 0x000000fb /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP252 0x000000fc /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP253 0x000000fd /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP254 0x000000fe /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT0_GRP255 0x000000ff /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT1 15:8 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT1_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT2 23:16 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT2_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT3 31:24 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MUX_SELECT_M1SELECT3_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_CTRL 0x00000d08 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_CTRL__PRIV_LEVEL_MASK 0x00000810 /* */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_CTRL_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_CTRL_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_0 0x00000d0c /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_0_NCISOC_CREDIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_0_NCISOC_CREDIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_0_HEADER_RAM_LOWER_LIMIT 20:10 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_0_HEADER_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_0_HEADER_RAM_UPPER_LIMIT 31:21 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_0_HEADER_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_1 0x00000d10 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_1_NCISOC_CREDIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_1_NCISOC_CREDIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_1_HEADER_RAM_LOWER_LIMIT 20:10 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_1_HEADER_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_1_HEADER_RAM_UPPER_LIMIT 31:21 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_1_HEADER_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_2 0x00000d14 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_2_NCISOC_CREDIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_2_NCISOC_CREDIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_2_HEADER_RAM_LOWER_LIMIT 20:10 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_2_HEADER_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_2_HEADER_RAM_UPPER_LIMIT 31:21 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_2_HEADER_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_3 0x00000d18 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_3_NCISOC_CREDIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_3_NCISOC_CREDIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_3_HEADER_RAM_LOWER_LIMIT 20:10 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_3_HEADER_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_3_HEADER_RAM_UPPER_LIMIT 31:21 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_3_HEADER_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_4 0x00000d1c /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_4_NCISOC_CREDIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_4_NCISOC_CREDIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_4_HEADER_RAM_LOWER_LIMIT 20:10 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_4_HEADER_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_4_HEADER_RAM_UPPER_LIMIT 31:21 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_4_HEADER_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_5 0x00000d20 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_5_NCISOC_CREDIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_5_NCISOC_CREDIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_5_HEADER_RAM_LOWER_LIMIT 20:10 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_5_HEADER_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_5_HEADER_RAM_UPPER_LIMIT 31:21 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_5_HEADER_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_6 0x00000d24 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_6_NCISOC_CREDIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_6_NCISOC_CREDIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_6_HEADER_RAM_LOWER_LIMIT 20:10 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_6_HEADER_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_6_HEADER_RAM_UPPER_LIMIT 31:21 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_6_HEADER_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_7 0x00000d28 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_7_NCISOC_CREDIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_7_NCISOC_CREDIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_7_HEADER_RAM_LOWER_LIMIT 20:10 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_7_HEADER_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_7_HEADER_RAM_UPPER_LIMIT 31:21 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_7_HEADER_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_8 0x00000d2c /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_8_DATA_RAM_LOWER_LIMIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_8_DATA_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_8_DATA_RAM_UPPER_LIMIT 25:16 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_8_DATA_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_9 0x00000d30 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_9_DATA_RAM_LOWER_LIMIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_9_DATA_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_9_DATA_RAM_UPPER_LIMIT 25:16 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_9_DATA_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_10 0x00000d34 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_10_DATA_RAM_LOWER_LIMIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_10_DATA_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_10_DATA_RAM_UPPER_LIMIT 25:16 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_10_DATA_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_11 0x00000d38 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_11_DATA_RAM_LOWER_LIMIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_11_DATA_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_11_DATA_RAM_UPPER_LIMIT 25:16 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_11_DATA_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_12 0x00000d3c /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_12_DATA_RAM_LOWER_LIMIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_12_DATA_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_12_DATA_RAM_UPPER_LIMIT 25:16 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_12_DATA_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_13 0x00000d40 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_13_DATA_RAM_LOWER_LIMIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_13_DATA_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_13_DATA_RAM_UPPER_LIMIT 25:16 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_13_DATA_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_14 0x00000d44 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_14_DATA_RAM_LOWER_LIMIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_14_DATA_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_14_DATA_RAM_UPPER_LIMIT 25:16 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_14_DATA_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_15 0x00000d48 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_15_DATA_RAM_LOWER_LIMIT 9:0 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_15_DATA_RAM_LOWER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_15_DATA_RAM_UPPER_LIMIT 25:16 /* R-EVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_15_DATA_RAM_UPPER_LIMIT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_16 0x00000d4c /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_16_IDLE 7:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_16_IDLE_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_16_STALL 16:16 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_16_STALL_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_16_STALL_ACK 17:17 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_16_STALL_ACK_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_16_CREDIT_CLEAR 18:18 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_16_CREDIT_CLEAR_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_16_CREDIT_CLEAR_ACK 19:19 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_16_CREDIT_CLEAR_ACK_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC0 0x00000d50 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC0_CTRLVLD 0:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC0_CTRLVLD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC0_CTRLHEAD 18:1 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC0_CTRLHEAD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC1 0x00000d54 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC1_CTRLVLD 0:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC1_CTRLVLD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC1_CTRLHEAD 18:1 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC1_CTRLHEAD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC2 0x00000d58 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC2_CTRLVLD 0:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC2_CTRLVLD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC2_CTRLHEAD 18:1 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC2_CTRLHEAD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC3 0x00000d5c /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC3_CTRLVLD 0:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC3_CTRLVLD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC3_CTRLHEAD 18:1 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC3_CTRLHEAD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC4 0x00000d60 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC4_CTRLVLD 0:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC4_CTRLVLD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC4_CTRLHEAD 18:1 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC4_CTRLHEAD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC5 0x00000d64 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC5_CTRLVLD 0:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC5_CTRLVLD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC5_CTRLHEAD 18:1 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC5_CTRLHEAD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC6 0x00000d68 /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC6_CTRLVLD 0:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC6_CTRLVLD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC6_CTRLHEAD 18:1 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC6_CTRLHEAD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC7 0x00000d6c /* R--4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC7_CTRLVLD 0:0 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC7_CTRLVLD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC7_CTRLHEAD 18:1 /* R-DVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_MISC_VC7_CTRLHEAD_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC0 0x00000d70 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC0__PRIV_LEVEL_MASK 0x00000810 /* */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC0_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC0_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC0_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC0_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC0_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC0_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC0_MODE_RESERVED 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC0_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC0_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC0_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC0_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC1 0x00000d74 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC1__PRIV_LEVEL_MASK 0x00000810 /* */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC1_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC1_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC1_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC1_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC1_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC1_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC1_MODE_RESERVED 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC1_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC1_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC1_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC1_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC2 0x00000d78 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC2__PRIV_LEVEL_MASK 0x00000810 /* */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC2_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC2_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC2_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC2_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC2_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC2_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC2_MODE_RESERVED 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC2_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC2_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC2_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC2_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC3 0x00000d7c /* RW-4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC3__PRIV_LEVEL_MASK 0x00000810 /* */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC3_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC3_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC3_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC3_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC3_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC3_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC3_MODE_RESERVED 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC3_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC3_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC3_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC3_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC4 0x00000d80 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC4__PRIV_LEVEL_MASK 0x00000810 /* */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC4_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC4_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC4_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC4_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC4_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC4_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC4_MODE_RESERVED 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC4_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC4_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC4_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC4_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC5 0x00000d84 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC5__PRIV_LEVEL_MASK 0x00000810 /* */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC5_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC5_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC5_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC5_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC5_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC5_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC5_MODE_RESERVED 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC5_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC5_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC5_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC5_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC6 0x00000d88 /* RW-4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC6__PRIV_LEVEL_MASK 0x00000810 /* */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC6_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC6_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC6_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC6_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC6_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC6_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC6_MODE_RESERVED 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC6_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC6_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC6_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC6_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC7 0x00000d8c /* RW-4R */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC7__PRIV_LEVEL_MASK 0x00000810 /* */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC7_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC7_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC7_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC7_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC7_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC7_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC7_MODE_RESERVED 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC7_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC7_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC7_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_RX_SYS_DEBUG_STALL_VC7_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0 0x00001000 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1 0x00001004 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2 0x00001008 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask2" /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK2_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3 0x0000100c /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask3" /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK3_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4 0x00001010 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask4" /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK4_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5 0x00001014 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask5" /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK5_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6 0x00001018 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK6_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7 0x0000101c /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask7" /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_TX_LNK_PRIV_LEVEL_MASK7_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_SCRATCH_WARM 0x000017c0 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_SCRATCH_WARM_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_LNK_SCRATCH_COLD 0x000017c4 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_SCRATCH_COLD_DATA 31:0 /* RWIVF */
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#define NV_NVLTLC_TX_LNK_SCRATCH_COLD_DATA_INIT 0xdeadbaad /* RWI-V */
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#define NV_NVLTLC_TX_LNK_SCRATCH_COLD_AND_DEBUG 0x000017c8 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_SCRATCH_COLD_AND_DEBUG_DATA 31:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_SCRATCH_COLD_AND_DEBUG_DATA_INIT 0xdeadbaad /* RWD-V */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK0 0x000017d0 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK0__PRIV_LEVEL_MASK 0x00001000 /* */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK0_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK0_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK1 0x000017d4 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK1__PRIV_LEVEL_MASK 0x00001004 /* */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK1_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK1_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK2 0x000017d8 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK2__PRIV_LEVEL_MASK 0x00001008 /* */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK2_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK2_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK3 0x000017dc /* RW-4R */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK3__PRIV_LEVEL_MASK 0x0000100c /* */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK3_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK3_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK4 0x000017e0 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK4__PRIV_LEVEL_MASK 0x00001010 /* */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK4_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK4_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK5 0x000017e4 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK5__PRIV_LEVEL_MASK 0x00001014 /* */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK5_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK5_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK6 0x000017e8 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK6__PRIV_LEVEL_MASK 0x00001018 /* */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK6_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK6_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK7 0x000017ec /* RW-4R */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK7__PRIV_LEVEL_MASK 0x0000101c /* */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK7_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_SCRATCH_PRIVMASK7_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG 0x00001100 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG__PRIV_LEVEL_MASK 0x0000101c /* */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_COLLAPSED_RESPONSE_DISABLE 1:1 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_COLLAPSED_RESPONSE_DISABLE_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_COLLAPSED_RESPONSE_DISABLE_DISABLED 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_FORCEAE 3:3 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_FORCEAE_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_AECDISABLE 4:4 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_AECDISABLE_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_AECDISABLE_DISABLED 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_POISON_ENABLE 5:5 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_POISON_ENABLE_INIT 0x00000001 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_STICKYPARTITION 11:8 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_STICKYPARTITION_INIT 0x00000008 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_INSERTNOPCREDIT 12:12 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_INSERTNOPCREDIT_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_INSERTNOPBOUNDARY 14:13 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_INSERTNOPBOUNDARY_4_CREDITS 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_INSERTNOPBOUNDARY_8_CREDITS 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_INSERTNOPBOUNDARY_12_CREDITS 0x00000002 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_LINK_CONFIG_INSERTNOPBOUNDARY_16_CREDITS 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC0 0x00001104 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC0__PRIV_LEVEL_MASK 0x0000100c /* */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC0_TIME_IN_100NS 23:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC0_TIME_IN_100NS_INIT 0x0000000a /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC1 0x00001108 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC1__PRIV_LEVEL_MASK 0x0000100c /* */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC1_TIME_IN_100NS 23:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC1_TIME_IN_100NS_INIT 0x0000000a /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC2 0x0000110c /* RW-4R */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC2__PRIV_LEVEL_MASK 0x0000100c /* */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC2_TIME_IN_100NS 23:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC2_TIME_IN_100NS_INIT 0x0000000a /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC3 0x00001110 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC3__PRIV_LEVEL_MASK 0x0000100c /* */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC3_TIME_IN_100NS 23:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC3_TIME_IN_100NS_INIT 0x0000000a /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC4 0x00001114 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC4__PRIV_LEVEL_MASK 0x0000100c /* */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC4_TIME_IN_100NS 23:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC4_TIME_IN_100NS_INIT 0x0000000a /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC5 0x00001118 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC5__PRIV_LEVEL_MASK 0x0000100c /* */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC5_TIME_IN_100NS 23:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC5_TIME_IN_100NS_INIT 0x0000000a /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC6 0x0000111c /* RW-4R */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC6__PRIV_LEVEL_MASK 0x0000100c /* */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC6_TIME_IN_100NS 23:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC6_TIME_IN_100NS_INIT 0x0000000a /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC7 0x00001120 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC7__PRIV_LEVEL_MASK 0x0000100c /* */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC7_TIME_IN_100NS 23:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_VCTO_VC7_TIME_IN_100NS_INIT 0x0000000a /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_HEARTBEAT 0x00001124 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_CTRL_HEARTBEAT__PRIV_LEVEL_MASK 0x0000100c /* */
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#define NV_NVLTLC_TX_LNK_CTRL_HEARTBEAT_TIME_IN_100NS 23:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_HEARTBEAT_TIME_IN_100NS_INIT 0x0000000a /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_HEARTBEAT_ENABLE 31:31 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_HEARTBEAT_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_HEARTBEAT_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_TIMER 0x00001128 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_TIMER__PRIV_LEVEL_MASK 0x00001004 /* */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_TIMER_RESIDENCY_LIMIT 11:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_TIMER_RESIDENCY_LIMIT_INIT 0x00000008 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL 0x0000112c /* RW-4R */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL__PRIV_LEVEL_MASK 0x00001004 /* */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_RESIDENCY_TIMER_ENABLE 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_RESIDENCY_TIMER_ENABLE_ENABLE 0x00000001 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_RESIDENCY_TIMER_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_BUFFER_ENABLE 11:8 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_BUFFER_ENABLE_ZERO_ENABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_BUFFER_ENABLE_ONE_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_BUFFER_ENABLE_TWO_ENABLED 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_BUFFER_ENABLE_THREE_ENABLED 0x00000007 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_BUFFER_ENABLE_FOUR_ENABLED 0x0000000f /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_BUFFER_VCSET 19:16 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_BUFFER_VCSET_VCSET0_4_VCSET1_0 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_BUFFER_VCSET_VCSET0_3_VCSET1_1 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_BUFFER_VCSET_VCSET0_2_VCSET1_2 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_BUFFER_VCSET_VCSET0_1_VCSET1_3 0x00000007 /* RW--V */
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#define NV_NVLTLC_TX_LNK_CTRL_BUFFER_COMPQ_CTRL_BUFFER_VCSET_VCSET0_0_VCSET1_4 0x0000000f /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL 0x00001200 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL__PRIV_LEVEL_MASK 0x00001018 /* */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL_CREQ_RAM_ECC_ENABLE 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL_CREQ_RAM_ECC_ENABLE_ENABLE 0x00000001 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL_CREQ_RAM_ECC_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL_RSP_RAM_ECC_ENABLE 1:1 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL_RSP_RAM_ECC_ENABLE_ENABLE 0x00000001 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL_RSP_RAM_ECC_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL_COM_RAM_ECC_ENABLE 2:2 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL_COM_RAM_ECC_ENABLE_ENABLE 0x00000001 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL_COM_RAM_ECC_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL_RSP1_RAM_ECC_ENABLE 3:3 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL_RSP1_RAM_ECC_ENABLE_ENABLE 0x00000001 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_ECC_CTRL_RSP1_RAM_ECC_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_COUNTER 0x00001204 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_COUNTER__PRIV_LEVEL_MASK 0x00001018 /* */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_COUNTER_LIMIT 0x00001208 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_COUNTER_LIMIT__PRIV_LEVEL_MASK 0x00001018 /* */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_ADDRESS 0x0000120c /* R--4R */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_ADDRESS_VALID 0x00001210 /* R--4R */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_LNK_ERR_CREQ_RAM_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_COUNTER 0x00001214 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_COUNTER__PRIV_LEVEL_MASK 0x00001018 /* */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_COUNTER_LIMIT 0x00001218 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_COUNTER_LIMIT__PRIV_LEVEL_MASK 0x00001018 /* */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_ADDRESS 0x0000121c /* R--4R */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_ADDRESS_VALID 0x00001220 /* R--4R */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_LNK_ERR_RSP_RAM_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_COUNTER 0x00001224 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_COUNTER__PRIV_LEVEL_MASK 0x00001018 /* */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_COUNTER_LIMIT 0x00001228 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_COUNTER_LIMIT__PRIV_LEVEL_MASK 0x00001018 /* */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_ADDRESS 0x0000122c /* R--4R */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_ADDRESS_VALID 0x00001230 /* R--4R */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_LNK_ERR_COM_RAM_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_COUNTER 0x00001234 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_COUNTER__PRIV_LEVEL_MASK 0x00001018 /* */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_COUNTER_ERROR_COUNT 23:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_COUNTER_ERROR_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_COUNTER_LIMIT 0x00001238 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_COUNTER_LIMIT__PRIV_LEVEL_MASK 0x00001018 /* */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT 23:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_COUNTER_LIMIT_ERROR_LIMIT_INIT 0x00ffffff /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_ADDRESS 0x0000123c /* R--4R */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS 15:0 /* R-DVF */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_ADDRESS_ERROR_ADDRESS_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_ADDRESS_VALID 0x00001240 /* R--4R */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_ADDRESS_VALID_VALID 0:0 /* R-DVF */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_ADDRESS_VALID_VALID_INVALID 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_LNK_ERR_RSP1_RAM_ECC_ERROR_ADDRESS_VALID_VALID_VALID 0x00000001 /* R---V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0 0x00001280 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_TXDLCREDITPARITYERR 17:17 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_TXDLCREDITPARITYERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_TXDLCREDITPARITYERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_CREQ_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_COM_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_0_RSP1_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0 0x00001284 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0__PRIV_LEVEL_MASK 0x0000101c /* */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_TXDLCREDITPARITYERR 17:17 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_TXDLCREDITPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_TXDLCREDITPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_CREQ_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_CREQ_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_COM_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_COM_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_COM_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_COM_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_COM_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_COM_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_0_RSP1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0 0x00001288 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR 17:17 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0 0x0000128c /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR 17:17 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_TXDLCREDITPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0 0x00001290 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_TXDLCREDITPARITYERR 17:17 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_TXDLCREDITPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_TXDLCREDITPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_CREQ_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_COM_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_COM_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_COM_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSP1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0 0x00001294 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0__PRIV_LEVEL_MASK 0x0000101c /* */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_TXDLCREDITPARITYERR 17:17 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_TXDLCREDITPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_TXDLCREDITPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_CREQ_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_CREQ_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_CREQ_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_CREQ_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_COM_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_COM_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_COM_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_COM_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_COM_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_COM_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP1_RAM_HDR_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP1_RAM_DAT_ECC_DBE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP1_RAM_ECC_LIMIT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_0_RSP1_RAM_ECC_LIMIT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0 0x00001298 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0__PRIV_LEVEL_MASK 0x00001010 /* */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_TXDLCREDITPARITYERR 17:17 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_TXDLCREDITPARITYERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_TXDLCREDITPARITYERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_CREQ_RAM_HDR_ECC_DBE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_CREQ_RAM_HDR_ECC_DBE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_CREQ_RAM_DAT_ECC_DBE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_CREQ_RAM_DAT_ECC_DBE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_CREQ_RAM_ECC_LIMIT_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_CREQ_RAM_ECC_LIMIT_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP_RAM_HDR_ECC_DBE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP_RAM_HDR_ECC_DBE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP_RAM_DAT_ECC_DBE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP_RAM_DAT_ECC_DBE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP_RAM_ECC_LIMIT_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP_RAM_ECC_LIMIT_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_COM_RAM_HDR_ECC_DBE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_COM_RAM_HDR_ECC_DBE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_COM_RAM_DAT_ECC_DBE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_COM_RAM_DAT_ECC_DBE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_COM_RAM_ECC_LIMIT_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_COM_RAM_ECC_LIMIT_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP1_RAM_HDR_ECC_DBE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP1_RAM_HDR_ECC_DBE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP1_RAM_DAT_ECC_DBE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP1_RAM_DAT_ECC_DBE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP1_RAM_ECC_LIMIT_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_0_RSP1_RAM_ECC_LIMIT_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0 0x0000129c /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_TXDLCREDITPARITYERR 17:17 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_TXDLCREDITPARITYERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_TXDLCREDITPARITYERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_HDR_ECC_DBE_ERR 18:18 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_DAT_ECC_DBE_ERR 19:19 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_ECC_LIMIT_ERR 20:20 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_CREQ_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_HDR_ECC_DBE_ERR 21:21 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_DAT_ECC_DBE_ERR 22:22 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_ECC_LIMIT_ERR 23:23 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_HDR_ECC_DBE_ERR 24:24 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_DAT_ECC_DBE_ERR 25:25 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_ECC_LIMIT_ERR 26:26 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_COM_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_HDR_ECC_DBE_ERR 27:27 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_HDR_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_HDR_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_DAT_ECC_DBE_ERR 28:28 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_DAT_ECC_DBE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_DAT_ECC_DBE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_ECC_LIMIT_ERR 29:29 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_ECC_LIMIT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_0_RSP1_RAM_ECC_LIMIT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1 0x000012a0 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC0 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC0_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC0_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC1 1:1 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC1_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC1_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC2 2:2 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC2_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC2_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC3 3:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC3_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC3_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC4 4:4 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC4_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC4_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC5 5:5 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC5_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC5_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC6 6:6 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC6_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC6_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC7 7:7 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC7_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_STATUS_1_AN1_TIMEOUT_VC7_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1 0x000012a4 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1__PRIV_LEVEL_MASK 0x0000101c /* */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC0 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC0_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC0_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC1 1:1 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC1_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC1_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC2 2:2 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC2_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC2_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC3 3:3 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC3_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC3_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC4 4:4 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC4_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC4_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC5 5:5 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC5_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC5_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC6 6:6 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC6_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC6_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC7 7:7 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC7_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_LOG_EN_1_AN1_TIMEOUT_VC7_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1 0x000012a8 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC0 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC0_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC0_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC1 1:1 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC1_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC1_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC2 2:2 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC2_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC2_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC3 3:3 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC3_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC3_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC4 4:4 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC4_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC4_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC5 5:5 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC5_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC5_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC6 6:6 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC6_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC6_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC7 7:7 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC7_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC7_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1 0x000012ac /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC0 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC0_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC0_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC1 1:1 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC1_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC1_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC2 2:2 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC2_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC2_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC3 3:3 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC3_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC3_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC4 4:4 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC4_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC4_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC5 5:5 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC5_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC5_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC6 6:6 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC6_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC6_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC7 7:7 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC7_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_TIMEOUT_VC7_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1 0x000012b0 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC0 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC0_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC0_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC1 1:1 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC1_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC1_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC2 2:2 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC2_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC2_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC3 3:3 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC3_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC3_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC4 4:4 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC4_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC4_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC5 5:5 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC5_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC5_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC6 6:6 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC6_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC6_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC7 7:7 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC7_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_TIMEOUT_VC7_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1 0x000012b4 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1__PRIV_LEVEL_MASK 0x0000101c /* */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC0 0:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC0_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC0_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC1 1:1 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC1_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC1_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC2 2:2 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC2_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC2_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC3 3:3 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC3_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC3_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC4 4:4 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC4_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC4_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC5 5:5 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC5_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC5_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC6 6:6 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC6_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC6_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC7 7:7 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC7_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_ERR_CONTAIN_EN_1_AN1_TIMEOUT_VC7_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1 0x000012b8 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1__PRIV_LEVEL_MASK 0x00001010 /* */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC0 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC0_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC0_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC1 1:1 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC1_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC1_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC2 2:2 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC2_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC2_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC3 3:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC3_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC3_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC4 4:4 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC4_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC4_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC5 5:5 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC5_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC5_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC6 6:6 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC6_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC6_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC7 7:7 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC7_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_REPORT_INJECT_1_AN1_TIMEOUT_VC7_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1 0x000012bc /* RW-4R */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC0 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC0_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC0_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC1 1:1 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC1_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC1_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC2 2:2 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC2_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC2_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC3 3:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC3_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC3_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC4 4:4 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC4_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC4_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC5 5:5 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC5_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC5_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC6 6:6 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC6_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC6_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC7 7:7 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC7_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_ERR_FIRST_1_AN1_TIMEOUT_VC7_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL 0x00001400 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL__PRIV_LEVEL_MASK 0x00001014 /* */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_CURRENTSTATE 0:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_CURRENTSTATE_LP 0x00000001 /* R---V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_CURRENTSTATE_FB 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_REMOTEDESIRED 1:1 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_REMOTEDESIRED_LP 0x00000001 /* R---V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_REMOTEDESIRED_FB 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_SOFTWAREDESIRED 2:2 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_SOFTWAREDESIRED_LP 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_SOFTWAREDESIRED_FB 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_HARDWAREDISABLE 3:3 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_HARDWAREDISABLE_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_HARDWAREDESIRED 4:4 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_HARDWAREDESIRED_LP 0x00000001 /* R---V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_HARDWAREDESIRED_FB 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_COUNTSTART 5:5 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_SW_CTRL_COUNTSTART_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC 0x00001404 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PWRM_IC__PRIV_LEVEL_MASK 0x00001014 /* */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_IDLECOUNT 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_IDLECOUNT_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_INC 0x00001408 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_INC__PRIV_LEVEL_MASK 0x00001014 /* */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_INC_FBINC 15:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_INC_FBINC_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_INC_LPINC 31:16 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_INC_LPINC_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_DEC 0x0000140c /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_DEC__PRIV_LEVEL_MASK 0x00001014 /* */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_DEC_FBDEC 15:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_DEC_FBDEC_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_DEC_LPDEC 31:16 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_DEC_LPDEC_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_LP_ENTER_THRESHOLD 0x00001410 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_LP_ENTER_THRESHOLD__PRIV_LEVEL_MASK 0x00001014 /* */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_LP_ENTER_THRESHOLD_THRESHOLD 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_LP_ENTER_THRESHOLD_THRESHOLD_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_LP_EXIT_THRESHOLD 0x00001414 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_LP_EXIT_THRESHOLD__PRIV_LEVEL_MASK 0x00001014 /* */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_LP_EXIT_THRESHOLD_THRESHOLD 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_LP_EXIT_THRESHOLD_THRESHOLD_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_LIMIT 0x00001418 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_LIMIT__PRIV_LEVEL_MASK 0x00001014 /* */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_LIMIT_LIMIT 31:0 /* RWEVF */
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#define NV_NVLTLC_TX_LNK_PWRM_IC_LIMIT_LIMIT_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_CTRL 0x00001500 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_CTRL_GROUP252 3:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_CTRL_GROUP252_INIT 0x0000000f /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_CTRL_GROUP253 7:4 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_CTRL_GROUP253_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_CTRL_GROUP254 11:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_CTRL_GROUP254_INIT 0x0000000e /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_CTRL_GROUP255 15:12 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_CTRL_GROUP255_INIT 0x00000001 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_CTRL_WATCHBUSENABLE 31:31 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_CTRL_WATCHBUSENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT 0x00001504 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0 7:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP0 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP1 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP2 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP3 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP4 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP5 0x00000005 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP6 0x00000006 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP7 0x00000007 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP8 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP9 0x00000009 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP10 0x0000000a /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP11 0x0000000b /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP12 0x0000000c /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP13 0x0000000d /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP14 0x0000000e /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP15 0x0000000f /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP16 0x00000010 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP17 0x00000011 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP18 0x00000012 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP19 0x00000013 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP20 0x00000014 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP21 0x00000015 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP22 0x00000016 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP23 0x00000017 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP24 0x00000018 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP25 0x00000019 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP26 0x0000001a /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP27 0x0000001b /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP28 0x0000001c /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP29 0x0000001d /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP30 0x0000001e /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP31 0x0000001f /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP32 0x00000020 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP33 0x00000021 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP34 0x00000022 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP35 0x00000023 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP36 0x00000024 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP37 0x00000025 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP38 0x00000026 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP39 0x00000027 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP40 0x00000028 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP41 0x00000029 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP42 0x0000002a /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP43 0x0000002b /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP44 0x0000002c /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP45 0x0000002d /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP46 0x0000002e /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP47 0x0000002f /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP48 0x00000030 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP49 0x00000031 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP50 0x00000032 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP51 0x00000033 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP52 0x00000034 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP53 0x00000035 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP54 0x00000036 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP55 0x00000037 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP56 0x00000038 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP57 0x00000039 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP58 0x0000003a /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP59 0x0000003b /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP60 0x0000003c /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP61 0x0000003d /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP62 0x0000003e /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP63 0x0000003f /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP64 0x00000040 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP65 0x00000041 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP66 0x00000042 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP67 0x00000043 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP68 0x00000044 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP69 0x00000045 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP70 0x00000046 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP71 0x00000047 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP72 0x00000048 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP73 0x00000049 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP74 0x0000004a /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP75 0x0000004b /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP76 0x0000004c /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP77 0x0000004d /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP78 0x0000004e /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP79 0x0000004f /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP80 0x00000050 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP81 0x00000051 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP82 0x00000052 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP83 0x00000053 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP84 0x00000054 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP85 0x00000055 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP86 0x00000056 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP87 0x00000057 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP88 0x00000058 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP89 0x00000059 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP90 0x0000005a /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP91 0x0000005b /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP92 0x0000005c /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP93 0x0000005d /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP94 0x0000005e /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP95 0x0000005f /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP96 0x00000060 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP97 0x00000061 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP98 0x00000062 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP99 0x00000063 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP100 0x00000064 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP101 0x00000065 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP102 0x00000066 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP103 0x00000067 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP104 0x00000068 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP105 0x00000069 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP106 0x0000006a /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP107 0x0000006b /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP108 0x0000006c /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP109 0x0000006d /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP110 0x0000006e /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP111 0x0000006f /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP112 0x00000070 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP113 0x00000071 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP114 0x00000072 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP115 0x00000073 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP116 0x00000074 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP117 0x00000075 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP118 0x00000076 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP119 0x00000077 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP120 0x00000078 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP121 0x00000079 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP122 0x0000007a /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP123 0x0000007b /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP124 0x0000007c /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP125 0x0000007d /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP126 0x0000007e /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP127 0x0000007f /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP128 0x00000080 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP129 0x00000081 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP130 0x00000082 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP131 0x00000083 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP132 0x00000084 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP133 0x00000085 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP134 0x00000086 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP135 0x00000087 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP136 0x00000088 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP137 0x00000089 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP138 0x0000008a /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP139 0x0000008b /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP140 0x0000008c /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP141 0x0000008d /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP142 0x0000008e /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP143 0x0000008f /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP144 0x00000090 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP145 0x00000091 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP146 0x00000092 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP147 0x00000093 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP148 0x00000094 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP149 0x00000095 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP150 0x00000096 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP151 0x00000097 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP152 0x00000098 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP153 0x00000099 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP154 0x0000009a /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP155 0x0000009b /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP156 0x0000009c /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP157 0x0000009d /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP158 0x0000009e /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP159 0x0000009f /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP160 0x000000a0 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP161 0x000000a1 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP162 0x000000a2 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP163 0x000000a3 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP164 0x000000a4 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP165 0x000000a5 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP166 0x000000a6 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP167 0x000000a7 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP168 0x000000a8 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP169 0x000000a9 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP170 0x000000aa /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP171 0x000000ab /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP172 0x000000ac /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP173 0x000000ad /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP174 0x000000ae /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP175 0x000000af /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP176 0x000000b0 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP177 0x000000b1 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP178 0x000000b2 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP179 0x000000b3 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP180 0x000000b4 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP181 0x000000b5 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP182 0x000000b6 /* RW--V */
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|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP183 0x000000b7 /* RW--V */
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|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP184 0x000000b8 /* RW--V */
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|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP185 0x000000b9 /* RW--V */
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|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP186 0x000000ba /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP187 0x000000bb /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP188 0x000000bc /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP189 0x000000bd /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP190 0x000000be /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP191 0x000000bf /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP192 0x000000c0 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP193 0x000000c1 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP194 0x000000c2 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP195 0x000000c3 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP196 0x000000c4 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP197 0x000000c5 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP198 0x000000c6 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP199 0x000000c7 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP200 0x000000c8 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP201 0x000000c9 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP202 0x000000ca /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP203 0x000000cb /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP204 0x000000cc /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP205 0x000000cd /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP206 0x000000ce /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP207 0x000000cf /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP208 0x000000d0 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP209 0x000000d1 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP210 0x000000d2 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP211 0x000000d3 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP212 0x000000d4 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP213 0x000000d5 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP214 0x000000d6 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP215 0x000000d7 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP216 0x000000d8 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP217 0x000000d9 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP218 0x000000da /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP219 0x000000db /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP220 0x000000dc /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP221 0x000000dd /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP222 0x000000de /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP223 0x000000df /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP224 0x000000e0 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP225 0x000000e1 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP226 0x000000e2 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP227 0x000000e3 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP228 0x000000e4 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP229 0x000000e5 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP230 0x000000e6 /* RW--V */
|
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP231 0x000000e7 /* RW--V */
|
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP232 0x000000e8 /* RW--V */
|
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP233 0x000000e9 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP234 0x000000ea /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP235 0x000000eb /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP236 0x000000ec /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP237 0x000000ed /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP238 0x000000ee /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP239 0x000000ef /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP240 0x000000f0 /* RW--V */
|
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP241 0x000000f1 /* RW--V */
|
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP242 0x000000f2 /* RW--V */
|
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP243 0x000000f3 /* RW--V */
|
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP244 0x000000f4 /* RW--V */
|
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP245 0x000000f5 /* RW--V */
|
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#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP246 0x000000f6 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP247 0x000000f7 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP248 0x000000f8 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP249 0x000000f9 /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP250 0x000000fa /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP251 0x000000fb /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP252 0x000000fc /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP253 0x000000fd /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP254 0x000000fe /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP255 0x000000ff /* RW--V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT1 15:8 /* RWDVF */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT1_INIT 0x00000000 /* RWD-V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT2 23:16 /* RWDVF */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT2_INIT 0x00000000 /* RWD-V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT3 31:24 /* RWDVF */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_MUX_SELECT_M1SELECT3_INIT 0x00000000 /* RWD-V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL 0x00001508 /* RW-4R */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_ENTX0 0:0 /* RWDVF */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_ENTX0_INIT 0x00000000 /* RWD-V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_ENTX1 1:1 /* RWDVF */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_ENTX1_INIT 0x00000000 /* RWD-V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_ENTX2 2:2 /* RWDVF */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_ENTX2_INIT 0x00000000 /* RWD-V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_ENTX3 3:3 /* RWDVF */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_ENTX3_INIT 0x00000000 /* RWD-V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_RESETTX0 16:16 /* RWDVF */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_RESETTX0_INIT 0x00000000 /* RWD-V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_RESETTX1 17:17 /* RWDVF */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_RESETTX1_INIT 0x00000000 /* RWD-V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_RESETTX2 18:18 /* RWDVF */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_RESETTX2_INIT 0x00000000 /* RWD-V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_RESETTX3 19:19 /* RWDVF */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_RESETTX3_INIT 0x00000000 /* RWD-V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE0 24:24 /* RWDVF */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE0_INIT 0x00000000 /* RWD-V */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE1 25:25 /* RWDVF */
|
|
#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE1_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE2 26:26 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE2_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE3 27:27 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE3_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_HW_FORCE_ILA_TRIGGER_ENABLE 29:29 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_HW_FORCE_ILA_TRIGGER_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_HW_FORCE_ILA_TRIGGER_ENABLE_DISABLE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_HW_TP_ENABLE 30:30 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_HW_TP_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_HW_TP_ENABLE_DISABLE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_HW_TP_CAPTURE_ENABLE 31:31 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_HW_TP_CAPTURE_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_HW_TP_CAPTURE_ENABLE_DISABLE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0(i) (0x0000150c+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT 2:1 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_CYCLES 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_PACKETS 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_FLITS 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_BYTES 0x00000003 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER 7:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_HEAD 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_AE 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_BE 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_DATA 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_IDLE 0x00000010 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE 9:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_INIT 0x00000003 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_VCSET0 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_VCSET1 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE 19:17 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_ONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_TWO 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_FOUR 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_EIGHT 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_SIXTEEN 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_THIRTYTWO 0x00000005 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_SIXTYFOUR 0x00000006 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_ONETWENTYEIGHT 0x00000007 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_1(i) (0x00001510+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_1__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_1_PKTFILTERRSPMODE 1:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_1_PKTFILTERRSPMODE_BASE_ONLY 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_1_PKTFILTERRSPMODE_COLLAPSED_IN_BASE_PLUS1 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_1_PKTFILTERRSPMODE_COLLAPSED_IN_BASE 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_1_PKT_FILTER_COLLAPSED_RSP_BIN 15:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_1_PKT_FILTER_COLLAPSED_RSP_BIN_INIT 0x000000ff /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_1_PKT_FILTER_COLLAPSED_RSP_BIN_EN 16:16 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CTRL_1_PKT_FILTER_COLLAPSED_RSP_BIN_EN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX0_FILTER(i) (0x00001514+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX0_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQID_FILTER 8:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQID_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQID_MASK 19:11 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQID_MASK_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQLAN_FILTER 25:22 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQLAN_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQLAN_MASK 30:27 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQLAN_MASK_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX1_FILTER(i) (0x00001518+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX1_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTID_FILTER 10:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTID_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTID_MASK 21:11 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTID_MASK_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTLAN_FILTER 25:22 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTLAN_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTLAN_MASK 30:27 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTLAN_MASK_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER(i) (0x0000151c+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_IRL 1:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_IRL_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_IRL_ENABLE 4:4 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_IRL_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_EST 8:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_EST_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_EST_ENABLE 10:10 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_EST_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_BECN 16:16 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_BECN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_BECN_ENABLE 19:19 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_BECN_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER(i) (0x00001520+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE 31:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_INIT 0x75beca8f /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_NOP 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_READ_NCP 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_READ_NCNP 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_READ_RWC 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_WRITE_NCP 0x00000080 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_WRITE_NCNP 0x00000200 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_UPGRADE 0x00000800 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_DOWNGRADE 0x00004000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_PROBE_I_N 0x00008000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_PROBE_I_MO 0x00020000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_PROBE_X_MO 0x00040000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_RMW_NCP 0x00080000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_RMW_NCNP 0x00100000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATOMIC_NONRED_NCP 0x00200000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATOMIC_RED_NCP 0x00800000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATOMIC_NONRED_NCNP 0x01000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATOMIC_RED_NCNP 0x04000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATR 0x10000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATSD_NONFLUSH 0x20000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATSD_FLUSH 0x40000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER(i) (0x00001524+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE 31:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_INIT 0xff7870ef /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_WRITE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_RMW 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_ATOMIC_RED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_ATOMIC 0x00000008 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_UPGRADE 0x00000020 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_READ_NC 0x00000040 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_READ_RWC 0x00000080 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_ATRRSP 0x00001000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_ATSDRSP 0x00002000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_DOWNGRADERSP 0x00004000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_D_I 0x00080000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_D_X 0x00100000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_D_E 0x00200000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_D_M 0x00400000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_ND_I 0x01000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_ND_X 0x02000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_ND_E 0x04000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_TRANSDONE_RMW 0x08000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_TRANSDONE_UPGRADE 0x10000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_TRANSDONE_DOWNGRADE_G 0x20000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_TRANSDONE_DOWNGRADE_C 0x40000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_TRANSDONE_READ_RWC 0x80000000 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER(i) (0x00001528+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_PKTSTATUSFILTER 1:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_PKTSTATUSFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_PKTSTATUSFILTEREN 2:2 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_PKTSTATUSFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_RSPSTATUSFILTER 4:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_RSPSTATUSFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_RSPSTATUSFILTEREN 5:5 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_RSPSTATUSFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_NCRFILTER 6:6 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_NCRFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_NCRFILTEREN 7:7 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_NCRFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ADDRTYPEFILTER 9:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ADDRTYPEFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ADDRTYPEFILTEREN 11:11 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ADDRTYPEFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICCMDFILTER 15:12 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICCMDFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICCMDFILTEREN 17:17 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICCMDFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICSIZEFILTER 20:18 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICSIZEFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICSIZEFILTEREN 22:22 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICSIZEFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_DATLENFILTER 26:23 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_DATLENFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_DATLENFILTEREN 27:27 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_DATLENFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1(i) (0x0000152c+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_REQCONTEXT_FILTER 15:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_REQCONTEXT_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_REQCONTEXT_FILTER_ENABLE 16:16 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_REQCONTEXT_FILTER_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_RSPDATAATTR_FILTER 26:17 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_RSPDATAATTR_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_RSPDATAATTR_FILTER_ENABLE 28:28 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_RSPDATAATTR_FILTER_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_2(i) (0x00001530+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_2__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_2_REQATTR_31_0_FILTER 31:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_2_REQATTR_31_0_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_3(i) (0x00001534+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_3__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_3_REQATTR_35_32_FILTER 3:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_3_REQATTR_35_32_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_3_REQATTR_FILTER_ENABLE 16:16 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_MISC_FILTER_3_REQATTR_FILTER_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER(i) (0x00001538+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER 2:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_DISABLED 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_CYCLES_IN_HS_WITHOUT_SL_DESIRED 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_CYCLES_IN_HS_WITH_SL_DESIRED 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_CYCLES_IN_SL_WITHOUT_HS_DESIRED 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_CYCLES_IN_SL_WITH_HS_DESIRED 0x00000004 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_TRANSITION_HS_TO_SL 0x00000005 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_ENABLE 3:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_COMPQ_USAGE 10:4 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_COMPQ_USAGE_INIT 0x0000000f /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_COMPQ_USAGE_ENABLE 12:12 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_COMPQ_USAGE_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_PACKET_DEBUG_TRACE_FILTER 17:16 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_PACKET_DEBUG_TRACE_FILTER_NO_CAPTURE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_PACKET_DEBUG_TRACE_FILTER_CAPTURE_HEADER 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_PACKET_DEBUG_TRACE_FILTER_CAPTURE_PACKET 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_PACKET_DEBUG_TRACE_FILTER_RESERVED 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_PACKET_DEBUG_TRACE_FILTER_ENABLE 19:19 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HW_FILTER_PACKET_DEBUG_TRACE_FILTER_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_LO_FILTER(i) (0x0000153c+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_LO_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_LO_FILTER_ADDRESSFILTER 31:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_LO_FILTER_ADDRESSFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_HI_FILTER(i) (0x00001540+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_HI_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_HI_FILTER_ADDRESSFILTER 31:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_HI_FILTER_ADDRESSFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_LO_MASK(i) (0x00001544+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_LO_MASK__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_LO_MASK_ADDRESSMASK 31:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_LO_MASK_ADDRESSMASK_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_HI_MASK(i) (0x00001548+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_HI_MASK__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_HI_MASK_ADDRESSMASK 31:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ADDR_HI_MASK_ADDRESSMASK_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_LO(i) (0x0000154c+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_LO__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_LO_COUNT 31:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_LO_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI(i) (0x00001550+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI_COUNT 30:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER 31:31 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CAPTURE_LO(i) (0x00001554+(i)*0x54) /* R--4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CAPTURE_LO__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CAPTURE_LO_COUNTER 31:0 /* R-DVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CAPTURE_LO_COUNTER_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CAPTURE_HI(i) (0x00001558+(i)*0x54) /* R--4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CAPTURE_HI__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CAPTURE_HI_COUNTER 31:0 /* R-DVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_CAPTURE_HI_COUNTER_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ILA_CTRL(i) (0x0000155c+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ILA_CTRL__SIZE_1 4 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRIGGER 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRIGGER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRACE 9:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRACE_NO_CAPTURE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRACE_CAPTURE_HEADER 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRACE_CAPTURE_PACKET 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRACE_RESERVED 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_CTRL 0x00001680 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_CTRL__PRIV_LEVEL_MASK 0x00001010 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_CTRL_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_CTRL_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_CTRL_STALLTRIGGERENABLE 1:1 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_CTRL_STALLTRIGGERENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_CTRL_STOMPTRIGGERENABLE 2:2 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_CTRL_STOMPTRIGGERENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_CTRL_SWSTALLORINJECT 3:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_CTRL_SWSTALLORINJECT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_0 0x00001684 /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_0_REFORMAT_ENTRY0 15:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_0_REFORMAT_ENTRY0_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_0_REFORMAT_ENTRY1 31:16 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_0_REFORMAT_ENTRY1_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_1 0x00001688 /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_1_REFORMAT_ENTRY2 15:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_1_REFORMAT_ENTRY2_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_1_REFORMAT_ENTRY3 31:16 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_1_REFORMAT_ENTRY3_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_2 0x0000168c /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_2_REFORMAT_ENTRY4 15:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_2_REFORMAT_ENTRY4_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_2_REFORMAT_ENTRY5 31:16 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_2_REFORMAT_ENTRY5_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_3 0x00001690 /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_3_REFORMAT_ENTRY6 15:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_3_REFORMAT_ENTRY6_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_3_REFORMAT_ENTRY7 31:16 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_3_REFORMAT_ENTRY7_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_4 0x00001694 /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_4_VC0_TLTX_DATA_CREDITS 11:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_4_VC0_TLTX_DATA_CREDITS_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_4_TX_DBG_REFORMAT_IDX 14:12 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_4_TX_DBG_REFORMAT_IDX_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_4_VC5_TLTX_DATA_CREDITS 27:16 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_4_VC5_TLTX_DATA_CREDITS_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_5 0x00001698 /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_5_VC6_TLTX_DATA_CREDITS 11:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_5_VC6_TLTX_DATA_CREDITS_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_5_VC7_TLTX_DATA_CREDITS 27:16 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_5_VC7_TLTX_DATA_CREDITS_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC0 0x0000169c /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC0_FIFO_VLD 0:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC0_FIFO_VLD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC0_FIFO_RD_COUNT 7:1 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC0_FIFO_RD_COUNT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC0_FIFO_HEAD 16:8 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC0_FIFO_HEAD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC0_HDR_CREDITS 28:17 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC0_HDR_CREDITS_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC1 0x000016a0 /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC1_FIFO_VLD 0:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC1_FIFO_VLD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC1_FIFO_RD_COUNT 7:1 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC1_FIFO_RD_COUNT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC1_FIFO_HEAD 16:8 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC1_FIFO_HEAD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC1_HDR_CREDITS 28:17 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC1_HDR_CREDITS_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC2 0x000016a4 /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC2_FIFO_VLD 0:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC2_FIFO_VLD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC2_FIFO_RD_COUNT 7:1 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC2_FIFO_RD_COUNT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC2_FIFO_HEAD 16:8 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC2_FIFO_HEAD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC2_HDR_CREDITS 28:17 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC2_HDR_CREDITS_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC3 0x000016a8 /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC3_FIFO_VLD 0:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC3_FIFO_VLD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC3_FIFO_RD_COUNT 7:1 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC3_FIFO_RD_COUNT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC3_FIFO_HEAD 16:8 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC3_FIFO_HEAD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC3_HDR_CREDITS 28:17 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC3_HDR_CREDITS_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC4 0x000016ac /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC4_FIFO_VLD 0:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC4_FIFO_VLD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC4_FIFO_RD_COUNT 7:1 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC4_FIFO_RD_COUNT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC4_FIFO_HEAD 16:8 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC4_FIFO_HEAD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC4_HDR_CREDITS 28:17 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC4_HDR_CREDITS_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC5 0x000016b0 /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC5_FIFO_VLD 0:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC5_FIFO_VLD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC5_FIFO_RD_COUNT 7:1 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC5_FIFO_RD_COUNT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC5_FIFO_HEAD 16:8 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC5_FIFO_HEAD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC5_HDR_CREDITS 28:17 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC5_HDR_CREDITS_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC6 0x000016b4 /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC6_FIFO_VLD 0:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC6_FIFO_VLD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC6_FIFO_RD_COUNT 7:1 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC6_FIFO_RD_COUNT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC6_FIFO_HEAD 16:8 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC6_FIFO_HEAD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC6_HDR_CREDITS 28:17 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC6_HDR_CREDITS_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC7 0x000016b8 /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC7_FIFO_VLD 0:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC7_FIFO_VLD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC7_FIFO_RD_COUNT 7:1 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC7_FIFO_RD_COUNT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC7_FIFO_HEAD 16:8 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC7_FIFO_HEAD_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC7_HDR_CREDITS 28:17 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_VC7_HDR_CREDITS_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC0 0x000016bc /* RW-4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC0__PRIV_LEVEL_MASK 0x00001010 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC0_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC0_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC0_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC0_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC0_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC0_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC0_MODE_TRIGGER 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC0_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC0_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC0_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC0_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC1 0x000016c0 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC1__PRIV_LEVEL_MASK 0x00001010 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC1_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC1_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC1_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC1_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC1_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC1_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC1_MODE_TRIGGER 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC1_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC1_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC1_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC1_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC2 0x000016c4 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC2__PRIV_LEVEL_MASK 0x00001010 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC2_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC2_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC2_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC2_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC2_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC2_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC2_MODE_TRIGGER 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC2_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC2_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC2_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC2_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC3 0x000016c8 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC3__PRIV_LEVEL_MASK 0x00001010 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC3_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC3_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC3_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC3_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC3_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC3_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC3_MODE_TRIGGER 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC3_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC3_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC3_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC3_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC4 0x000016cc /* RW-4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC4__PRIV_LEVEL_MASK 0x00001010 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC4_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC4_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC4_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC4_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC4_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC4_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC4_MODE_TRIGGER 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC4_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC4_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC4_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC4_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC5 0x000016d0 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC5__PRIV_LEVEL_MASK 0x00001010 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC5_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC5_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC5_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC5_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC5_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC5_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC5_MODE_TRIGGER 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC5_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC5_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC5_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC5_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC6 0x000016d4 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC6__PRIV_LEVEL_MASK 0x00001010 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC6_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC6_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC6_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC6_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC6_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC6_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC6_MODE_TRIGGER 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC6_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC6_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC6_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC6_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC7 0x000016d8 /* RW-4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC7__PRIV_LEVEL_MASK 0x00001010 /* */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC7_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC7_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC7_MODE 2:1 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC7_MODE_ONCE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC7_MODE_TOGGLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC7_MODE_INFINITE 0x00000002 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC7_MODE_TRIGGER 0x00000003 /* RW--V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC7_SMALLCOUNTMODE 3:3 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC7_SMALLCOUNTMODE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC7_COUNT 31:8 /* RWDVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_STALL_VC7_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10 0x000016dc /* R--4R */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_EMPTY_STATE 2:0 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_EMPTY_STATE_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_EMPTY_DBG_EMPTY_REQ 3:3 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_EMPTY_DBG_EMPTY_REQ_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_EMPTY_DBG_STALL_ACK 4:4 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_EMPTY_DBG_STALL_ACK_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_EMPTY_DBG_TIMER_DONE 5:5 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_EMPTY_DBG_TIMER_DONE_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_EMPTY_DBG_RCVD_LAST_CDT 6:6 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_EMPTY_DBG_RCVD_LAST_CDT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_EMPTY_DBG_SENT_LAST_CDT 7:7 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_EMPTY_DBG_SENT_LAST_CDT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_VCTO_IN 15:8 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_TX_VCTO_IN_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_RSP_COMPQ_0_EMPTY 16:16 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_RSP_COMPQ_0_EMPTY_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_RSP_COMPQ_1_EMPTY 20:20 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_RSP_COMPQ_1_EMPTY_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_RSP_COMPQ_2_EMPTY 24:24 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_RSP_COMPQ_2_EMPTY_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_RSP_COMPQ_3_EMPTY 28:28 /* R-EVF */
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#define NV_NVLTLC_TX_LNK_DEBUG_MISC_10_RSP_COMPQ_3_EMPTY_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0 0x00001800 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1 0x00001804 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2 0x00001808 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask2" /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK2_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3 0x0000180c /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask3" /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK3_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4 0x00001810 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask4" /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK4_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5 0x00001814 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask5" /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK5_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6 0x00001818 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION__FUSE_SIGNAL "sram_ecc" /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK6_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7 0x0000181c /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask7" /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_NVLTLC_RX_LNK_PRIV_LEVEL_MASK7_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_SCRATCH_WARM 0x00001fc0 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_SCRATCH_WARM_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_LNK_SCRATCH_COLD 0x00001fc4 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_SCRATCH_COLD_DATA 31:0 /* RWIVF */
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#define NV_NVLTLC_RX_LNK_SCRATCH_COLD_DATA_INIT 0xdeadbaad /* RWI-V */
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#define NV_NVLTLC_RX_LNK_SCRATCH_COLD_AND_DEBUG 0x00001fc8 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_SCRATCH_COLD_AND_DEBUG_DATA 31:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_SCRATCH_COLD_AND_DEBUG_DATA_INIT 0xdeadbaad /* RWD-V */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK0 0x00001fd0 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK0__PRIV_LEVEL_MASK 0x00001800 /* */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK0_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK0_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK1 0x00001fd4 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK1__PRIV_LEVEL_MASK 0x00001804 /* */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK1_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK1_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK2 0x00001fd8 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK2__PRIV_LEVEL_MASK 0x00001808 /* */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK2_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK2_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK3 0x00001fdc /* RW-4R */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK3__PRIV_LEVEL_MASK 0x0000180c /* */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK3_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK3_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK4 0x00001fe0 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK4__PRIV_LEVEL_MASK 0x00001810 /* */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK4_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK4_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK5 0x00001fe4 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK5__PRIV_LEVEL_MASK 0x00001814 /* */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK5_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK5_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK6 0x00001fe8 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK6__PRIV_LEVEL_MASK 0x00001818 /* */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK6_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK6_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK7 0x00001fec /* RW-4R */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK7__PRIV_LEVEL_MASK 0x0000181c /* */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK7_DATA 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_SCRATCH_PRIVMASK7_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_NVLTLC_RX_LNK_CTRL_LINK_CONFIG 0x00001900 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_CTRL_LINK_CONFIG__PRIV_LEVEL_MASK 0x0000181c /* */
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#define NV_NVLTLC_RX_LNK_CTRL_LINK_CONFIG_POISON_ENABLE 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_CTRL_LINK_CONFIG_POISON_ENABLE_ENABLED 0x00000001 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_CTRL_LINK_CONFIG_POISON_ENABLE_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_CTRL_LINK_CONFIG_ALLOW_COLLAPSED_RESPONSES 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_CTRL_LINK_CONFIG_ALLOW_COLLAPSED_RESPONSES_ENABLED 0x00000001 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_CTRL_LINK_CONFIG_ALLOW_COLLAPSED_RESPONSES_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_CTRL_LINK_CONFIG_ALLOWAEC 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_CTRL_LINK_CONFIG_ALLOWAEC_ENABLED 0x00000001 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_CTRL_LINK_CONFIG_ALLOWAEC_DISABLED 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_CTRL_HEARTBEAT_TIMEOUT 0x00001904 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_CTRL_HEARTBEAT_TIMEOUT__PRIV_LEVEL_MASK 0x0000180c /* */
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#define NV_NVLTLC_RX_LNK_CTRL_HEARTBEAT_TIMEOUT_TIME_IN_100US 23:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_CTRL_HEARTBEAT_TIMEOUT_TIME_IN_100US_INIT 0x00000064 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_CTRL_HEARTBEAT_TIMEOUT_ENABLE 31:31 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_CTRL_HEARTBEAT_TIMEOUT_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_CTRL_HEARTBEAT_TIMEOUT_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT 0x00001a00 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT__PRIV_LEVEL_MASK 0x00001818 /* */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_HDR_ECC_SBE 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_HDR_ECC_SBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_HDR_ECC_SBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_HDR_ECC_DBE 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_HDR_ECC_DBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_HDR_ECC_DBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_DAT0_ECC_SBE 2:2 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_DAT0_ECC_SBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_DAT0_ECC_SBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_DAT0_ECC_DBE 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_DAT0_ECC_DBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_DAT0_ECC_DBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_DAT1_ECC_SBE 4:4 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_DAT1_ECC_SBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_DAT1_ECC_SBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_DAT1_ECC_DBE 5:5 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_DAT1_ECC_DBE_INJECT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_INJECT_DAT1_ECC_DBE_NO_INJECT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT 0x00001a04 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT__PRIV_LEVEL_MASK 0x00001818 /* */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_REQUEST 2:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_REQUEST_NOP 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_REQUEST_SBE_HDR_SBE_INJECT_ARM 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_REQUEST_DBE_HDR_DBE_INJECT_ARM 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_REQUEST_SBE_DATA_SBE_INJECT_ARM 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_REQUEST_DBE_DATA_DBE_INJECT_ARM 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_REQUEST_INJECT_DISARM 0x00000007 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_VC 10:8 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_VC_CREQ 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_VC_DGD 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_VC_ATR 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_VC_ATSD 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_VC_PRB 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_VC_RSP 0x00000005 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_VC_CREQ_VCSET1 0x00000006 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_VC_RSP_VCSET1 0x00000007 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_READY 31:31 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_ERR_ECC_PRECISE_INJECT_READY_INIT 0x00000001 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0 0x00001a80 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLHDRPARITYERR 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLHDRPARITYERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLHDRPARITYERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLDATAPARITYERR 1:1 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLDATAPARITYERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLDATAPARITYERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLCTRLPARITYERR 2:2 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLCTRLPARITYERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXDLCTRLPARITYERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXINVALIDAEERR 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXINVALIDAEERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXINVALIDAEERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXINVALIDBEERR 4:4 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXINVALIDBEERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXINVALIDBEERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXINVALIDADDRALIGNERR 5:5 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXINVALIDADDRALIGNERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXINVALIDADDRALIGNERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXPKTLENERR 6:6 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXPKTLENERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXPKTLENERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCMDENCERR 7:7 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCMDENCERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCMDENCERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVDATLENENCERR 8:8 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVDATLENENCERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVDATLENENCERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVPKTSTATUSERR 9:9 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVPKTSTATUSERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVPKTSTATUSERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBEREQERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBEREQERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBERSPERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RSVCACHEATTRPROBERSPERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENGTRMWREQMAXERR 12:12 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENGTRMWREQMAXERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENGTRMWREQMAXERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENLTATRRSPMINERR 13:13 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENLTATRRSPMINERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_DATLENLTATRRSPMINERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALIDCACHEATTRPOERR 14:14 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALIDCACHEATTRPOERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALIDCACHEATTRPOERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_HW_ERR 16:16 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_HW_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_HW_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_UR_ERR 17:17 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_UR_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_UR_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_PRIV_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_RXRSPSTATUS_PRIV_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALID_COLLAPSED_RESPONSE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_0_INVALID_COLLAPSED_RESPONSE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0 0x00001a84 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0__PRIV_LEVEL_MASK 0x0000181c /* */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXDLHDRPARITYERR 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXDLHDRPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXDLHDRPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXDLDATAPARITYERR 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXDLDATAPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXDLDATAPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXDLCTRLPARITYERR 2:2 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXDLCTRLPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXDLCTRLPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXINVALIDAEERR 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXINVALIDAEERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXINVALIDAEERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXINVALIDBEERR 4:4 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXINVALIDBEERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXINVALIDBEERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXINVALIDADDRALIGNERR 5:5 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXINVALIDADDRALIGNERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXINVALIDADDRALIGNERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXPKTLENERR 6:6 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXPKTLENERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXPKTLENERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVCMDENCERR 7:7 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVCMDENCERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVCMDENCERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVDATLENENCERR 8:8 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVDATLENENCERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVDATLENENCERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVPKTSTATUSERR 9:9 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVPKTSTATUSERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVPKTSTATUSERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVCACHEATTRPROBEREQERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVCACHEATTRPROBEREQERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVCACHEATTRPROBERSPERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RSVCACHEATTRPROBERSPERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_DATLENGTRMWREQMAXERR 12:12 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_DATLENGTRMWREQMAXERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_DATLENGTRMWREQMAXERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_DATLENLTATRRSPMINERR 13:13 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_DATLENLTATRRSPMINERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_DATLENLTATRRSPMINERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_INVALIDCACHEATTRPOERR 14:14 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_INVALIDCACHEATTRPOERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_INVALIDCACHEATTRPOERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXRSPSTATUS_HW_ERR 16:16 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXRSPSTATUS_UR_ERR 17:17 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_RXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0 0x00001a88 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLHDRPARITYERR 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLHDRPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLHDRPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLDATAPARITYERR 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLDATAPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLDATAPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR 2:2 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXINVALIDAEERR 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXINVALIDAEERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXINVALIDAEERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXINVALIDBEERR 4:4 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXINVALIDBEERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXINVALIDBEERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXINVALIDADDRALIGNERR 5:5 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXINVALIDADDRALIGNERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXINVALIDADDRALIGNERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXPKTLENERR 6:6 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXPKTLENERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXPKTLENERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCMDENCERR 7:7 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCMDENCERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCMDENCERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVDATLENENCERR 8:8 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVDATLENENCERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVDATLENENCERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVPKTSTATUSERR 9:9 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVPKTSTATUSERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVPKTSTATUSERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR 12:12 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR 13:13 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR 14:14 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR 16:16 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR 17:17 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0 0x00001a8c /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLHDRPARITYERR 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLHDRPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLHDRPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLDATAPARITYERR 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLDATAPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLDATAPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR 2:2 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXDLCTRLPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXINVALIDAEERR 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXINVALIDAEERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXINVALIDAEERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXINVALIDBEERR 4:4 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXINVALIDBEERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXINVALIDBEERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXINVALIDADDRALIGNERR 5:5 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXINVALIDADDRALIGNERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXINVALIDADDRALIGNERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXPKTLENERR 6:6 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXPKTLENERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXPKTLENERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCMDENCERR 7:7 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCMDENCERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCMDENCERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVDATLENENCERR 8:8 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVDATLENENCERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVDATLENENCERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVPKTSTATUSERR 9:9 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVPKTSTATUSERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVPKTSTATUSERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR 12:12 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENGTRMWREQMAXERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR 13:13 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_DATLENLTATRRSPMINERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR 14:14 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALIDCACHEATTRPOERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR 16:16 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR 17:17 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0 0x00001a90 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXDLHDRPARITYERR 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXDLHDRPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXDLHDRPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXDLDATAPARITYERR 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXDLDATAPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXDLDATAPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXDLCTRLPARITYERR 2:2 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXDLCTRLPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXDLCTRLPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXINVALIDAEERR 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXINVALIDAEERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXINVALIDAEERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXINVALIDBEERR 4:4 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXINVALIDBEERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXINVALIDBEERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXINVALIDADDRALIGNERR 5:5 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXINVALIDADDRALIGNERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXINVALIDADDRALIGNERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXPKTLENERR 6:6 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXPKTLENERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXPKTLENERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVCMDENCERR 7:7 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVCMDENCERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVCMDENCERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVDATLENENCERR 8:8 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVDATLENENCERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVDATLENENCERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVPKTSTATUSERR 9:9 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVPKTSTATUSERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVPKTSTATUSERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVCACHEATTRPROBEREQERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RSVCACHEATTRPROBERSPERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_DATLENGTRMWREQMAXERR 12:12 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_DATLENGTRMWREQMAXERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_DATLENGTRMWREQMAXERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_DATLENLTATRRSPMINERR 13:13 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_DATLENLTATRRSPMINERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_DATLENLTATRRSPMINERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_INVALIDCACHEATTRPOERR 14:14 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_INVALIDCACHEATTRPOERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_INVALIDCACHEATTRPOERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXRSPSTATUS_HW_ERR 16:16 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXRSPSTATUS_UR_ERR 17:17 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_RXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0 0x00001a94 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0__PRIV_LEVEL_MASK 0x0000181c /* */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXDLHDRPARITYERR 0:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXDLHDRPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXDLHDRPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXDLDATAPARITYERR 1:1 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXDLDATAPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXDLDATAPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXDLCTRLPARITYERR 2:2 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXDLCTRLPARITYERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXDLCTRLPARITYERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXINVALIDAEERR 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXINVALIDAEERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXINVALIDAEERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXINVALIDBEERR 4:4 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXINVALIDBEERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXINVALIDBEERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXINVALIDADDRALIGNERR 5:5 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXINVALIDADDRALIGNERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXINVALIDADDRALIGNERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXPKTLENERR 6:6 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXPKTLENERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXPKTLENERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVCMDENCERR 7:7 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVCMDENCERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVCMDENCERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVDATLENENCERR 8:8 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVDATLENENCERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVDATLENENCERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVPKTSTATUSERR 9:9 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVPKTSTATUSERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVPKTSTATUSERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVCACHEATTRPROBEREQERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVCACHEATTRPROBEREQERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVCACHEATTRPROBERSPERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RSVCACHEATTRPROBERSPERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_DATLENGTRMWREQMAXERR 12:12 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_DATLENGTRMWREQMAXERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_DATLENGTRMWREQMAXERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_DATLENLTATRRSPMINERR 13:13 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_DATLENLTATRRSPMINERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_DATLENLTATRRSPMINERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_INVALIDCACHEATTRPOERR 14:14 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_INVALIDCACHEATTRPOERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_INVALIDCACHEATTRPOERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXRSPSTATUS_HW_ERR 16:16 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXRSPSTATUS_HW_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXRSPSTATUS_HW_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXRSPSTATUS_UR_ERR 17:17 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXRSPSTATUS_UR_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXRSPSTATUS_UR_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXRSPSTATUS_PRIV_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_RXRSPSTATUS_PRIV_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_0_INVALID_COLLAPSED_RESPONSE_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0 0x00001a98 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0__PRIV_LEVEL_MASK 0x00001810 /* */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXDLHDRPARITYERR 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXDLHDRPARITYERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXDLHDRPARITYERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXDLDATAPARITYERR 1:1 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXDLDATAPARITYERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXDLDATAPARITYERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXDLCTRLPARITYERR 2:2 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXDLCTRLPARITYERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXDLCTRLPARITYERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXINVALIDAEERR 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXINVALIDAEERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXINVALIDAEERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXINVALIDBEERR 4:4 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXINVALIDBEERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXINVALIDBEERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXINVALIDADDRALIGNERR 5:5 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXINVALIDADDRALIGNERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXINVALIDADDRALIGNERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXPKTLENERR 6:6 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXPKTLENERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXPKTLENERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVCMDENCERR 7:7 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVCMDENCERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVCMDENCERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVDATLENENCERR 8:8 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVDATLENENCERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVDATLENENCERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVPKTSTATUSERR 9:9 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVPKTSTATUSERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVPKTSTATUSERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVCACHEATTRPROBEREQERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVCACHEATTRPROBEREQERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVCACHEATTRPROBERSPERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RSVCACHEATTRPROBERSPERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_DATLENGTRMWREQMAXERR 12:12 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_DATLENGTRMWREQMAXERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_DATLENGTRMWREQMAXERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_DATLENLTATRRSPMINERR 13:13 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_DATLENLTATRRSPMINERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_DATLENLTATRRSPMINERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_INVALIDCACHEATTRPOERR 14:14 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_INVALIDCACHEATTRPOERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_INVALIDCACHEATTRPOERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXRSPSTATUS_HW_ERR 16:16 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXRSPSTATUS_HW_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXRSPSTATUS_HW_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXRSPSTATUS_UR_ERR 17:17 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXRSPSTATUS_UR_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXRSPSTATUS_UR_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXRSPSTATUS_PRIV_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_RXRSPSTATUS_PRIV_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_INVALID_COLLAPSED_RESPONSE_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_0_INVALID_COLLAPSED_RESPONSE_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0 0x00001a9c /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLHDRPARITYERR 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLHDRPARITYERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLHDRPARITYERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLDATAPARITYERR 1:1 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLDATAPARITYERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLDATAPARITYERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLCTRLPARITYERR 2:2 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLCTRLPARITYERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXDLCTRLPARITYERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXINVALIDAEERR 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXINVALIDAEERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXINVALIDAEERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXINVALIDBEERR 4:4 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXINVALIDBEERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXINVALIDBEERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXINVALIDADDRALIGNERR 5:5 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXINVALIDADDRALIGNERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXINVALIDADDRALIGNERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXPKTLENERR 6:6 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXPKTLENERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXPKTLENERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCMDENCERR 7:7 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCMDENCERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCMDENCERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVDATLENENCERR 8:8 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVDATLENENCERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVDATLENENCERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVPKTSTATUSERR 9:9 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVPKTSTATUSERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVPKTSTATUSERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBEREQERR 10:10 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBEREQERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBEREQERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBERSPERR 11:11 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBERSPERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RSVCACHEATTRPROBERSPERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENGTRMWREQMAXERR 12:12 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENGTRMWREQMAXERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENGTRMWREQMAXERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENLTATRRSPMINERR 13:13 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENLTATRRSPMINERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_DATLENLTATRRSPMINERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALIDCACHEATTRPOERR 14:14 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALIDCACHEATTRPOERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALIDCACHEATTRPOERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_HW_ERR 16:16 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_HW_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_HW_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_UR_ERR 17:17 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_UR_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_UR_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_PRIV_ERR 18:18 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_PRIV_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_RXRSPSTATUS_PRIV_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALID_COLLAPSED_RESPONSE_ERR 19:19 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALID_COLLAPSED_RESPONSE_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_0_INVALID_COLLAPSED_RESPONSE_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1 0x00001aa0 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXHDROVFERR 7:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXHDROVFERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXHDROVFERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXDATAOVFERR 15:8 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXDATAOVFERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXDATAOVFERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_STOMPDETERR 16:16 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_STOMPDETERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_STOMPDETERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXPOISONERR 17:17 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXPOISONERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_RXPOISONERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_AN1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_AN1_HEARTBEAT_TIMEOUT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_STATUS_1_AN1_HEARTBEAT_TIMEOUT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1 0x00001aa4 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1__PRIV_LEVEL_MASK 0x0000181c /* */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_RXHDROVFERR 7:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_RXHDROVFERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_RXHDROVFERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_RXDATAOVFERR 15:8 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_RXDATAOVFERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_RXDATAOVFERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_STOMPDETERR 16:16 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_STOMPDETERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_STOMPDETERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_RXPOISONERR 17:17 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_RXPOISONERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_RXPOISONERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_LOG_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1 0x00001aa8 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXHDROVFERR 7:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXHDROVFERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXHDROVFERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXDATAOVFERR 15:8 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXDATAOVFERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXDATAOVFERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_STOMPDETERR 16:16 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_STOMPDETERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_STOMPDETERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXPOISONERR 17:17 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXPOISONERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_RXPOISONERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_FATAL_REPORT_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1 0x00001aac /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXHDROVFERR 7:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXHDROVFERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXHDROVFERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXDATAOVFERR 15:8 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXDATAOVFERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXDATAOVFERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_STOMPDETERR 16:16 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_STOMPDETERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_STOMPDETERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXPOISONERR 17:17 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXPOISONERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_RXPOISONERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_NON_FATAL_REPORT_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1 0x00001ab0 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_RXHDROVFERR 7:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_RXHDROVFERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_RXHDROVFERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_RXDATAOVFERR 15:8 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_RXDATAOVFERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_RXDATAOVFERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_STOMPDETERR 16:16 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_STOMPDETERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_STOMPDETERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_RXPOISONERR 17:17 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_RXPOISONERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_RXPOISONERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CORRECTABLE_REPORT_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1 0x00001ab4 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1__PRIV_LEVEL_MASK 0x0000181c /* */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_RXHDROVFERR 7:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_RXHDROVFERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_RXHDROVFERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_RXDATAOVFERR 15:8 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_RXDATAOVFERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_RXDATAOVFERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_STOMPDETERR 16:16 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_STOMPDETERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_STOMPDETERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_RXPOISONERR 17:17 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_RXPOISONERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_RXPOISONERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR_DISABLE 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_ERR_CONTAIN_EN_1_AN1_HEARTBEAT_TIMEOUT_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1 0x00001ab8 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1__PRIV_LEVEL_MASK 0x00001810 /* */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXHDROVFERR 7:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXHDROVFERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXHDROVFERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXDATAOVFERR 15:8 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXDATAOVFERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXDATAOVFERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_STOMPDETERR 16:16 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_STOMPDETERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_STOMPDETERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXPOISONERR 17:17 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXPOISONERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_RXPOISONERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_AN1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_AN1_HEARTBEAT_TIMEOUT_ERR_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_REPORT_INJECT_1_AN1_HEARTBEAT_TIMEOUT_ERR_INSERT 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1 0x00001abc /* RW-4R */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXHDROVFERR 7:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXHDROVFERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXHDROVFERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXDATAOVFERR 15:8 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXDATAOVFERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXDATAOVFERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_STOMPDETERR 16:16 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_STOMPDETERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_STOMPDETERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXPOISONERR 17:17 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXPOISONERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_RXPOISONERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_AN1_HEARTBEAT_TIMEOUT_ERR 18:18 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_AN1_HEARTBEAT_TIMEOUT_ERR_NONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_ERR_FIRST_1_AN1_HEARTBEAT_TIMEOUT_ERR_CLEAR 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_0 0x00001ac0 /* R--4R */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_0_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_0_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_1 0x00001ac4 /* R--4R */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_1_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_1_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_2 0x00001ac8 /* R--4R */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_2_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_2_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_3 0x00001acc /* R--4R */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_3_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_3_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_LNK_ERR_AE_LOG_0 0x00001ad0 /* R--4R */
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#define NV_NVLTLC_RX_LNK_ERR_AE_LOG_0_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_RX_LNK_ERR_AE_LOG_0_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_LNK_ERR_AE_LOG_1 0x00001ad4 /* R--4R */
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#define NV_NVLTLC_RX_LNK_ERR_AE_LOG_1_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_RX_LNK_ERR_AE_LOG_1_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_LNK_ERR_AE_LOG_2 0x00001ad8 /* R--4R */
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#define NV_NVLTLC_RX_LNK_ERR_AE_LOG_2_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_RX_LNK_ERR_AE_LOG_2_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_LNK_ERR_AE_LOG_3 0x00001adc /* R--4R */
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#define NV_NVLTLC_RX_LNK_ERR_AE_LOG_3_DW 31:0 /* R-DVF */
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#define NV_NVLTLC_RX_LNK_ERR_AE_LOG_3_DW_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_VALID 0x00001ae0 /* R--4R */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_VALID_VALID 0:0 /* R-DVF */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_VALID_VALID_INVALID 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_LNK_ERR_HEADER_LOG_VALID_VALID_VALID 0x00000001 /* R---V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL 0x00001c00 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL__PRIV_LEVEL_MASK 0x00001814 /* */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_CURRENTSTATE 0:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_CURRENTSTATE_LP 0x00000001 /* R---V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_CURRENTSTATE_FB 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_REMOTEDESIRED 1:1 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_REMOTEDESIRED_LP 0x00000001 /* R---V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_REMOTEDESIRED_FB 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_SOFTWAREDESIRED 2:2 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_SOFTWAREDESIRED_LP 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_SOFTWAREDESIRED_FB 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_HARDWAREDISABLE 3:3 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_HARDWAREDISABLE_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_HARDWAREDESIRED 4:4 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_HARDWAREDESIRED_LP 0x00000001 /* R---V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_HARDWAREDESIRED_FB 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_COUNTSTART 5:5 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_SW_CTRL_COUNTSTART_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC 0x00001c04 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PWRM_IC__PRIV_LEVEL_MASK 0x00001814 /* */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_IDLECOUNT 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_IDLECOUNT_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_INC 0x00001c08 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_INC__PRIV_LEVEL_MASK 0x00001814 /* */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_INC_FBINC 15:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_INC_FBINC_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_INC_LPINC 31:16 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_INC_LPINC_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_DEC 0x00001c0c /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_DEC__PRIV_LEVEL_MASK 0x00001814 /* */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_DEC_FBDEC 15:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_DEC_FBDEC_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_DEC_LPDEC 31:16 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_DEC_LPDEC_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_LP_ENTER_THRESHOLD 0x00001c10 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_LP_ENTER_THRESHOLD__PRIV_LEVEL_MASK 0x00001814 /* */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_LP_ENTER_THRESHOLD_THRESHOLD 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_LP_ENTER_THRESHOLD_THRESHOLD_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_LP_EXIT_THRESHOLD 0x00001c14 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_LP_EXIT_THRESHOLD__PRIV_LEVEL_MASK 0x00001814 /* */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_LP_EXIT_THRESHOLD_THRESHOLD 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_LP_EXIT_THRESHOLD_THRESHOLD_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_LIMIT 0x00001c18 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_LIMIT__PRIV_LEVEL_MASK 0x00001814 /* */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_LIMIT_LIMIT 31:0 /* RWEVF */
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#define NV_NVLTLC_RX_LNK_PWRM_IC_LIMIT_LIMIT_INIT 0x00000000 /* RWE-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_CTRL 0x00001d00 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_CTRL_GROUP252 3:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_CTRL_GROUP252_INIT 0x0000000d /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_CTRL_GROUP253 7:4 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_CTRL_GROUP253_INIT 0x00000002 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_CTRL_GROUP254 11:8 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_CTRL_GROUP254_INIT 0x0000000c /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_CTRL_GROUP255 15:12 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_CTRL_GROUP255_INIT 0x00000003 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_CTRL_WATCHBUSENABLE 31:31 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_CTRL_WATCHBUSENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT 0x00001d04 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0 7:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP0 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP1 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP2 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP3 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP4 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP5 0x00000005 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP6 0x00000006 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP7 0x00000007 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP8 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP9 0x00000009 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP10 0x0000000a /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP11 0x0000000b /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP12 0x0000000c /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP13 0x0000000d /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP14 0x0000000e /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP15 0x0000000f /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP16 0x00000010 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP17 0x00000011 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP18 0x00000012 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP19 0x00000013 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP20 0x00000014 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP21 0x00000015 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP22 0x00000016 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP23 0x00000017 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP24 0x00000018 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP25 0x00000019 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP26 0x0000001a /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP27 0x0000001b /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP28 0x0000001c /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP29 0x0000001d /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP30 0x0000001e /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP31 0x0000001f /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP32 0x00000020 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP33 0x00000021 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP34 0x00000022 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP35 0x00000023 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP36 0x00000024 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP37 0x00000025 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP38 0x00000026 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP39 0x00000027 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP40 0x00000028 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP41 0x00000029 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP42 0x0000002a /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP43 0x0000002b /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP44 0x0000002c /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP45 0x0000002d /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP46 0x0000002e /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP47 0x0000002f /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP48 0x00000030 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP49 0x00000031 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP50 0x00000032 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP51 0x00000033 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP52 0x00000034 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP53 0x00000035 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP54 0x00000036 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP55 0x00000037 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP56 0x00000038 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP57 0x00000039 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP58 0x0000003a /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP59 0x0000003b /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP60 0x0000003c /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP61 0x0000003d /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP62 0x0000003e /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP63 0x0000003f /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP64 0x00000040 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP65 0x00000041 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP66 0x00000042 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP67 0x00000043 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP68 0x00000044 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP69 0x00000045 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP70 0x00000046 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP71 0x00000047 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP72 0x00000048 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP73 0x00000049 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP74 0x0000004a /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP75 0x0000004b /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP76 0x0000004c /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP77 0x0000004d /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP78 0x0000004e /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP79 0x0000004f /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP80 0x00000050 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP81 0x00000051 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP82 0x00000052 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP83 0x00000053 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP84 0x00000054 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP85 0x00000055 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP86 0x00000056 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP87 0x00000057 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP88 0x00000058 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP89 0x00000059 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP90 0x0000005a /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP91 0x0000005b /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP92 0x0000005c /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP93 0x0000005d /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP94 0x0000005e /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP95 0x0000005f /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP96 0x00000060 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP97 0x00000061 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP98 0x00000062 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP99 0x00000063 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP100 0x00000064 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP101 0x00000065 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP102 0x00000066 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP103 0x00000067 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP104 0x00000068 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP105 0x00000069 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP106 0x0000006a /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP107 0x0000006b /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP108 0x0000006c /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP109 0x0000006d /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP110 0x0000006e /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP111 0x0000006f /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP112 0x00000070 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP113 0x00000071 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP114 0x00000072 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP115 0x00000073 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP116 0x00000074 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP117 0x00000075 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP118 0x00000076 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP119 0x00000077 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP120 0x00000078 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP121 0x00000079 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP122 0x0000007a /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP123 0x0000007b /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP124 0x0000007c /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP125 0x0000007d /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP126 0x0000007e /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP127 0x0000007f /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP128 0x00000080 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP129 0x00000081 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP130 0x00000082 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP131 0x00000083 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP132 0x00000084 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP133 0x00000085 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP134 0x00000086 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP135 0x00000087 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP136 0x00000088 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP137 0x00000089 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP138 0x0000008a /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP139 0x0000008b /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP140 0x0000008c /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP141 0x0000008d /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP142 0x0000008e /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP143 0x0000008f /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP144 0x00000090 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP145 0x00000091 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP146 0x00000092 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP147 0x00000093 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP148 0x00000094 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP149 0x00000095 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP150 0x00000096 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP151 0x00000097 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP152 0x00000098 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP153 0x00000099 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP154 0x0000009a /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP155 0x0000009b /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP156 0x0000009c /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP157 0x0000009d /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP158 0x0000009e /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP159 0x0000009f /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP160 0x000000a0 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP161 0x000000a1 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP162 0x000000a2 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP163 0x000000a3 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP164 0x000000a4 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP165 0x000000a5 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP166 0x000000a6 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP167 0x000000a7 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP168 0x000000a8 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP169 0x000000a9 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP170 0x000000aa /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP171 0x000000ab /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP172 0x000000ac /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP173 0x000000ad /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP174 0x000000ae /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP175 0x000000af /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP176 0x000000b0 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP177 0x000000b1 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP178 0x000000b2 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP179 0x000000b3 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP180 0x000000b4 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP181 0x000000b5 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP182 0x000000b6 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP183 0x000000b7 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP184 0x000000b8 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP185 0x000000b9 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP186 0x000000ba /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP187 0x000000bb /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP188 0x000000bc /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP189 0x000000bd /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP190 0x000000be /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP191 0x000000bf /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP192 0x000000c0 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP193 0x000000c1 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP194 0x000000c2 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP195 0x000000c3 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP196 0x000000c4 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP197 0x000000c5 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP198 0x000000c6 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP199 0x000000c7 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP200 0x000000c8 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP201 0x000000c9 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP202 0x000000ca /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP203 0x000000cb /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP204 0x000000cc /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP205 0x000000cd /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP206 0x000000ce /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP207 0x000000cf /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP208 0x000000d0 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP209 0x000000d1 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP210 0x000000d2 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP211 0x000000d3 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP212 0x000000d4 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP213 0x000000d5 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP214 0x000000d6 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP215 0x000000d7 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP216 0x000000d8 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP217 0x000000d9 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP218 0x000000da /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP219 0x000000db /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP220 0x000000dc /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP221 0x000000dd /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP222 0x000000de /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP223 0x000000df /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP224 0x000000e0 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP225 0x000000e1 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP226 0x000000e2 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP227 0x000000e3 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP228 0x000000e4 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP229 0x000000e5 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP230 0x000000e6 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP231 0x000000e7 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP232 0x000000e8 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP233 0x000000e9 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP234 0x000000ea /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP235 0x000000eb /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP236 0x000000ec /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP237 0x000000ed /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP238 0x000000ee /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP239 0x000000ef /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP240 0x000000f0 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP241 0x000000f1 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP242 0x000000f2 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP243 0x000000f3 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP244 0x000000f4 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP245 0x000000f5 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP246 0x000000f6 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP247 0x000000f7 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP248 0x000000f8 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP249 0x000000f9 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP250 0x000000fa /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP251 0x000000fb /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP252 0x000000fc /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP253 0x000000fd /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP254 0x000000fe /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT0_GRP255 0x000000ff /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT1 15:8 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT1_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT2 23:16 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT2_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT3 31:24 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MUX_SELECT_M1SELECT3_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL 0x00001d08 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_ENRX0 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_ENRX0_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_ENRX1 1:1 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_ENRX1_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_ENRX2 2:2 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_ENRX2_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_ENRX3 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_ENRX3_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_RESETRX0 16:16 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_RESETRX0_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_RESETRX1 17:17 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_RESETRX1_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_RESETRX2 18:18 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_RESETRX2_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_RESETRX3 19:19 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_RESETRX3_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE0 24:24 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE0_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE1 25:25 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE1_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE2 26:26 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE2_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE3 27:27 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_CAPTURE3_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_HW_TP_ENABLE 30:30 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_HW_TP_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_HW_TP_ENABLE_DISABLE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_HW_TP_CAPTURE_ENABLE 31:31 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_HW_TP_CAPTURE_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_HW_TP_CAPTURE_ENABLE_DISABLE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0(i) (0x00001d0c+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT 2:1 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_CYCLES 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_PACKETS 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_FLITS 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_UNIT_BYTES 0x00000003 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER 7:3 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_HEAD 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_AE 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_BE 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_DATA 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_FLITFILTER_IDLE 0x00000010 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE 9:8 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_INIT 0x00000003 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_VCSET0 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_VCSETFILTERMODE_VCSET1 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE 19:17 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_ONE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_TWO 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_FOUR 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_EIGHT 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_SIXTEEN 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_THIRTYTWO 0x00000005 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_SIXTYFOUR 0x00000006 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_0_PMSIZE_ONETWENTYEIGHT 0x00000007 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_1(i) (0x00001d10+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_1__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_1_PKTFILTERRSPMODE 1:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_1_PKTFILTERRSPMODE_BASE_ONLY 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_1_PKTFILTERRSPMODE_COLLAPSED_IN_BASE_PLUS1 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_1_PKTFILTERRSPMODE_COLLAPSED_IN_BASE 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_1_PKT_FILTER_COLLAPSED_RSP_BIN 15:8 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_1_PKT_FILTER_COLLAPSED_RSP_BIN_INIT 0x000000ff /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_1_PKT_FILTER_COLLAPSED_RSP_BIN_EN 16:16 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CTRL_1_PKT_FILTER_COLLAPSED_RSP_BIN_EN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX0_FILTER(i) (0x00001d14+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX0_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQID_FILTER 8:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQID_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQID_MASK 19:11 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQID_MASK_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQLAN_FILTER 25:22 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQLAN_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQLAN_MASK 30:27 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX0_FILTER_REQLAN_MASK_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX1_FILTER(i) (0x00001d18+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX1_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTID_FILTER 10:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTID_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTID_MASK 21:11 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTID_MASK_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTLAN_FILTER 25:22 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTLAN_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTLAN_MASK 30:27 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX1_FILTER_TGTLAN_MASK_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER(i) (0x00001d1c+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_IRL 1:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_IRL_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_IRL_ENABLE 4:4 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_IRL_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_EST 8:8 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_EST_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_EST_ENABLE 10:10 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_EST_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_BECN 16:16 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_BECN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_BECN_ENABLE 19:19 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_SWX2_FILTER_BECN_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER(i) (0x00001d20+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE 31:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_INIT 0x75beca8f /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_NOP 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_READ_NCP 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_READ_NCNP 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_READ_RWC 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_WRITE_NCP 0x00000080 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_WRITE_NCNP 0x00000200 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_UPGRADE 0x00000800 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_DOWNGRADE 0x00004000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_PROBE_I_N 0x00008000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_PROBE_I_MO 0x00020000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_PROBE_X_MO 0x00040000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_RMW_NCP 0x00080000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_RMW_NCNP 0x00100000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATOMIC_NONRED_NCP 0x00200000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATOMIC_RED_NCP 0x00800000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATOMIC_NONRED_NCNP 0x01000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATOMIC_RED_NCNP 0x04000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATR 0x10000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATSD_NONFLUSH 0x20000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_REQ_FILTER_REQUESTFILTERMODE_ATSD_FLUSH 0x40000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER(i) (0x00001d24+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE 31:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_INIT 0xff7870ef /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_NONE 0x00000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_WRITE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_RMW 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_ATOMIC_RED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_ATOMIC 0x00000008 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_UPGRADE 0x00000020 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_READ_NC 0x00000040 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_REQRSP_READ_RWC 0x00000080 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_ATRRSP 0x00001000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_ATSDRSP 0x00002000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_DOWNGRADERSP 0x00004000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_D_I 0x00080000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_D_X 0x00100000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_D_E 0x00200000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_D_M 0x00400000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_ND_I 0x01000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_ND_X 0x02000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_PROBERSP_ND_E 0x04000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_TRANSDONE_RMW 0x08000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_TRANSDONE_UPGRADE 0x10000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_TRANSDONE_DOWNGRADE_G 0x20000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_TRANSDONE_DOWNGRADE_C 0x40000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_RSP_FILTER_RESPONSEFILTERMODE_TRANSDONE_READ_RWC 0x80000000 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER(i) (0x00001d28+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_PKTSTATUSFILTER 1:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_PKTSTATUSFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_PKTSTATUSFILTEREN 2:2 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_PKTSTATUSFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_RSPSTATUSFILTER 4:3 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_RSPSTATUSFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_RSPSTATUSFILTEREN 5:5 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_RSPSTATUSFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_NCRFILTER 6:6 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_NCRFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_NCRFILTEREN 7:7 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_NCRFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ADDRTYPEFILTER 9:8 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ADDRTYPEFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ADDRTYPEFILTEREN 11:11 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ADDRTYPEFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICCMDFILTER 15:12 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICCMDFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICCMDFILTEREN 17:17 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICCMDFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICSIZEFILTER 20:18 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICSIZEFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICSIZEFILTEREN 22:22 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_ATOMICSIZEFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_DATLENFILTER 26:23 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_DATLENFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_DATLENFILTEREN 27:27 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_DATLENFILTEREN_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1(i) (0x00001d2c+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_REQCONTEXT_FILTER 15:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_REQCONTEXT_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_REQCONTEXT_FILTER_ENABLE 16:16 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_REQCONTEXT_FILTER_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_RSPDATAATTR_FILTER 26:17 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_RSPDATAATTR_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_RSPDATAATTR_FILTER_ENABLE 28:28 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_1_RSPDATAATTR_FILTER_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_2(i) (0x00001d30+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_2__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_2_REQATTR_31_0_FILTER 31:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_2_REQATTR_31_0_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_3(i) (0x00001d34+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_3__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_3_REQATTR_35_32_FILTER 3:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_3_REQATTR_35_32_FILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_3_REQATTR_FILTER_ENABLE 16:16 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_MISC_FILTER_3_REQATTR_FILTER_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HW_FILTER(i) (0x00001d38+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HW_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER 2:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_DISABLED 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_CYCLES_IN_HS_WITHOUT_SL_DESIRED 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_CYCLES_IN_HS_WITH_SL_DESIRED 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_CYCLES_IN_SL_WITHOUT_HS_DESIRED 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_CYCLES_IN_SL_WITH_HS_DESIRED 0x00000004 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_TRANSITION_HS_TO_SL 0x00000005 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_ENABLE 3:3 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HW_FILTER_SINGLE_LANE_FILTER_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_LO_FILTER(i) (0x00001d3c+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_LO_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_LO_FILTER_ADDRESSFILTER 31:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_LO_FILTER_ADDRESSFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_HI_FILTER(i) (0x00001d40+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_HI_FILTER__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_HI_FILTER_ADDRESSFILTER 31:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_HI_FILTER_ADDRESSFILTER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_LO_MASK(i) (0x00001d44+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_LO_MASK__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_LO_MASK_ADDRESSMASK 31:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_LO_MASK_ADDRESSMASK_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_HI_MASK(i) (0x00001d48+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_HI_MASK__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_HI_MASK_ADDRESSMASK 31:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ADDR_HI_MASK_ADDRESSMASK_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_LO(i) (0x00001d4c+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_LO__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_LO_COUNT 31:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_LO_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI(i) (0x00001d50+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_COUNT 30:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_COUNT_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER 31:31 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_HI_ROLLOVER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CAPTURE_LO(i) (0x00001d54+(i)*0x54) /* R--4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CAPTURE_LO__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CAPTURE_LO_COUNTER 31:0 /* R-DVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CAPTURE_LO_COUNTER_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CAPTURE_HI(i) (0x00001d58+(i)*0x54) /* R--4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CAPTURE_HI__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CAPTURE_HI_COUNTER 31:0 /* R-DVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_CAPTURE_HI_COUNTER_INIT 0x00000000 /* R-D-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ILA_CTRL(i) (0x00001d5c+(i)*0x54) /* RW-4A */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ILA_CTRL__SIZE_1 4 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRIGGER 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRIGGER_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRACE 9:8 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRACE_NO_CAPTURE 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRACE_CAPTURE_HEADER 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRACE_CAPTURE_PACKET 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_TP_CNTR_ILA_CTRL_TRACE_RESERVED 0x00000003 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_CTRL 0x00001e80 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_CTRL__PRIV_LEVEL_MASK 0x00001810 /* */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_CTRL_ENABLE 0:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_CTRL_ENABLE_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_0 0x00001e84 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_0_RESERVED 31:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_0_RESERVED_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_1 0x00001e88 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_1_RESERVED 31:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_1_RESERVED_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_2 0x00001e8c /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_2_RESERVED 31:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_2_RESERVED_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_3 0x00001e90 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_3_RESERVED 31:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_3_RESERVED_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_4 0x00001e94 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_4_RESERVED 31:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_4_RESERVED_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_5 0x00001e98 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_5_RESERVED 31:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_5_RESERVED_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_6 0x00001e9c /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_6_RESERVED 31:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_6_RESERVED_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_7 0x00001ea0 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_7_RESERVED 31:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_7_RESERVED_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_8 0x00001ea4 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_8_PARSESTPTR 3:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_8_PARSESTPTR_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9 0x00001ea8 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST0 3:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST0_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST1 7:4 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST1_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST2 11:8 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST2_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST3 15:12 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST3_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST4 19:16 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST4_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST5 23:20 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST5_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST6 27:24 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST6_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST7 31:28 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_9_PARSEST7_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10 0x00001eac /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST8 3:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST8_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST9 7:4 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST9_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST10 11:8 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST10_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST11 15:12 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST11_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST12 19:16 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST12_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST13 23:20 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST13_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST14 27:24 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST14_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST15 31:28 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_10_PARSEST15_INIT 0x0000000f /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12 0x00001eb0 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY7 3:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY7_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY6 7:4 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY6_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY5 11:8 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY5_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY4 15:12 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY4_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY3 19:16 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY3_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY2 23:20 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY2_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY1 27:24 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY1_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY0 31:28 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_12_STICKYENTRY0_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13 0x00001eb4 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY7 3:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY7_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY6 7:4 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY6_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY5 11:8 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY5_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY4 15:12 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY4_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY3 19:16 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY3_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY2 23:20 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY2_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY1 27:24 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY1_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY0 31:28 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_13_STICKYENTRY0_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14 0x00001eb8 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY7 3:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY7_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY6 7:4 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY6_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY5 11:8 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY5_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY4 15:12 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY4_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY3 19:16 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY3_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY2 23:20 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY2_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY1 27:24 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY1_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY0 31:28 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_14_STICKYENTRY0_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_16 0x00001ebc /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_16_VC0STICKYPTR 3:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_16_VC0STICKYPTR_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_16_VC1STICKYPTR 11:8 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_16_VC1STICKYPTR_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_16_VC2STICKYPTR 19:16 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_MISC_16_VC2STICKYPTR_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_CTRL 0x00001ec0 /* RW-4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_CTRL_VC 3:0 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_CTRL_VC_REQUEST 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_CTRL_VC_DOWNGRADE 0x00000001 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_CTRL_VC_PROBE 0x00000002 /* RW--V */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_CTRL_ENTRY 19:16 /* RWDVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_CTRL_ENTRY_INIT 0x00000000 /* RWD-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_RA 0x00001ec4 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_RA_REQATTR 31:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_RA_REQATTR_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_UA 0x00001ec8 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_UA_UA 10:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_UA_UA_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_UA_ADDRTYPE 17:11 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_UA_ADDRTYPE_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_UA_NCR 18:18 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_UA_NCR_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_UA_VCSET 19:19 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_UA_VCSET_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_UA_REQATTR35TO32 23:20 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_UA_REQATTR35TO32_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_REQCONTEXT 0x00001ecc /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_REQCONTEXT_REQCONTEXT 15:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_REQCONTEXT_REQCONTEXT_INIT 0x00000000 /* R-E-V */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_SA 0x00001ed0 /* R--4R */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_SA_SA 28:0 /* R-EVF */
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#define NV_NVLTLC_RX_LNK_DEBUG_STICKY_SA_SA_INIT 0x00000000 /* R-E-V */
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#endif // __ga102_dev_nvltlc_ip_h__
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