511 lines
44 KiB
C
511 lines
44 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_master_h__
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#define __ga102_dev_master_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PMC 0x00000fff:0x00000000 /* RW--D */
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#define NV_PMC_BOOT_0 0x00000000 /* R--4R */
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#define NV_PMC_BOOT_0_ID 31:0 /* */
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#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* R--VF */
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#define NV_PMC_BOOT_0_MINOR_REVISION_1 0x00000001 /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_2 0x00000002 /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_3 0x00000003 /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_4 0x00000004 /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_5 0x00000005 /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_6 0x00000006 /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_7 0x00000007 /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_8 0x00000008 /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_9 0x00000009 /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_10 0x0000000A /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_11 0x0000000B /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_12 0x0000000C /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_13 0x0000000D /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_14 0x0000000E /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_15 0x0000000F /* R---V */
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#define NV_PMC_BOOT_0_MINOR_REVISION_INIT 0x00000001 /* R---V */
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#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* R--VF */
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#define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x0000000A /* R---V */
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#define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x0000000B /* R---V */
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#define NV_PMC_BOOT_0_MAJOR_REVISION_C 0x0000000C /* R---V */
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#define NV_PMC_BOOT_0_MAJOR_REVISION_D 0x0000000D /* R---V */
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#define NV_PMC_BOOT_0_MAJOR_REVISION_E 0x0000000E /* R---V */
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#define NV_PMC_BOOT_0_MAJOR_REVISION_F 0x0000000F /* R---V */
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#define NV_PMC_BOOT_0_MAJOR_REVISION_INIT 0x00000000 /* R---V */
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#define NV_PMC_BOOT_0_RESERVED_0 11:8 /* */
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#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 /* R--VF */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_0 0x00000000 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_1 0x00000001 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_2 0x00000002 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_3 0x00000003 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_4 0x00000004 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_5 0x00000005 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_6 0x00000006 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_7 0x00000007 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_8 0x00000008 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_9 0x00000009 /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_A 0x0000000A /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0x0000000B /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_C 0x0000000C /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_D 0x0000000D /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_E 0x0000000E /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_F 0x0000000F /* R---V */
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#define NV_PMC_BOOT_0_IMPLEMENTATION_INIT 0x00000000 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 /* R--VF */
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#define NV_PMC_BOOT_0_ARCHITECTURE_NV10 0x00000001 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_NV20 0x00000002 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_NV30 0x00000003 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_NV40 0x00000004 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_NV50 0x00000005 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_NV60 0x00000006 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_NV70 0x00000007 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_NV80 0x00000008 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_G80 0x00000008 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_NV90 0x00000009 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_G90 0x00000009 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_NV100 0x0000000A /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_G100 0x0000000A /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GF100 0x0000000C /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GF110 0x0000000D /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GK100 0x0000000E /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GK110 0x0000000F /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GK200 0x00000010 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GM000 0x00000011 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GM100 0x00000011 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GM200 0x00000012 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GP100 0x00000013 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GV100 0x00000014 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GV110 0x00000015 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_TU100 0x00000016 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_TU110 0x00000016 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_LR10 0x00000016 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 0x00000017 /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_G000 0x0000001E /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_AMODEL 0x0000001F /* R---V */
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#define NV_PMC_BOOT_0_ARCHITECTURE_INIT 0x00000000 /* R---V */
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#define NV_PMC_BOOT_0_FOUNDRY 31:29 /* R--VF */
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#define NV_PMC_BOOT_0_FOUNDRY_TSMC 0x00000000 /* R---V */
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#define NV_PMC_BOOT_0_FOUNDRY_UMC 0x00000001 /* R---V */
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#define NV_PMC_BOOT_0_FOUNDRY_IBM 0x00000002 /* R---V */
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#define NV_PMC_BOOT_0_FOUNDRY_SMIC 0x00000003 /* R---V */
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#define NV_PMC_BOOT_0_FOUNDRY_CHARTERED 0x00000004 /* R---V */
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#define NV_PMC_BOOT_0_FOUNDRY_SEC 0x00000005 /* R---V */
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#define NV_PMC_BOOT_0_FOUNDRY_SONY 0x00000006 /* R---V */
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#define NV_PMC_BOOT_0_FOUNDRY_TOSHIBA 0x00000007 /* R---V */
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#define NV_PMC_BOOT_0_FOUNDRY_INIT 5 /* R---V */
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#define NV_PMC_BOOT_1 0x00000004 /* C--4R */
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#define NV_PMC_BOOT_1_VGPU8 8:8 /* C--VF */
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#define NV_PMC_BOOT_1_VGPU8_REAL 0x00000000 /* C---V */
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#define NV_PMC_BOOT_1_VGPU8_VIRTUAL 0x00000001 /* ----V */
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#define NV_PMC_BOOT_1_VGPU16 16:16 /* */
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#define NV_PMC_BOOT_1_VGPU16_REAL 0x00000000 /* */
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#define NV_PMC_BOOT_1_VGPU16_VIRTUAL 0x00000001 /* */
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#define NV_PMC_BOOT_1_VGPU 17:16 /* C--VF */
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#define NV_PMC_BOOT_1_VGPU_REAL 0x00000000 /* C---V */
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#define NV_PMC_BOOT_1_VGPU_PV 0x00000001 /* ----V */
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#define NV_PMC_BOOT_1_VGPU_VF 0x00000002 /* ----V */
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#define NV_PMC_BOOT_2 0x00000008 /* R--4R */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION 3:0 /* R-XVF */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_0 0x00000000 /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_1 0x00000001 /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_2 0x00000002 /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_3 0x00000003 /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_4 0x00000004 /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_5 0x00000005 /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_6 0x00000006 /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_7 0x00000007 /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_8 0x00000008 /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_9 0x00000009 /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_A 0x0000000A /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_B 0x0000000B /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_C 0x0000000C /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_D 0x0000000D /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_E 0x0000000E /* R---V */
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#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_F 0x0000000F /* R---V */
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#define NV_PMC_BOOT_2_FAB_ID 7:4 /* R-XVF */
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#define NV_PMC_BOOT_2_FAB_ID_0 0x00000000 /* R---V */
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#define NV_PMC_BOOT_2_FAB_ID_1 0x00000001 /* R---V */
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#define NV_PMC_BOOT_2_FAB_ID_2 0x00000002 /* R---V */
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#define NV_PMC_BOOT_2_FAB_ID_3 0x00000003 /* R---V */
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#define NV_PMC_BOOT_2_EMULATION 31:31 /* R-XVF */
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#define NV_PMC_BOOT_2_EMULATION_NO 0x00000000 /* R---V */
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#define NV_PMC_BOOT_2_EMULATION_YES 0x00000001 /* R---V */
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#define NV_PMC_BOOT_42 0x00000A00 /* R--4R */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION 11:8 /* R-XVF */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_0 0x00000000 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_1 0x00000001 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_2 0x00000002 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_3 0x00000003 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_4 0x00000004 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_5 0x00000005 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_6 0x00000006 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_7 0x00000007 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_8 0x00000008 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_9 0x00000009 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_A 0x0000000A /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_B 0x0000000B /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_C 0x0000000C /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_D 0x0000000D /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_E 0x0000000E /* R---V */
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#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_F 0x0000000F /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION 15:12 /* R-XVF */
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#define NV_PMC_BOOT_42_MINOR_REVISION_1 0x00000001 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_2 0x00000002 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_3 0x00000003 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_4 0x00000004 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_5 0x00000005 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_6 0x00000006 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_7 0x00000007 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_8 0x00000008 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_9 0x00000009 /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_10 0x0000000A /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_11 0x0000000B /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_12 0x0000000C /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_13 0x0000000D /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_14 0x0000000E /* R---V */
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#define NV_PMC_BOOT_42_MINOR_REVISION_15 0x0000000F /* R---V */
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#define NV_PMC_BOOT_42_MAJOR_REVISION 19:16 /* R-XVF */
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#define NV_PMC_BOOT_42_MAJOR_REVISION_A 0x0000000A /* R---V */
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#define NV_PMC_BOOT_42_MAJOR_REVISION_B 0x0000000B /* R---V */
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#define NV_PMC_BOOT_42_MAJOR_REVISION_C 0x0000000C /* R---V */
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#define NV_PMC_BOOT_42_MAJOR_REVISION_D 0x0000000D /* R---V */
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#define NV_PMC_BOOT_42_MAJOR_REVISION_E 0x0000000E /* R---V */
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#define NV_PMC_BOOT_42_MAJOR_REVISION_F 0x0000000F /* R---V */
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#define NV_PMC_BOOT_42_IMPLEMENTATION 23:20 /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_0 0x00000000 /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_1 0x00000001 /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_2 0x00000002 /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_3 0x00000003 /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_4 0x00000004 /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_5 0x00000005 /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_6 0x00000006 /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_7 0x00000007 /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_8 0x00000008 /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_9 0x00000009 /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_A 0x0000000A /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_B 0x0000000B /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_C 0x0000000C /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_D 0x0000000D /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_E 0x0000000E /* */
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#define NV_PMC_BOOT_42_IMPLEMENTATION_F 0x0000000F /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE 28:24 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_NV10 0x00000001 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_NV20 0x00000002 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_NV30 0x00000003 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_NV40 0x00000004 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_NV50 0x00000005 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_NV60 0x00000006 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_NV70 0x00000007 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_NV80 0x00000008 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_G80 0x00000008 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_NV90 0x00000009 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_G90 0x00000009 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_NV100 0x0000000A /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_G100 0x0000000A /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_GF100 0x0000000C /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_GF110 0x0000000D /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_GK100 0x0000000E /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_GK110 0x0000000F /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_GK200 0x00000010 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_GM000 0x00000011 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_GM100 0x00000011 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_GM200 0x00000012 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_GP100 0x00000013 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_GV100 0x00000014 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_GV110 0x00000015 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_TU100 0x00000016 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_LR10 0x00000016 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_GA100 0x00000017 /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_G000 0x0000001E /* */
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#define NV_PMC_BOOT_42_ARCHITECTURE_AMODEL 0x0000001F /* */
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#define NV_PMC_BOOT_42_CHIP_ID 28:20 /* R-XVF */
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#define NV_PMC_BOOT_42_CHIP_ID_G94 0x00000094 /* R---V */
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#define NV_PMC_BOOT_42_CHIP_ID_G98 0x00000098 /* R---V */
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#define NV_PMC_BOOT_42_CHIP_ID_GT200 0x000000A0 /* R---V */
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#define NV_PMC_BOOT_42_CHIP_ID_GT206 0x000000A6 /* R---V */
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#define NV_PMC_BOOT_42_CHIP_ID_IGT206 0x000000A7 /* R---V */
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#define NV_PMC_BOOT_42_CHIP_ID_GT212 0x000000A2 /* R---V */
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#define NV_PMC_BOOT_42_CHIP_ID_IGT209 0x000000A9 /* R---V */
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#define NV_PMC_BOOT_42_CHIP_ID_GT214 0x000000A4 /* R---V */
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#define NV_PMC_BOOT_42_CHIP_ID_GT215 0x000000A3 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GT216 0x000000A5 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GT218 0x000000A8 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GF100 0x000000C0 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GF104 0x000000C4 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GF105 0x000000C5 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GF106 0x000000C3 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GF108 0x000000C1 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GF110 0x000000D0 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GF110D 0x000000C6 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GF110F 0x000000C7 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GF112 0x000000D2 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GF114 0x000000D4 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GF116 0x000000D6 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GF117 0x000000D7 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GF118 0x000000D8 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GF119 0x000000D9 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GF11A 0x000000CA /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GK100 0x000000E0 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GK104 0x000000E4 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GK106 0x000000E6 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GK107 0x000000E7 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GK110 0x000000F0 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GK20A 0x000000EA /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GK207 0x00000107 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GK208 0x00000108 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GK209 0x00000109 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GM000 0x00000110 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GM107 0x00000117 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GM108 0x00000118 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GM109 0x00000119 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GM20C 0x0000011C /* R---V */
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#define NV_PMC_BOOT_42_CHIP_ID_GM20B 0x0000012B /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GM20D 0x0000012D /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GM104 0x00000114 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GM204 0x00000124 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GM206 0x00000126 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GM200 0x00000120 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GP000 0x00000131 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GP100 0x00000130 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GP102 0x00000132 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GP104 0x00000134 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GP104V 0x00000139 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GP106 0x00000136 /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GP107F 0x00000133 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GP107 0x00000137 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GP108 0x00000138 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GP108V 0x0000013A /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GP10B 0x0000013B /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GP10D 0x0000013D /* R---V */
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|
#define NV_PMC_BOOT_42_CHIP_ID_GV100 0x00000140 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GV000 0x00000141 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GV100F 0x0000014F /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GV10B 0x0000014B /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GV11B 0x0000015B /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_TU100 0x00000160 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_TU101 0x00000160 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_LR10 0x00000160 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_TU000 0x00000161 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_TU102 0x00000162 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_TU104 0x00000164 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_TU105 0x00000165 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_TU106 0x00000166 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_TU107 0x00000167 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_TU117 0x00000167 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_TU116 0x00000168 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GA100 0x00000170 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GA000 0x00000171 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GA101 0x00000171 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GA102 0x00000172 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GA102F 0x0000017F /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GA103 0x00000173 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GA104 0x00000174 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GA106 0x00000176 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GA107 0x00000177 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_GA114 0x00000179 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_G000 0x000001E0 /* R---V */
|
|
#define NV_PMC_BOOT_42_CHIP_ID_G000_SOC 0x000001E1 /* R---V */
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|
#define NV_PMC_BOOT_42_RSVD 31:29 /* */
|
|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK 0x00000080 /* RW-4R */
|
|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmc_host_grp0" /* */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLE_FUSE0 15 /* RWI-V */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE_FUSE1 8 /* RW--V */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */
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#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */
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#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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|
#define NV_PMC_GRP0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK 0x00000084 /* RW-4R */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
|
|
#define NV_PMC_DEVICE_ENABLE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
|
|
#define NV_PMC_VIRTUAL_BOOT_1 0x00000090 /* C--4R */
|
|
#define NV_PMC_VIRTUAL_BOOT_1_VGPU 17:16 /* C--VF */
|
|
#define NV_PMC_VIRTUAL_BOOT_1_VGPU_REAL 0x00000000 /* ----V */
|
|
#define NV_PMC_VIRTUAL_BOOT_1_VGPU_PV 0x00000001 /* ----V */
|
|
#define NV_PMC_VIRTUAL_BOOT_1_VGPU_VF 0x00000002 /* C---V */
|
|
#define NV_PMC_INTR_LTC 0x000001C0 /* R--4R */
|
|
#define NV_PMC_INTR_LTC_PART_MASK 31:0 /* R--VF */
|
|
#define NV_PMC_INTR_LTC_PART_MASK_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PMC_INTR_LTC_PART_MASK_PENDING 0x00000001 /* R---V */
|
|
#define NV_PMC_INTR_LTC_PART(i) (i):(i) /* */
|
|
#define NV_PMC_INTR_LTC_PART__SIZE_1 32 /* */
|
|
#define NV_PMC_INTR_LTC_PART_NOT_PENDING 0x00000000 /* */
|
|
#define NV_PMC_INTR_LTC_PART_PENDING 0x00000001 /* */
|
|
#define NV_PMC_INTR_FBPA 0x000001D0 /* R--4R */
|
|
#define NV_PMC_INTR_FBPA_PART_MASK 29:0 /* R--VF */
|
|
#define NV_PMC_INTR_FBPA_PART_MASK_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PMC_INTR_FBPA_PART_MASK_PENDING 0x00000001 /* R---V */
|
|
#define NV_PMC_INTR_FBPA_FBFALCON_INTR_NOSTALL 30:30 /* R--VF */
|
|
#define NV_PMC_INTR_FBPA_FBFALCON_INTR_NOSTALL_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PMC_INTR_FBPA_FBFALCON_INTR_NOSTALL_PENDING 0x00000001 /* R---V */
|
|
#define NV_PMC_INTR_FBPA_FBFALCON_INTR_STALL 31:31 /* R--VF */
|
|
#define NV_PMC_INTR_FBPA_FBFALCON_INTR_STALL_NOT_PENDING 0x00000000 /* R---V */
|
|
#define NV_PMC_INTR_FBPA_FBFALCON_INTR_STALL_PENDING 0x00000001 /* R---V */
|
|
#define NV_PMC_INTR_FBPA_PART(i) (i):(i) /* */
|
|
#define NV_PMC_INTR_FBPA_PART__SIZE_1 30 /* */
|
|
#define NV_PMC_INTR_FBPA_PART_NOT_PENDING 0x00000000 /* */
|
|
#define NV_PMC_INTR_FBPA_PART_PENDING 0x00000001 /* */
|
|
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
|
|
#define NV_PMC_ENABLE_DEVICE(i) (i):(i) /* */
|
|
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
|
|
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
|
|
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
|
|
#define NV_PMC_ENABLE_PMEDIA 4:4 /* */
|
|
#define NV_PMC_ENABLE_PMEDIA_DISABLED 0x00000000 /* */
|
|
#define NV_PMC_ENABLE_PMEDIA_ENABLED 0x00000001 /* */
|
|
#define NV_PMC_ENABLE_PWR 13:13 /* */
|
|
#define NV_PMC_ENABLE_PWR_DISABLED 0x00000000 /* */
|
|
#define NV_PMC_ENABLE_PWR_ENABLED 0x00000001 /* */
|
|
#define NV_PMC_ENABLE_NVLINK 25:25 /* RWIVF */
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#define NV_PMC_ENABLE_NVLINK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PMC_ENABLE_NVLINK_ENABLED 0x00000001 /* RW--V */
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#define NV_PMC_ENABLE_ZPW 26:26 /* RWIVF */
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#define NV_PMC_ENABLE_ZPW_DISABLED 0x00000000 /* RWI-V */
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#define NV_PMC_ENABLE_ZPW_ENABLED 0x00000001 /* RW--V */
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#define NV_PMC_ENABLE_PERFMON 28:28 /* RWIVF */
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#define NV_PMC_ENABLE_PERFMON_DISABLED 0x00000000 /* RWI-V */
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#define NV_PMC_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */
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#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
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#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
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#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
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#define NV_PMC_ENABLE_SEC 1:1 /* */
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#define NV_PMC_ENABLE_SEC_DISABLED 0x00000000 /* */
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#define NV_PMC_ENABLE_SEC_ENABLED 0x00000001 /* */
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#define NV_PMC_ENABLE_NVDEC 15:15 /* */
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#define NV_PMC_ENABLE_NVDEC_DISABLED 0x00000000 /* */
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#define NV_PMC_ENABLE_NVDEC_ENABLED 0x00000001 /* */
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#define NV_PMC_ELPG_ENABLE 0x0000020C /* RW-4R */
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#define NV_PMC_ELPG_ENABLE__PRIV_LEVEL_MASK 0x00000080 /* */
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#define NV_PMC_ELPG_ENABLE_DEVICE(i) (i):(i) /* */
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#define NV_PMC_ELPG_ENABLE_DEVICE__SIZE_1 32 /* */
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#define NV_PMC_ELPG_ENABLE_DEVICE_DISABLE 0x00000000 /* */
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#define NV_PMC_ELPG_ENABLE_DEVICE_ENABLE 0x00000001 /* */
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#define NV_PMC_ELPG_ENABLE_XBAR 2:2 /* RWIVF */
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#define NV_PMC_ELPG_ENABLE_XBAR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PMC_ELPG_ENABLE_XBAR_ENABLED 0x00000001 /* RW--V */
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#define NV_PMC_ELPG_ENABLE_L2 3:3 /* RWIVF */
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#define NV_PMC_ELPG_ENABLE_L2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PMC_ELPG_ENABLE_L2_ENABLED 0x00000001 /* RW--V */
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#define NV_PMC_ELPG_ENABLE_HUB 29:29 /* RWIVF */
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#define NV_PMC_ELPG_ENABLE_HUB_DISABLED 0x00000000 /* RWI-V */
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#define NV_PMC_ELPG_ENABLE_HUB_ENABLED 0x00000001 /* RW--V */
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#define NV_PMC_DEVICE_ENABLE(i) (0x000000600+(i)*4) /* RW-4A */
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#define NV_PMC_DEVICE_ENABLE__SIZE_1 1 /* */
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#define NV_PMC_DEVICE_ENABLE__PRIV_LEVEL_MASK 0x00000084 /* */
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#define NV_PMC_DEVICE_ENABLE_STATUS 31:0 /* RWIVF */
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#define NV_PMC_DEVICE_ENABLE_STATUS_DISABLE_ALL 0x00000000 /* RWI-V */
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#define NV_PMC_DEVICE_ENABLE_STATUS_BIT(i) (i):(i) /* */
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#define NV_PMC_DEVICE_ENABLE_STATUS_BIT__SIZE_1 26 /* */
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#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_DISABLE 0x00000000 /* */
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#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_ENABLE 0x00000001 /* */
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#define NV_PMC_DEVICE_ELPG_ENABLE(i) (0x000000700+(i)*4) /* RW-4A */
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#define NV_PMC_DEVICE_ELPG_ENABLE__SIZE_1 1 /* */
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#define NV_PMC_DEVICE_ELPG_ENABLE__PRIV_LEVEL_MASK 0x00000084 /* */
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#define NV_PMC_DEVICE_ELPG_ENABLE_STATUS 31:0 /* RWIVF */
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#define NV_PMC_DEVICE_ELPG_ENABLE_STATUS_ENABLE_ALL 0xFFFFFFFF /* RWI-V */
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#define NV_PMC_DEVICE_ELPG_ENABLE_STATUS_BIT(i) (i):(i) /* */
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#define NV_PMC_DEVICE_ELPG_ENABLE_STATUS_BIT__SIZE_1 26 /* */
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#define NV_PMC_DEVICE_ELPG_ENABLE_STATUS_BIT_DISABLE 0x00000000 /* */
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#define NV_PMC_DEVICE_ELPG_ENABLE_STATUS_BIT_ENABLE 0x00000001 /* */
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#define NV_PMC_PRI_PMC_CG1 0x00000800 /* RW-4R */
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#define NV_PMC_PRI_PMC_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_PMC_PRI_PMC_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PMC_PRI_PMC_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_PMC_PRI_PMC_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
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#define NV_PMC_PRI_PMC_CG1_SLCG 1:1 /* RWIVF */
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#define NV_PMC_PRI_PMC_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_PMC_PRI_PMC_CG1_SLCG_DISABLED 0x00000001 /* RWI-V */
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#define NV_PMC_PRI_PMC_CG1_SLCG__PROD 0x00000001 /* RW--V */
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#endif // __ga102_dev_master_h__
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