12679 lines
1.3 MiB
12679 lines
1.3 MiB
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_fuse_h__
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#define __ga102_dev_fuse_h__
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/* This file is autogenerated. Do not edit */
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#define NV_FUSE 0x00825fff:0x00820000 /* RW--D */
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#define NV_FUSE_FUSECTRL 0x00820000 /* RW-4R */
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#define NV_FUSE_FUSECTRL__PRIV_LEVEL_MASK 0x008200F8 /* */
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#define NV_FUSE_FUSECTRL_CMD 1:0 /* -WIVF */
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#define NV_FUSE_FUSECTRL_CMD_IDLE 0x00000000 /* -WI-V */
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#define NV_FUSE_FUSECTRL_CMD_READ 0x00000001 /* -W--V */
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#define NV_FUSE_FUSECTRL_CMD_WRITE 0x00000002 /* -W--V */
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#define NV_FUSE_FUSECTRL_CMD_SENSE_CTRL 0x00000003 /* -W--V */
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#define NV_FUSE_FUSECTRL_STATE 20:16 /* R--VF */
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#define NV_FUSE_FUSECTRL_STATE_RESET 0x00000000 /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_POST_RESET 0x00000001 /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_LOAD_ROW0 0x00000002 /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_LOAD_ROW1 0x00000003 /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_IDLE 0x00000004 /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_READ_SETUP 0x00000005 /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_READ_STROBE 0x00000006 /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_SAMPLE_FUSES 0x00000007 /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_READ_HOLD 0x00000008 /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_FUSE_SRC_SETUP 0x00000009 /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_WRITE_SETUP 0x0000000A /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_WRITE_ADDR_SETUP 0x0000000B /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_WRITE_PROGRAM 0x0000000C /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_WRITE_ADDR_HOLD 0x0000000D /* R---V */
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#define NV_FUSE_FUSECTRL_STATE_FUSE_SRC_HOLD 0x0000000E /* R---V */
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#define NV_FUSE_FUSECTRL_FUSE_INIT_SENSE_DONE 29:29 /* R--VF */
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#define NV_FUSE_FUSECTRL_FUSE_INIT_SENSE_DONE_NO 0x00000000 /* R---V */
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#define NV_FUSE_FUSECTRL_FUSE_INIT_SENSE_DONE_YES 0x00000001 /* R---V */
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#define NV_FUSE_FUSECTRL_FUSE_SENSE_DONE 30:30 /* R--VF */
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#define NV_FUSE_FUSECTRL_FUSE_SENSE_DONE_NO 0x00000000 /* R---V */
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#define NV_FUSE_FUSECTRL_FUSE_SENSE_DONE_YES 0x00000001 /* R---V */
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#define NV_FUSE_FUSECTRL_RECORD_SHIFT_DONE 31:31 /* R--VF */
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#define NV_FUSE_FUSECTRL_RECORD_SHIFT_DONE_NO 0x00000000 /* R---V */
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#define NV_FUSE_FUSECTRL_RECORD_SHIFT_DONE_YES 0x00000001 /* R---V */
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#define NV_FUSE_FUSEADDR 0x00820004 /* RW-4R */
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#define NV_FUSE_FUSEADDR__PRIV_LEVEL_MASK 0x008200F8 /* */
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#define NV_FUSE_FUSEADDR_VLDFLD 9:0 /* RWIVF */
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#define NV_FUSE_FUSEADDR_VLDFLD_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_FUSERDATA 0x00820008 /* R--4R */
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#define NV_FUSE_FUSERDATA__PRIV_LEVEL_MASK 0x008200F8 /* */
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#define NV_FUSE_FUSERDATA_DATA 31:0 /* R-IVF */
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#define NV_FUSE_FUSERDATA_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_FUSEWDATA 0x0082000C /* -W-4R */
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#define NV_FUSE_FUSEWDATA__PRIV_LEVEL_MASK 0x008200F4 /* */
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#define NV_FUSE_FUSEWDATA_DATA 31:0 /* -WIVF */
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#define NV_FUSE_FUSEWDATA_DATA_INIT 0x00000000 /* -WI-V */
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#define NV_FUSE_FUSETIME_RD1 0x00820010 /* RW-4R */
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#define NV_FUSE_FUSETIME_RD1__PRIV_LEVEL_MASK 0x008200E4 /* */
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#define NV_FUSE_FUSETIME_RD1_TSUR_MAX 7:0 /* RWIVF */
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#define NV_FUSE_FUSETIME_RD1_TSUR_MAX_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_FUSETIME_RD1_TSUR_MAX_WIDTH 8 /* */
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#define NV_FUSE_FUSETIME_RD1_TSUR_FUSEOUT 15:8 /* RWIVF */
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#define NV_FUSE_FUSETIME_RD1_TSUR_FUSEOUT_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_FUSETIME_RD1_TSUR_FUSEOUT_WIDTH 8 /* */
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#define NV_FUSE_FUSETIME_RD1_THR_MAX 23:16 /* RWIVF */
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#define NV_FUSE_FUSETIME_RD1_THR_MAX_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_FUSETIME_RD1_THR_MAX_WIDTH 8 /* */
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#define NV_FUSE_FUSETIME_RD2 0x00820014 /* RW-4R */
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#define NV_FUSE_FUSETIME_RD2__PRIV_LEVEL_MASK 0x008200E4 /* */
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#define NV_FUSE_FUSETIME_RD2_TWIDTH_RD 15:0 /* RWIVF */
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#define NV_FUSE_FUSETIME_RD2_TWIDTH_RD_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_FUSETIME_RD2_TWIDTH_RD_WIDTH 16 /* */
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#define NV_FUSE_FUSETIME_PGM1 0x00820018 /* RW-4R */
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#define NV_FUSE_FUSETIME_PGM1__PRIV_LEVEL_MASK 0x008200E4 /* */
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#define NV_FUSE_FUSETIME_PGM1_TSUP_MAX 7:0 /* RWIVF */
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#define NV_FUSE_FUSETIME_PGM1_TSUP_MAX_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_FUSETIME_PGM1_TSUP_MAX_WIDTH 8 /* */
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#define NV_FUSE_FUSETIME_PGM1_TSUP_ADDR 15:8 /* RWIVF */
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#define NV_FUSE_FUSETIME_PGM1_TSUP_ADDR_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_FUSETIME_PGM1_TSUP_ADDR_WIDTH 8 /* */
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#define NV_FUSE_FUSETIME_PGM1_THP_ADDR 23:16 /* RWIVF */
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#define NV_FUSE_FUSETIME_PGM1_THP_ADDR_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_FUSETIME_PGM1_THP_ADDR_WIDTH 8 /* */
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#define NV_FUSE_FUSETIME_PGM1_THP_PS 31:24 /* RWIVF */
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#define NV_FUSE_FUSETIME_PGM1_THP_PS_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_FUSETIME_PGM1_THP_PS_WIDTH 8 /* */
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#define NV_FUSE_FUSETIME_PGM2 0x0082001C /* RW-4R */
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#define NV_FUSE_FUSETIME_PGM2__PRIV_LEVEL_MASK 0x008200E4 /* */
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#define NV_FUSE_FUSETIME_PGM2_TWIDTH_PGM 15:0 /* RWIVF */
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#define NV_FUSE_FUSETIME_PGM2_TWIDTH_PGM_INIT 0x0000010E /* RWI-V */
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#define NV_FUSE_FUSETIME_PGM2_TWIDTH_PGM_WIDTH 16 /* */
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#define NV_FUSE_FUSETIME_PGM2_TSUP_PS 23:16 /* RWIVF */
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#define NV_FUSE_FUSETIME_PGM2_TSUP_PS_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_FUSETIME_PGM2_TSUP_PS_WIDTH 8 /* */
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#define NV_FUSE_PRIV2INTFC 0x00820028 /* RW-4R */
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#define NV_FUSE_PRIV2INTFC__PRIV_LEVEL_MASK 0x008200E0 /* */
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#define NV_FUSE_PRIV2INTFC_START_DATA 0:0 /* RWIVF */
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#define NV_FUSE_PRIV2INTFC_START_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_EN_SW_OVERRIDE 0x00820040 /* RW-4R */
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#define NV_FUSE_EN_SW_OVERRIDE__PRIV_LEVEL_MASK 0x008200F8 /* */
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#define NV_FUSE_EN_SW_OVERRIDE_VAL 0:0 /* RWIUF */
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#define NV_FUSE_EN_SW_OVERRIDE_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_EN_SW_OVERRIDE_VAL_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_EN_SW_OVERRIDE_VAL_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_IFF_RECORD 0x00820050 /* RW-4R */
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#define NV_FUSE_IFF_RECORD__PRIV_LEVEL_MASK 0x008200E0 /* */
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#define NV_FUSE_IFF_RECORD_START 9:0 /* RWIVF */
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#define NV_FUSE_IFF_RECORD_START_NONE 0x00000000 /* RWI-V */
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#define NV_FUSE_IFF_RECORD_START_WIDTH 10 /* */
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#define NV_FUSE_IFF_RECORD_LAST 25:16 /* RWIVF */
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#define NV_FUSE_IFF_RECORD_LAST_NONE 0x00000000 /* RWI-V */
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#define NV_FUSE_IFF_RECORD_LAST_WIDTH 10 /* */
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#define NV_FUSE_FUSETESTRDATA 0x0082005C /* R--4R */
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#define NV_FUSE_FUSETESTRDATA__PRIV_LEVEL_MASK 0x008200F8 /* */
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#define NV_FUSE_FUSETESTRDATA_DATA 1:0 /* R-IVF */
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#define NV_FUSE_FUSETESTRDATA_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_DEBUGCTRL 0x00820060 /* RW-4R */
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#define NV_FUSE_DEBUGCTRL__PRIV_LEVEL_MASK 0x008200E0 /* */
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#define NV_FUSE_DEBUGCTRL_MARGIN_READ 0:0 /* RWIVF */
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#define NV_FUSE_DEBUGCTRL_MARGIN_READ_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_DEBUGCTRL_MARGIN_READ_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_MARGIN_READ_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_TRCS 2:2 /* RWIVF */
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#define NV_FUSE_DEBUGCTRL_TRCS_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_DEBUGCTRL_TRCS_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_TRCS_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_AT1 3:3 /* RWIVF */
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#define NV_FUSE_DEBUGCTRL_AT1_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_DEBUGCTRL_AT1_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_AT1_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_AT0 4:4 /* RWIVF */
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#define NV_FUSE_DEBUGCTRL_AT0_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_DEBUGCTRL_AT0_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_AT0_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_SKIP_RECORDS_DATA 7:7 /* RWIVF */
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#define NV_FUSE_DEBUGCTRL_SKIP_RECORDS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_DEBUGCTRL_RESENSE_NORMAL_DATA 11:11 /* RWIVF */
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#define NV_FUSE_DEBUGCTRL_RESENSE_NORMAL_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_DEBUGCTRL_RESENSE_FPF_DATA 12:12 /* RWIVF */
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#define NV_FUSE_DEBUGCTRL_RESENSE_FPF_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_DEBUGCTRL_RESENSE_RECORD_DATA 13:13 /* RWIVF */
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#define NV_FUSE_DEBUGCTRL_RESENSE_RECORD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_DEBUGCTRL_RESENSE_KFUSE_DATA 14:14 /* RWIVF */
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#define NV_FUSE_DEBUGCTRL_RESENSE_KFUSE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_DEBUGCTRL_PMARGIN_READ 16:15 /* RWIVF */
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#define NV_FUSE_DEBUGCTRL_PMARGIN_READ_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_DEBUGCTRL_PMARGIN_READ_00 0x00000000 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_PMARGIN_READ_01 0x00000001 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_PMARGIN_READ_10 0x00000002 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_PMARGIN_READ_11 0x00000003 /* RW--V */
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#define NV_FUSE_SPARE_ADDR_START 0x00820068 /* R--4R */
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#define NV_FUSE_SPARE_ADDR_START__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_ADDR_START_DATA 31:0 /* R-IVF */
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#define NV_FUSE_SPARE_ADDR_START_DATA_INIT 0x008243B8 /* R-I-V */
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#define NV_FUSE_SPARE_ENDIS_ADDR_START 0x0082006C /* R--4R */
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#define NV_FUSE_SPARE_ENDIS_ADDR_START__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_ENDIS_ADDR_START_DATA 31:0 /* R-IVF */
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#define NV_FUSE_SPARE_ENDIS_ADDR_START_DATA_INIT 0x00824528 /* R-I-V */
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#define NV_FUSE_CRC_STATUS 0x00820070 /* R--4R */
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#define NV_FUSE_CRC_STATUS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_CRC_STATUS_H0 2:0 /* R-IVF */
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#define NV_FUSE_CRC_STATUS_H0_CRC_NOT_PARSED_YET 0x00000000 /* R-I-V */
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#define NV_FUSE_CRC_STATUS_H0_CRC_NOT_PRESENT 0x00000004 /* R---V */
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#define NV_FUSE_CRC_STATUS_H0_CRC_PRESENT_NO_ERRORS 0x00000005 /* R---V */
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#define NV_FUSE_CRC_STATUS_H0_CRC_PRESENT_CORRECTED_ERRORS 0x00000006 /* R---V */
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#define NV_FUSE_CRC_STATUS_H0_CRC_PRESENT_UNCORRECTED_ERRORS 0x00000007 /* R---V */
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#define NV_FUSE_CRC_STATUS_H1 6:4 /* R-IVF */
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#define NV_FUSE_CRC_STATUS_H1_CRC_NOT_PARSED_YET 0x00000000 /* R-I-V */
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#define NV_FUSE_CRC_STATUS_H1_CRC_NOT_PRESENT 0x00000004 /* R---V */
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#define NV_FUSE_CRC_STATUS_H1_CRC_PRESENT_NO_ERRORS 0x00000005 /* R---V */
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#define NV_FUSE_CRC_STATUS_H1_CRC_PRESENT_CORRECTED_ERRORS 0x00000006 /* R---V */
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#define NV_FUSE_CRC_STATUS_H1_CRC_PRESENT_UNCORRECTED_ERRORS 0x00000007 /* R---V */
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#define NV_FUSE_CRC_STATUS_H2 10:8 /* R-IVF */
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#define NV_FUSE_CRC_STATUS_H2_CRC_NOT_PARSED_YET 0x00000000 /* R-I-V */
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#define NV_FUSE_CRC_STATUS_H2_CRC_NOT_PRESENT 0x00000004 /* R---V */
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#define NV_FUSE_CRC_STATUS_H2_CRC_PRESENT_NO_ERRORS 0x00000005 /* R---V */
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#define NV_FUSE_CRC_STATUS_H2_CRC_PRESENT_CORRECTED_ERRORS 0x00000006 /* R---V */
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#define NV_FUSE_CRC_STATUS_H2_CRC_PRESENT_UNCORRECTED_ERRORS 0x00000007 /* R---V */
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#define NV_FUSE_CRC_STATUS_H3 14:12 /* R-IVF */
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#define NV_FUSE_CRC_STATUS_H3_CRC_NOT_PARSED_YET 0x00000000 /* R-I-V */
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#define NV_FUSE_CRC_STATUS_H3_CRC_NOT_PRESENT 0x00000004 /* R---V */
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#define NV_FUSE_CRC_STATUS_H3_CRC_PRESENT_NO_ERRORS 0x00000005 /* R---V */
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#define NV_FUSE_CRC_STATUS_H3_CRC_PRESENT_CORRECTED_ERRORS 0x00000006 /* R---V */
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#define NV_FUSE_CRC_STATUS_H3_CRC_PRESENT_UNCORRECTED_ERRORS 0x00000007 /* R---V */
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#define NV_FUSE_ENABLE_FUSE_PROGRAM_STATUS 0x00820078 /* R--4R */
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#define NV_FUSE_ENABLE_FUSE_PROGRAM_STATUS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_ENABLE_FUSE_PROGRAM_STATUS_DATA 0:0 /* R-IVF */
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#define NV_FUSE_ENABLE_FUSE_PROGRAM_STATUS_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_DISABLE_SW_OVERRIDE_STATUS 0x00820084 /* R--4R */
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#define NV_FUSE_DISABLE_SW_OVERRIDE_STATUS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_DISABLE_SW_OVERRIDE_STATUS_DATA 0:0 /* R-IVF */
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#define NV_FUSE_DISABLE_SW_OVERRIDE_STATUS_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_IFF_SW_FUSING 0x00820088 /* RW-4R */
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#define NV_FUSE_IFF_SW_FUSING__PRIV_LEVEL_MASK 0x008200E0 /* */
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#define NV_FUSE_IFF_SW_FUSING_VAL 0:0 /* RWIVF */
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#define NV_FUSE_IFF_SW_FUSING_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_IFF_SW_FUSING_VAL_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_IFF_SW_FUSING_VAL_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10 0x00825820 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_10_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10 0x00825824 /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_10_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11 0x00825828 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_11_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11 0x0082582C /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_11_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12 0x00825830 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_12_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12 0x00825834 /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_12_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13 0x00825838 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_13_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13 0x0082583C /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_13_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14 0x00825840 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_14_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14 0x00825844 /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_14_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15 0x00825848 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_15_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15 0x0082584C /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_15_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16 0x00825850 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_16_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16 0x00825854 /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_16_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3 0x00825858 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_10_VAL 10:10 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_10_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_11_VAL 11:11 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_11_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_12_VAL 12:12 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_12_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_13_VAL 13:13 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_13_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_14_VAL 14:14 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_14_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_15_VAL 15:15 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_15_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_16_VAL 16:16 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_16_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_17_VAL 17:17 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_17_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_18_VAL 18:18 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_18_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_19_VAL 19:19 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_3_SEG_19_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3 0x0082585C /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_10_VAL 10:10 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_10_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_11_VAL 11:11 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_11_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_12_VAL 12:12 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_12_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_13_VAL 13:13 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_13_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_14_VAL 14:14 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_14_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_15_VAL 15:15 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_15_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_16_VAL 16:16 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_16_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_17_VAL 17:17 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_17_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_18_VAL 18:18 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_18_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_19_VAL 19:19 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_3_SEG_19_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4 0x00825860 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_10_VAL 10:10 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_10_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_11_VAL 11:11 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_11_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_12_VAL 12:12 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_12_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_13_VAL 13:13 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_13_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_14_VAL 14:14 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_14_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_15_VAL 15:15 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_15_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_16_VAL 16:16 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_16_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_17_VAL 17:17 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_17_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_18_VAL 18:18 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_18_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_19_VAL 19:19 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_4_SEG_19_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4 0x00825864 /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_10_VAL 10:10 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_10_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_11_VAL 11:11 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_11_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_12_VAL 12:12 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_12_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_13_VAL 13:13 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_13_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_14_VAL 14:14 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_14_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_15_VAL 15:15 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_15_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_16_VAL 16:16 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_16_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_17_VAL 17:17 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_17_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_18_VAL 18:18 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_18_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_19_VAL 19:19 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_4_SEG_19_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5 0x00825868 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_10_VAL 10:10 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_10_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_11_VAL 11:11 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_11_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_12_VAL 12:12 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_12_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_13_VAL 13:13 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_13_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_14_VAL 14:14 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_14_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_15_VAL 15:15 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_15_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_16_VAL 16:16 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_16_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_17_VAL 17:17 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_17_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_18_VAL 18:18 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_18_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_19_VAL 19:19 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_5_SEG_19_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5 0x0082586C /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_10_VAL 10:10 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_10_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_11_VAL 11:11 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_11_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_12_VAL 12:12 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_12_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_13_VAL 13:13 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_13_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_14_VAL 14:14 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_14_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_15_VAL 15:15 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_15_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_16_VAL 16:16 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_16_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_17_VAL 17:17 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_17_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_18_VAL 18:18 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_18_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_19_VAL 19:19 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_5_SEG_19_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6 0x00825870 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_10_VAL 10:10 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_10_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_11_VAL 11:11 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_11_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_12_VAL 12:12 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_6_SEG_12_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6 0x00825874 /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_10_VAL 10:10 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_10_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_11_VAL 11:11 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_11_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_12_VAL 12:12 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_6_SEG_12_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7 0x00825878 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_10_VAL 10:10 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_10_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_11_VAL 11:11 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_11_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_12_VAL 12:12 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_7_SEG_12_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7 0x0082587C /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_10_VAL 10:10 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_10_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_11_VAL 11:11 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_11_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_12_VAL 12:12 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_7_SEG_12_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8 0x00825880 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_10_VAL 10:10 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_10_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_11_VAL 11:11 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_11_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_12_VAL 12:12 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_8_SEG_12_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8 0x00825884 /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_10_VAL 10:10 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_10_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_11_VAL 11:11 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_11_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_12_VAL 12:12 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_8_SEG_12_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9 0x00825888 /* RW-4R */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_0_VAL 0:0 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_1_VAL 1:1 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_2_VAL 2:2 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_3_VAL 3:3 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_4_VAL 4:4 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_4_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_5_VAL 5:5 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_5_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_6_VAL 6:6 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_6_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_7_VAL 7:7 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_7_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_8_VAL 8:8 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_8_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_9_VAL 9:9 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_9_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_10_VAL 10:10 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_10_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_11_VAL 11:11 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_11_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_12_VAL 12:12 /* RWIUF */
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#define NV_FUSE_RESHIFT_TRIGGER_CHAIN_9_SEG_12_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9 0x0082588C /* R-E4R */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_0_VAL 0:0 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_0_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_1_VAL 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_1_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_2_VAL 2:2 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_2_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_3_VAL 3:3 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_3_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_4_VAL 4:4 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_4_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_5_VAL 5:5 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_5_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_6_VAL 6:6 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_6_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_7_VAL 7:7 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_7_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_8_VAL 8:8 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_8_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_9_VAL 9:9 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_9_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_10_VAL 10:10 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_10_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_11_VAL 11:11 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_11_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_12_VAL 12:12 /* R-EVF */
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#define NV_FUSE_RESHIFT_STATUS_CHAIN_9_SEG_12_VAL_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK 0x00823B14 /* RWE4R */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK 0x008200E0 /* RWE4R */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fuse_debugctrl" /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_DEBUGCTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK 0x00823804 /* RWE4R */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "feature_override_quadro" /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK 0x00823800 /* RWE4R */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "feature_override_ecc" /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK 0x00823B04 /* RWE4R */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK 0x00823B18 /* RWE4R */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "feature_override_memqual" /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK 0x00823B00 /* RWE4R */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "feature_override_remapper" /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_FEATURE_OVERRIDE_REMAPPER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK 0x008200DC /* RWE4R */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fuse_floorsweep" /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK 0x008200F8 /* RWE4R */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fuse_ctrl" /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_FUSECTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK 0x008200E4 /* RWE4R */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWE-V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_FUSETIME_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK 0x008200F0 /* RWE4R */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fuse_iddqinfo" /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_IDDQINFO_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK 0x008200D4 /* RWE4R */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fuse_kappainfo" /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_KAPPAINFO_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK 0x00823B08 /* RWE4R */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "kfuse" /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_KFUSE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK 0x008200FC /* RWE4R */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_OPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK 0x008200D8 /* RWE4R */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWE-V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_RECONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK 0x00823B10 /* RWE4R */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reshift_gpc_rail" /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK 0x00823B0C /* RWE4R */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reshift_gpc_rail" /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_RAIL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK 0x00823B1C /* RWE4R */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "sec_fault_config" /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK 0x008200EC /* RWE4R */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fuse_speedoinfo" /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_SPEEDOINFO_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK 0x008200E8 /* RWE4R */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "fuse_sram_vmin" /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000C /* RW--V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_SRAM_VMIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK 0x008200D0 /* RWE4R */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fuse_floorsweep" /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_TPC_FLOORSWEEP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK 0x008200F4 /* RWE4R */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "fuse_wdata" /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000F /* RWE-V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_FUSE_WDATA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_FUSE_OPT_SCI_BG_TEMP_COEFF 0x00820100 /* RW-4R */
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#define NV_FUSE_OPT_SCI_BG_TEMP_COEFF__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SCI_BG_TEMP_COEFF_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SCI_BG_TEMP_COEFF_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C0_WR_SECURE 0x00820104 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C0_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C0_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C0_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C0_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C0_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SCI_BG_VOLTAGE 0x00820108 /* RW-4R */
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#define NV_FUSE_OPT_SCI_BG_VOLTAGE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SCI_BG_VOLTAGE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_SCI_BG_VOLTAGE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C1_WR_SECURE 0x0082010C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C1_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C1_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C1_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C1_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C1_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SCI_BG_VALID 0x00820110 /* RW-4R */
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#define NV_FUSE_OPT_SCI_BG_VALID__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SCI_BG_VALID_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SCI_BG_VALID_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SCI_BG_VALID_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SCI_BG_VALID_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C2_WR_SECURE 0x00820114 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C2_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C2_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C2_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C2_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C2_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC 0x00820118 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C3_WR_SECURE 0x0082011C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C3_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C3_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C3_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C3_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C3_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C4_WR_SECURE 0x00820124 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C4_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C4_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C4_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C4_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C4_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HOST_DBG_BUS_WR_SECURE 0x00820128 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_HOST_DBG_BUS_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_HOST_DBG_BUS_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_HOST_DBG_BUS_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HOST_DBG_BUS_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HOST_DBG_BUS_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C5_WR_SECURE 0x0082012C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C5_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C5_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C5_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C5_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C5_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE 0x00820130 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C6_WR_SECURE 0x00820134 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C6_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C6_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C6_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C6_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C6_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SRAM_ECC_WR_SECURE 0x00820138 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_SRAM_ECC_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_SRAM_ECC_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_SRAM_ECC_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SRAM_ECC_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SRAM_ECC_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C7_WR_SECURE 0x0082013C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C7_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C7_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C7_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C7_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C7_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_ADCS_WR_SECURE 0x00820140 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_ADCS_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_ADCS_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_ADCS_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_ADCS_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_ADCS_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C8_WR_SECURE 0x00820144 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C8_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C8_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C8_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C8_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C8_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE 0x00820148 /* RW-4R */
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#define NV_FUSE_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C9_WR_SECURE 0x0082014C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C9_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C9_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C9_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C9_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_I2C9_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_IST_DISABLE_DEBUG_FEATURES 0x00820150 /* RW-4R */
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#define NV_FUSE_OPT_IST_DISABLE_DEBUG_FEATURES__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_IST_DISABLE_DEBUG_FEATURES_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_PADCTL_WR_SECURE 0x00820154 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_PADCTL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_PADCTL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_PADCTL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_PADCTL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_PADCTL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_PWR_WR_SECURE 0x0082015C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_PWR_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_PWR_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_PWR_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_PWR_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_PWR_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE 0x00820160 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_ROM_WR_SECURE 0x00820164 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_ROM_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_ROM_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_ROM_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_ROM_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_ROM_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SM_TTU_EN 0x00820168 /* RW-4R */
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#define NV_FUSE_OPT_SM_TTU_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SM_TTU_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SM_TTU_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SM_TTU_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SM_TTU_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_ELPG_WR_SECURE 0x0082016C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_ELPG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_ELPG_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_ELPG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_ELPG_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_ELPG_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PJTAG_ACCESS_WR_SECURE 0x00820170 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PJTAG_ACCESS_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PJTAG_ACCESS_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PJTAG_ACCESS_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PJTAG_ACCESS_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PJTAG_ACCESS_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_RST_WR_SECURE 0x00820174 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_RST_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_RST_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_RST_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_RST_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_RST_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_KAPPA_INFO 0x00820178 /* RW-4R */
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#define NV_FUSE_OPT_KAPPA_INFO__PRIV_LEVEL_MASK 0x008200D4 /* */
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#define NV_FUSE_OPT_KAPPA_INFO_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_KAPPA_INFO_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FUSE_UCODE_NVENC_REV 0x0082017C /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_NVENC_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_NVENC_REV_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_NVENC_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FUSE_UCODE_SCRUBBER_BIN_REV 0x00820180 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_SCRUBBER_BIN_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_SCRUBBER_BIN_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_SCRUBBER_BIN_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FUSE_UCODE_SEC2_REV 0x00820184 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_SEC2_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_SEC2_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_SEC2_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE 0x00820188 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_FANTACH_WR_SECURE 0x0082018C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_FANTACH_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_FANTACH_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_FANTACH_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_FANTACH_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_FANTACH_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE 0x00820190 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FBPA_ECC_WR_SECURE 0x00820194 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FBPA_ECC_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_SECURE_FBPA_ECC_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FBPA_ECC_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FBPA_ECC_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FBPA_ECC_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_MMU_PLM_WR_SECURE 0x00820198 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_MMU_PLM_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_MMU_PLM_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_MMU_PLM_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_MMU_PLM_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_MMU_PLM_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE 0x0082019C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_INTRUPT_WR_SECURE 0x008201A0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_INTRUPT_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_INTRUPT_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_INTRUPT_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_INTRUPT_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_INTRUPT_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_UPHY_CFG_WR_SECURE 0x008201A4 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_UPHY_CFG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_UPHY_CFG_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_UPHY_CFG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_UPHY_CFG_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_UPHY_CFG_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_PP_WR_SECURE 0x008201A8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_PP_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_PP_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_PP_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_PP_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_PP_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE 0x008201AC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE 0x008201B0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_RAM 0x008201B8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_RAM__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_RAM_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_RAM_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_RAM_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_RAM_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE 0x008201BC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_DEBUG 0x008201C0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_DEBUG__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_DEBUG_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_DEBUG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_FAN 0x008201C4 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_FAN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_FAN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_FAN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_FAN_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_FAN_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_DEBUG 0x008201C8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_DEBUG__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_DEBUG_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_DEBUG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_DEBUG_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_DEBUG_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SYSTEM 0x008201CC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SYSTEM__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SYSTEM_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SYSTEM_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SYSTEM_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SYSTEM_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE 0x008201D0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE 0x008201D4 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE 0x008201D8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE 0x008201DC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE 0x008201E0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE 0x008201E4 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_VIDCTRL_WR_SECURE 0x008201E8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_VIDCTRL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_VIDCTRL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_VIDCTRL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_VIDCTRL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_VIDCTRL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ 0x008201F0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_MAST_FSM 0x008201F4 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_MAST_FSM__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_MAST_FSM_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_MAST_FSM_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE 0x008201F8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_INVALID_BITS_ATE 0x008201FC /* RW-4R */
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#define NV_FUSE_OPT_INVALID_BITS_ATE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_INVALID_BITS_ATE_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_INVALID_BITS_ATE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_OPENGL_EN 0x00820200 /* RW-4R */
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#define NV_FUSE_OPT_OPENGL_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_OPENGL_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_OPENGL_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_OPENGL_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_OPENGL_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_MCHIP_EN 0x00820204 /* RW-4R */
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#define NV_FUSE_OPT_MCHIP_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_MCHIP_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_MCHIP_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_MCHIP_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_MCHIP_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE 0x00820208 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NOTEBOOK 0x0082020C /* RW-4R */
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#define NV_FUSE_OPT_NOTEBOOK__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NOTEBOOK_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NOTEBOOK_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NOTEBOOK_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NOTEBOOK_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PRIV_SFK_0 0x00820210 /* RW-4R */
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#define NV_FUSE_OPT_PRIV_SFK_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PRIV_SFK_0_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PRIV_SFK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PRIV_SFK_1 0x00820214 /* RW-4R */
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#define NV_FUSE_OPT_PRIV_SFK_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PRIV_SFK_1_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PRIV_SFK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_JTAG2HOST_PRIV_SEC_EN 0x00820218 /* RW-4R */
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#define NV_FUSE_OPT_JTAG2HOST_PRIV_SEC_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_JTAG2HOST_PRIV_SEC_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_JTAG2HOST_PRIV_SEC_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_JTAG2HOST_PRIV_SEC_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_JTAG2HOST_PRIV_SEC_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PRIV_SFK_2 0x0082021C /* RW-4R */
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#define NV_FUSE_OPT_PRIV_SFK_2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PRIV_SFK_2_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PRIV_SFK_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_I2CS_WIDE_EN 0x00820220 /* RW-4R */
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#define NV_FUSE_OPT_I2CS_WIDE_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_I2CS_WIDE_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_I2CS_WIDE_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_I2CS_WIDE_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_I2CS_WIDE_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_DP 0x00820224 /* RW-4R */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_DP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_DP_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_DP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_DP_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_DP_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_ECC_EN 0x00820228 /* RW-4R */
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#define NV_FUSE_OPT_ECC_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ECC_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_ECC_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ECC_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_ECC_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_GPC_DISABLE_CP 0x0082022C /* RW-4R */
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#define NV_FUSE_OPT_GPC_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_GPC_DISABLE_CP_DATA 6:0 /* RWIVF */
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#define NV_FUSE_OPT_GPC_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC0_DISABLE_CP 0x00820230 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC0_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC0_DISABLE_CP_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC0_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FBP_DISABLE_CP 0x00820234 /* RW-4R */
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#define NV_FUSE_OPT_FBP_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FBP_DISABLE_CP_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_FBP_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PRIV_SFK_3 0x00820238 /* RW-4R */
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#define NV_FUSE_OPT_PRIV_SFK_3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PRIV_SFK_3_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PRIV_SFK_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SCC_DIS 0x0082023C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_SCC_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_SCC_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_SCC_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SCC_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SCC_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE 0x00820240 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SPLIT_RAIL_SD_CLAMP_BYPASS 0x00820244 /* RW-4R */
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#define NV_FUSE_OPT_SPLIT_RAIL_SD_CLAMP_BYPASS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SPLIT_RAIL_SD_CLAMP_BYPASS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SPLIT_RAIL_SD_CLAMP_BYPASS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SPLIT_RAIL_SD_CLAMP_BYPASS_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SPLIT_RAIL_SD_CLAMP_BYPASS_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PCIE_LANE_DISABLE_CP 0x00820248 /* RW-4R */
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#define NV_FUSE_OPT_PCIE_LANE_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PCIE_LANE_DISABLE_CP_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_PCIE_LANE_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DISPLAY_DISABLE_CP 0x0082024C /* RW-4R */
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#define NV_FUSE_OPT_DISPLAY_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_DISPLAY_DISABLE_CP_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_DISPLAY_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DISPLAY_DISABLE_CP_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_DISPLAY_DISABLE_CP_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_DISABLE_GEN3_SPEED 0x00820250 /* RW-4R */
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#define NV_FUSE_OPT_DISABLE_GEN3_SPEED__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_DISABLE_GEN3_SPEED_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_DISABLE_GEN3_SPEED_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DISABLE_GEN3_SPEED_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_DISABLE_GEN3_SPEED_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FUSE_UCODE_ACR_HS_REV 0x00820254 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_ACR_HS_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_ACR_HS_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_ACR_HS_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FUSE_UCODE_GFW_REV 0x00820258 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_GFW_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_GFW_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_GFW_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_VENDOR_CODE 0x0082025C /* RW-4R */
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#define NV_FUSE_OPT_VENDOR_CODE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_VENDOR_CODE_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_VENDOR_CODE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FAB_CODE 0x00820260 /* RW-4R */
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#define NV_FUSE_OPT_FAB_CODE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FAB_CODE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_FAB_CODE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_LOT_CODE_0 0x00820264 /* RW-4R */
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#define NV_FUSE_OPT_LOT_CODE_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_LOT_CODE_0_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_LOT_CODE_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_LOT_CODE_1 0x00820268 /* RW-4R */
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#define NV_FUSE_OPT_LOT_CODE_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_LOT_CODE_1_DATA 27:0 /* RWIVF */
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#define NV_FUSE_OPT_LOT_CODE_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_WAFER_ID 0x0082026C /* RW-4R */
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#define NV_FUSE_OPT_WAFER_ID__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_WAFER_ID_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_WAFER_ID_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_X_COORDINATE 0x00820270 /* RW-4R */
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#define NV_FUSE_OPT_X_COORDINATE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_X_COORDINATE_DATA 8:0 /* RWIVF */
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#define NV_FUSE_OPT_X_COORDINATE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_Y_COORDINATE 0x00820274 /* RW-4R */
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#define NV_FUSE_OPT_Y_COORDINATE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_Y_COORDINATE_DATA 8:0 /* RWIVF */
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#define NV_FUSE_OPT_Y_COORDINATE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_OPS_RESERVED 0x00820278 /* RW-4R */
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#define NV_FUSE_OPT_OPS_RESERVED__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_OPS_RESERVED_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_OPS_RESERVED_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_INT_TS_OTOB_EN 0x0082027C /* RW-4R */
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#define NV_FUSE_OPT_INT_TS_OTOB_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_INT_TS_OTOB_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_INT_TS_OTOB_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_INT_TS_OTOB_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_INT_TS_OTOB_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_INT_TS_A 0x00820280 /* RW-4R */
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#define NV_FUSE_OPT_INT_TS_A__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_INT_TS_A_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_INT_TS_A_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_INT_TS_B 0x00820284 /* RW-4R */
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#define NV_FUSE_OPT_INT_TS_B__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_INT_TS_B_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_INT_TS_B_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TS_CALIBRATE 0x00820288 /* RW-4R */
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#define NV_FUSE_OPT_TS_CALIBRATE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TS_CALIBRATE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_TS_CALIBRATE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HS_DIS_NVDEC3 0x0082028C /* RW-4R */
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#define NV_FUSE_OPT_HS_DIS_NVDEC3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_HS_DIS_NVDEC3_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_HS_DIS_NVDEC3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HS_DIS_NVDEC3_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_HS_DIS_NVDEC3_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_INT_TS_VALID 0x00820290 /* RW-4R */
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#define NV_FUSE_OPT_INT_TS_VALID__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_INT_TS_VALID_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_INT_TS_VALID_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_INT_TS_VALID_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_INT_TS_VALID_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_I2CS_ADDR_SEL 0x00820294 /* RW-4R */
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#define NV_FUSE_OPT_I2CS_ADDR_SEL__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_I2CS_ADDR_SEL_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_I2CS_ADDR_SEL_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE 0x00820298 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SW_SMC_DISABLE 0x0082029C /* RW-4R */
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#define NV_FUSE_OPT_SW_SMC_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SW_SMC_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SW_SMC_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SW_SMC_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SW_SMC_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FUSE_UCODE_ROM_FLASH_REV 0x008202A0 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_ROM_FLASH_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_ROM_FLASH_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_ROM_FLASH_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FUSE_UCODE_PR_VPR_REV 0x008202A4 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_PR_VPR_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_PR_VPR_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_PR_VPR_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE 0x008202A8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_TITAN_EN 0x008202AC /* RW-4R */
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#define NV_FUSE_OPT_TITAN_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TITAN_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_TITAN_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TITAN_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_TITAN_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SRAM_REPAIR 0x008202B0 /* RW-4R */
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#define NV_FUSE_OPT_SRAM_REPAIR__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SRAM_REPAIR_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_SRAM_REPAIR_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FIB_REVISION_ID 0x008202B4 /* RW-4R */
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#define NV_FUSE_OPT_FIB_REVISION_ID__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FIB_REVISION_ID_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FIB_REVISION_ID_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_MASK_REVISION_ID 0x008202B8 /* RW-4R */
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#define NV_FUSE_OPT_MASK_REVISION_ID__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_MASK_REVISION_ID_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_MASK_REVISION_ID_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_MINOR_EXT_REVISION_ID 0x008202BC /* RW-4R */
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#define NV_FUSE_OPT_MINOR_EXT_REVISION_ID__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_MINOR_EXT_REVISION_ID_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_MINOR_EXT_REVISION_ID_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FAB_ID 0x008202C0 /* RW-4R */
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#define NV_FUSE_OPT_FAB_ID__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FAB_ID_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_FAB_ID_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_LTC_DISABLE 0x008202C4 /* RW-4R */
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#define NV_FUSE_OPT_LTC_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_LTC_DISABLE_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_LTC_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CP_BIN 0x008202C8 /* RW-4R */
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#define NV_FUSE_OPT_CP_BIN__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_CP_BIN_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_CP_BIN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FUSE_UCODE_NVDEC_REV 0x008202CC /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_NVDEC_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_NVDEC_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_NVDEC_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DONE_MAP 0x008202D0 /* RW-4R */
|
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#define NV_FUSE_OPT_DONE_MAP__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_DONE_MAP_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_DONE_MAP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_IDDQ 0x008202D4 /* RW-4R */
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#define NV_FUSE_OPT_IDDQ__PRIV_LEVEL_MASK 0x008200F0 /* */
|
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#define NV_FUSE_OPT_IDDQ_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_IDDQ_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_OFA_DISABLE 0x008202D8 /* RW-4R */
|
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#define NV_FUSE_OPT_OFA_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
|
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#define NV_FUSE_OPT_OFA_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_OFA_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_OFA_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_OFA_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PFG 0x008202DC /* RW-4R */
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#define NV_FUSE_OPT_PFG__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_PFG_DATA 6:0 /* RWIVF */
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#define NV_FUSE_OPT_PFG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE 0x008202E0 /* RW-4R */
|
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#define NV_FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_DATA_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_LTC_DISABLE_CP 0x008202E4 /* RW-4R */
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#define NV_FUSE_OPT_LTC_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_LTC_DISABLE_CP_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_LTC_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_XTAL16X_FSM_DISABLE 0x008202E8 /* RW-4R */
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#define NV_FUSE_OPT_XTAL16X_FSM_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_XTAL16X_FSM_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_XTAL16X_FSM_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_XTAL16X_FSM_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_XTAL16X_FSM_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_OFA_DISABLE_CP 0x008202EC /* RW-4R */
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#define NV_FUSE_OPT_OFA_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_OFA_DISABLE_CP_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_OFA_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_OFA_DISABLE_CP_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_OFA_DISABLE_CP_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_OFA_DEFECTIVE 0x008202F0 /* RW-4R */
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#define NV_FUSE_OPT_OFA_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_OFA_DEFECTIVE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_OFA_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_OFA_DEFECTIVE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_OFA_DEFECTIVE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV 0x008202F4 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HS_DIS_NVDEC4 0x008202F8 /* RW-4R */
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#define NV_FUSE_OPT_HS_DIS_NVDEC4__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_HS_DIS_NVDEC4_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_HS_DIS_NVDEC4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HS_DIS_NVDEC4_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_HS_DIS_NVDEC4_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_HDCP_EN 0x008202FC /* RW-4R */
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#define NV_FUSE_OPT_HDCP_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_HDCP_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_HDCP_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HDCP_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_HDCP_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_0 0x00820300 /* RW-4R */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_0_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_1 0x00820304 /* RW-4R */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_1_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_2 0x00820308 /* RW-4R */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_2_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_NVHS_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_PCIE 0x0082030C /* RW-4R */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_PCIE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_PCIE_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_UPHY_PLL_BANDGAP_TRIM_PCIE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_CLK_WR_SECURE 0x00820310 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FUSE_CLK_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FUSE_CLK_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FUSE_CLK_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_CLK_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_CLK_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURED_BURN_FEATURE_ENABLE 0x00820314 /* RW-4R */
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#define NV_FUSE_OPT_SECURED_BURN_FEATURE_ENABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURED_BURN_FEATURE_ENABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURED_BURN_FEATURE_ENABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURED_BURN_FEATURE_ENABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURED_BURN_FEATURE_ENABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_ISM_WR_SECURE 0x00820318 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_ISM_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_ISM_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_ISM_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_ISM_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_ISM_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING 0x0082031C /* RW-4R */
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#define NV_FUSE_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PRIVKEY_ACC_DIS 0x00820324 /* R--4R */
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#define NV_FUSE_OPT_PRIVKEY_ACC_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PRIVKEY_ACC_DIS_DATA 2:0 /* R-IVF */
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#define NV_FUSE_OPT_PRIVKEY_ACC_DIS_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_OPT_FB_CONFIG 0x00820328 /* RW-4R */
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#define NV_FUSE_OPT_FB_CONFIG__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FB_CONFIG_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FB_CONFIG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SAMPLE_BIN 0x0082032C /* RW-4R */
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#define NV_FUSE_OPT_SAMPLE_BIN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SAMPLE_BIN_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SAMPLE_BIN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SAMPLE_TYPE 0x00820330 /* RW-4R */
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#define NV_FUSE_OPT_SAMPLE_TYPE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SAMPLE_TYPE_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SAMPLE_TYPE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_LOCAL_TRAP_WR_SECURE 0x00820334 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_LOCAL_TRAP_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_LOCAL_TRAP_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_LOCAL_TRAP_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_LOCAL_TRAP_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_LOCAL_TRAP_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PRI_SEQUENCER_WR_SECURE 0x00820338 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PRI_SEQUENCER_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PRI_SEQUENCER_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PRI_SEQUENCER_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PRI_SEQUENCER_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PRI_SEQUENCER_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SUBREVISION 0x0082033C /* RW-4R */
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#define NV_FUSE_OPT_SUBREVISION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SUBREVISION_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_SUBREVISION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_MEMORY_LOCKED_ENABLED 0x00820340 /* RW-4R */
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#define NV_FUSE_OPT_MEMORY_LOCKED_ENABLED__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_MEMORY_LOCKED_ENABLED_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_MEMORY_LOCKED_ENABLED_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_MEMORY_LOCKED_ENABLED_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_MEMORY_LOCKED_ENABLED_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PDI_0 0x00820344 /* RW-4R */
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#define NV_FUSE_OPT_PDI_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PDI_0_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PDI_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PDI_1 0x00820348 /* RW-4R */
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#define NV_FUSE_OPT_PDI_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PDI_1_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PDI_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PLTS_IQ_WR_SECURE 0x0082034C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PLTS_IQ_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PLTS_IQ_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PLTS_IQ_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PLTS_IQ_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_IQ_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_GPC_DISABLE 0x00820350 /* RW-4R */
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#define NV_FUSE_OPT_GPC_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_GPC_DISABLE_DATA 6:0 /* RWIVF */
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#define NV_FUSE_OPT_GPC_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_OVERT 0x00820354 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_OVERT__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_OVERT_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_OVERT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_OVERT_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_OVERT_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_DISABLE_FPF_FUSE_PROGRAMMING 0x00820358 /* RW-4R */
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#define NV_FUSE_OPT_DISABLE_FPF_FUSE_PROGRAMMING__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_DISABLE_FPF_FUSE_PROGRAMMING_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_DISABLE_FPF_FUSE_PROGRAMMING_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DISABLE_FPF_FUSE_PROGRAMMING_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_DISABLE_FPF_FUSE_PROGRAMMING_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_ZCULL_DISABLE 0x0082035C /* RW-4R */
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#define NV_FUSE_OPT_ZCULL_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_ZCULL_DISABLE_DATA 27:0 /* RWIVF */
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#define NV_FUSE_OPT_ZCULL_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE 0x00820360 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FBP_DISABLE 0x00820364 /* RW-4R */
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#define NV_FUSE_OPT_FBP_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_FBP_DISABLE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_FBP_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FBIO_DISABLE 0x0082036C /* RW-4R */
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#define NV_FUSE_OPT_FBIO_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_FBIO_DISABLE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_FBIO_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVJPG_DISABLE 0x00820370 /* RW-4R */
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#define NV_FUSE_OPT_NVJPG_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_NVJPG_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVJPG_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVJPG_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVJPG_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FUSE_CLK_SWITCH_DISABLE 0x00820374 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_CLK_SWITCH_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_CLK_SWITCH_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_CLK_SWITCH_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FUSE_CLK_SWITCH_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FUSE_CLK_SWITCH_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVDEC_DISABLE 0x00820378 /* RW-4R */
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#define NV_FUSE_OPT_NVDEC_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_NVDEC_DISABLE_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_NVDEC_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DISPLAY_DISABLE 0x0082037C /* RW-4R */
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#define NV_FUSE_OPT_DISPLAY_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_DISPLAY_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_DISPLAY_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DISPLAY_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_DISPLAY_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_RAM_SVOP_DP 0x00820384 /* RW-4R */
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#define NV_FUSE_OPT_RAM_SVOP_DP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RAM_SVOP_DP_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_RAM_SVOP_DP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RAM_SVOP_PDP 0x00820388 /* RW-4R */
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#define NV_FUSE_OPT_RAM_SVOP_PDP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RAM_SVOP_PDP_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_RAM_SVOP_PDP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE 0x0082038C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_RAM_SVOP_SP 0x00820390 /* RW-4R */
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#define NV_FUSE_OPT_RAM_SVOP_SP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RAM_SVOP_SP_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_RAM_SVOP_SP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PCIE_LANE_DISABLE 0x00820394 /* RW-4R */
|
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#define NV_FUSE_OPT_PCIE_LANE_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_PCIE_LANE_DISABLE_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_PCIE_LANE_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SPARE_FS 0x00820398 /* RW-4R */
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#define NV_FUSE_OPT_SPARE_FS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SPARE_FS_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_SPARE_FS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_GLOBAL_POISON_EN 0x0082039C /* RW-4R */
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#define NV_FUSE_OPT_GLOBAL_POISON_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_GLOBAL_POISON_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_GLOBAL_POISON_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_GLOBAL_POISON_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_GLOBAL_POISON_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_COH_WR_SECURE 0x008203A0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_COH_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_COH_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_COH_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_COH_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_COH_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_FLW0 0x008203A4 /* RW-4R */
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#define NV_FUSE_FLW0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_FLW0_DATA 0:0 /* RWIVF */
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#define NV_FUSE_FLW0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_FLW0_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_FLW0_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_FLW1 0x008203A8 /* RW-4R */
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#define NV_FUSE_FLW1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_FLW1_DATA 0:0 /* RWIVF */
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#define NV_FUSE_FLW1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_FLW1_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_FLW1_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_FLW2 0x008203AC /* RW-4R */
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#define NV_FUSE_FLW2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_FLW2_DATA 0:0 /* RWIVF */
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#define NV_FUSE_FLW2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_FLW2_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_FLW2_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_FLW3 0x008203B0 /* RW-4R */
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#define NV_FUSE_FLW3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_FLW3_DATA 0:0 /* RWIVF */
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#define NV_FUSE_FLW3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_FLW3_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_FLW3_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_AUTO_EN 0x008203B8 /* RW-4R */
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#define NV_FUSE_OPT_AUTO_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_AUTO_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_AUTO_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_AUTO_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_AUTO_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_0 0x008203BC /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_0_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_1 0x008203C0 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_1_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_2 0x008203C4 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_2_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_3 0x008203C8 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_3_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_0 0x008203CC /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_0_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_1 0x008203D0 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_1_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_2 0x008203D4 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_2_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_3 0x008203D8 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_3_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SE_CONTROL_SECURE 0x008203DC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_SE_CONTROL_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_SE_CONTROL_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_SE_CONTROL_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SE_CONTROL_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SE_CONTROL_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE 0x008203F0 /* RW-4R */
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#define NV_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_INTERNAL_SKU 0x008203F4 /* RW-4R */
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#define NV_FUSE_OPT_INTERNAL_SKU__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_INTERNAL_SKU_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_INTERNAL_SKU_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_INTERNAL_SKU_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_INTERNAL_SKU_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_ROM_DRV_STR 0x008203F8 /* RW-4R */
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#define NV_FUSE_OPT_ROM_DRV_STR__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ROM_DRV_STR_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_ROM_DRV_STR_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PFB_AMAP_WR_SECURE 0x008203FC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PFB_AMAP_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PFB_AMAP_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PFB_AMAP_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PFB_AMAP_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_AMAP_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_CYA_WR_SECURE 0x00820400 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PFB_CYA_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PFB_CYA_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PFB_CYA_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PFB_CYA_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_CYA_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FUSE_UCODE_GSP_REV 0x00820404 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_GSP_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_GSP_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_GSP_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE 0x00820408 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE 0x0082040C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PRI_SOURCE_ISOLATION_EN 0x00820410 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PRI_SOURCE_ISOLATION_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PRI_SOURCE_ISOLATION_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PRI_SOURCE_ISOLATION_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PRI_SOURCE_ISOLATION_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PRI_SOURCE_ISOLATION_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVENC_DISABLE 0x00820414 /* RW-4R */
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#define NV_FUSE_OPT_NVENC_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_NVENC_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVENC_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVENC_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVENC_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_DISP_HEAD_DISABLE 0x00820418 /* RW-4R */
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#define NV_FUSE_OPT_DISP_HEAD_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_DISP_HEAD_DISABLE_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_DISP_HEAD_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE 0x0082041C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE 0x00820428 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_GPC2CLK_CAP 0x0082042C /* RW-4R */
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#define NV_FUSE_OPT_GPC2CLK_CAP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_GPC2CLK_CAP_DATA 4:0 /* RWIVF */
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#define NV_FUSE_OPT_GPC2CLK_CAP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PRIV_SEC_EN 0x00820434 /* RW-4R */
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#define NV_FUSE_OPT_PRIV_SEC_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PRIV_SEC_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_PRIV_SEC_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PRIV_SEC_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PRIV_SEC_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE 0x00820438 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE 0x0082043C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE 0x00820440 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE 0x00820444 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XBAR_CYA_WR_SECURE 0x00820448 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_XBAR_CYA_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_XBAR_CYA_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_XBAR_CYA_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XBAR_CYA_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XBAR_CYA_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XBAR_PM_WR_SECURE 0x0082044C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_XBAR_PM_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_XBAR_PM_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_XBAR_PM_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XBAR_PM_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XBAR_PM_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_DISP_HEAD_DISABLE_CP 0x00820450 /* RW-4R */
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#define NV_FUSE_OPT_DISP_HEAD_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_DISP_HEAD_DISABLE_CP_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_DISP_HEAD_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVDEC_DISABLE_CP 0x00820458 /* RW-4R */
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#define NV_FUSE_OPT_NVDEC_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVDEC_DISABLE_CP_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_NVDEC_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVENC_DISABLE_CP 0x0082045C /* RW-4R */
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#define NV_FUSE_OPT_NVENC_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVENC_DISABLE_CP_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVENC_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVENC_DISABLE_CP_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVENC_DISABLE_CP_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FBIO_DISABLE_CP 0x00820460 /* RW-4R */
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#define NV_FUSE_OPT_FBIO_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FBIO_DISABLE_CP_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_FBIO_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PLTS_CBC_WR_SECURE 0x00820464 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PLTS_CBC_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PLTS_CBC_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PLTS_CBC_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PLTS_CBC_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_CBC_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_WR_SECURE 0x0082046C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE 0x00820470 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_DSTG_WR_SECURE 0x00820474 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PLTS_DSTG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PLTS_DSTG_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PLTS_DSTG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PLTS_DSTG_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_DSTG_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE 0x00820478 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_WR_SECURE 0x0082047C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_TSTG_WR_SECURE 0x00820480 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PLTS_TSTG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PLTS_TSTG_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PLTS_TSTG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PLTS_TSTG_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_TSTG_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_CGATE_WR_SECURE 0x00820484 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PLTS_CGATE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PLTS_CGATE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PLTS_CGATE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PLTS_CGATE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PLTS_CGATE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVJPG_DISABLE_CP 0x00820488 /* RW-4R */
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#define NV_FUSE_OPT_NVJPG_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVJPG_DISABLE_CP_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVJPG_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVJPG_DISABLE_CP_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVJPG_DISABLE_CP_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_WDATA_WR_SECURE 0x0082048C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FUSE_WDATA_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FUSE_WDATA_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FUSE_WDATA_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_WDATA_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_WDATA_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_RD_SECURE 0x00820490 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_RD_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_RD_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_RD_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_RD_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_RD_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE 0x00820494 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_HALF_FBPA_ENABLE 0x0082049C /* RW-4R */
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#define NV_FUSE_OPT_HALF_FBPA_ENABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_HALF_FBPA_ENABLE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_HALF_FBPA_ENABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SPEEDO_REV 0x008204A0 /* RW-4R */
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#define NV_FUSE_OPT_SPEEDO_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SPEEDO_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SPEEDO_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_IDDQ_REV 0x008204A4 /* RW-4R */
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#define NV_FUSE_OPT_IDDQ_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_IDDQ_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_IDDQ_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SPEEDO0 0x008204A8 /* RW-4R */
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#define NV_FUSE_OPT_SPEEDO0__PRIV_LEVEL_MASK 0x008200EC /* */
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#define NV_FUSE_OPT_SPEEDO0_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_SPEEDO0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SPEEDO1 0x008204AC /* RW-4R */
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#define NV_FUSE_OPT_SPEEDO1__PRIV_LEVEL_MASK 0x008200EC /* */
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#define NV_FUSE_OPT_SPEEDO1_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_SPEEDO1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SPEEDO2 0x008204B0 /* RW-4R */
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#define NV_FUSE_OPT_SPEEDO2__PRIV_LEVEL_MASK 0x008200EC /* */
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#define NV_FUSE_OPT_SPEEDO2_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_SPEEDO2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FT_REV 0x008204B4 /* RW-4R */
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#define NV_FUSE_OPT_FT_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FT_REV_DATA 10:0 /* RWIVF */
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#define NV_FUSE_OPT_FT_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CP_REV 0x008204B8 /* RW-4R */
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#define NV_FUSE_OPT_CP_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_CP_REV_DATA 10:0 /* RWIVF */
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#define NV_FUSE_OPT_CP_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SLT_REV 0x008204BC /* RW-4R */
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#define NV_FUSE_OPT_SLT_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SLT_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_SLT_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TS_TC 0x008204C0 /* RW-4R */
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#define NV_FUSE_OPT_TS_TC__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TS_TC_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_TS_TC_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC4_DISABLE_CP 0x008204C4 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC4_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC4_DISABLE_CP_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC4_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC5_DISABLE_CP 0x008204CC /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC5_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC5_DISABLE_CP_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC5_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_MAJOR_REVISION_ID 0x008204D0 /* RW-4R */
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#define NV_FUSE_OPT_MAJOR_REVISION_ID__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_MAJOR_REVISION_ID_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_MAJOR_REVISION_ID_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_MINOR_REVISION_ID 0x008204D4 /* RW-4R */
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#define NV_FUSE_OPT_MINOR_REVISION_ID__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_MINOR_REVISION_ID_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_MINOR_REVISION_ID_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PCIE_DEVIDA 0x008204D8 /* RW-4R */
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#define NV_FUSE_OPT_PCIE_DEVIDA__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PCIE_DEVIDA_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_PCIE_DEVIDA_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CUST_ATE_REV 0x008204DC /* RW-4R */
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#define NV_FUSE_OPT_CUST_ATE_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_CUST_ATE_REV_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_CUST_ATE_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FBPA_IOBIST_WR_SECURE 0x008204E0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FBPA_IOBIST_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FBPA_IOBIST_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FBPA_IOBIST_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FBPA_IOBIST_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FBPA_IOBIST_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SLT_DONE 0x008204E4 /* RW-4R */
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#define NV_FUSE_OPT_SLT_DONE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SLT_DONE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SLT_DONE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SLT_DONE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SLT_DONE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FBPA_ILA_WR_SECURE 0x008204EC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FBPA_ILA_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FBPA_ILA_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FBPA_ILA_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FBPA_ILA_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FBPA_ILA_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NNE_ID 0x008204F0 /* RW-4R */
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#define NV_FUSE_OPT_NNE_ID__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NNE_ID_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NNE_ID_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NNE_ID_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NNE_ID_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FT_DONE 0x008204F4 /* RW-4R */
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#define NV_FUSE_OPT_FT_DONE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FT_DONE_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_FT_DONE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVS_EN 0x008204F8 /* RW-4R */
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#define NV_FUSE_OPT_NVS_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVS_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVS_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVS_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVS_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SEC_DISABLE 0x008204FC /* RW-4R */
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#define NV_FUSE_OPT_SEC_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_SEC_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SEC_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SEC_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SEC_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_VP8_VP9_DISABLE 0x00820500 /* RW-4R */
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#define NV_FUSE_OPT_VP8_VP9_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_VP8_VP9_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_VP8_VP9_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_VP8_VP9_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_VP8_VP9_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_TPC_GPC1_DISABLE_CP 0x00820504 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC1_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC1_DISABLE_CP_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC1_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC1_DEFECTIVE 0x00820508 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC1_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC1_DEFECTIVE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC1_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC2_DEFECTIVE 0x0082050C /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC2_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC2_DEFECTIVE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC2_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_VGX_EN 0x00820510 /* RW-4R */
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#define NV_FUSE_OPT_VGX_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_VGX_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_VGX_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_VGX_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_VGX_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_TPC_GPC3_DEFECTIVE 0x00820514 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC3_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC3_DEFECTIVE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC3_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_B 0x00820518 /* RW-4R */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_B__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_B_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_B_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_C 0x0082051C /* RW-4R */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_C__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_C_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_C_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PEX_PLL_EN_TERM100 0x00820524 /* RW-4R */
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#define NV_FUSE_OPT_PEX_PLL_EN_TERM100__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PEX_PLL_EN_TERM100_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_PEX_PLL_EN_TERM100_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PEX_PLL_EN_TERM100_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PEX_PLL_EN_TERM100_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R1_1 0x00820528 /* RW-4R */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R1_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R1_1_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R1_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R1_0 0x0082052C /* RW-4R */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R1_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R1_0_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R1_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R2_1 0x00820530 /* RW-4R */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R2_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R2_1_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R2_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R2_0 0x00820534 /* RW-4R */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R2_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R2_0_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R2_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_XP_DFE_ENABLE_CTRL 0x00820538 /* RW-4R */
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#define NV_FUSE_OPT_XP_DFE_ENABLE_CTRL__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_XP_DFE_ENABLE_CTRL_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_XP_DFE_ENABLE_CTRL_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_XP_DFE_ENABLE_CTRL_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_XP_DFE_ENABLE_CTRL_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R3_0 0x0082053C /* RW-4R */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R3_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R3_0_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R3_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_XP_DC_GAIN_ADAPTIVE_CTRL 0x00820540 /* RW-4R */
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#define NV_FUSE_OPT_XP_DC_GAIN_ADAPTIVE_CTRL__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_XP_DC_GAIN_ADAPTIVE_CTRL_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_XP_DC_GAIN_ADAPTIVE_CTRL_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_XP_DC_GAIN_ADAPTIVE_CTRL_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_XP_DC_GAIN_ADAPTIVE_CTRL_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R3_1 0x00820544 /* RW-4R */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R3_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R3_1_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_3GIO_PADCFG_LUT_ADR_R3_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_XP_DYNAMIC_EQ_TRAINING_CTRL 0x00820548 /* RW-4R */
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#define NV_FUSE_OPT_XP_DYNAMIC_EQ_TRAINING_CTRL__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_XP_DYNAMIC_EQ_TRAINING_CTRL_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_XP_DYNAMIC_EQ_TRAINING_CTRL_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_XP_DYNAMIC_EQ_TRAINING_CTRL_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_XP_DYNAMIC_EQ_TRAINING_CTRL_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_GC6_NVVDD_OK_THRESHOLD 0x0082054C /* RW-4R */
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#define NV_FUSE_OPT_GC6_NVVDD_OK_THRESHOLD__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_GC6_NVVDD_OK_THRESHOLD_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_GC6_NVVDD_OK_THRESHOLD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_A 0x00820558 /* RW-4R */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_A__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_A_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_A_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CP1_DVS_COMPLETE 0x0082055C /* RW-4R */
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#define NV_FUSE_OPT_CP1_DVS_COMPLETE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_CP1_DVS_COMPLETE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_CP1_DVS_COMPLETE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CP1_DVS_COMPLETE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_CP1_DVS_COMPLETE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_CP2_DVS_COMPLETE 0x00820560 /* RW-4R */
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#define NV_FUSE_OPT_CP2_DVS_COMPLETE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_CP2_DVS_COMPLETE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_CP2_DVS_COMPLETE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CP2_DVS_COMPLETE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_CP2_DVS_COMPLETE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_TPC_GPC4_DEFECTIVE 0x00820564 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC4_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC4_DEFECTIVE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC4_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_GC6_ISLAND_DISABLE 0x00820568 /* RW-4R */
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#define NV_FUSE_OPT_GC6_ISLAND_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_GC6_ISLAND_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_GC6_ISLAND_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_GC6_ISLAND_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_GC6_ISLAND_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PCIE_DEVIDB 0x0082056C /* RW-4R */
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#define NV_FUSE_OPT_PCIE_DEVIDB__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PCIE_DEVIDB_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_PCIE_DEVIDB_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CP1_COMPLETE 0x00820570 /* RW-4R */
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#define NV_FUSE_OPT_CP1_COMPLETE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_CP1_COMPLETE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_CP1_COMPLETE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CP1_COMPLETE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_CP1_COMPLETE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_CP2_COMPLETE 0x00820574 /* RW-4R */
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#define NV_FUSE_OPT_CP2_COMPLETE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_CP2_COMPLETE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_CP2_COMPLETE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CP2_COMPLETE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_CP2_COMPLETE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_IDDQ_CP 0x00820578 /* RW-4R */
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#define NV_FUSE_OPT_IDDQ_CP__PRIV_LEVEL_MASK 0x008200F0 /* */
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#define NV_FUSE_OPT_IDDQ_CP_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_IDDQ_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PCIE_BOOT_GEN23_DISABLE 0x0082057C /* RW-4R */
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#define NV_FUSE_OPT_PCIE_BOOT_GEN23_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PCIE_BOOT_GEN23_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_PCIE_BOOT_GEN23_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PCIE_BOOT_GEN23_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PCIE_BOOT_GEN23_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PCIE_BOOT_GEN3_DISABLE 0x00820580 /* RW-4R */
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#define NV_FUSE_OPT_PCIE_BOOT_GEN3_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PCIE_BOOT_GEN3_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_PCIE_BOOT_GEN3_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PCIE_BOOT_GEN3_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PCIE_BOOT_GEN3_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_DEVID_SW_OVERRIDE_DIS 0x00820584 /* RW-4R */
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#define NV_FUSE_OPT_DEVID_SW_OVERRIDE_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_DEVID_SW_OVERRIDE_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_DEVID_SW_OVERRIDE_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DEVID_SW_OVERRIDE_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_DEVID_SW_OVERRIDE_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_ATE_VMIN 0x00820588 /* RW-4R */
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#define NV_FUSE_OPT_ATE_VMIN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ATE_VMIN_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_ATE_VMIN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_LTSSM_FAILSAFE_TIMEOUT_DIS 0x0082058C /* RW-4R */
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#define NV_FUSE_OPT_LTSSM_FAILSAFE_TIMEOUT_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_LTSSM_FAILSAFE_TIMEOUT_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_LTSSM_FAILSAFE_TIMEOUT_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_LTSSM_FAILSAFE_TIMEOUT_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_LTSSM_FAILSAFE_TIMEOUT_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FUSE_FUSEBLOW_REV 0x00820590 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_FUSEBLOW_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_FUSEBLOW_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_FUSEBLOW_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ASSR_STICKY_DISABLE 0x00820594 /* RW-4R */
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#define NV_FUSE_OPT_ASSR_STICKY_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ASSR_STICKY_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_ASSR_STICKY_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ASSR_STICKY_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_ASSR_STICKY_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE 0x00820598 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_FFMA 0x0082059C /* RW-4R */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_FFMA__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_FFMA_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_FFMA_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC3_DISABLE_CP 0x008205A0 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC3_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC3_DISABLE_CP_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC3_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_BA_WR_SECURE 0x008205A4 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_BA_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_BA_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_BA_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_BA_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_BA_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SFK_ACC_DIS 0x008205A8 /* R--4R */
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#define NV_FUSE_OPT_SFK_ACC_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SFK_ACC_DIS_DATA 0:0 /* R-IVF */
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#define NV_FUSE_OPT_SFK_ACC_DIS_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_OPT_SFK_ACC_DIS_DATA_NO 0x00000000 /* R---V */
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#define NV_FUSE_OPT_SFK_ACC_DIS_DATA_YES 0x00000001 /* R---V */
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#define NV_FUSE_OPT_TPC_GPC5_DEFECTIVE 0x008205AC /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC5_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC5_DEFECTIVE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC5_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_CTRL_WR_SECURE 0x008205B4 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FUSE_CTRL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FUSE_CTRL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FUSE_CTRL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_CTRL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_CTRL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE 0x008205B8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVJPG_DEFECTIVE 0x008205BC /* RW-4R */
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#define NV_FUSE_OPT_NVJPG_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVJPG_DEFECTIVE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVJPG_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVJPG_DEFECTIVE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVJPG_DEFECTIVE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_RESET_DELAY_DISABLE 0x008205C0 /* RW-4R */
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#define NV_FUSE_OPT_RESET_DELAY_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RESET_DELAY_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_RESET_DELAY_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RESET_DELAY_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_RESET_DELAY_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_GPC_DEFECTIVE 0x008205C4 /* RW-4R */
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#define NV_FUSE_OPT_GPC_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_GPC_DEFECTIVE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_GPC_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC0_DEFECTIVE 0x008205C8 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC0_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC0_DEFECTIVE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC0_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FBP_DEFECTIVE 0x008205CC /* RW-4R */
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#define NV_FUSE_OPT_FBP_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FBP_DEFECTIVE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_FBP_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FBIO_DEFECTIVE 0x008205D4 /* RW-4R */
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#define NV_FUSE_OPT_FBIO_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FBIO_DEFECTIVE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_FBIO_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DISPLAY_DEFECTIVE 0x008205D8 /* RW-4R */
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#define NV_FUSE_OPT_DISPLAY_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_DISPLAY_DEFECTIVE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_DISPLAY_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DISPLAY_DEFECTIVE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_DISPLAY_DEFECTIVE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVENC_DEFECTIVE 0x008205DC /* RW-4R */
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#define NV_FUSE_OPT_NVENC_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVENC_DEFECTIVE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVENC_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVENC_DEFECTIVE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVENC_DEFECTIVE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVDEC_DEFECTIVE 0x008205E0 /* RW-4R */
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#define NV_FUSE_OPT_NVDEC_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVDEC_DEFECTIVE_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_NVDEC_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PCIE_LANE_DEFECTIVE 0x008205E4 /* RW-4R */
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#define NV_FUSE_OPT_PCIE_LANE_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PCIE_LANE_DEFECTIVE_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_PCIE_LANE_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_LTC_DEFECTIVE 0x008205E8 /* RW-4R */
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#define NV_FUSE_OPT_LTC_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_LTC_DEFECTIVE_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_LTC_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_WPR_ENABLED 0x008205EC /* RW-4R */
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#define NV_FUSE_OPT_WPR_ENABLED__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_WPR_ENABLED_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_WPR_ENABLED_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_WPR_ENABLED_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_WPR_ENABLED_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SUB_REGION_NO_OVERRIDE 0x008205F0 /* RW-4R */
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#define NV_FUSE_OPT_SUB_REGION_NO_OVERRIDE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SUB_REGION_NO_OVERRIDE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SUB_REGION_NO_OVERRIDE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SUB_REGION_NO_OVERRIDE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SUB_REGION_NO_OVERRIDE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_TPC_GPC2_DISABLE_CP 0x008205F4 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC2_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC2_DISABLE_CP_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC2_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FBPA_I1500_WR_SECURE 0x008205F8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FBPA_I1500_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FBPA_I1500_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FBPA_I1500_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FBPA_I1500_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FBPA_I1500_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_DECODE_TRAP_WR_SECURE 0x008205FC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_DECODE_TRAP_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_DECODE_TRAP_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_DECODE_TRAP_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_DECODE_TRAP_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_DECODE_TRAP_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE 0x00820600 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE 0x00820604 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE 0x00820608 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_HALF_LTC_ENABLE 0x0082060C /* RW-4R */
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#define NV_FUSE_OPT_HALF_LTC_ENABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_HALF_LTC_ENABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_HALF_LTC_ENABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HALF_LTC_ENABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_HALF_LTC_ENABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVENC_THROTTLE 0x00820610 /* RW-4R */
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#define NV_FUSE_OPT_NVENC_THROTTLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVENC_THROTTLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVENC_THROTTLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVENC_THROTTLE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVENC_THROTTLE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_TARGET_MASK_WR_SECURE 0x00820614 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_TARGET_MASK_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_TARGET_MASK_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_TARGET_MASK_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_TARGET_MASK_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_TARGET_MASK_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FBPA_MEM_WR_SECURE 0x00820618 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FBPA_MEM_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FBPA_MEM_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FBPA_MEM_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FBPA_MEM_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FBPA_MEM_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FBIO_WR_SECURE 0x00820620 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FBIO_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FBIO_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FBIO_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FBIO_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FBIO_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_RD_SECURE 0x00820624 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_RD_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_RD_SECURE_DATA 4:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_RD_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_WR_SECURE 0x00820628 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_WR_SECURE_DATA 6:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENABLE_CR_JTAG_SECURITY 0x0082062C /* RW-4R */
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#define NV_FUSE_OPT_ENABLE_CR_JTAG_SECURITY__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENABLE_CR_JTAG_SECURITY_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_ENABLE_CR_JTAG_SECURITY_DATA_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_OPT_ENABLE_CR_JTAG_SECURITY_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_ENABLE_CR_JTAG_SECURITY_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE 0x00820630 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_REFURBISHED 0x00820634 /* RW-4R */
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#define NV_FUSE_OPT_REFURBISHED__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_REFURBISHED_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_REFURBISHED_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_REFURBISHED_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_REFURBISHED_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_JTAG_SECUREID_VALID 0x00820638 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_JTAG_SECUREID_VALID__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_JTAG_SECUREID_VALID_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_JTAG_SECUREID_VALID_DATA_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_JTAG_SECUREID_VALID_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_JTAG_SECUREID_VALID_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS 0x0082063C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS 0x00820640 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS 0x00820644 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_HS_DIS_NVDEC1 0x00820648 /* RW-4R */
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#define NV_FUSE_OPT_HS_DIS_NVDEC1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_HS_DIS_NVDEC1_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_HS_DIS_NVDEC1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HS_DIS_NVDEC1_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_HS_DIS_NVDEC1_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_HS_DIS_NVDEC2 0x0082066C /* RW-4R */
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#define NV_FUSE_OPT_HS_DIS_NVDEC2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_HS_DIS_NVDEC2_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_HS_DIS_NVDEC2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HS_DIS_NVDEC2_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_HS_DIS_NVDEC2_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FB_FALCON_PRI_ACCESS_DISABLE 0x00820670 /* RW-4R */
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#define NV_FUSE_OPT_FB_FALCON_PRI_ACCESS_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FB_FALCON_PRI_ACCESS_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FB_FALCON_PRI_ACCESS_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FB_FALCON_PRI_ACCESS_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FB_FALCON_PRI_ACCESS_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE 0x00820674 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE 0x00820678 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_VPR_ENABLED 0x0082067C /* RW-4R */
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#define NV_FUSE_OPT_VPR_ENABLED__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_VPR_ENABLED_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_VPR_ENABLED_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_VPR_ENABLED_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_VPR_ENABLED_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HDCP22_CTRL_WR_SECURE 0x00820680 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_HDCP22_CTRL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_HDCP22_CTRL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_HDCP22_CTRL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HDCP22_CTRL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HDCP22_CTRL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVLINK_DISABLE 0x00820684 /* RW-4R */
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#define NV_FUSE_OPT_NVLINK_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_NVLINK_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVLINK_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVLINK_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVLINK_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVLINK_DISABLE_CP 0x00820688 /* RW-4R */
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#define NV_FUSE_OPT_NVLINK_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVLINK_DISABLE_CP_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_NVLINK_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVLINK_DEFECTIVE 0x0082068C /* RW-4R */
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#define NV_FUSE_OPT_NVLINK_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVLINK_DEFECTIVE_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_NVLINK_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PES_DISABLE 0x00820690 /* RW-4R */
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#define NV_FUSE_OPT_PES_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_PES_DISABLE_DATA 20:0 /* RWIVF */
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#define NV_FUSE_OPT_PES_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PES_DISABLE_CP 0x00820694 /* RW-4R */
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#define NV_FUSE_OPT_PES_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PES_DISABLE_CP_DATA 20:0 /* RWIVF */
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#define NV_FUSE_OPT_PES_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PES_DEFECTIVE 0x00820698 /* RW-4R */
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#define NV_FUSE_OPT_PES_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PES_DEFECTIVE_DATA 20:0 /* RWIVF */
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#define NV_FUSE_OPT_PES_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RAM_RTSEL_TSMCSP 0x0082069C /* RW-4R */
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#define NV_FUSE_OPT_RAM_RTSEL_TSMCSP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RAM_RTSEL_TSMCSP_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_RAM_RTSEL_TSMCSP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RAM_WTSEL_TSMCSP 0x008206A0 /* RW-4R */
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#define NV_FUSE_OPT_RAM_WTSEL_TSMCSP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RAM_WTSEL_TSMCSP_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_RAM_WTSEL_TSMCSP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RAM_RTSEL_TSMCPDP 0x008206A4 /* RW-4R */
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#define NV_FUSE_OPT_RAM_RTSEL_TSMCPDP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RAM_RTSEL_TSMCPDP_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_RAM_RTSEL_TSMCPDP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RAM_MTSEL_TSMCPDP 0x008206A8 /* RW-4R */
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#define NV_FUSE_OPT_RAM_MTSEL_TSMCPDP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RAM_MTSEL_TSMCPDP_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_RAM_MTSEL_TSMCPDP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RAM_WTSEL_TSMCPDP 0x008206AC /* RW-4R */
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#define NV_FUSE_OPT_RAM_WTSEL_TSMCPDP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RAM_WTSEL_TSMCPDP_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_RAM_WTSEL_TSMCPDP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RAM_RCT_TSMCDP 0x008206B0 /* RW-4R */
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#define NV_FUSE_OPT_RAM_RCT_TSMCDP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RAM_RCT_TSMCDP_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_RAM_RCT_TSMCDP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RAM_WCT_TSMCDP 0x008206B4 /* RW-4R */
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#define NV_FUSE_OPT_RAM_WCT_TSMCDP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RAM_WCT_TSMCDP_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_RAM_WCT_TSMCDP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RAM_KP_TSMCDP 0x008206B8 /* RW-4R */
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#define NV_FUSE_OPT_RAM_KP_TSMCDP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RAM_KP_TSMCDP_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_RAM_KP_TSMCDP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_H0 0x008206BC /* RW-4R */
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#define NV_FUSE_H0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_H0_DATA 31:0 /* RWIVF */
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#define NV_FUSE_H0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_H1 0x008206C0 /* RW-4R */
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#define NV_FUSE_H1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_H1_DATA 31:0 /* RWIVF */
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#define NV_FUSE_H1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_H2 0x008206C4 /* RW-4R */
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#define NV_FUSE_H2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_H2_DATA 31:0 /* RWIVF */
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#define NV_FUSE_H2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_H3 0x008206C8 /* RW-4R */
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#define NV_FUSE_H3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_H3_DATA 31:0 /* RWIVF */
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#define NV_FUSE_H3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE 0x008206D0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE_DATA 23:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SCI_TEMP_COEFF_ADJ_A 0x008206D4 /* RW-4R */
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#define NV_FUSE_OPT_SCI_TEMP_COEFF_ADJ_A__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SCI_TEMP_COEFF_ADJ_A_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_SCI_TEMP_COEFF_ADJ_A_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SCI_TEMP_COEFF_ADJ_B 0x008206D8 /* RW-4R */
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#define NV_FUSE_OPT_SCI_TEMP_COEFF_ADJ_B__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SCI_TEMP_COEFF_ADJ_B_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_SCI_TEMP_COEFF_ADJ_B_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HDA_LPBK_DISABLE 0x008206DC /* RW-4R */
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#define NV_FUSE_OPT_HDA_LPBK_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_HDA_LPBK_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_HDA_LPBK_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HDA_LPBK_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_HDA_LPBK_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SW_VPR_ENABLED 0x008206F4 /* RW-4R */
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#define NV_FUSE_OPT_SW_VPR_ENABLED__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SW_VPR_ENABLED_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SW_VPR_ENABLED_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SW_VPR_ENABLED_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SW_VPR_ENABLED_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FUSE_UCODE_CTXSW_REV 0x008206F8 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_CTXSW_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_CTXSW_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_CTXSW_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS 0x008206FC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FUSE_UCODE_MINION_REV 0x00820700 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_MINION_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_MINION_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_MINION_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE 0x00820704 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE 0x00820708 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE 0x0082070C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_DATA_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FUSE_UCODE_FBFALCON_REV 0x00820710 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_FBFALCON_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_FBFALCON_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_FBFALCON_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PKC_PK_0 0x00820718 /* RW-4R */
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#define NV_FUSE_OPT_PKC_PK_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_PK_0_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_PK_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PKC_PK_1 0x0082071C /* RW-4R */
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#define NV_FUSE_OPT_PKC_PK_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_PK_1_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_PK_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PKC_PK_2 0x00820720 /* RW-4R */
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#define NV_FUSE_OPT_PKC_PK_2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_PK_2_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_PK_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PKC_PK_3 0x00820724 /* RW-4R */
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#define NV_FUSE_OPT_PKC_PK_3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_PK_3_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_PK_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PKC_PK_4 0x00820728 /* RW-4R */
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#define NV_FUSE_OPT_PKC_PK_4__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_PK_4_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_PK_4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PKC_PK_5 0x0082072C /* RW-4R */
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#define NV_FUSE_OPT_PKC_PK_5__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_PK_5_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_PK_5_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PKC_PK_6 0x00820730 /* RW-4R */
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#define NV_FUSE_OPT_PKC_PK_6__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_PK_6_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_PK_6_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PKC_PK_7 0x00820734 /* RW-4R */
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#define NV_FUSE_OPT_PKC_PK_7__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_PK_7_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_PK_7_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PKC_PK_SELECTION 0x00820738 /* RW-4R */
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#define NV_FUSE_OPT_PKC_PK_SELECTION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_PK_SELECTION_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_PK_SELECTION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PKC_PK_SELECTION_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PKC_PK_SELECTION_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PKC_PMU_ALGO_DISABLE 0x0082073C /* RW-4R */
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#define NV_FUSE_OPT_PKC_PMU_ALGO_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_PMU_ALGO_DISABLE_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_PMU_ALGO_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PKC_NVDEC_ALGO_DISABLE 0x00820740 /* RW-4R */
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#define NV_FUSE_OPT_PKC_NVDEC_ALGO_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_NVDEC_ALGO_DISABLE_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_NVDEC_ALGO_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PKC_SEC_ALGO_DISABLE 0x00820744 /* RW-4R */
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#define NV_FUSE_OPT_PKC_SEC_ALGO_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_SEC_ALGO_DISABLE_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_SEC_ALGO_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PKC_PK_ARRAY_INDEX 0x00820748 /* RW-4R */
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#define NV_FUSE_OPT_PKC_PK_ARRAY_INDEX__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_PK_ARRAY_INDEX_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_PK_ARRAY_INDEX_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS 0x0082074C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_SHA2_EN 0x00820750 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_SHA2_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_SHA2_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_SHA2_EN_DATA_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_SHA2_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_SHA2_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PKC_GSP_ALGO_DISABLE 0x00820754 /* RW-4R */
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#define NV_FUSE_OPT_PKC_GSP_ALGO_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PKC_GSP_ALGO_DISABLE_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_PKC_GSP_ALGO_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE 0x00820758 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_STANDARD_MODE 0x0082075C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_STANDARD_MODE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_STANDARD_MODE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_STANDARD_MODE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_STANDARD_MODE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HOST2JTAG_STANDARD_MODE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_TPC_GPC0_DISABLE 0x00820760 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC0_DISABLE__PRIV_LEVEL_MASK 0x008200D0 /* */
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#define NV_FUSE_OPT_TPC_GPC0_DISABLE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC0_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC1_DISABLE 0x00820764 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC1_DISABLE__PRIV_LEVEL_MASK 0x008200D0 /* */
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#define NV_FUSE_OPT_TPC_GPC1_DISABLE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC1_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC2_DISABLE 0x00820768 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC2_DISABLE__PRIV_LEVEL_MASK 0x008200D0 /* */
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#define NV_FUSE_OPT_TPC_GPC2_DISABLE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC2_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC3_DISABLE 0x0082076C /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC3_DISABLE__PRIV_LEVEL_MASK 0x008200D0 /* */
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#define NV_FUSE_OPT_TPC_GPC3_DISABLE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC3_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC4_DISABLE 0x00820770 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC4_DISABLE__PRIV_LEVEL_MASK 0x008200D0 /* */
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#define NV_FUSE_OPT_TPC_GPC4_DISABLE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC4_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC5_DISABLE 0x00820774 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC5_DISABLE__PRIV_LEVEL_MASK 0x008200D0 /* */
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#define NV_FUSE_OPT_TPC_GPC5_DISABLE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC5_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC6_DISABLE 0x00820778 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC6_DISABLE__PRIV_LEVEL_MASK 0x008200D0 /* */
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#define NV_FUSE_OPT_TPC_GPC6_DISABLE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC6_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC0_RECONFIG 0x00820788 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC0_RECONFIG__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_TPC_GPC0_RECONFIG_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC0_RECONFIG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC1_RECONFIG 0x0082078C /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC1_RECONFIG__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_TPC_GPC1_RECONFIG_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC1_RECONFIG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC2_RECONFIG 0x00820790 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC2_RECONFIG__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_TPC_GPC2_RECONFIG_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC2_RECONFIG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC3_RECONFIG 0x00820794 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC3_RECONFIG__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_TPC_GPC3_RECONFIG_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC3_RECONFIG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC4_RECONFIG 0x00820798 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC4_RECONFIG__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_TPC_GPC4_RECONFIG_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC4_RECONFIG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC5_RECONFIG 0x0082079C /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC5_RECONFIG__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_TPC_GPC5_RECONFIG_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC5_RECONFIG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_HEADER_PLAINTEXT 0x008207A0 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_HEADER_PLAINTEXT__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_HEADER_PLAINTEXT_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_HEADER_PLAINTEXT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RAM_SVOP_PDP_SMRF 0x008207A4 /* RW-4R */
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#define NV_FUSE_OPT_RAM_SVOP_PDP_SMRF__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RAM_SVOP_PDP_SMRF_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_RAM_SVOP_PDP_SMRF_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_XUSB_REG_SECURE_EN 0x008207C0 /* RW-4R */
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#define NV_FUSE_OPT_XUSB_REG_SECURE_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_XUSB_REG_SECURE_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_XUSB_REG_SECURE_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_XUSB_REG_SECURE_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_XUSB_REG_SECURE_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PPC_EXT_REG_ACCESS_DIS 0x008207C4 /* RW-4R */
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#define NV_FUSE_OPT_PPC_EXT_REG_ACCESS_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PPC_EXT_REG_ACCESS_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_PPC_EXT_REG_ACCESS_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PPC_EXT_REG_ACCESS_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PPC_EXT_REG_ACCESS_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE 0x008207C8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE 0x008207CC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE 0x008207D0 /* RW-4R */
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#define NV_FUSE_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_FMLA16 0x008207D4 /* RW-4R */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_FMLA16__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_FMLA16_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_FMLA16_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_FMLA32 0x008207D8 /* RW-4R */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_FMLA32__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_FMLA32_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_FMLA32_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA0 0x008207DC /* RW-4R */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA0_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA1 0x008207E0 /* RW-4R */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA1_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA2 0x008207E4 /* RW-4R */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA2_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA3 0x008207E8 /* RW-4R */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA3_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA4 0x008207EC /* RW-4R */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA4__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA4_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SM_SPEED_SELECT_IMLA4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PERLINK_DISABLE 0x008207F0 /* RW-4R */
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#define NV_FUSE_OPT_PERLINK_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_PERLINK_DISABLE_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_PERLINK_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HDCP_RAM_ACCESS_DIS 0x008207F4 /* RW-4R */
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#define NV_FUSE_OPT_HDCP_RAM_ACCESS_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_HDCP_RAM_ACCESS_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_HDCP_RAM_ACCESS_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HDCP_RAM_ACCESS_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_HDCP_RAM_ACCESS_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE 0x008207F8 /* RW-4R */
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#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FUSE_UCODE_NVJPG_REV 0x008207FC /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_NVJPG_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_NVJPG_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_NVJPG_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_0 0x00820B20 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_0_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_1 0x00820B24 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_1_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_2 0x00820B28 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_2_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_3 0x00820B2C /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_3_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_4 0x00820B30 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_4__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_4_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_5 0x00820B34 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_5__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_5_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_5_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_6 0x00820B38 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_6__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_6_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_6_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_7 0x00820B3C /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_7__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_7_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_7_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_8 0x00820B40 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_8__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_8_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_8_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_9 0x00820B44 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_9__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_9_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_9_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_10 0x00820B48 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_10__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_10_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_10_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_11 0x00820B4C /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_11__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_11_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_11_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_12 0x00820B50 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_12__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_12_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_12_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_13 0x00820B54 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_13__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_13_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_13_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_14 0x00820B58 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_14__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_14_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_14_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_15 0x00820B5C /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_15__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_15_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_15_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_16 0x00820B60 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_16__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_16_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_16_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_17 0x00820B64 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_17__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_17_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_17_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_18 0x00820B68 /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_18__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_18_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_18_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_19 0x00820B6C /* RW-4R */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_19__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_19_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_19_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE 0x00820B7C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_TPC_GPC6_DEFECTIVE 0x00820B84 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC6_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC6_DEFECTIVE_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC6_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC6_DISABLE_CP 0x00820B8C /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC6_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TPC_GPC6_DISABLE_CP_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC6_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TPC_GPC6_RECONFIG 0x00820B94 /* RW-4R */
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#define NV_FUSE_OPT_TPC_GPC6_RECONFIG__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_TPC_GPC6_RECONFIG_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_TPC_GPC6_RECONFIG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS 0x00820B98 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_USB2_CAL 0x00820B9C /* RW-4R */
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#define NV_FUSE_OPT_USB2_CAL__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_USB2_CAL_DATA 28:0 /* RWIVF */
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#define NV_FUSE_OPT_USB2_CAL_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE 0x00820BD0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE 0x00820BD4 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE 0x00820BD8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE 0x00820BDC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE 0x00820BE0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE 0x00820BE8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE 0x00820BEC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE 0x00820BF0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE 0x00820BF4 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE 0x00820BF8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_FMON_WR_SECURE 0x00820BFC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_CLOCKS_FMON_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_CLOCKS_FMON_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_CLOCKS_FMON_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_FMON_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_FMON_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE 0x00820E00 /* RW-4R */
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE 0x00820E04 /* RW-4R */
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SRAM_VMIN_BIN 0x00820E08 /* RW-4R */
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#define NV_FUSE_OPT_SRAM_VMIN_BIN__PRIV_LEVEL_MASK 0x008200E8 /* */
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#define NV_FUSE_OPT_SRAM_VMIN_BIN_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_SRAM_VMIN_BIN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SRAM_VMIN_BIN_REV 0x00820E0C /* RW-4R */
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#define NV_FUSE_OPT_SRAM_VMIN_BIN_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SRAM_VMIN_BIN_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_SRAM_VMIN_BIN_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE 0x00820E10 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FUSE_UCODE_XUSB_REV 0x00820E14 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_XUSB_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_XUSB_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_XUSB_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_IST_DISABLE 0x00820E18 /* RW-4R */
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#define NV_FUSE_OPT_IST_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_IST_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_IST_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_IST_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_IST_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_DEBUG_SW_OVERRIDE_ENABLE 0x00820E20 /* RW-4R */
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#define NV_FUSE_OPT_DEBUG_SW_OVERRIDE_ENABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_DEBUG_SW_OVERRIDE_ENABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_DEBUG_SW_OVERRIDE_ENABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DEBUG_SW_OVERRIDE_ENABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_DEBUG_SW_OVERRIDE_ENABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FUSE_UCODE_LSPMU_REV 0x00820E24 /* RW-4R */
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#define NV_FUSE_OPT_FUSE_UCODE_LSPMU_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_UCODE_LSPMU_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_UCODE_LSPMU_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_TSENSE_WR_SECURE 0x00821000 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_TSENSE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_TSENSE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_TSENSE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_TSENSE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_TSENSE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_TS_DIS_MASK 0x00821004 /* RW-4R */
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#define NV_FUSE_OPT_TS_DIS_MASK__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TS_DIS_MASK_DATA 20:0 /* RWIVF */
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#define NV_FUSE_OPT_TS_DIS_MASK_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TS_CAL_AVG 0x00821008 /* RW-4R */
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#define NV_FUSE_OPT_TS_CAL_AVG__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TS_CAL_AVG_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_TS_CAL_AVG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_0 0x0082100C /* RW-4R */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_0_DATA 4:0 /* RWIVF */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_1 0x00821010 /* RW-4R */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_1_DATA 4:0 /* RWIVF */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_2 0x00821014 /* RW-4R */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_2_DATA 4:0 /* RWIVF */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_3 0x00821018 /* RW-4R */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_3_DATA 4:0 /* RWIVF */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_4 0x0082101C /* RW-4R */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_4__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_4_DATA 4:0 /* RWIVF */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_5 0x00821020 /* RW-4R */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_5__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_5_DATA 4:0 /* RWIVF */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_5_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_6 0x00821024 /* RW-4R */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_6__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_6_DATA 4:0 /* RWIVF */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_6_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_7 0x00821028 /* RW-4R */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_7__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_7_DATA 4:0 /* RWIVF */
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#define NV_FUSE_OPT_TS_CAL_OFFSET_7_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ROW_REMAPPER_EN 0x0082102C /* RW-4R */
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#define NV_FUSE_OPT_ROW_REMAPPER_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ROW_REMAPPER_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_ROW_REMAPPER_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ROW_REMAPPER_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_ROW_REMAPPER_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_NV_P2P_PLM_WR_SECURE 0x00821030 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_NV_P2P_PLM_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_NV_P2P_PLM_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_NV_P2P_PLM_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_NV_P2P_PLM_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_NV_P2P_PLM_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE 0x00821034 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE 0x00821038 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_CWD_CYA_WR_SECURE 0x0082103C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_CWD_CYA_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_CWD_CYA_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_CWD_CYA_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_CWD_CYA_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_CWD_CYA_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_RAM_SVOP_PDPF 0x00821040 /* RW-4R */
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#define NV_FUSE_OPT_RAM_SVOP_PDPF__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RAM_SVOP_PDPF_DATA 5:0 /* RWIVF */
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#define NV_FUSE_OPT_RAM_SVOP_PDPF_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GCC_DBG_WR_SECURE 0x00821044 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_GCC_DBG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_GCC_DBG_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_GCC_DBG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_GCC_DBG_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_GCC_DBG_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE 0x00821050 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_FAN_WR_SECURE 0x00821054 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_FAN_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_FAN_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_FAN_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_FAN_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_FAN_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_RESENSE_DISABLE 0x00821058 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FUSE_RESENSE_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FUSE_RESENSE_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FUSE_RESENSE_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_RESENSE_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_RESENSE_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FUSE_FILE_VERSION 0x0082105C /* RW-4R */
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#define NV_FUSE_OPT_FUSE_FILE_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FUSE_FILE_VERSION_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FUSE_FILE_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SKU_ID 0x00821060 /* RW-4R */
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#define NV_FUSE_OPT_SKU_ID__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SKU_ID_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_SKU_ID_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_XV2CLK_RESET_RETIME_DISABLE 0x00821064 /* RW-4R */
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#define NV_FUSE_OPT_XV2CLK_RESET_RETIME_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_XV2CLK_RESET_RETIME_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_XV2CLK_RESET_RETIME_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_XV2CLK_RESET_RETIME_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_XV2CLK_RESET_RETIME_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_XVE_10B_TAG_REQUESTER_DISABLE 0x00821068 /* RW-4R */
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#define NV_FUSE_OPT_XVE_10B_TAG_REQUESTER_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_XVE_10B_TAG_REQUESTER_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_XVE_10B_TAG_REQUESTER_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_XVE_10B_TAG_REQUESTER_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_XVE_10B_TAG_REQUESTER_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE 0x0082106C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE 0x00821070 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE 0x00821074 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE 0x00821078 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE 0x0082107C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE 0x00821080 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_CPM0 0x00821088 /* RW-4R */
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#define NV_FUSE_OPT_CPM0__PRIV_LEVEL_MASK 0x008200EC /* */
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#define NV_FUSE_OPT_CPM0_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_CPM0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CPM1 0x0082108C /* RW-4R */
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#define NV_FUSE_OPT_CPM1__PRIV_LEVEL_MASK 0x008200EC /* */
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#define NV_FUSE_OPT_CPM1_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_CPM1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CPM2 0x00821090 /* RW-4R */
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#define NV_FUSE_OPT_CPM2__PRIV_LEVEL_MASK 0x008200EC /* */
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#define NV_FUSE_OPT_CPM2_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_CPM2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CPM_REV 0x00821094 /* RW-4R */
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#define NV_FUSE_OPT_CPM_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_CPM_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_CPM_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE 0x008210C0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SPI_CLK_DIV_SET_SEL 0x008210FC /* RW-4R */
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#define NV_FUSE_OPT_SPI_CLK_DIV_SET_SEL__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SPI_CLK_DIV_SET_SEL_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_SPI_CLK_DIV_SET_SEL_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVLIPT_RESET_COND_DISABLE 0x00821100 /* RW-4R */
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#define NV_FUSE_OPT_NVLIPT_RESET_COND_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVLIPT_RESET_COND_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVLIPT_RESET_COND_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVLIPT_RESET_COND_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVLIPT_RESET_COND_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVLIPT_RESET_SEQ_DISABLE 0x00821104 /* RW-4R */
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#define NV_FUSE_OPT_NVLIPT_RESET_SEQ_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVLIPT_RESET_SEQ_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVLIPT_RESET_SEQ_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVLIPT_RESET_SEQ_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVLIPT_RESET_SEQ_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_ROP_DISABLE 0x00821108 /* RW-4R */
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#define NV_FUSE_OPT_ROP_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_ROP_DISABLE_DATA 13:0 /* RWIVF */
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#define NV_FUSE_OPT_ROP_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ROP_DISABLE_CP 0x00821110 /* RW-4R */
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#define NV_FUSE_OPT_ROP_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ROP_DISABLE_CP_DATA 13:0 /* RWIVF */
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#define NV_FUSE_OPT_ROP_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ROP_DEFECTIVE 0x00821114 /* RW-4R */
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#define NV_FUSE_OPT_ROP_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ROP_DEFECTIVE_DATA 13:0 /* RWIVF */
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#define NV_FUSE_OPT_ROP_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SKED_CYA_WR_SECURE 0x00821118 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_SKED_CYA_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_SKED_CYA_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_SKED_CYA_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SKED_CYA_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SKED_CYA_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SKED_DEBUG_WR_SECURE 0x0082111C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_SKED_DEBUG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_SKED_DEBUG_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_SKED_DEBUG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SKED_DEBUG_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SKED_DEBUG_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_HDCP22_LC128_0 0x00821120 /* RW-4R */
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#define NV_FUSE_OPT_HDCP22_LC128_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_HDCP22_LC128_0_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_HDCP22_LC128_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HDCP22_LC128_1 0x00821124 /* RW-4R */
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#define NV_FUSE_OPT_HDCP22_LC128_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_HDCP22_LC128_1_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_HDCP22_LC128_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HDCP22_LC128_2 0x00821128 /* RW-4R */
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#define NV_FUSE_OPT_HDCP22_LC128_2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_HDCP22_LC128_2_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_HDCP22_LC128_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_HDCP22_LC128_3 0x0082112C /* RW-4R */
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#define NV_FUSE_OPT_HDCP22_LC128_3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_HDCP22_LC128_3_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_HDCP22_LC128_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE 0x00821130 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE 0x00821134 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE 0x00821138 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE 0x0082113C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE 0x00821140 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE 0x00821144 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE 0x00821148 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE 0x0082114C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE 0x00821150 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE 0x00821154 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE 0x00821158 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE 0x0082115C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE 0x00821160 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE 0x00821164 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE 0x00821168 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE 0x0082116C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE 0x00821170 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE 0x00821174 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE 0x00821178 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE 0x0082117C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE 0x00821180 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE 0x00821184 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE 0x00821188 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE 0x0082118C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE 0x00821190 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE 0x00821194 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE 0x00821198 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE 0x0082119C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE 0x008211A0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE 0x008211A4 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE 0x008211A8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE 0x008211AC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE 0x008211B0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE 0x008211B4 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE 0x008211B8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE 0x008211BC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE 0x008211C0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE 0x008211C4 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE 0x008211C8 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE 0x008211CC /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_DLPPE_WR_SECURE 0x008211D0 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_THERM_DLPPE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_THERM_DLPPE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_THERM_DLPPE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_THERM_DLPPE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_THERM_DLPPE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_UCODE_DRIVER_FUB_REV 0x008211D4 /* RW-4R */
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#define NV_FUSE_OPT_FPF_UCODE_DRIVER_FUB_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_UCODE_DRIVER_FUB_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_UCODE_DRIVER_FUB_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ROM_PMGR_SROM_FEEDBACK_MODE 0x008211D8 /* RW-4R */
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#define NV_FUSE_OPT_ROM_PMGR_SROM_FEEDBACK_MODE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ROM_PMGR_SROM_FEEDBACK_MODE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_ROM_PMGR_SROM_FEEDBACK_MODE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ROM_PMGR_SROM_FEEDBACK_MODE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_ROM_PMGR_SROM_FEEDBACK_MODE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PMGR_SROM_FEEDBACK_CLK_ADJ 0x008211DC /* RW-4R */
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#define NV_FUSE_OPT_PMGR_SROM_FEEDBACK_CLK_ADJ__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PMGR_SROM_FEEDBACK_CLK_ADJ_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_PMGR_SROM_FEEDBACK_CLK_ADJ_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PMGR_IFR_ROM_ADDR_OFFSET 0x008211E0 /* RW-4R */
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#define NV_FUSE_OPT_PMGR_IFR_ROM_ADDR_OFFSET__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PMGR_IFR_ROM_ADDR_OFFSET_DATA 21:0 /* RWIVF */
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#define NV_FUSE_OPT_PMGR_IFR_ROM_ADDR_OFFSET_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE 0x008211E4 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_L2SLICE_FBP0_DISABLE 0x00821200 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP0_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP0_DISABLE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP0_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP1_DISABLE 0x00821204 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP1_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP1_DISABLE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP1_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP2_DISABLE 0x00821208 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP2_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP2_DISABLE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP2_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP3_DISABLE 0x0082120C /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP3_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP3_DISABLE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP3_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP4_DISABLE 0x00821210 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP4_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP4_DISABLE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP4_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP5_DISABLE 0x00821214 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP5_DISABLE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP5_DISABLE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP5_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP0_DISABLE_CP 0x00821220 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP0_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP0_DISABLE_CP_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP0_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP1_DISABLE_CP 0x00821224 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP1_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP1_DISABLE_CP_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP1_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP2_DISABLE_CP 0x00821228 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP2_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP2_DISABLE_CP_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP2_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP3_DISABLE_CP 0x0082122C /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP3_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP3_DISABLE_CP_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP3_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP4_DISABLE_CP 0x00821230 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP4_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP4_DISABLE_CP_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP4_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP5_DISABLE_CP 0x00821234 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP5_DISABLE_CP__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP5_DISABLE_CP_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP5_DISABLE_CP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE 0x00821240 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP1_DEFECTIVE 0x00821244 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP1_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP1_DEFECTIVE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP1_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP2_DEFECTIVE 0x00821248 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP2_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP2_DEFECTIVE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP2_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP3_DEFECTIVE 0x0082124C /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP3_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP3_DEFECTIVE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP3_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE 0x00821250 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_L2SLICE_FBP5_DEFECTIVE 0x00821254 /* RW-4R */
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#define NV_FUSE_OPT_L2SLICE_FBP5_DEFECTIVE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_L2SLICE_FBP5_DEFECTIVE_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_L2SLICE_FBP5_DEFECTIVE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL 0x008212F8 /* RW-4R */
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_RASTER_SPEED_SELECT 0x008212FC /* RW-4R */
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#define NV_FUSE_OPT_RASTER_SPEED_SELECT__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RASTER_SPEED_SELECT_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_RASTER_SPEED_SELECT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_GPCRR_ENABLE 0x00821300 /* RW-4R */
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#define NV_FUSE_OPT_GPCRR_ENABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_GPCRR_ENABLE_DATA 6:0 /* RWIVF */
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#define NV_FUSE_OPT_GPCRR_ENABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CAL_FUSE_REV 0x00821304 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CAL_FUSE_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CAL_FUSE_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CAL_FUSE_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CAL_FUSE_TESTSTAGE 0x00821308 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CAL_FUSE_TESTSTAGE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CAL_FUSE_TESTSTAGE_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CAL_FUSE_TESTSTAGE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_FUSE_REV 0x00821350 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_FUSE_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_FUSE_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_FUSE_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE 0x00821378 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SPEEDO_ADJ 0x0082137C /* RW-4R */
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#define NV_FUSE_OPT_SPEEDO_ADJ__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SPEEDO_ADJ_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SPEEDO_ADJ_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SPEEDO_ADJ_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SPEEDO_ADJ_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_ISFI_DISABLE 0x00821380 /* RW-4R */
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#define NV_FUSE_OPT_ISFI_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ISFI_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_ISFI_DISABLE_DATA_INIT 0x00000001 /* RWI-V */
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#define NV_FUSE_OPT_ISFI_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_ISFI_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_FUSE_REV 0x00821398 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_FUSE_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_FUSE_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_FUSE_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_FUSE_REV 0x008213E0 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_FUSE_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_FUSE_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_FUSE_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ISENSE_ADC_FUSE_TESTSTAGE 0x008213E4 /* RW-4R */
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#define NV_FUSE_OPT_ISENSE_ADC_FUSE_TESTSTAGE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ISENSE_ADC_FUSE_TESTSTAGE_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_ISENSE_ADC_FUSE_TESTSTAGE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_KFUSE_WR_SECURE 0x00821600 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_KFUSE_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_KFUSE_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_KFUSE_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_KFUSE_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_KFUSE_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN 0x00821604 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_POD_SEC_FAULT_EN 0x00821608 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FUSE_POD_SEC_FAULT_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FUSE_POD_SEC_FAULT_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FUSE_POD_SEC_FAULT_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FUSE_POD_SEC_FAULT_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FUSE_POD_SEC_FAULT_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN 0x0082160C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_BLCG_RESET_PWR_SAVING_DISABLE 0x00821610 /* RW-4R */
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#define NV_FUSE_OPT_BLCG_RESET_PWR_SAVING_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_BLCG_RESET_PWR_SAVING_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_BLCG_RESET_PWR_SAVING_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_BLCG_RESET_PWR_SAVING_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_BLCG_RESET_PWR_SAVING_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVL_TS_DIS_MASK 0x00821700 /* RW-4R */
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#define NV_FUSE_OPT_NVL_TS_DIS_MASK__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVL_TS_DIS_MASK_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_NVL_TS_DIS_MASK_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PMGR_SROM_LEGACY_MODE_CYA 0x00821704 /* RW-4R */
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#define NV_FUSE_OPT_PMGR_SROM_LEGACY_MODE_CYA__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PMGR_SROM_LEGACY_MODE_CYA_DATA 1:0 /* RWIVF */
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#define NV_FUSE_OPT_PMGR_SROM_LEGACY_MODE_CYA_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE 0x00821710 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE 0x00821714 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_INTR_1_WR_SECURE 0x00821718 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_INTR_1_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_INTR_1_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_INTR_1_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_INTR_1_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_INTR_1_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_INTR_0_WR_SECURE 0x0082171C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_INTR_0_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_INTR_0_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_INTR_0_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_INTR_0_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_INTR_0_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE 0x00821720 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE 0x00821724 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE 0x00821728 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE 0x0082172C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE 0x00821730 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE 0x00821734 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE 0x00821738 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN 0x0082173C /* RW-4R */
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#define NV_FUSE_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN 0x00821740 /* RW-4R */
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#define NV_FUSE_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SEC_FAULT_RESET_EN 0x00821748 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_SEC_FAULT_RESET_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_SEC_FAULT_RESET_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_SEC_FAULT_RESET_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SEC_FAULT_RESET_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SEC_FAULT_RESET_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_GC6_BSI_RAM_RPG_ENABLE 0x0082174C /* RW-4R */
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#define NV_FUSE_OPT_GC6_BSI_RAM_RPG_ENABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_GC6_BSI_RAM_RPG_ENABLE_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_GC6_BSI_RAM_RPG_ENABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE 0x00821750 /* RW-4R */
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#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_RISCV_DCLS_EN 0x00821754 /* RW-4R */
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#define NV_FUSE_OPT_RISCV_DCLS_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RISCV_DCLS_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_RISCV_DCLS_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RISCV_DCLS_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_RISCV_DCLS_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_ISFI_WR_SECURE 0x00821760 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_ISFI_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_ISFI_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_ISFI_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_ISFI_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_ISFI_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_GSP_FALCON_BOOT_FROM_HS_EN 0x00821764 /* RW-4R */
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#define NV_FUSE_OPT_GSP_FALCON_BOOT_FROM_HS_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_GSP_FALCON_BOOT_FROM_HS_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_GSP_FALCON_BOOT_FROM_HS_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_GSP_FALCON_BOOT_FROM_HS_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_GSP_FALCON_BOOT_FROM_HS_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_GSP_FALCON_MOD_EN_AES_RO_EN 0x00821768 /* RW-4R */
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#define NV_FUSE_OPT_GSP_FALCON_MOD_EN_AES_RO_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_GSP_FALCON_MOD_EN_AES_RO_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_GSP_FALCON_MOD_EN_AES_RO_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_GSP_FALCON_MOD_EN_AES_RO_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_GSP_FALCON_MOD_EN_AES_RO_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SEC_FALCON_BOOT_FROM_HS_EN 0x0082176C /* RW-4R */
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#define NV_FUSE_OPT_SEC_FALCON_BOOT_FROM_HS_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SEC_FALCON_BOOT_FROM_HS_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SEC_FALCON_BOOT_FROM_HS_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SEC_FALCON_BOOT_FROM_HS_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SEC_FALCON_BOOT_FROM_HS_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SEC_FALCON_MOD_EN_AES_RO_EN 0x00821770 /* RW-4R */
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#define NV_FUSE_OPT_SEC_FALCON_MOD_EN_AES_RO_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SEC_FALCON_MOD_EN_AES_RO_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SEC_FALCON_MOD_EN_AES_RO_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SEC_FALCON_MOD_EN_AES_RO_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SEC_FALCON_MOD_EN_AES_RO_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PMU_FALCON_BOOT_FROM_HS_EN 0x00821774 /* RW-4R */
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#define NV_FUSE_OPT_PMU_FALCON_BOOT_FROM_HS_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PMU_FALCON_BOOT_FROM_HS_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_PMU_FALCON_BOOT_FROM_HS_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PMU_FALCON_BOOT_FROM_HS_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PMU_FALCON_BOOT_FROM_HS_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PMU_FALCON_MOD_EN_AES_RO_EN 0x00821778 /* RW-4R */
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#define NV_FUSE_OPT_PMU_FALCON_MOD_EN_AES_RO_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PMU_FALCON_MOD_EN_AES_RO_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_PMU_FALCON_MOD_EN_AES_RO_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PMU_FALCON_MOD_EN_AES_RO_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PMU_FALCON_MOD_EN_AES_RO_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_GSP_RISCV_DEV_DIS 0x0082177C /* RW-4R */
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#define NV_FUSE_OPT_GSP_RISCV_DEV_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_GSP_RISCV_DEV_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_GSP_RISCV_DEV_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_GSP_RISCV_DEV_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_GSP_RISCV_DEV_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SEC_RISCV_DEV_DIS 0x00821780 /* RW-4R */
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#define NV_FUSE_OPT_SEC_RISCV_DEV_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SEC_RISCV_DEV_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SEC_RISCV_DEV_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SEC_RISCV_DEV_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SEC_RISCV_DEV_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PMU_RISCV_DEV_DIS 0x00821784 /* RW-4R */
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#define NV_FUSE_OPT_PMU_RISCV_DEV_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PMU_RISCV_DEV_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_PMU_RISCV_DEV_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PMU_RISCV_DEV_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PMU_RISCV_DEV_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT 0x00821788 /* RW-4R */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT 0x0082178C /* RW-4R */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT 0x00821790 /* RW-4R */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE 0x00821798 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_MCLK_WR_SECURE 0x0082179C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_CLOCKS_MCLK_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_CLOCKS_MCLK_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_CLOCKS_MCLK_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_MCLK_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_CLOCKS_MCLK_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SEC_DEFAULT_CORE_SELECT 0x00821800 /* RW-4R */
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#define NV_FUSE_OPT_SEC_DEFAULT_CORE_SELECT__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SEC_DEFAULT_CORE_SELECT_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SEC_DEFAULT_CORE_SELECT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SEC_DEFAULT_CORE_SELECT_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SEC_DEFAULT_CORE_SELECT_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_PMU_DEFAULT_CORE_SELECT 0x00821804 /* RW-4R */
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#define NV_FUSE_OPT_PMU_DEFAULT_CORE_SELECT__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PMU_DEFAULT_CORE_SELECT_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_PMU_DEFAULT_CORE_SELECT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PMU_DEFAULT_CORE_SELECT_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_PMU_DEFAULT_CORE_SELECT_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_GSP_DEFAULT_CORE_SELECT 0x00821808 /* RW-4R */
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#define NV_FUSE_OPT_GSP_DEFAULT_CORE_SELECT__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_GSP_DEFAULT_CORE_SELECT_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_GSP_DEFAULT_CORE_SELECT_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_GSP_DEFAULT_CORE_SELECT_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_GSP_DEFAULT_CORE_SELECT_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE 0x00821814 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE 0x00821818 /* RW-4R */
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#define NV_FUSE_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE 0x0082181C /* RW-4R */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_IST_PRI_FILLER_WR_SECURE 0x00821820 /* RW-4R */
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#define NV_FUSE_OPT_IST_PRI_FILLER_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_IST_PRI_FILLER_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_IST_PRI_FILLER_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_IST_PRI_FILLER_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_IST_PRI_FILLER_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FB_TRIM_REV 0x00821824 /* RW-4R */
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#define NV_FUSE_OPT_FB_TRIM_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FB_TRIM_REV_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FB_TRIM_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION 0x00824100 /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION 0x00824104 /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION 0x00824108 /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION 0x0082410C /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION 0x00824110 /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION 0x00824114 /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION 0x00824118 /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION 0x0082411C /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION 0x00824120 /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION 0x00824124 /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION 0x00824128 /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION 0x0082412C /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION 0x00824130 /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION 0x00824134 /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION 0x00824138 /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION 0x0082413C /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION 0x00824140 /* RW-4R */
|
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#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION 0x00824144 /* RW-4R */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION 0x00824148 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION 0x0082414C /* RW-4R */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION_DATA 15:0 /* RWIVF */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION 0x00824150 /* RW-4R */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION_DATA 15:0 /* RWIVF */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION 0x00824154 /* RW-4R */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION 0x00824158 /* RW-4R */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION_DATA 15:0 /* RWIVF */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION 0x0082415C /* RW-4R */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION 0x00824160 /* RW-4R */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION 0x00824164 /* RW-4R */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION_DATA 15:0 /* RWIVF */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION 0x00824168 /* RW-4R */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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|
#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION 0x0082416C /* RW-4R */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION 0x00824170 /* RW-4R */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION 0x00824174 /* RW-4R */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION 0x00824178 /* RW-4R */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION 0x0082417C /* RW-4R */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_PMU_UCODE1_VERSION 0x00824180 /* RW-4R */
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#define NV_FUSE_OPT_FPF_PMU_UCODE1_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_PMU_UCODE1_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_PMU_UCODE1_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_PMU_UCODE2_VERSION 0x00824184 /* RW-4R */
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#define NV_FUSE_OPT_FPF_PMU_UCODE2_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_PMU_UCODE2_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_PMU_UCODE2_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_PMU_UCODE3_VERSION 0x00824188 /* RW-4R */
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#define NV_FUSE_OPT_FPF_PMU_UCODE3_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_PMU_UCODE3_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_PMU_UCODE3_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_PMU_UCODE4_VERSION 0x0082418C /* RW-4R */
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#define NV_FUSE_OPT_FPF_PMU_UCODE4_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_PMU_UCODE4_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_PMU_UCODE4_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_PMU_UCODE5_VERSION 0x00824190 /* RW-4R */
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#define NV_FUSE_OPT_FPF_PMU_UCODE5_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_PMU_UCODE5_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_PMU_UCODE5_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
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#define NV_FUSE_OPT_FPF_PMU_UCODE6_VERSION 0x00824194 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE6_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE6_VERSION_DATA 15:0 /* RWIVF */
|
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#define NV_FUSE_OPT_FPF_PMU_UCODE6_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE7_VERSION 0x00824198 /* RW-4R */
|
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#define NV_FUSE_OPT_FPF_PMU_UCODE7_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE7_VERSION_DATA 15:0 /* RWIVF */
|
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#define NV_FUSE_OPT_FPF_PMU_UCODE7_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE8_VERSION 0x0082419C /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE8_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE8_VERSION_DATA 15:0 /* RWIVF */
|
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#define NV_FUSE_OPT_FPF_PMU_UCODE8_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE9_VERSION 0x008241A0 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE9_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE9_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE9_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE10_VERSION 0x008241A4 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE10_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE10_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE10_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE11_VERSION 0x008241A8 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE11_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE11_VERSION_DATA 15:0 /* RWIVF */
|
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#define NV_FUSE_OPT_FPF_PMU_UCODE11_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE12_VERSION 0x008241AC /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE12_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE12_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE12_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE13_VERSION 0x008241B0 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE13_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE13_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE13_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE14_VERSION 0x008241B4 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE14_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE14_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE14_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE15_VERSION 0x008241B8 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE15_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE15_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE15_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE16_VERSION 0x008241BC /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE16_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE16_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE16_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION 0x008241C0 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION 0x008241C4 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION 0x008241C8 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION 0x008241CC /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION 0x008241D0 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION 0x008241D4 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION 0x008241D8 /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION 0x008241DC /* RW-4R */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION_DATA 15:0 /* RWIVF */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION 0x008241E0 /* RW-4R */
|
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#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION 0x008241E4 /* RW-4R */
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#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION 0x008241E8 /* RW-4R */
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#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION 0x008241EC /* RW-4R */
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#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION 0x008241F0 /* RW-4R */
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#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION 0x008241F4 /* RW-4R */
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#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION 0x008241F8 /* RW-4R */
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#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION 0x008241FC /* RW-4R */
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#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE1_VERSION 0x00824200 /* RW-4R */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE1_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE1_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE1_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE2_VERSION 0x00824204 /* RW-4R */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE2_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE2_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE2_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE3_VERSION 0x00824208 /* RW-4R */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE3_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE3_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE3_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE4_VERSION 0x0082420C /* RW-4R */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE4_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE4_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE4_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE5_VERSION 0x00824210 /* RW-4R */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE5_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE5_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE5_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE6_VERSION 0x00824214 /* RW-4R */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE6_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE6_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE6_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE7_VERSION 0x00824218 /* RW-4R */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE7_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE7_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE7_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE8_VERSION 0x0082421C /* RW-4R */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE8_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE8_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_XUSB_UCODE8_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE1_VERSION 0x00824220 /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE1_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE1_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE1_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE2_VERSION 0x00824224 /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE2_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE2_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE2_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE3_VERSION 0x00824228 /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE3_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE3_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE3_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE4_VERSION 0x0082422C /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE4_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE4_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE4_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE5_VERSION 0x00824230 /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE5_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE5_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE5_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE6_VERSION 0x00824234 /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE6_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE6_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE6_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE7_VERSION 0x00824238 /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE7_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE7_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE7_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE8_VERSION 0x0082423C /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE8_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE8_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE8_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_CTKID 0x00824240 /* RW-4R */
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#define NV_FUSE_OPT_FPF_CTKID__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_CTKID_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_CTKID_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_UCODE_SCRUBBER_BIN_REV 0x00824244 /* RW-4R */
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#define NV_FUSE_OPT_FPF_UCODE_SCRUBBER_BIN_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_UCODE_SCRUBBER_BIN_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_UCODE_SCRUBBER_BIN_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_UCODE_SEC2_REV 0x00824248 /* RW-4R */
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#define NV_FUSE_OPT_FPF_UCODE_SEC2_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_UCODE_SEC2_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_UCODE_SEC2_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_UCODE_PR_VPR_REV 0x0082424C /* RW-4R */
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#define NV_FUSE_OPT_FPF_UCODE_PR_VPR_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_UCODE_PR_VPR_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_UCODE_PR_VPR_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_UCODE_ACR_HS_REV 0x00824250 /* RW-4R */
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#define NV_FUSE_OPT_FPF_UCODE_ACR_HS_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_UCODE_ACR_HS_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_UCODE_ACR_HS_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_UCODE_GFW_REV 0x00824254 /* RW-4R */
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#define NV_FUSE_OPT_FPF_UCODE_GFW_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_UCODE_GFW_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_UCODE_GFW_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_UCODE_ROM_FLASH_REV 0x00824258 /* RW-4R */
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#define NV_FUSE_OPT_FPF_UCODE_ROM_FLASH_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_UCODE_ROM_FLASH_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_UCODE_ROM_FLASH_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_UCODE_NVDEC_REV 0x0082425C /* RW-4R */
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#define NV_FUSE_OPT_FPF_UCODE_NVDEC_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_UCODE_NVDEC_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_UCODE_NVDEC_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_UCODE_CTXSW_REV 0x00824260 /* RW-4R */
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#define NV_FUSE_OPT_FPF_UCODE_CTXSW_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_UCODE_CTXSW_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_UCODE_CTXSW_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_UCODE_FBFALCON_REV 0x00824264 /* RW-4R */
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#define NV_FUSE_OPT_FPF_UCODE_FBFALCON_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_UCODE_FBFALCON_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_UCODE_FBFALCON_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_UCODE_GSP_REV 0x00824268 /* RW-4R */
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#define NV_FUSE_OPT_FPF_UCODE_GSP_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_UCODE_GSP_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_UCODE_GSP_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_0 0x0082426C /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_0_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_1 0x00824270 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_1_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_2 0x00824274 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_2_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_3 0x00824278 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_3_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_4 0x0082427C /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_4__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_4_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_5 0x00824280 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_5__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_5_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_5_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_6 0x00824284 /* RW-4R */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_6__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_6_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_6_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_7 0x00824288 /* RW-4R */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_7__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_7_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_7_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_8 0x0082428C /* RW-4R */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_8__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_8_DATA 3:0 /* RWIVF */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_8_DATA_INIT 0x00000000 /* RWI-V */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_9 0x00824290 /* RW-4R */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_9__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_9_DATA 3:0 /* RWIVF */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_9_DATA_INIT 0x00000000 /* RWI-V */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_10 0x00824294 /* RW-4R */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_10__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_10_DATA 3:0 /* RWIVF */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_10_DATA_INIT 0x00000000 /* RWI-V */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_11 0x00824298 /* RW-4R */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_11__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_11_DATA 3:0 /* RWIVF */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_11_DATA_INIT 0x00000000 /* RWI-V */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_12 0x0082429C /* RW-4R */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_12__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_12_DATA 3:0 /* RWIVF */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_12_DATA_INIT 0x00000000 /* RWI-V */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_13 0x008242A0 /* RW-4R */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_13__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_13_DATA 3:0 /* RWIVF */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_13_DATA_INIT 0x00000000 /* RWI-V */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_14 0x008242A4 /* RW-4R */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_14__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_14_DATA 3:0 /* RWIVF */
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_14_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_15 0x008242A8 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_15__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_15_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_15_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_16 0x008242AC /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_16__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_16_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_16_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_17 0x008242B0 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_17__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_17_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_17_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_18 0x008242B4 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_18__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_18_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_18_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_19 0x008242B8 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_19__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_19_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_19_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_20 0x008242BC /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_20__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_20_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_20_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_21 0x008242C0 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_21__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_21_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_21_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_22 0x008242C4 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_22__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_22_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_22_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_23 0x008242C8 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_23__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_23_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_23_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_24 0x008242CC /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_24__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_24_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_24_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_25 0x008242D0 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_25__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_25_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_25_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_26 0x008242D4 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_26__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_26_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_26_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_27 0x008242D8 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_27__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_27_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_27_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_28 0x008242DC /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_28__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_28_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_28_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_29 0x008242E0 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_29__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_29_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_29_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_30 0x008242E4 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_30__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_30_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_30_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_31 0x008242E8 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_31__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_31_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_31_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_SKU_CONVERSION 0x008242EC /* RW-4R */
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#define NV_FUSE_OPT_FPF_SKU_CONVERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_SKU_CONVERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SKU_CONVERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT0 0x008242F0 /* RW-4R */
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT0_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT1 0x008242F4 /* RW-4R */
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT1_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_OVERLOCK_INFO 0x008242F8 /* RW-4R */
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#define NV_FUSE_OPT_FPF_OVERLOCK_INFO__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_OVERLOCK_INFO_DATA 3:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_OVERLOCK_INFO_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_0 0x008242FC /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_0_DATA 2:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_1 0x00824304 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_1_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_2 0x00824308 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_2_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3 0x0082430C /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4 0x00824310 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5 0x00824314 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6 0x00824318 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7 0x0082431C /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8 0x00824320 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9 0x00824324 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10 0x00824328 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11 0x0082432C /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12 0x00824330 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13 0x00824334 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14 0x00824338 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15 0x0082433C /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16 0x00824340 /* RW-4R */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_SEC_RISCV_PL3_DISABLE 0x00824344 /* RW-4R */
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#define NV_FUSE_OPT_FPF_SEC_RISCV_PL3_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_SEC_RISCV_PL3_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC_RISCV_PL3_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_SEC_RISCV_PL3_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_SEC_RISCV_PL3_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_PMU_RISCV_PL3_DISABLE 0x00824348 /* RW-4R */
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#define NV_FUSE_OPT_FPF_PMU_RISCV_PL3_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_PMU_RISCV_PL3_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_PMU_RISCV_PL3_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_PMU_RISCV_PL3_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_PMU_RISCV_PL3_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_GSP_RISCV_PL3_DISABLE 0x0082434C /* RW-4R */
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#define NV_FUSE_OPT_FPF_GSP_RISCV_PL3_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_GSP_RISCV_PL3_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_GSP_RISCV_PL3_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_GSP_RISCV_PL3_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_GSP_RISCV_PL3_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE 0x00824350 /* RW-4R */
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#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE 0x00824354 /* RW-4R */
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#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE 0x00824358 /* RW-4R */
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE9_VERSION 0x0082435C /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE9_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE9_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE9_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE10_VERSION 0x00824360 /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE10_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE10_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE10_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE11_VERSION 0x00824364 /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE11_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE11_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE11_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE12_VERSION 0x00824368 /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE12_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE12_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE12_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE13_VERSION 0x0082436C /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE13_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE13_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE13_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE14_VERSION 0x00824370 /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE14_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE14_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE14_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE15_VERSION 0x00824374 /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE15_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE15_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE15_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_MINION_UCODE16_VERSION 0x00824378 /* RW-4R */
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#define NV_FUSE_OPT_FPF_MINION_UCODE16_VERSION__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_MINION_UCODE16_VERSION_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_MINION_UCODE16_VERSION_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_UCODE_MINION_REV 0x0082437C /* RW-4R */
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#define NV_FUSE_OPT_FPF_UCODE_MINION_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_UCODE_MINION_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_UCODE_MINION_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS 0x00824380 /* RW-4R */
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#define NV_FUSE_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_GSP_FALCON_BR_VHR_DIS 0x00824384 /* RW-4R */
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#define NV_FUSE_OPT_FPF_GSP_FALCON_BR_VHR_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_GSP_FALCON_BR_VHR_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_GSP_FALCON_BR_VHR_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_GSP_FALCON_BR_VHR_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_GSP_FALCON_BR_VHR_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_SEC_FALCON_BR_VHR_DIS 0x00824388 /* RW-4R */
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#define NV_FUSE_OPT_FPF_SEC_FALCON_BR_VHR_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_SEC_FALCON_BR_VHR_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC_FALCON_BR_VHR_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_SEC_FALCON_BR_VHR_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_SEC_FALCON_BR_VHR_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_PMU_FALCON_BR_VHR_DIS 0x0082438C /* RW-4R */
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#define NV_FUSE_OPT_FPF_PMU_FALCON_BR_VHR_DIS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_PMU_FALCON_BR_VHR_DIS_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_PMU_FALCON_BR_VHR_DIS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_PMU_FALCON_BR_VHR_DIS_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_PMU_FALCON_BR_VHR_DIS_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN 0x00824390 /* RW-4R */
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN 0x00824394 /* RW-4R */
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN 0x00824398 /* RW-4R */
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_PRI_FILLER_WR_SECURE 0x0082439C /* RW-4R */
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#define NV_FUSE_OPT_FPF_PRI_FILLER_WR_SECURE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_PRI_FILLER_WR_SECURE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_PRI_FILLER_WR_SECURE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_PRI_FILLER_WR_SECURE_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_PRI_FILLER_WR_SECURE_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_UNLOCK 0x008243A0 /* RW-4R */
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_UNLOCK__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_UNLOCK_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_UNLOCK_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_UNLOCK_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_UNLOCK_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_LOCK 0x008243A4 /* RW-4R */
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_LOCK__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_LOCK_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_LOCK_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_LOCK_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_LOCK_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_IST_DISABLE 0x008243A8 /* RW-4R */
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#define NV_FUSE_OPT_FPF_IST_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_IST_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_IST_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_IST_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_IST_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_RMA_IST_ENABLE 0x008243AC /* RW-4R */
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#define NV_FUSE_OPT_FPF_RMA_IST_ENABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_RMA_IST_ENABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_RMA_IST_ENABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_RMA_IST_ENABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_RMA_IST_ENABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_RMA_IST_DISABLE 0x008243B0 /* RW-4R */
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#define NV_FUSE_OPT_FPF_RMA_IST_DISABLE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_RMA_IST_DISABLE_DATA 0:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_RMA_IST_DISABLE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FPF_RMA_IST_DISABLE_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_OPT_FPF_RMA_IST_DISABLE_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_FPF_UCODE_LSPMU_REV 0x008243B4 /* RW-4R */
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#define NV_FUSE_OPT_FPF_UCODE_LSPMU_REV__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FPF_UCODE_LSPMU_REV_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_FPF_UCODE_LSPMU_REV_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_0 0x008243B8 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_0_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_0_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_0_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_1 0x008243BC /* RW-4R */
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#define NV_FUSE_SPARE_BIT_1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_1_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_1_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_1_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_2 0x008243C0 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_2_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_2_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_2_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_3 0x008243C4 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_3_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_3_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_3_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_4 0x008243C8 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_4__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_4_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_4_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_4_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_5 0x008243CC /* RW-4R */
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#define NV_FUSE_SPARE_BIT_5__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_5_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_5_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_5_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_5_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_6 0x008243D0 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_6__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_6_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_6_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_6_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_6_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_7 0x008243D4 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_7__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_7_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_7_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_7_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_7_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_8 0x008243D8 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_8__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_8_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_8_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_8_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_8_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_9 0x008243DC /* RW-4R */
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#define NV_FUSE_SPARE_BIT_9__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_9_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_9_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_9_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_9_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_10 0x008243E0 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_10__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_10_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_10_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_10_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_10_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_11 0x008243E4 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_11__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_11_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_11_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_11_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_11_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_12 0x008243E8 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_12__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_12_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_12_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_12_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_12_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_13 0x008243EC /* RW-4R */
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#define NV_FUSE_SPARE_BIT_13__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_13_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_13_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_13_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_13_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_14 0x008243F0 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_14__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_14_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_14_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_14_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_14_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_15 0x008243F4 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_15__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_SPARE_BIT_15_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_15_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_15_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_15_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_16 0x008243F8 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_16__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_SPARE_BIT_16_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_16_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_16_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_16_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_17 0x008243FC /* RW-4R */
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#define NV_FUSE_SPARE_BIT_17__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_17_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_17_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_17_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_17_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_18 0x00824400 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_18__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_18_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_18_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_18_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_18_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_19 0x00824404 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_19__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_19_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_19_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_19_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_19_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_20 0x00824408 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_20__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_20_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_20_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_20_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_20_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_21 0x0082440C /* RW-4R */
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#define NV_FUSE_SPARE_BIT_21__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_21_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_21_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_21_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_21_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_22 0x00824410 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_22__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_22_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_22_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_22_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_22_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_23 0x00824414 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_23__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_23_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_23_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_23_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_23_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_24 0x00824418 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_24__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_24_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_24_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_24_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_24_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_25 0x0082441C /* RW-4R */
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#define NV_FUSE_SPARE_BIT_25__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_25_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_25_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_25_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_25_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_26 0x00824420 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_26__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_26_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_26_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_26_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_26_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_27 0x00824424 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_27__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_27_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_27_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_27_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_27_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_28 0x00824428 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_28__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_28_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_28_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_28_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_28_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_29 0x0082442C /* RW-4R */
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#define NV_FUSE_SPARE_BIT_29__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_29_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_29_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_29_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_29_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_30 0x00824430 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_30__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_30_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_30_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_30_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_30_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_31 0x00824434 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_31__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_31_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_31_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_31_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_31_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_32 0x00824438 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_32__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_32_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_32_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_32_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_32_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_33 0x0082443C /* RW-4R */
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#define NV_FUSE_SPARE_BIT_33__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_33_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_33_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_33_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_33_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_34 0x00824440 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_34__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_34_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_34_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_34_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_34_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_35 0x00824444 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_35__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_35_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_35_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_35_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_35_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_36 0x00824448 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_36__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_36_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_36_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_36_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_36_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_37 0x0082444C /* RW-4R */
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#define NV_FUSE_SPARE_BIT_37__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_37_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_37_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_37_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_37_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_38 0x00824450 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_38__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_38_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_38_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_38_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_38_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_39 0x00824454 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_39__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_39_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_39_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_39_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_39_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_40 0x00824458 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_40__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_40_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_40_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_40_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_40_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_41 0x0082445C /* RW-4R */
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#define NV_FUSE_SPARE_BIT_41__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_41_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_41_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_41_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_41_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_42 0x00824460 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_42__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_42_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_42_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_42_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_42_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_43 0x00824464 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_43__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_43_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_43_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_43_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_43_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_44 0x00824468 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_44__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_44_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_44_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_44_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_44_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_45 0x0082446C /* RW-4R */
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#define NV_FUSE_SPARE_BIT_45__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_45_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_45_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_45_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_45_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_46 0x00824470 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_46__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_46_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_46_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_46_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_46_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_47 0x00824474 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_47__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_47_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_47_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_47_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_47_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_48 0x00824478 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_48__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_48_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_48_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_48_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_48_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_49 0x0082447C /* RW-4R */
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#define NV_FUSE_SPARE_BIT_49__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_49_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_49_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_49_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_49_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_50 0x00824480 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_50__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_SPARE_BIT_50_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_50_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_50_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_50_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_51 0x00824484 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_51__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_SPARE_BIT_51_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_51_DATA_INIT 0x00000000 /* RWI-V */
|
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#define NV_FUSE_SPARE_BIT_51_DATA_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_FUSE_SPARE_BIT_51_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_52 0x00824488 /* RW-4R */
|
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#define NV_FUSE_SPARE_BIT_52__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_SPARE_BIT_52_DATA 0:0 /* RWIVF */
|
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#define NV_FUSE_SPARE_BIT_52_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_SPARE_BIT_52_DATA_DISABLE 0x00000000 /* RW--V */
|
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#define NV_FUSE_SPARE_BIT_52_DATA_ENABLE 0x00000001 /* RW--V */
|
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#define NV_FUSE_SPARE_BIT_53 0x0082448C /* RW-4R */
|
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#define NV_FUSE_SPARE_BIT_53__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_SPARE_BIT_53_DATA 0:0 /* RWIVF */
|
|
#define NV_FUSE_SPARE_BIT_53_DATA_INIT 0x00000000 /* RWI-V */
|
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#define NV_FUSE_SPARE_BIT_53_DATA_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_FUSE_SPARE_BIT_53_DATA_ENABLE 0x00000001 /* RW--V */
|
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#define NV_FUSE_SPARE_BIT_54 0x00824490 /* RW-4R */
|
|
#define NV_FUSE_SPARE_BIT_54__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_SPARE_BIT_54_DATA 0:0 /* RWIVF */
|
|
#define NV_FUSE_SPARE_BIT_54_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_SPARE_BIT_54_DATA_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_FUSE_SPARE_BIT_54_DATA_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_FUSE_SPARE_BIT_55 0x00824494 /* RW-4R */
|
|
#define NV_FUSE_SPARE_BIT_55__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_SPARE_BIT_55_DATA 0:0 /* RWIVF */
|
|
#define NV_FUSE_SPARE_BIT_55_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_SPARE_BIT_55_DATA_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_FUSE_SPARE_BIT_55_DATA_ENABLE 0x00000001 /* RW--V */
|
|
#define NV_FUSE_SPARE_BIT_56 0x00824498 /* RW-4R */
|
|
#define NV_FUSE_SPARE_BIT_56__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_SPARE_BIT_56_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_56_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_56_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_56_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_57 0x0082449C /* RW-4R */
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#define NV_FUSE_SPARE_BIT_57__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_57_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_57_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_57_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_57_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_58 0x008244A0 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_58__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_58_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_58_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_58_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_58_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_59 0x008244A4 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_59__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_59_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_59_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_59_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_59_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_60 0x008244A8 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_60__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_60_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_60_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_60_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_60_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_61 0x008244AC /* RW-4R */
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#define NV_FUSE_SPARE_BIT_61__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_61_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_61_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_61_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_61_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_62 0x008244B0 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_62__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_62_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_62_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_62_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_62_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_63 0x008244B4 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_63__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_63_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_63_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_63_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_63_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_64 0x008244B8 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_64__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_64_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_64_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_64_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_64_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_65 0x008244BC /* RW-4R */
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#define NV_FUSE_SPARE_BIT_65__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_65_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_65_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_65_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_65_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_66 0x008244C0 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_66__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_66_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_66_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_66_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_66_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_67 0x008244C4 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_67__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_67_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_67_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_67_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_67_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_68 0x008244C8 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_68__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_68_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_68_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_68_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_68_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_69 0x008244CC /* RW-4R */
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#define NV_FUSE_SPARE_BIT_69__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_69_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_69_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_69_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_69_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_70 0x008244D0 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_70__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_70_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_70_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_70_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_70_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_71 0x008244D4 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_71__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_71_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_71_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_71_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_71_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_72 0x008244D8 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_72__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_72_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_72_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_72_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_72_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_73 0x008244DC /* RW-4R */
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#define NV_FUSE_SPARE_BIT_73__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_73_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_73_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_73_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_73_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_74 0x008244E0 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_74__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_74_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_74_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_74_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_74_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_75 0x008244E4 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_75__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_75_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_75_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_75_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_75_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_76 0x008244E8 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_76__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_76_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_76_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_76_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_76_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_77 0x008244EC /* RW-4R */
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#define NV_FUSE_SPARE_BIT_77__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_77_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_77_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_77_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_77_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_78 0x008244F0 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_78__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_78_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_78_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_78_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_78_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_79 0x008244F4 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_79__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_79_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_79_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_79_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_79_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_80 0x008244F8 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_80__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_80_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_80_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_80_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_80_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_81 0x008244FC /* RW-4R */
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#define NV_FUSE_SPARE_BIT_81__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_81_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_81_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_81_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_81_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_82 0x00824500 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_82__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_82_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_82_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_82_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_82_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_83 0x00824504 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_83__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_83_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_83_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_83_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_83_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_84 0x00824508 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_84__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_84_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_84_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_84_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_84_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_85 0x0082450C /* RW-4R */
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#define NV_FUSE_SPARE_BIT_85__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_85_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_85_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_85_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_85_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_86 0x00824510 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_86__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_86_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_86_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_86_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_86_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_87 0x00824514 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_87__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_87_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_87_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_87_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_87_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_88 0x00824518 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_88__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_88_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_88_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_88_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_88_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_89 0x0082451C /* RW-4R */
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#define NV_FUSE_SPARE_BIT_89__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_89_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_89_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_89_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_89_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_90 0x00824520 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_90__PRIV_LEVEL_MASK 0x008200FC /* */
|
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#define NV_FUSE_SPARE_BIT_90_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_90_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_90_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_90_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_91 0x00824524 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_91__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_SPARE_BIT_91_DATA 0:0 /* RWIVF */
|
|
#define NV_FUSE_SPARE_BIT_91_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_SPARE_BIT_91_DATA_DISABLE 0x00000000 /* RW--V */
|
|
#define NV_FUSE_SPARE_BIT_91_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_ENDIS_0 0x00824528 /* RW-4R */
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|
#define NV_FUSE_SPARE_BIT_ENDIS_0__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_0_DATA 0:0 /* RWIVF */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_0_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_0_DATA_NO 0x00000000 /* RW--V */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_0_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_SPARE_BIT_ENDIS_1 0x0082452C /* RW-4R */
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#define NV_FUSE_SPARE_BIT_ENDIS_1__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_1_DATA 0:0 /* RWIVF */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_ENDIS_1_DATA_NO 0x00000000 /* RW--V */
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|
#define NV_FUSE_SPARE_BIT_ENDIS_1_DATA_YES 0x00000001 /* RW--V */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2 0x00824530 /* RW-4R */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2_DATA 0:0 /* RWIVF */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2_DATA_NO 0x00000000 /* RW--V */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2_DATA_YES 0x00000001 /* RW--V */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3 0x00824534 /* RW-4R */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3__PRIV_LEVEL_MASK 0x008200FC /* */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3_DATA 0:0 /* RWIVF */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3_DATA_INIT 0x00000000 /* RWI-V */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3_DATA_NO 0x00000000 /* RW--V */
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3_DATA_YES 0x00000001 /* RW--V */
|
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#define NV_FUSE_SPARE_BIT_ENDIS_4 0x00824538 /* RW-4R */
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#define NV_FUSE_SPARE_BIT_ENDIS_4__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_SPARE_BIT_ENDIS_4_DATA 0:0 /* RWIVF */
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#define NV_FUSE_SPARE_BIT_ENDIS_4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_SPARE_BIT_ENDIS_4_DATA_NO 0x00000000 /* RW--V */
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#define NV_FUSE_SPARE_BIT_ENDIS_4_DATA_YES 0x00000001 /* RW--V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_SHARED 0x00821354 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_SHARED__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_SHARED_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_SHARED_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_SHARED_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_SHARED_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_SHARED_CODE_DELTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_SHARED_CODE_DELTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC6 0x00821328 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CAL_GPC6__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC6_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CAL_GPC6_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CAL_GPC6_OFFSET_CALIBRATION_DATA 6:0 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC6_OFFSET_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC6_GAIN_CALIBRATION_DATA 11:7 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC6_GAIN_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC6_OFFSET_COARSE_CALIBRATION_DATA 15:12 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC6_OFFSET_COARSE_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC0 0x00821358 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC0_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC0_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC0_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC0_CODE_DELTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC0_CODE_DELTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_SHARED 0x0082139C /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_SHARED__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_SHARED_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_SHARED_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_SHARED_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_SHARED_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_SHARED_CODE_DEHTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_SHARED_CODE_DEHTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC1 0x00821314 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CAL_GPC1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC1_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CAL_GPC1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CAL_GPC1_OFFSET_CALIBRATION_DATA 6:0 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC1_OFFSET_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC1_GAIN_CALIBRATION_DATA 11:7 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC1_GAIN_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC1_OFFSET_COARSE_CALIBRATION_DATA 15:12 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC1_OFFSET_COARSE_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBB_PADS_TRIM 0x008211EC /* RW-4R */
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#define NV_FUSE_OPT_FBB_PADS_TRIM__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FBB_PADS_TRIM_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_FBB_PADS_TRIM_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FBB_PADS_TRIM_VAUXC_TRIM_DATA 2:0 /* */
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#define NV_FUSE_OPT_FBB_PADS_TRIM_VAUXC_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBB_PADS_TRIM_VAUXP_TRIM_DATA 5:3 /* */
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#define NV_FUSE_OPT_FBB_PADS_TRIM_VAUXP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBB_PADS_TRIM_VCLAMP_TRIM_DATA 8:6 /* */
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#define NV_FUSE_OPT_FBB_PADS_TRIM_VCLAMP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBB_PADS_TRIM_BGAP_TRIM_DATA 11:9 /* */
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#define NV_FUSE_OPT_FBB_PADS_TRIM_BGAP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_SENSE 0x008213E8 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CAL_SENSE__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_DATA 24:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_VCM_OFFSET_CALIBRATION_DATA 6:0 /* */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_VCM_OFFSET_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_DIFFERENTIAL_GAIN_CALIBRATION_DATA 11:7 /* */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_DIFFERENTIAL_GAIN_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_VCM_COARSE_CALIBRATION_DATA 15:12 /* */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_VCM_COARSE_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_DIFFERENTIAL_OFFSET_CALIBRATION_DATA 24:16 /* */
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#define NV_FUSE_OPT_ADC_CAL_SENSE_DIFFERENTIAL_OFFSET_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBF_PADS_TRIM 0x008211FC /* RW-4R */
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#define NV_FUSE_OPT_FBF_PADS_TRIM__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FBF_PADS_TRIM_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_FBF_PADS_TRIM_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FBF_PADS_TRIM_VAUXC_TRIM_DATA 2:0 /* */
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#define NV_FUSE_OPT_FBF_PADS_TRIM_VAUXC_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBF_PADS_TRIM_VAUXP_TRIM_DATA 5:3 /* */
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#define NV_FUSE_OPT_FBF_PADS_TRIM_VAUXP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBF_PADS_TRIM_VCLAMP_TRIM_DATA 8:6 /* */
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#define NV_FUSE_OPT_FBF_PADS_TRIM_VCLAMP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBF_PADS_TRIM_BGAP_TRIM_DATA 11:9 /* */
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#define NV_FUSE_OPT_FBF_PADS_TRIM_BGAP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC5 0x008213B4 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC5__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC5_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC5_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC5_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC5_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC5_CODE_DEHTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC5_CODE_DEHTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_D 0x00820520 /* RW-4R */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_D__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_D_DATA 31:0 /* RWIVF */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_D_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_D_RESERVED_0_DATA 24:0 /* */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_D_RESERVED_0_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_D_GEN4_SPEED_DISABLE_DATA 25:25 /* */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_D_GEN4_SPEED_DISABLE_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_D_GEN4_SPEED_DISABLE_DATA_DISABLE 0x00000000 /* */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_D_GEN4_SPEED_DISABLE_DATA_ENABLE 0x00000001 /* */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_D_RESERVED_1_DATA 31:26 /* */
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#define NV_FUSE_OPT_PCIE_MAGIC_BITS_D_RESERVED_1_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBD_PADS_TRIM 0x008211F4 /* RW-4R */
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#define NV_FUSE_OPT_FBD_PADS_TRIM__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FBD_PADS_TRIM_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_FBD_PADS_TRIM_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FBD_PADS_TRIM_VAUXC_TRIM_DATA 2:0 /* */
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#define NV_FUSE_OPT_FBD_PADS_TRIM_VAUXC_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBD_PADS_TRIM_VAUXP_TRIM_DATA 5:3 /* */
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#define NV_FUSE_OPT_FBD_PADS_TRIM_VAUXP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBD_PADS_TRIM_VCLAMP_TRIM_DATA 8:6 /* */
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#define NV_FUSE_OPT_FBD_PADS_TRIM_VCLAMP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBD_PADS_TRIM_BGAP_TRIM_DATA 11:9 /* */
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#define NV_FUSE_OPT_FBD_PADS_TRIM_BGAP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC2 0x00821360 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC2_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC2_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC2_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC2_CODE_DELTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC2_CODE_DELTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_CP2_TDIODE_OFFSET 0x00820120 /* RW-4R */
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#define NV_FUSE_OPT_CP2_TDIODE_OFFSET__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_CP2_TDIODE_OFFSET_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_CP2_TDIODE_OFFSET_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CP2_TDIODE_OFFSET_FRACTION_DATA 1:0 /* */
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#define NV_FUSE_OPT_CP2_TDIODE_OFFSET_FRACTION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_CP2_TDIODE_OFFSET_INTEGER_DATA 7:2 /* */
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#define NV_FUSE_OPT_CP2_TDIODE_OFFSET_INTEGER_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBC_PADS_TRIM 0x008211F0 /* RW-4R */
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#define NV_FUSE_OPT_FBC_PADS_TRIM__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FBC_PADS_TRIM_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_FBC_PADS_TRIM_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FBC_PADS_TRIM_VAUXC_TRIM_DATA 2:0 /* */
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#define NV_FUSE_OPT_FBC_PADS_TRIM_VAUXC_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBC_PADS_TRIM_VAUXP_TRIM_DATA 5:3 /* */
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#define NV_FUSE_OPT_FBC_PADS_TRIM_VAUXP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBC_PADS_TRIM_VCLAMP_TRIM_DATA 8:6 /* */
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#define NV_FUSE_OPT_FBC_PADS_TRIM_VCLAMP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBC_PADS_TRIM_BGAP_TRIM_DATA 11:9 /* */
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#define NV_FUSE_OPT_FBC_PADS_TRIM_BGAP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC6 0x008213B8 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC6__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC6_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC6_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC6_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC6_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC6_CODE_DEHTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC6_CODE_DEHTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC5 0x0082136C /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC5__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC5_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC5_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC5_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC5_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC5_CODE_DELTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC5_CODE_DELTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC3 0x00821364 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC3_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC3_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC3_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC3_CODE_DELTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC3_CODE_DELTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC1 0x008213A4 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC1_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC1_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC1_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC1_CODE_DEHTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC1_CODE_DEHTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC4 0x00821368 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC4__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC4_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC4_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC4_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC4_CODE_DELTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC4_CODE_DELTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC3 0x0082131C /* RW-4R */
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#define NV_FUSE_OPT_ADC_CAL_GPC3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC3_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CAL_GPC3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CAL_GPC3_OFFSET_CALIBRATION_DATA 6:0 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC3_OFFSET_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC3_GAIN_CALIBRATION_DATA 11:7 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC3_GAIN_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC3_OFFSET_COARSE_CALIBRATION_DATA 15:12 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC3_OFFSET_COARSE_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC6 0x00821370 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC6__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC6_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC6_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC6_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC6_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC6_CODE_DELTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC6_CODE_DELTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC0 0x00821310 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CAL_GPC0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC0_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CAL_GPC0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CAL_GPC0_OFFSET_CALIBRATION_DATA 6:0 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC0_OFFSET_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC0_GAIN_CALIBRATION_DATA 11:7 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC0_GAIN_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC0_OFFSET_COARSE_CALIBRATION_DATA 15:12 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC0_OFFSET_COARSE_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC4 0x00821320 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CAL_GPC4__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC4_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CAL_GPC4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CAL_GPC4_OFFSET_CALIBRATION_DATA 6:0 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC4_OFFSET_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC4_GAIN_CALIBRATION_DATA 11:7 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC4_GAIN_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC4_OFFSET_COARSE_CALIBRATION_DATA 15:12 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC4_OFFSET_COARSE_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC2 0x00821318 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CAL_GPC2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC2_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CAL_GPC2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CAL_GPC2_OFFSET_CALIBRATION_DATA 6:0 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC2_OFFSET_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC2_GAIN_CALIBRATION_DATA 11:7 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC2_GAIN_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC2_OFFSET_COARSE_CALIBRATION_DATA 15:12 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC2_OFFSET_COARSE_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC1 0x0082135C /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC1__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC1_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC1_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC1_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC1_CODE_DELTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_GPC1_CODE_DELTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC3 0x008213AC /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC3__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC3_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC3_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC3_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC3_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC3_CODE_DEHTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC3_CODE_DEHTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC4 0x008213B0 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC4__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC4_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC4_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC4_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC4_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC4_CODE_DEHTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC4_CODE_DEHTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_SHARED 0x0082130C /* RW-4R */
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#define NV_FUSE_OPT_ADC_CAL_SHARED__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CAL_SHARED_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CAL_SHARED_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CAL_SHARED_OFFSET_CALIBRATION_DATA 6:0 /* */
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#define NV_FUSE_OPT_ADC_CAL_SHARED_OFFSET_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_SHARED_GAIN_CALIBRATION_DATA 11:7 /* */
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#define NV_FUSE_OPT_ADC_CAL_SHARED_GAIN_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_SHARED_OFFSET_COARSE_CALIBRATION_DATA 15:12 /* */
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#define NV_FUSE_OPT_ADC_CAL_SHARED_OFFSET_COARSE_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC0 0x008213A0 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC0__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC0_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC0_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC0_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC0_CODE_DEHTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC0_CODE_DEHTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBA_PADS_TRIM 0x008211E8 /* RW-4R */
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#define NV_FUSE_OPT_FBA_PADS_TRIM__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FBA_PADS_TRIM_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_FBA_PADS_TRIM_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FBA_PADS_TRIM_VAUXC_TRIM_DATA 2:0 /* */
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#define NV_FUSE_OPT_FBA_PADS_TRIM_VAUXC_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBA_PADS_TRIM_VAUXP_TRIM_DATA 5:3 /* */
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#define NV_FUSE_OPT_FBA_PADS_TRIM_VAUXP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBA_PADS_TRIM_VCLAMP_TRIM_DATA 8:6 /* */
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#define NV_FUSE_OPT_FBA_PADS_TRIM_VCLAMP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBA_PADS_TRIM_BGAP_TRIM_DATA 11:9 /* */
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#define NV_FUSE_OPT_FBA_PADS_TRIM_BGAP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC2 0x008213A8 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC2__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC2_DATA 9:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC2_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC2_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC2_CODE_ERROR_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC2_CODE_DEHTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_GPC2_CODE_DEHTA_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBE_PADS_TRIM 0x008211F8 /* RW-4R */
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#define NV_FUSE_OPT_FBE_PADS_TRIM__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_FBE_PADS_TRIM_DATA 11:0 /* RWIVF */
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#define NV_FUSE_OPT_FBE_PADS_TRIM_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_FBE_PADS_TRIM_VAUXC_TRIM_DATA 2:0 /* */
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#define NV_FUSE_OPT_FBE_PADS_TRIM_VAUXC_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBE_PADS_TRIM_VAUXP_TRIM_DATA 5:3 /* */
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#define NV_FUSE_OPT_FBE_PADS_TRIM_VAUXP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBE_PADS_TRIM_VCLAMP_TRIM_DATA 8:6 /* */
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#define NV_FUSE_OPT_FBE_PADS_TRIM_VCLAMP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_FBE_PADS_TRIM_BGAP_TRIM_DATA 11:9 /* */
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#define NV_FUSE_OPT_FBE_PADS_TRIM_BGAP_TRIM_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_CP1_TDIODE_OFFSET 0x008204C8 /* RW-4R */
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#define NV_FUSE_OPT_CP1_TDIODE_OFFSET__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_CP1_TDIODE_OFFSET_DATA 7:0 /* RWIVF */
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#define NV_FUSE_OPT_CP1_TDIODE_OFFSET_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_CP1_TDIODE_OFFSET_FRACTION_DATA 1:0 /* */
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#define NV_FUSE_OPT_CP1_TDIODE_OFFSET_FRACTION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_CP1_TDIODE_OFFSET_INTEGER_DATA 7:2 /* */
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#define NV_FUSE_OPT_CP1_TDIODE_OFFSET_INTEGER_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC5 0x00821324 /* RW-4R */
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#define NV_FUSE_OPT_ADC_CAL_GPC5__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC5_DATA 15:0 /* RWIVF */
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#define NV_FUSE_OPT_ADC_CAL_GPC5_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_OPT_ADC_CAL_GPC5_OFFSET_CALIBRATION_DATA 6:0 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC5_OFFSET_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC5_GAIN_CALIBRATION_DATA 11:7 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC5_GAIN_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC5_OFFSET_COARSE_CALIBRATION_DATA 15:12 /* */
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#define NV_FUSE_OPT_ADC_CAL_GPC5_OFFSET_COARSE_CALIBRATION_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_NVJPG 0x0082080C /* RWI4R */
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#define NV_FUSE_CTRL_OPT_NVJPG__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_NVJPG_DATA 0:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_NVJPG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_NVJPG_DATA_ENABLE 0x00000000 /* RW--V */
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#define NV_FUSE_CTRL_OPT_NVJPG_DATA_DISABLE 0x00000001 /* RW--V */
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#define NV_FUSE_CTRL_OPT_NVJPG_IDX(i) (i):(i) /* */
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#define NV_FUSE_CTRL_OPT_NVJPG_IDX__SIZE_1 1 /* */
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#define NV_FUSE_CTRL_OPT_NVJPG_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_NVJPG_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_NVENC 0x00820968 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_NVENC__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_NVENC_DATA 0:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_NVENC_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_NVENC_DATA_ENABLE 0x00000000 /* RW--V */
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#define NV_FUSE_CTRL_OPT_NVENC_DATA_DISABLE 0x00000001 /* RW--V */
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#define NV_FUSE_CTRL_OPT_NVENC_IDX(i) (i):(i) /* */
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#define NV_FUSE_CTRL_OPT_NVENC_IDX__SIZE_1 1 /* */
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#define NV_FUSE_CTRL_OPT_NVENC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_NVENC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_ROP_GPC(i) (0x00822000+(i)*4) /* RWI4A */
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#define NV_FUSE_CTRL_OPT_ROP_GPC__SIZE_1 16 /* */
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#define NV_FUSE_CTRL_OPT_ROP_GPC__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_ROP_GPC_DATA 31:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_ROP_GPC_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_ROP_GPC_IDX(j) (j):(j) /* */
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#define NV_FUSE_CTRL_OPT_ROP_GPC_IDX__SIZE_1 32 /* */
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#define NV_FUSE_CTRL_OPT_ROP_GPC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_ROP_GPC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_SEC 0x00820828 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_SEC__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_SEC_DATA 0:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_SEC_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_SEC_DATA_ENABLE 0x00000000 /* RW--V */
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#define NV_FUSE_CTRL_OPT_SEC_DATA_DISABLE 0x00000001 /* RW--V */
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#define NV_FUSE_CTRL_OPT_FBP 0x00820938 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_FBP__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_FBP_DATA 15:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_FBP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_FBP_IDX(i) (i):(i) /* */
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#define NV_FUSE_CTRL_OPT_FBP_IDX__SIZE_1 16 /* */
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#define NV_FUSE_CTRL_OPT_FBP_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_FBP_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_OFA 0x00820BC0 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_OFA__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_OFA_DATA 0:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_OFA_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_OFA_DATA_ENABLE 0x00000000 /* RW--V */
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#define NV_FUSE_CTRL_OPT_OFA_DATA_DISABLE 0x00000001 /* RW--V */
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#define NV_FUSE_CTRL_OPT_OFA_IDX(i) (i):(i) /* */
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#define NV_FUSE_CTRL_OPT_OFA_IDX__SIZE_1 1 /* */
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#define NV_FUSE_CTRL_OPT_OFA_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_OFA_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_PERLINK 0x00820820 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_PERLINK__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_PERLINK_DATA 3:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_PERLINK_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_NVDEC 0x00820824 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_NVDEC__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_NVDEC_DATA 1:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_NVDEC_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_NVDEC_IDX(i) (i):(i) /* */
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#define NV_FUSE_CTRL_OPT_NVDEC_IDX__SIZE_1 2 /* */
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#define NV_FUSE_CTRL_OPT_NVDEC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_NVDEC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_PES_GPC(i) (0x008209bc+(i)*4) /* RWI4A */
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#define NV_FUSE_CTRL_OPT_PES_GPC__SIZE_1 16 /* */
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#define NV_FUSE_CTRL_OPT_PES_GPC__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_PES_GPC_DATA 15:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_PES_GPC_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_PES_GPC_IDX(j) (j):(j) /* */
|
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#define NV_FUSE_CTRL_OPT_PES_GPC_IDX__SIZE_1 16 /* */
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#define NV_FUSE_CTRL_OPT_PES_GPC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_PES_GPC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_FBIO 0x00820814 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_FBIO__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_FBIO_DATA 31:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_FBIO_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_FBIO_IDX(i) (i):(i) /* */
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#define NV_FUSE_CTRL_OPT_FBIO_IDX__SIZE_1 32 /* */
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#define NV_FUSE_CTRL_OPT_FBIO_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_FBIO_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_DISP_HEAD 0x00820808 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_DISP_HEAD__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_DISP_HEAD_DATA 3:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_DISP_HEAD_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_DISP_HEAD_IDX(i) (i):(i) /* */
|
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#define NV_FUSE_CTRL_OPT_DISP_HEAD_IDX__SIZE_1 4 /* */
|
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#define NV_FUSE_CTRL_OPT_DISP_HEAD_IDX_ENABLE 0x00000000 /* */
|
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#define NV_FUSE_CTRL_OPT_DISP_HEAD_IDX_DISABLE 0x00000001 /* */
|
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#define NV_FUSE_CTRL_OPT_GPC 0x0082081C /* RWI4R */
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#define NV_FUSE_CTRL_OPT_GPC__PRIV_LEVEL_MASK 0x008200DC /* */
|
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#define NV_FUSE_CTRL_OPT_GPC_DATA 31:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_GPC_DATA_INIT 0x00000000 /* RWI-V */
|
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#define NV_FUSE_CTRL_OPT_GPC_IDX(i) (i):(i) /* */
|
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#define NV_FUSE_CTRL_OPT_GPC_IDX__SIZE_1 32 /* */
|
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#define NV_FUSE_CTRL_OPT_GPC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_GPC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_SPARE_FS 0x00820830 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_SPARE_FS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_CTRL_OPT_SPARE_FS_DATA 31:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_SPARE_FS_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_SPARE_FS_IDX(i) (i):(i) /* */
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#define NV_FUSE_CTRL_OPT_SPARE_FS_IDX__SIZE_1 32 /* */
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#define NV_FUSE_CTRL_OPT_SPARE_FS_IDX_NO 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_SPARE_FS_IDX_YES 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_PCIE_LANE 0x0082082C /* RWI4R */
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#define NV_FUSE_CTRL_OPT_PCIE_LANE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_PCIE_LANE_DATA 1:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_PCIE_LANE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_PCIE_LANE_IDX(i) (i):(i) /* */
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#define NV_FUSE_CTRL_OPT_PCIE_LANE_IDX__SIZE_1 2 /* */
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#define NV_FUSE_CTRL_OPT_PCIE_LANE_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_PCIE_LANE_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_NVLINK 0x008209B8 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_NVLINK__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_NVLINK_DATA 15:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_NVLINK_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_NVLINK_IDX(i) (i):(i) /* */
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#define NV_FUSE_CTRL_OPT_NVLINK_IDX__SIZE_1 16 /* */
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#define NV_FUSE_CTRL_OPT_NVLINK_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_NVLINK_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_TPC_GPC(i) (0x00820838+(i)*4) /* RWI4A */
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#define NV_FUSE_CTRL_OPT_TPC_GPC__SIZE_1 32 /* */
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#define NV_FUSE_CTRL_OPT_TPC_GPC__PRIV_LEVEL_MASK 0x008200D0 /* */
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#define NV_FUSE_CTRL_OPT_TPC_GPC_DATA 31:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_TPC_GPC_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_TPC_GPC_IDX(j) (j):(j) /* */
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#define NV_FUSE_CTRL_OPT_TPC_GPC_IDX__SIZE_1 32 /* */
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#define NV_FUSE_CTRL_OPT_TPC_GPC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_TPC_GPC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_HALF_FBPA 0x00820800 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_HALF_FBPA__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_HALF_FBPA_DATA 31:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_HALF_FBPA_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_HALF_FBPA_IDX(i) (i):(i) /* */
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#define NV_FUSE_CTRL_OPT_HALF_FBPA_IDX__SIZE_1 32 /* */
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#define NV_FUSE_CTRL_OPT_HALF_FBPA_IDX_DISABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_HALF_FBPA_IDX_ENABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_GC6_ISLAND 0x0082096C /* RWI4R */
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#define NV_FUSE_CTRL_OPT_GC6_ISLAND__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_GC6_ISLAND_DATA 0:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_GC6_ISLAND_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_GC6_ISLAND_DATA_ENABLE 0x00000000 /* RW--V */
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#define NV_FUSE_CTRL_OPT_GC6_ISLAND_DATA_DISABLE 0x00000001 /* RW--V */
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#define NV_FUSE_CTRL_OPT_L2SLICE_FBP(i) (0x00822080+(i)*4) /* RWI4A */
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#define NV_FUSE_CTRL_OPT_L2SLICE_FBP__SIZE_1 16 /* */
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#define NV_FUSE_CTRL_OPT_L2SLICE_FBP__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_L2SLICE_FBP_DATA 31:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_L2SLICE_FBP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_L2SLICE_FBP_IDX(j) (j):(j) /* */
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#define NV_FUSE_CTRL_OPT_L2SLICE_FBP_IDX__SIZE_1 32 /* */
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#define NV_FUSE_CTRL_OPT_L2SLICE_FBP_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_L2SLICE_FBP_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_HALF_LTC 0x00820810 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_HALF_LTC__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_HALF_LTC_DATA 0:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_HALF_LTC_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_HALF_LTC_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_CTRL_OPT_HALF_LTC_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_CTRL_OPT_DISPLAY 0x00820804 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_DISPLAY__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_DISPLAY_DATA 0:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_DISPLAY_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_DISPLAY_DATA_ENABLE 0x00000000 /* RW--V */
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#define NV_FUSE_CTRL_OPT_DISPLAY_DATA_DISABLE 0x00000001 /* RW--V */
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#define NV_FUSE_CTRL_OPT_FB_CONFIG 0x00820834 /* RWI4R */
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#define NV_FUSE_CTRL_OPT_FB_CONFIG__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_CTRL_OPT_FB_CONFIG_DATA 3:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_FB_CONFIG_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_FB_CONFIG_IDX(i) (i):(i) /* */
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#define NV_FUSE_CTRL_OPT_FB_CONFIG_IDX__SIZE_1 4 /* */
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#define NV_FUSE_CTRL_OPT_FB_CONFIG_IDX_NO 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_FB_CONFIG_IDX_YES 0x00000001 /* */
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#define NV_FUSE_CTRL_OPT_LTC_FBP(i) (0x00820970+(i)*4) /* RWI4A */
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#define NV_FUSE_CTRL_OPT_LTC_FBP__SIZE_1 16 /* */
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#define NV_FUSE_CTRL_OPT_LTC_FBP__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_CTRL_OPT_LTC_FBP_DATA 31:0 /* RWIVF */
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#define NV_FUSE_CTRL_OPT_LTC_FBP_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_CTRL_OPT_LTC_FBP_IDX(j) (j):(j) /* */
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#define NV_FUSE_CTRL_OPT_LTC_FBP_IDX__SIZE_1 32 /* */
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#define NV_FUSE_CTRL_OPT_LTC_FBP_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_CTRL_OPT_LTC_FBP_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_NVJPG 0x00820C0C /* R-I4R */
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#define NV_FUSE_STATUS_OPT_NVJPG__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_NVJPG_DATA 0:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_NVJPG_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_NVJPG_DATA_ENABLE 0x00000000 /* R---V */
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#define NV_FUSE_STATUS_OPT_NVJPG_DATA_DISABLE 0x00000001 /* R---V */
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#define NV_FUSE_STATUS_OPT_NVJPG_IDX(i) (i):(i) /* */
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#define NV_FUSE_STATUS_OPT_NVJPG_IDX__SIZE_1 1 /* */
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#define NV_FUSE_STATUS_OPT_NVJPG_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_NVJPG_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_NVENC 0x00820D68 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_NVENC__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_NVENC_DATA 0:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_NVENC_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_NVENC_DATA_ENABLE 0x00000000 /* R---V */
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#define NV_FUSE_STATUS_OPT_NVENC_DATA_DISABLE 0x00000001 /* R---V */
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#define NV_FUSE_STATUS_OPT_NVENC_IDX(i) (i):(i) /* */
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#define NV_FUSE_STATUS_OPT_NVENC_IDX__SIZE_1 1 /* */
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#define NV_FUSE_STATUS_OPT_NVENC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_NVENC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_ROP_GPC(i) (0x00822880+(i)*4) /* R-I4A */
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#define NV_FUSE_STATUS_OPT_ROP_GPC__SIZE_1 16 /* */
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#define NV_FUSE_STATUS_OPT_ROP_GPC__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_ROP_GPC_DATA 31:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_ROP_GPC_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_ROP_GPC_IDX(j) (j):(j) /* */
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#define NV_FUSE_STATUS_OPT_ROP_GPC_IDX__SIZE_1 32 /* */
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#define NV_FUSE_STATUS_OPT_ROP_GPC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_ROP_GPC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_SEC 0x00820C28 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_SEC__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_SEC_DATA 0:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_SEC_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_SEC_DATA_ENABLE 0x00000000 /* R---V */
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#define NV_FUSE_STATUS_OPT_SEC_DATA_DISABLE 0x00000001 /* R---V */
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#define NV_FUSE_STATUS_OPT_FBP 0x00820D38 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_FBP__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_FBP_DATA 15:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_FBP_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_FBP_IDX(i) (i):(i) /* */
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#define NV_FUSE_STATUS_OPT_FBP_IDX__SIZE_1 16 /* */
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#define NV_FUSE_STATUS_OPT_FBP_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_FBP_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_OFA 0x00820E34 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_OFA__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_OFA_DATA 0:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_OFA_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_OFA_DATA_ENABLE 0x00000000 /* R---V */
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#define NV_FUSE_STATUS_OPT_OFA_DATA_DISABLE 0x00000001 /* R---V */
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#define NV_FUSE_STATUS_OPT_OFA_IDX(i) (i):(i) /* */
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#define NV_FUSE_STATUS_OPT_OFA_IDX__SIZE_1 1 /* */
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#define NV_FUSE_STATUS_OPT_OFA_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_OFA_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_PERLINK 0x00820C20 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_PERLINK__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_PERLINK_DATA 3:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_PERLINK_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_NVDEC 0x00820C24 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_NVDEC__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_NVDEC_DATA 1:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_NVDEC_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_NVDEC_IDX(i) (i):(i) /* */
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#define NV_FUSE_STATUS_OPT_NVDEC_IDX__SIZE_1 2 /* */
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#define NV_FUSE_STATUS_OPT_NVDEC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_NVDEC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_PES_GPC(i) (0x00820dbc+(i)*4) /* R-I4A */
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#define NV_FUSE_STATUS_OPT_PES_GPC__SIZE_1 16 /* */
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#define NV_FUSE_STATUS_OPT_PES_GPC__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_PES_GPC_DATA 15:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_PES_GPC_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_PES_GPC_IDX(j) (j):(j) /* */
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#define NV_FUSE_STATUS_OPT_PES_GPC_IDX__SIZE_1 16 /* */
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#define NV_FUSE_STATUS_OPT_PES_GPC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_PES_GPC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_FBIO 0x00820C14 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_FBIO__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_FBIO_DATA 31:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_FBIO_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_FBIO_IDX(i) (i):(i) /* */
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#define NV_FUSE_STATUS_OPT_FBIO_IDX__SIZE_1 32 /* */
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#define NV_FUSE_STATUS_OPT_FBIO_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_FBIO_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_DISP_HEAD 0x00820C08 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_DISP_HEAD__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_DISP_HEAD_DATA 3:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_DISP_HEAD_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_DISP_HEAD_IDX(i) (i):(i) /* */
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#define NV_FUSE_STATUS_OPT_DISP_HEAD_IDX__SIZE_1 4 /* */
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#define NV_FUSE_STATUS_OPT_DISP_HEAD_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_DISP_HEAD_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_GPC 0x00820C1C /* R-I4R */
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#define NV_FUSE_STATUS_OPT_GPC__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_GPC_DATA 31:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_GPC_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_GPC_IDX(i) (i):(i) /* */
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#define NV_FUSE_STATUS_OPT_GPC_IDX__SIZE_1 32 /* */
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#define NV_FUSE_STATUS_OPT_GPC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_GPC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_SPARE_FS 0x00820C30 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_SPARE_FS__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_STATUS_OPT_SPARE_FS_DATA 31:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_SPARE_FS_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_SPARE_FS_IDX(i) (i):(i) /* */
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#define NV_FUSE_STATUS_OPT_SPARE_FS_IDX__SIZE_1 32 /* */
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#define NV_FUSE_STATUS_OPT_SPARE_FS_IDX_NO 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_SPARE_FS_IDX_YES 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_PCIE_LANE 0x00820C2C /* R-I4R */
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#define NV_FUSE_STATUS_OPT_PCIE_LANE__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_PCIE_LANE_DATA 1:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_PCIE_LANE_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_PCIE_LANE_IDX(i) (i):(i) /* */
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#define NV_FUSE_STATUS_OPT_PCIE_LANE_IDX__SIZE_1 2 /* */
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#define NV_FUSE_STATUS_OPT_PCIE_LANE_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_PCIE_LANE_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_NVLINK 0x00820DB8 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_NVLINK__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_NVLINK_DATA 15:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_NVLINK_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_NVLINK_IDX(i) (i):(i) /* */
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#define NV_FUSE_STATUS_OPT_NVLINK_IDX__SIZE_1 16 /* */
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#define NV_FUSE_STATUS_OPT_NVLINK_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_NVLINK_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_TPC_GPC(i) (0x00820c38+(i)*4) /* R-I4A */
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#define NV_FUSE_STATUS_OPT_TPC_GPC__SIZE_1 32 /* */
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#define NV_FUSE_STATUS_OPT_TPC_GPC__PRIV_LEVEL_MASK 0x008200D0 /* */
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#define NV_FUSE_STATUS_OPT_TPC_GPC_DATA 31:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_TPC_GPC_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_TPC_GPC_IDX(j) (j):(j) /* */
|
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#define NV_FUSE_STATUS_OPT_TPC_GPC_IDX__SIZE_1 32 /* */
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#define NV_FUSE_STATUS_OPT_TPC_GPC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_TPC_GPC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_HALF_FBPA 0x00820C00 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_HALF_FBPA__PRIV_LEVEL_MASK 0x008200DC /* */
|
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#define NV_FUSE_STATUS_OPT_HALF_FBPA_DATA 31:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_HALF_FBPA_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_HALF_FBPA_IDX(i) (i):(i) /* */
|
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#define NV_FUSE_STATUS_OPT_HALF_FBPA_IDX__SIZE_1 32 /* */
|
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#define NV_FUSE_STATUS_OPT_HALF_FBPA_IDX_DISABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_HALF_FBPA_IDX_ENABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_GC6_ISLAND 0x00820D6C /* R-I4R */
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#define NV_FUSE_STATUS_OPT_GC6_ISLAND__PRIV_LEVEL_MASK 0x008200DC /* */
|
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#define NV_FUSE_STATUS_OPT_GC6_ISLAND_DATA 0:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_GC6_ISLAND_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_GC6_ISLAND_DATA_ENABLE 0x00000000 /* R---V */
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#define NV_FUSE_STATUS_OPT_GC6_ISLAND_DATA_DISABLE 0x00000001 /* R---V */
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#define NV_FUSE_STATUS_OPT_L2SLICE_FBP(i) (0x00822900+(i)*4) /* R-I4A */
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#define NV_FUSE_STATUS_OPT_L2SLICE_FBP__SIZE_1 16 /* */
|
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#define NV_FUSE_STATUS_OPT_L2SLICE_FBP__PRIV_LEVEL_MASK 0x008200DC /* */
|
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#define NV_FUSE_STATUS_OPT_L2SLICE_FBP_DATA 31:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_L2SLICE_FBP_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_L2SLICE_FBP_IDX(j) (j):(j) /* */
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#define NV_FUSE_STATUS_OPT_L2SLICE_FBP_IDX__SIZE_1 32 /* */
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#define NV_FUSE_STATUS_OPT_L2SLICE_FBP_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_L2SLICE_FBP_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_HALF_LTC 0x00820C10 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_HALF_LTC__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_HALF_LTC_DATA 0:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_HALF_LTC_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_HALF_LTC_DATA_DISABLE 0x00000000 /* R---V */
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#define NV_FUSE_STATUS_OPT_HALF_LTC_DATA_ENABLE 0x00000001 /* R---V */
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#define NV_FUSE_STATUS_OPT_DISPLAY 0x00820C04 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_DISPLAY__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_DISPLAY_DATA 0:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_DISPLAY_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_DISPLAY_DATA_ENABLE 0x00000000 /* R---V */
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#define NV_FUSE_STATUS_OPT_DISPLAY_DATA_DISABLE 0x00000001 /* R---V */
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#define NV_FUSE_STATUS_OPT_FB_CONFIG 0x00820C34 /* R-I4R */
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#define NV_FUSE_STATUS_OPT_FB_CONFIG__PRIV_LEVEL_MASK 0x008200FC /* */
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#define NV_FUSE_STATUS_OPT_FB_CONFIG_DATA 3:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_FB_CONFIG_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_FB_CONFIG_IDX(i) (i):(i) /* */
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#define NV_FUSE_STATUS_OPT_FB_CONFIG_IDX__SIZE_1 4 /* */
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#define NV_FUSE_STATUS_OPT_FB_CONFIG_IDX_NO 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_FB_CONFIG_IDX_YES 0x00000001 /* */
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#define NV_FUSE_STATUS_OPT_LTC_FBP(i) (0x00820d70+(i)*4) /* R-I4A */
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#define NV_FUSE_STATUS_OPT_LTC_FBP__SIZE_1 16 /* */
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#define NV_FUSE_STATUS_OPT_LTC_FBP__PRIV_LEVEL_MASK 0x008200DC /* */
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#define NV_FUSE_STATUS_OPT_LTC_FBP_DATA 31:0 /* R-IVF */
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#define NV_FUSE_STATUS_OPT_LTC_FBP_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_FUSE_STATUS_OPT_LTC_FBP_IDX(j) (j):(j) /* */
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#define NV_FUSE_STATUS_OPT_LTC_FBP_IDX__SIZE_1 32 /* */
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#define NV_FUSE_STATUS_OPT_LTC_FBP_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_STATUS_OPT_LTC_FBP_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_RECONFIG_OVERRIDE_OPT_TPC_GPC(i) (0x00820a40+(i)*4) /* RWI4A */
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#define NV_FUSE_RECONFIG_OVERRIDE_OPT_TPC_GPC__SIZE_1 32 /* */
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#define NV_FUSE_RECONFIG_OVERRIDE_OPT_TPC_GPC__PRIV_LEVEL_MASK 0x008200D8 /* */
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#define NV_FUSE_RECONFIG_OVERRIDE_OPT_TPC_GPC_DATA 31:0 /* RWIVF */
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#define NV_FUSE_RECONFIG_OVERRIDE_OPT_TPC_GPC_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_RECONFIG_OVERRIDE_OPT_TPC_GPC_IDX(j) (j):(j) /* */
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#define NV_FUSE_RECONFIG_OVERRIDE_OPT_TPC_GPC_IDX__SIZE_1 32 /* */
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#define NV_FUSE_RECONFIG_OVERRIDE_OPT_TPC_GPC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_RECONFIG_OVERRIDE_OPT_TPC_GPC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_DISABLE_EXTEND_OPT_TPC_GPC(i) (0x00822800+(i)*4) /* RWI4A */
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#define NV_FUSE_DISABLE_EXTEND_OPT_TPC_GPC__SIZE_1 32 /* */
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#define NV_FUSE_DISABLE_EXTEND_OPT_TPC_GPC__PRIV_LEVEL_MASK 0x008200D8 /* */
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#define NV_FUSE_DISABLE_EXTEND_OPT_TPC_GPC_DATA 31:0 /* RWIVF */
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#define NV_FUSE_DISABLE_EXTEND_OPT_TPC_GPC_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_FUSE_DISABLE_EXTEND_OPT_TPC_GPC_IDX(j) (j):(j) /* */
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#define NV_FUSE_DISABLE_EXTEND_OPT_TPC_GPC_IDX__SIZE_1 32 /* */
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#define NV_FUSE_DISABLE_EXTEND_OPT_TPC_GPC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_DISABLE_EXTEND_OPT_TPC_GPC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_KFUSE_STATE 0x00825c00 /* RW-4R */
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#define NV_FUSE_KFUSE_STATE__PRIV_LEVEL_MASK 0x00823b08 /* */
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#define NV_FUSE_KFUSE_STATE_CURBLOCK 5:0 /* R--VF */
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#define NV_FUSE_KFUSE_STATE_ERRBLOCK 13:8 /* R--VF */
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#define NV_FUSE_KFUSE_STATE_DONE 16:16 /* R--VF */
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#define NV_FUSE_KFUSE_STATE_CRCPASS 17:17 /* R--VF */
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#define NV_FUSE_KFUSE_STATE_RESTART 24:24 /* RWIVF */
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#define NV_FUSE_KFUSE_STATE_RESTART_INIT 0x0 /* RWI-V */
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#define NV_FUSE_KFUSE_STATE_RESTART_CMD_DONE 0x0 /* -W--T */
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#define NV_FUSE_KFUSE_STATE_STOP 25:25 /* RWIVF */
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#define NV_FUSE_KFUSE_STATE_STOP_INIT 0x0 /* RWI-V */
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#define NV_FUSE_KFUSE_STATE_RESET 31:31 /* RWIVF */
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#define NV_FUSE_KFUSE_STATE_RESET_INIT 0x0 /* RWI-V */
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#define NV_FUSE_KFUSE_ERRCOUNT 0x00825c04 /* R--4R */
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#define NV_FUSE_KFUSE_ERRCOUNT__PRIV_LEVEL_MASK 0x00823b08 /* */
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#define NV_FUSE_KFUSE_ERRCOUNT_ERR_1 6:0 /* R--VF */
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#define NV_FUSE_KFUSE_ERRCOUNT_ERR_2 14:8 /* R--VF */
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#define NV_FUSE_KFUSE_ERRCOUNT_ERR_3 22:16 /* R--VF */
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#define NV_FUSE_KFUSE_ERRCOUNT_ERR_FATAL 30:24 /* R--VF */
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#define NV_FUSE_KFUSE_KEYADDR 0x00825c08 /* RW-4R */
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#define NV_FUSE_KFUSE_KEYADDR__PRIV_LEVEL_MASK 0x00823b08 /* */
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#define NV_FUSE_KFUSE_KEYADDR_ADDR 7:0 /* RWIVF */
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#define NV_FUSE_KFUSE_KEYADDR_ADDR_INIT 0x0 /* RWI-V */
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#define NV_FUSE_KFUSE_KEYADDR_AUTOINC 16:16 /* RWIVF */
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#define NV_FUSE_KFUSE_KEYADDR_AUTOINC_INIT 0x1 /* RWI-V */
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#define NV_FUSE_KFUSE_KEYS 0x00825c0c /* R--4R */
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#define NV_FUSE_KFUSE_KEYS__PRIV_LEVEL_MASK 0x00823b08 /* */
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#define NV_FUSE_KFUSE_KEYS_DATA 31:0 /* R-XVF */
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#define NV_FUSE_KFUSE_DEBUG 0x00825c10 /* RW-4R */
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#define NV_FUSE_KFUSE_DEBUG__PRIV_LEVEL_MASK 0x00823b08 /* */
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#define NV_FUSE_KFUSE_DEBUG_KEYSREAD_EN 0:0 /* RWIVF */
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#define NV_FUSE_KFUSE_DEBUG_KEYSREAD_EN_INIT 0x0 /* RWI-V */
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#define NV_FUSE_KFUSE_KEYSET_STATUS 0x00825c14 /* R--4R */
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#define NV_FUSE_KFUSE_KEYSET_STATUS__PRIV_LEVEL_MASK 0x00823b08 /* */
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#define NV_FUSE_KFUSE_KEYSET_STATUS_KEYSET_CNT 12:0 /* R--VF */
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#define NV_FUSE_KFUSE_KEYSET_STATUS_HDCP1X_LEN 25:13 /* R--VF */
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#define NV_FUSE_KFUSE_KEYSET_STATUS_TRAN_DONE 26:26 /* R--VF */
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#define NV_FUSE_KFUSE_KEYSET_STATUS_RESERVED 31:27 /* R--VF */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO 0x00823808 /* RW-4R */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO__PRIV_LEVEL_MASK 0x00823804 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_SMOOTHLINE 1:0 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_SMOOTHLINE_QUADRO 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_SMOOTHLINE_CONSUMER1 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_SMOOTHLINE_CONSUMER2 0x00000002 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_SMOOTHLINE_CONSUMER3 0x00000003 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_SMOOTHLINE_OVERRIDE 3:3 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_SMOOTHLINE_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_SMOOTHLINE_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_POLYMODE 5:4 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_POLYMODE_QUADRO 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_POLYMODE_CONSUMER1 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_POLYMODE_CONSUMER2 0x00000002 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_POLYMODE_CONSUMER3 0x00000003 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_POLYMODE_OVERRIDE 7:7 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_POLYMODE_OVERRIDE_FALSE 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_POLYMODE_OVERRIDE_TRUE 0x00000001 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_TWOSIDED_LIGHT 9:8 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_TWOSIDED_LIGHT_QUADRO 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_TWOSIDED_LIGHT_CONSUMER1 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_TWOSIDED_LIGHT_CONSUMER2 0x00000002 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_TWOSIDED_LIGHT_CONSUMER3 0x00000003 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_TWOSIDED_LIGHT_OVERRIDE 11:11 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_TWOSIDED_LIGHT_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SETUP_TWOSIDED_LIGHT_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_TFQ 20:20 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_TFQ_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_TFQ_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_TFQ_OVERRIDE 23:23 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_TFQ_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_TFQ_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SM_TTU 24:24 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SM_TTU_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SM_TTU_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SM_TTU_OVERRIDE 25:25 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SM_TTU_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_QUADRO_SM_TTU_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC 0x0082380c /* RW-4R */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC__PRIV_LEVEL_MASK 0x00823800 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_LRF 0:0 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_LRF_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_LRF_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_LRF_OVERRIDE 3:3 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_LRF_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_LRF_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_L1_DATA 4:4 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_L1_DATA_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_L1_DATA_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_L1_DATA_OVERRIDE 7:7 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_L1_DATA_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_L1_DATA_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_L1_TAG 8:8 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_L1_TAG_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_L1_TAG_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_L1_TAG_OVERRIDE 11:11 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_L1_TAG_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_L1_TAG_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_LTC 12:12 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_LTC_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_LTC_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_LTC_OVERRIDE 15:15 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_LTC_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_LTC_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_DRAM 16:16 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_DRAM_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_DRAM_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_DRAM_OVERRIDE 19:19 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_DRAM_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_DRAM_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_CBU 20:20 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_CBU_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_CBU_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_CBU_OVERRIDE 23:23 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_CBU_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_SM_CBU_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1 0x00823810 /* RW-4R */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1__PRIV_LEVEL_MASK 0x00823800 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L0_ICACHE 0:0 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L0_ICACHE_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L0_ICACHE_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L0_ICACHE_OVERRIDE 1:1 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L0_ICACHE_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L0_ICACHE_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L1_ICACHE 2:2 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L1_ICACHE_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L1_ICACHE_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L1_ICACHE_OVERRIDE 3:3 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L1_ICACHE_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L1_ICACHE_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L1_MISS_LATENCY_FIFO 4:4 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L1_MISS_LATENCY_FIFO_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L1_MISS_LATENCY_FIFO_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L1_MISS_LATENCY_FIFO_OVERRIDE 5:5 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L1_MISS_LATENCY_FIFO_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_L1_MISS_LATENCY_FIFO_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_PIXRF 6:6 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_PIXRF_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_PIXRF_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_PIXRF_OVERRIDE 7:7 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_PIXRF_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_SM_PIXRF_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_LTC_L2_DCACHE_TAG 8:8 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_LTC_L2_DCACHE_TAG_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_LTC_L2_DCACHE_TAG_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_LTC_L2_DCACHE_TAG_OVERRIDE 9:9 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_LTC_L2_DCACHE_TAG_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_LTC_L2_DCACHE_TAG_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_FECS_FALCON 10:10 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_FECS_FALCON_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_FECS_FALCON_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_FECS_FALCON_OVERRIDE 11:11 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_FECS_FALCON_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_FECS_FALCON_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GPCCS_FALCON 12:12 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GPCCS_FALCON_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GPCCS_FALCON_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GPCCS_FALCON_OVERRIDE 13:13 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GPCCS_FALCON_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GPCCS_FALCON_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_PMU_FALCON 14:14 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_PMU_FALCON_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_PMU_FALCON_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_PMU_FALCON_OVERRIDE 15:15 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_PMU_FALCON_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_PMU_FALCON_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GCC_L1_5_CACHE 16:16 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GCC_L1_5_CACHE_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GCC_L1_5_CACHE_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GCC_L1_5_CACHE_OVERRIDE 17:17 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GCC_L1_5_CACHE_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GCC_L1_5_CACHE_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_HUBMMU 18:18 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_HUBMMU_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_HUBMMU_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_HUBMMU_OVERRIDE 19:19 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_HUBMMU_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_HUBMMU_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GPCMMU 20:20 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GPCMMU_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GPCMMU_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GPCMMU_OVERRIDE 21:21 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GPCMMU_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_GPCMMU_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_MINION_FALCON 22:22 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_MINION_FALCON_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_MINION_FALCON_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_MINION_FALCON_OVERRIDE 23:23 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_MINION_FALCON_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_1_MINION_FALCON_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_READOUT 0x00823814 /* R--4R */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_SMOOTHLINE 1:0 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_SMOOTHLINE_QUADRO 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_SMOOTHLINE_CONSUMER1 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_SMOOTHLINE_CONSUMER2 0x00000002 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_SMOOTHLINE_CONSUMER3 0x00000003 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_POLYMODE 3:2 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_POLYMODE_QUADRO 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_POLYMODE_CONSUMER1 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_POLYMODE_CONSUMER2 0x00000002 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_POLYMODE_CONSUMER3 0x00000003 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_TWOSIDED_LIGHT 5:4 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_TWOSIDED_LIGHT_QUADRO 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_TWOSIDED_LIGHT_CONSUMER1 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_TWOSIDED_LIGHT_CONSUMER2 0x00000002 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SETUP_TWOSIDED_LIGHT_CONSUMER3 0x00000003 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_TFQ 8:8 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_TFQ_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_TFQ_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SM_TTU 9:9 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SM_TTU_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_QUADRO_SM_TTU_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_LRF 12:12 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_LRF_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_LRF_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L1_DATA 13:13 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L1_DATA_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L1_DATA_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L1_TAG 14:14 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L1_TAG_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L1_TAG_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_LTC 15:15 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_LTC_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_LTC_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_DRAM 16:16 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_DRAM_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_DRAM_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_CBU 17:17 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_CBU_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_CBU_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L0_ICACHE 18:18 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L0_ICACHE_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L0_ICACHE_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L1_ICACHE 19:19 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L1_ICACHE_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L1_ICACHE_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L1_MISS_LATENCY_FIFO 23:23 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L1_MISS_LATENCY_FIFO_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_L1_MISS_LATENCY_FIFO_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_PIXRF 24:24 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_PIXRF_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_SM_PIXRF_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_LTC_L2_DCACHE_TAG 25:25 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_LTC_L2_DCACHE_TAG_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_LTC_L2_DCACHE_TAG_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_FECS_FALCON 26:26 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_FECS_FALCON_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_FECS_FALCON_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_GPCCS_FALCON 27:27 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_GPCCS_FALCON_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_GPCCS_FALCON_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_GCC_L1_5_CACHE 29:29 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_GCC_L1_5_CACHE_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_GCC_L1_5_CACHE_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_HUBMMU 30:30 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_HUBMMU_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_HUBMMU_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_GPCMMU 31:31 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_ECC_GPCMMU_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_ECC_GPCMMU_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1 0x00823818 /* R--4R */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA0 2:0 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA0_FULL_SPEED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA0_REDUCED_SPEED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_FMLA16 5:3 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_FMLA16_FULL_SPEED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_FMLA16_REDUCED_SPEED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_DP 6:6 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_DP_FULL_SPEED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_DP_REDUCED_SPEED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_FMLA32 9:7 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_FMLA32_FULL_SPEED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_FMLA32_REDUCED_SPEED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_FFMA 12:10 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_FFMA_FULL_SPEED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_FFMA_REDUCED_SPEED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA1 15:13 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA1_FULL_SPEED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA1_REDUCED_SPEED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA2 18:16 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA2_FULL_SPEED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA2_REDUCED_SPEED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA3 21:19 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA3_FULL_SPEED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA3_REDUCED_SPEED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA4 24:22 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA4_FULL_SPEED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_1_SM_SPEED_SELECT_IMLA4_REDUCED_SPEED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT 0x0082381c /* RW-4R */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT__PRIV_LEVEL_MASK 0x00823804 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA0 2:0 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA0_FULL_SPEED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA0_REDUCED_SPEED_1_2 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA0_REDUCED_SPEED_1_4 0x00000002 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA0_REDUCED_SPEED_1_8 0x00000003 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA0_REDUCED_SPEED_1_16 0x00000004 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA0_REDUCED_SPEED_1_32 0x00000005 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA0_REDUCED_SPEED_1_64 0x00000006 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA0_OVERRIDE 3:3 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA0_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA0_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA16 6:4 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA16_FULL_SPEED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA16_REDUCED_SPEED_1_2 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA16_REDUCED_SPEED_1_4 0x00000002 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA16_REDUCED_SPEED_1_8 0x00000003 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA16_REDUCED_SPEED_1_16 0x00000004 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA16_REDUCED_SPEED_1_32 0x00000005 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA16_OVERRIDE 7:7 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA16_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA16_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_DP 8:8 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_DP_FULL_SPEED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_DP_REDUCED_SPEED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_DP_OVERRIDE 11:11 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_DP_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_DP_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA32 14:12 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA32_FULL_SPEED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA32_REDUCED_SPEED_1_2 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA32_REDUCED_SPEED_1_4 0x00000002 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA32_REDUCED_SPEED_1_8 0x00000003 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA32_REDUCED_SPEED_1_16 0x00000004 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA32_REDUCED_SPEED_1_32 0x00000005 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA32_OVERRIDE 15:15 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA32_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FMLA32_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FFMA 18:16 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FFMA_FULL_SPEED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FFMA_REDUCED_SPEED_1_2 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FFMA_REDUCED_SPEED_1_4 0x00000002 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FFMA_REDUCED_SPEED_1_8 0x00000003 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FFMA_REDUCED_SPEED_1_16 0x00000004 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FFMA_REDUCED_SPEED_1_32 0x00000005 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FFMA_REDUCED_SPEED_1_64 0x00000006 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FFMA_OVERRIDE 19:19 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FFMA_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_FFMA_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA1 22:20 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA1_FULL_SPEED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA1_REDUCED_SPEED_1_2 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA1_REDUCED_SPEED_1_4 0x00000002 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA1_REDUCED_SPEED_1_8 0x00000003 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA1_REDUCED_SPEED_1_16 0x00000004 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA1_REDUCED_SPEED_1_32 0x00000005 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA1_REDUCED_SPEED_1_64 0x00000006 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA1_OVERRIDE 23:23 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA1_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA1_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA2 26:24 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA2_FULL_SPEED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA2_REDUCED_SPEED_1_2 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA2_REDUCED_SPEED_1_4 0x00000002 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA2_REDUCED_SPEED_1_8 0x00000003 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA2_REDUCED_SPEED_1_16 0x00000004 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA2_REDUCED_SPEED_1_32 0x00000005 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA2_REDUCED_SPEED_1_64 0x00000006 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA2_OVERRIDE 27:27 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA2_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA2_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA3 30:28 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA3_FULL_SPEED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA3_REDUCED_SPEED_1_2 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA3_REDUCED_SPEED_1_4 0x00000002 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA3_REDUCED_SPEED_1_8 0x00000003 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA3_REDUCED_SPEED_1_16 0x00000004 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA3_REDUCED_SPEED_1_32 0x00000005 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA3_REDUCED_SPEED_1_64 0x00000006 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA3_OVERRIDE 31:31 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA3_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_IMLA3_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_1 0x00823820 /* RW-4R */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_1__PRIV_LEVEL_MASK 0x00823804 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_1_IMLA4 2:0 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_1_IMLA4_FULL_SPEED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_1_IMLA4_REDUCED_SPEED_1_2 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_1_IMLA4_REDUCED_SPEED_1_4 0x00000002 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_1_IMLA4_REDUCED_SPEED_1_8 0x00000003 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_1_IMLA4_REDUCED_SPEED_1_16 0x00000004 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_1_IMLA4_REDUCED_SPEED_1_32 0x00000005 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_1_IMLA4_REDUCED_SPEED_1_64 0x00000006 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_1_IMLA4_OVERRIDE 3:3 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_1_IMLA4_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_SM_SPEED_SELECT_1_IMLA4_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ROW_REMAPPER 0x00823824 /* RW-4R */
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#define NV_FUSE_FEATURE_OVERRIDE_ROW_REMAPPER__PRIV_LEVEL_MASK 0x00823b00 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ROW_REMAPPER_DATA 0:0 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ROW_REMAPPER_DATA_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ROW_REMAPPER_DATA_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ROW_REMAPPER_OVERRIDE 1:1 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ROW_REMAPPER_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ROW_REMAPPER_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_READOUT_2 0x00823828 /* R--4R */
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#define NV_FUSE_FEATURE_READOUT_2_ROW_REMAPPER 0:0 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_2_ROW_REMAPPER_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_2_ROW_REMAPPER_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_2_ECC_LTC_CBC 1:1 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_2_ECC_LTC_CBC_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_2_ECC_LTC_CBC_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_2_ECC_SM_URF 2:2 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_2_ECC_SM_URF_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_2_ECC_SM_URF_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_2_ECC_MINION_FALCON 3:3 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_2_ECC_MINION_FALCON_DISABLED 0x00000000 /* R---V */
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#define NV_FUSE_FEATURE_READOUT_2_ECC_MINION_FALCON_ENABLED 0x00000001 /* R---V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2 0x0082382c /* RW-4R */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2__PRIV_LEVEL_MASK 0x00823800 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2_LTC_CBC 0:0 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2_LTC_CBC_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2_LTC_CBC_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2_LTC_CBC_OVERRIDE 1:1 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2_LTC_CBC_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2_LTC_CBC_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2_SM_URF 2:2 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2_SM_URF_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2_SM_URF_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2_SM_URF_OVERRIDE 3:3 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2_SM_URF_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_ECC_2_SM_URF_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT 0x00823830 /* RW-4R */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT__PRIV_LEVEL_MASK 0x00823b04 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_RASTER 1:0 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_RASTER_SLOW_DOWN 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_RASTER_REDUCED_SPEED_32 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_RASTER_REDUCED_SPEED_64 0x00000002 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_RASTER_REDUCED_SPEED_128 0x00000003 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_RASTER_OVERRIDE 2:2 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_RASTER_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_GFX_SPEED_SELECT_RASTER_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_READOUT_3 0x00823834 /* R--4R */
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#define NV_FUSE_FEATURE_READOUT_3_GFX_SPEED_SELECT_RASTER 1:0 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_3_GFX_SPEED_SELECT_RASTER_SLOW_DOWN 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_READOUT_3_GFX_SPEED_SELECT_RASTER_REDUCED_SPEED_32 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_READOUT_3_GFX_SPEED_SELECT_RASTER_REDUCED_SPEED_64 0x00000002 /* RW--V */
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#define NV_FUSE_FEATURE_READOUT_3_GFX_SPEED_SELECT_RASTER_REDUCED_SPEED_128 0x00000003 /* RW--V */
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#define NV_FUSE_FEATURE_READOUT_3_MEMQUAL_GLOBAL_POISON 2:2 /* R--VF */
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#define NV_FUSE_FEATURE_READOUT_3_MEMQUAL_GLOBAL_POISON_DIS 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_READOUT_3_MEMQUAL_GLOBAL_POISON_EN 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL 0x00823838 /* RW-4R */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL__PRIV_LEVEL_MASK 0x00823b18 /* */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_GLOBAL_POISON 0:0 /* RWXVF */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_GLOBAL_POISON_DIS 0x00000000 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_GLOBAL_POISON_EN 0x00000001 /* RW--V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_GLOBAL_POISON_OVERRIDE 1:1 /* RWIVF */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_GLOBAL_POISON_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_FUSE_FEATURE_OVERRIDE_MEMQUAL_GLOBAL_POISON_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR 0x00825800 /* R--4R */
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#define NV_FUSE_SECURITY_MONITOR_CLOCK_SOURCE 0:0 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_CLOCK_SOURCE_SECURE 0x00000000 /* R---V */
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#define NV_FUSE_SECURITY_MONITOR_CLOCK_SOURCE_UNSECURE 0x00000001 /* R---V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_STATUS 1:1 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_STATUS_RESET 0x00000000 /* R---V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_STATUS_FAULT 0x00000001 /* R---V */
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#define NV_FUSE_SECURITY_MONITOR_POD_STATUS 2:2 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_POD_STATUS_RESET 0x00000000 /* R---V */
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#define NV_FUSE_SECURITY_MONITOR_POD_STATUS_FAULT 0x00000001 /* R---V */
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#define NV_FUSE_RESHIFT_GPC_RAIL 0x00825808 /* RWE4R */
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#define NV_FUSE_RESHIFT_GPC_RAIL__PRIV_LEVEL_MASK 0x00823B0C /* */
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#define NV_FUSE_RESHIFT_GPC_RAIL_TRIGGER 0:0 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_RAIL_TRIGGER_START 0x00000001 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_TRIGGER_IDLE 0x00000000 /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_STATUS 1:1 /* R-EVF */
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#define NV_FUSE_RESHIFT_GPC_RAIL_STATUS_DONE 0x00000001 /* R---V */
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#define NV_FUSE_RESHIFT_GPC_RAIL_STATUS_NOT_DONE 0x00000000 /* R-E-V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA 0x0082580C /* RWE4R */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA__PRIV_LEVEL_MASK 0x00823B10 /* */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_HW_TRIGGER 0:0 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_HW_TRIGGER_DISABLE 0x00000000 /* RW--V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_HW_TRIGGER_ENABLE 0x00000001 /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_SW_TRIGGER 1:1 /* RWEVF */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_SW_TRIGGER_DISABLE 0x00000000 /* RWE-V */
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#define NV_FUSE_RESHIFT_GPC_CTRL_CYA_SW_TRIGGER_ENABLE 0x00000001 /* RW--V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL 0x00825810 /* RWE4R */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL__PRIV_LEVEL_MASK 0x00823B14 /* */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_RESET_VALUE 0:0 /* RWEVF */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_RESET_VALUE_ONE 0x00000001 /* RW--V */
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#define NV_FUSE_CLAMP_EN_RESET_CONTROL_RESET_VALUE_ZERO 0x00000000 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL 0x00825894 /* RWE4R */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL__PRIV_LEVEL_MASK 0x00823b1c /* */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_SCPM_EN 0:0 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_SCPM_EN_ENABLED 0x00000001 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_SCPM_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_CONFIG_VALID 4:4 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_CONFIG_VALID_ENABLED 0x00000001 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_CONFIG_VALID_DISABLED 0x00000000 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_RO_EN 5:5 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_RO_EN_DISABLED 0x00000000 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_RO_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_RESET_DIRECTN 6:6 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_RESET_DIRECTN_DISABLED 0x00000000 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_RESET_DIRECTN_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_DATAPATH_DEL_SEL 11:8 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_DATAPATH_DEL_SEL_INIT 0x00000007 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_MASK_TIMING_PATH 15:12 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_MASK_TIMING_PATH_INIT 0x00000000 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_SAMPLING_PERIOD 23:16 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_SAMPLING_PERIOD_INIT 0x00000000 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_SETUP 27:24 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_SETUP_INIT 0x00000000 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_PATH_ID 29:28 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_PATH_ID_INIT 0x00000003 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_FAULT_OVERRIDE_VALUE 31:31 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_FAULT_OVERRIDE_VALUE_CLEAR 0x00000000 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_CTRL_FAULT_OVERRIDE_VALUE_FAULTED 0x00000001 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_MON 0x00825898 /* R--4R */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_MON_HIGH_SOURCE_OUT 0:0 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_MON_HIGH_SOURCE_OUT_LOW 0x00000000 /* R---V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_MON_HIGH_SOURCE_OUT_HIGH 0x00000001 /* R---V */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_MON_OUTPUT 4:1 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_MON_PATH_TIMING_STATUS 8:5 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_SCPM_MON_RO_GRAY_COUNT 31:16 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL 0x0082589c /* RWE4R */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL__PRIV_LEVEL_MASK 0x00823b1c /* */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_POD_CHAR_CTRL_PRI 0:0 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_POD_CHAR_CTRL_PRI_DISABLED 0x00000000 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_POD_CHAR_CTRL_PRI_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_POD_EN 4:4 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_POD_EN_DISABLED 0x00000000 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_POD_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_POD_REQ_ENABLE 5:5 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_POD_REQ_ENABLE_DISABLED 0x00000000 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_POD_REQ_ENABLE_ENABLED 0x00000001 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_SPARE_IN 17:8 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_SPARE_IN_INIT 0x00000000 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_FAULT_OVERRIDE_VALUE 31:31 /* RWEVF */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_FAULT_OVERRIDE_VALUE_CLEAR 0x00000000 /* RWE-V */
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#define NV_FUSE_SECURITY_MONITOR_POD_CTRL_FAULT_OVERRIDE_VALUE_FAULTED 0x00000001 /* RW--V */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON 0x008258a0 /* R--4R */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON__PRIV_LEVEL_MASK 0x00823b1c /* */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_POD_CHAR_OBSERVE_PRI 1:0 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_POD_CHAR_OBSERVE_PRI_INIT 0x00000000 /* R---V */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_POD_CHAR_OBSERVE_PRI_0_STICKY 4:4 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_POD_CHAR_OBSERVE_PRI_0_STICKY_INIT 0x00000000 /* R---V */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_POD_CHAR_OBSERVE_JTAG 6:5 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_POD_CHAR_OBSERVE_JTAG_INIT 0x00000000 /* R---V */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_POD_CHAR_OBSERVE_JTAG_0_STICKY 7:7 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_POD_CHAR_OBSERVE_JTAG_0_STICKY_INIT 0x00000000 /* R---V */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_SPARE_OUT 17:8 /* R-EVF */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_SPARE_OUT_INIT 0x00000000 /* R-E-V */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_POD_FE_TRIGGER 24:24 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_POD_FE_TRIGGER_INIT 0x00000000 /* R---V */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_POD_BE_TRIGGER 25:25 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_POD_BE_TRIGGER_INIT 0x00000000 /* R---V */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_RST_REQ_N 26:26 /* R--VF */
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#define NV_FUSE_SECURITY_MONITOR_POD_MON_RST_REQ_N_INIT 0x00000000 /* R---V */
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#define NV_FUSE_ENABLE_FUSE_PROGRAM__WIDTH 1
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#define NV_FUSE_ENABLE_FUSE_PROGRAM__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_ENABLE_FUSE_PROGRAM__PRI_ALIAS_0_DATA 0:0
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#define NV_FUSE_ENABLE_FUSE_PROGRAM__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_ENABLE_FUSE_PROGRAM__RED_ALIAS_0 0x00000001
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#define NV_FUSE_ENABLE_FUSE_PROGRAM__RED_ALIAS_0_DATA 0:0
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#define NV_FUSE_ENABLE_FUSE_PROGRAM__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_DISABLE_FUSE_PROGRAM__WIDTH 1
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#define NV_FUSE_DISABLE_FUSE_PROGRAM__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_DISABLE_FUSE_PROGRAM__PRI_ALIAS_0_DATA 1:1
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#define NV_FUSE_DISABLE_FUSE_PROGRAM__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_DISABLE_FUSE_PROGRAM__RED_ALIAS_0 0x00000001
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#define NV_FUSE_DISABLE_FUSE_PROGRAM__RED_ALIAS_0_DATA 1:1
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#define NV_FUSE_DISABLE_FUSE_PROGRAM__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_JTAG_DIRECT_ACCESS_DISABLE__WIDTH 1
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#define NV_FUSE_JTAG_DIRECT_ACCESS_DISABLE__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_JTAG_DIRECT_ACCESS_DISABLE__PRI_ALIAS_0_DATA 1:1
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#define NV_FUSE_JTAG_DIRECT_ACCESS_DISABLE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_JTAG_DIRECT_ACCESS_DISABLE__RED_ALIAS_0 0x00000001
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#define NV_FUSE_JTAG_DIRECT_ACCESS_DISABLE__RED_ALIAS_0_DATA 1:1
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#define NV_FUSE_JTAG_DIRECT_ACCESS_DISABLE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_DISABLE_SW_OVERRIDE__WIDTH 1
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#define NV_FUSE_DISABLE_SW_OVERRIDE__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_DISABLE_SW_OVERRIDE__PRI_ALIAS_0_DATA 2:2
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#define NV_FUSE_DISABLE_SW_OVERRIDE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_DISABLE_SW_OVERRIDE__RED_ALIAS_0 0x00000001
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#define NV_FUSE_DISABLE_SW_OVERRIDE__RED_ALIAS_0_DATA 2:2
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#define NV_FUSE_DISABLE_SW_OVERRIDE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE__WIDTH 1
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#define NV_FUSE_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE__PRI_ALIAS_0_DATA 3:3
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#define NV_FUSE_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE__RED_ALIAS_0_DATA 3:3
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#define NV_FUSE_OPT_DEBUG_FEATURE_SW_OVERRIDE_ENABLE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURED_BURN_FEATURE_ENABLE__WIDTH 1
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#define NV_FUSE_OPT_SECURED_BURN_FEATURE_ENABLE__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURED_BURN_FEATURE_ENABLE__PRI_ALIAS_0_DATA 4:4
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#define NV_FUSE_OPT_SECURED_BURN_FEATURE_ENABLE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURED_BURN_FEATURE_ENABLE__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURED_BURN_FEATURE_ENABLE__RED_ALIAS_0_DATA 4:4
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#define NV_FUSE_OPT_SECURED_BURN_FEATURE_ENABLE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING__WIDTH 1
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#define NV_FUSE_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING__PRI_ALIAS_0_DATA 5:5
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#define NV_FUSE_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING__RED_ALIAS_0_DATA 5:5
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#define NV_FUSE_OPT_DISABLE_NONFPF_FUSE_PROGRAMMING__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_PRIVKEY_ACC_DIS__WIDTH 3
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#define NV_FUSE_OPT_PRIVKEY_ACC_DIS__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_PRIVKEY_ACC_DIS__PRI_ALIAS_0_DATA 8:6
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#define NV_FUSE_OPT_PRIVKEY_ACC_DIS__PRI_ALIAS_0_WIDTH 3
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#define NV_FUSE_OPT_PRIVKEY_ACC_DIS__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_PRIVKEY_ACC_DIS__RED_ALIAS_0_DATA 8:6
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#define NV_FUSE_OPT_PRIVKEY_ACC_DIS__RED_ALIAS_0_WIDTH 3
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#define NV_FUSE_OPT_DISABLE_FPF_FUSE_PROGRAMMING__WIDTH 1
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#define NV_FUSE_OPT_DISABLE_FPF_FUSE_PROGRAMMING__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_DISABLE_FPF_FUSE_PROGRAMMING__PRI_ALIAS_0_DATA 9:9
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#define NV_FUSE_OPT_DISABLE_FPF_FUSE_PROGRAMMING__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_DISABLE_FPF_FUSE_PROGRAMMING__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_DISABLE_FPF_FUSE_PROGRAMMING__RED_ALIAS_0_DATA 9:9
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#define NV_FUSE_OPT_DISABLE_FPF_FUSE_PROGRAMMING__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PRI_SOURCE_ISOLATION_EN__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PRI_SOURCE_ISOLATION_EN__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_PRI_SOURCE_ISOLATION_EN__PRI_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_SECURE_PRI_SOURCE_ISOLATION_EN__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PRI_SOURCE_ISOLATION_EN__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_PRI_SOURCE_ISOLATION_EN__RED_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_SECURE_PRI_SOURCE_ISOLATION_EN__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_PRIV_SEC_EN__WIDTH 1
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#define NV_FUSE_OPT_PRIV_SEC_EN__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_PRIV_SEC_EN__PRI_ALIAS_0_DATA 11:11
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#define NV_FUSE_OPT_PRIV_SEC_EN__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_PRIV_SEC_EN__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_PRIV_SEC_EN__RED_ALIAS_0_DATA 11:11
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#define NV_FUSE_OPT_PRIV_SEC_EN__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SFK_ACC_DIS__WIDTH 1
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#define NV_FUSE_OPT_SFK_ACC_DIS__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SFK_ACC_DIS__PRI_ALIAS_0_DATA 12:12
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#define NV_FUSE_OPT_SFK_ACC_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SFK_ACC_DIS__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SFK_ACC_DIS__RED_ALIAS_0_DATA 12:12
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#define NV_FUSE_OPT_SFK_ACC_DIS__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS__WIDTH 1
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS__PRI_ALIAS_0_DATA 13:13
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS__RED_ALIAS_0_DATA 13:13
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS_CONTROL__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS_CONTROL__PRI_ALIAS_0_DATA 14:14
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS_CONTROL__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS_CONTROL__RED_ALIAS_0_DATA 14:14
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#define NV_FUSE_OPT_SECURE_SECENGINE_DEBUG_DIS_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS__PRI_ALIAS_0_DATA 15:15
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS__RED_ALIAS_0_DATA 15:15
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS_CONTROL__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS_CONTROL__PRI_ALIAS_0_DATA 16:16
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS_CONTROL__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS_CONTROL__RED_ALIAS_0_DATA 16:16
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#define NV_FUSE_OPT_SECURE_PMU_DEBUG_DIS_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS__WIDTH 1
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS__PRI_ALIAS_0_DATA 17:17
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS__RED_ALIAS_0_DATA 17:17
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS_CONTROL__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS_CONTROL__PRI_ALIAS_0_DATA 18:18
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS_CONTROL__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS_CONTROL__RED_ALIAS_0_DATA 18:18
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#define NV_FUSE_OPT_SECURE_NVDEC_DEBUG_DIS_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS__WIDTH 1
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS__PRI_ALIAS_0_DATA 19:19
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS__RED_ALIAS_0_DATA 19:19
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS_CONTROL__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS_CONTROL__PRI_ALIAS_0_DATA 20:20
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS_CONTROL__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS_CONTROL__RED_ALIAS_0_DATA 20:20
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#define NV_FUSE_OPT_SECURE_MINION_DEBUG_DIS_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS__WIDTH 1
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS__PRI_ALIAS_0_DATA 21:21
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS__RED_ALIAS_0_DATA 21:21
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_CONTROL__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_CONTROL__PRI_ALIAS_0_DATA 22:22
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_CONTROL__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_CONTROL__RED_ALIAS_0_DATA 22:22
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#define NV_FUSE_OPT_SECURE_GSP_DEBUG_DIS_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_HDCP_RAM_ACCESS_DIS__WIDTH 1
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#define NV_FUSE_OPT_HDCP_RAM_ACCESS_DIS__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_HDCP_RAM_ACCESS_DIS__PRI_ALIAS_0_DATA 23:23
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#define NV_FUSE_OPT_HDCP_RAM_ACCESS_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_HDCP_RAM_ACCESS_DIS__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_HDCP_RAM_ACCESS_DIS__RED_ALIAS_0_DATA 23:23
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#define NV_FUSE_OPT_HDCP_RAM_ACCESS_DIS__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS__WIDTH 1
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS__PRI_ALIAS_0_DATA 24:24
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS__RED_ALIAS_0_DATA 24:24
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS_CONTROL__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS_CONTROL__PRI_ALIAS_0_DATA 25:25
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS_CONTROL__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS_CONTROL__RED_ALIAS_0_DATA 25:25
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#define NV_FUSE_OPT_SECURE_XUSB_DEBUG_DIS_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_DEBUG_SW_OVERRIDE_ENABLE__WIDTH 1
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#define NV_FUSE_OPT_DEBUG_SW_OVERRIDE_ENABLE__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_DEBUG_SW_OVERRIDE_ENABLE__PRI_ALIAS_0_DATA 26:26
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#define NV_FUSE_OPT_DEBUG_SW_OVERRIDE_ENABLE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_DEBUG_SW_OVERRIDE_ENABLE__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_DEBUG_SW_OVERRIDE_ENABLE__RED_ALIAS_0_DATA 26:26
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#define NV_FUSE_OPT_DEBUG_SW_OVERRIDE_ENABLE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_FUSE_RESENSE_DISABLE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_FUSE_RESENSE_DISABLE__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_SECURE_FUSE_RESENSE_DISABLE__PRI_ALIAS_0_DATA 27:27
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#define NV_FUSE_OPT_SECURE_FUSE_RESENSE_DISABLE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_FUSE_RESENSE_DISABLE__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_SECURE_FUSE_RESENSE_DISABLE__RED_ALIAS_0_DATA 27:27
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#define NV_FUSE_OPT_SECURE_FUSE_RESENSE_DISABLE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_XV2CLK_RESET_RETIME_DISABLE__WIDTH 1
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#define NV_FUSE_OPT_XV2CLK_RESET_RETIME_DISABLE__PRI_ALIAS_0 0x00000000
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#define NV_FUSE_OPT_XV2CLK_RESET_RETIME_DISABLE__PRI_ALIAS_0_DATA 28:28
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#define NV_FUSE_OPT_XV2CLK_RESET_RETIME_DISABLE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_XV2CLK_RESET_RETIME_DISABLE__RED_ALIAS_0 0x00000001
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#define NV_FUSE_OPT_XV2CLK_RESET_RETIME_DISABLE__RED_ALIAS_0_DATA 28:28
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#define NV_FUSE_OPT_XV2CLK_RESET_RETIME_DISABLE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C0_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C0_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_PMGR_I2C0_WR_SECURE__PRI_ALIAS_0_DATA 0:0
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#define NV_FUSE_OPT_SECURE_PMGR_I2C0_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C0_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PMGR_I2C0_WR_SECURE__RED_ALIAS_0_DATA 0:0
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#define NV_FUSE_OPT_SECURE_PMGR_I2C0_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C1_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C1_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_PMGR_I2C1_WR_SECURE__PRI_ALIAS_0_DATA 1:1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C1_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C1_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PMGR_I2C1_WR_SECURE__RED_ALIAS_0_DATA 1:1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C1_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C2_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C2_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_PMGR_I2C2_WR_SECURE__PRI_ALIAS_0_DATA 2:2
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#define NV_FUSE_OPT_SECURE_PMGR_I2C2_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C2_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PMGR_I2C2_WR_SECURE__RED_ALIAS_0_DATA 2:2
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#define NV_FUSE_OPT_SECURE_PMGR_I2C2_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC__WIDTH 1
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC__PRI_ALIAS_0_DATA 3:3
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC__RED_ALIAS_0_DATA 3:3
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#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ_MISC__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C3_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C3_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_PMGR_I2C3_WR_SECURE__PRI_ALIAS_0_DATA 4:4
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#define NV_FUSE_OPT_SECURE_PMGR_I2C3_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C3_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PMGR_I2C3_WR_SECURE__RED_ALIAS_0_DATA 4:4
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#define NV_FUSE_OPT_SECURE_PMGR_I2C3_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C4_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C4_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_PMGR_I2C4_WR_SECURE__PRI_ALIAS_0_DATA 5:5
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#define NV_FUSE_OPT_SECURE_PMGR_I2C4_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C4_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PMGR_I2C4_WR_SECURE__RED_ALIAS_0_DATA 5:5
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#define NV_FUSE_OPT_SECURE_PMGR_I2C4_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_HOST_DBG_BUS_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_HOST_DBG_BUS_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_HOST_DBG_BUS_WR_SECURE__PRI_ALIAS_0_DATA 6:6
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#define NV_FUSE_OPT_SECURE_HOST_DBG_BUS_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_HOST_DBG_BUS_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_HOST_DBG_BUS_WR_SECURE__RED_ALIAS_0_DATA 6:6
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#define NV_FUSE_OPT_SECURE_HOST_DBG_BUS_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C5_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C5_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_PMGR_I2C5_WR_SECURE__PRI_ALIAS_0_DATA 7:7
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#define NV_FUSE_OPT_SECURE_PMGR_I2C5_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C5_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PMGR_I2C5_WR_SECURE__RED_ALIAS_0_DATA 7:7
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#define NV_FUSE_OPT_SECURE_PMGR_I2C5_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE__PRI_ALIAS_0_DATA 8:8
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#define NV_FUSE_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE__RED_ALIAS_0_DATA 8:8
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#define NV_FUSE_OPT_SECURE_PMU_POWER_CONTROL_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C6_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C6_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_PMGR_I2C6_WR_SECURE__PRI_ALIAS_0_DATA 9:9
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#define NV_FUSE_OPT_SECURE_PMGR_I2C6_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C6_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PMGR_I2C6_WR_SECURE__RED_ALIAS_0_DATA 9:9
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#define NV_FUSE_OPT_SECURE_PMGR_I2C6_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_SRAM_ECC_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_SRAM_ECC_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_SRAM_ECC_WR_SECURE__PRI_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_SECURE_SRAM_ECC_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_SRAM_ECC_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_SRAM_ECC_WR_SECURE__RED_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_SECURE_SRAM_ECC_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C7_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C7_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_PMGR_I2C7_WR_SECURE__PRI_ALIAS_0_DATA 11:11
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#define NV_FUSE_OPT_SECURE_PMGR_I2C7_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C7_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PMGR_I2C7_WR_SECURE__RED_ALIAS_0_DATA 11:11
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#define NV_FUSE_OPT_SECURE_PMGR_I2C7_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_ADCS_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_ADCS_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_ADCS_WR_SECURE__PRI_ALIAS_0_DATA 12:12
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#define NV_FUSE_OPT_SECURE_ADCS_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_ADCS_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_ADCS_WR_SECURE__RED_ALIAS_0_DATA 12:12
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#define NV_FUSE_OPT_SECURE_ADCS_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C8_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C8_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_PMGR_I2C8_WR_SECURE__PRI_ALIAS_0_DATA 13:13
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#define NV_FUSE_OPT_SECURE_PMGR_I2C8_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C8_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PMGR_I2C8_WR_SECURE__RED_ALIAS_0_DATA 13:13
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#define NV_FUSE_OPT_SECURE_PMGR_I2C8_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C9_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C9_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_PMGR_I2C9_WR_SECURE__PRI_ALIAS_0_DATA 14:14
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#define NV_FUSE_OPT_SECURE_PMGR_I2C9_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_I2C9_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PMGR_I2C9_WR_SECURE__RED_ALIAS_0_DATA 14:14
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#define NV_FUSE_OPT_SECURE_PMGR_I2C9_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_IST_DISABLE_DEBUG_FEATURES__WIDTH 1
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#define NV_FUSE_OPT_IST_DISABLE_DEBUG_FEATURES__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_IST_DISABLE_DEBUG_FEATURES__PRI_ALIAS_0_DATA 15:15
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#define NV_FUSE_OPT_IST_DISABLE_DEBUG_FEATURES__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_IST_DISABLE_DEBUG_FEATURES__RED_ALIAS_0 0x00000003
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|
#define NV_FUSE_OPT_IST_DISABLE_DEBUG_FEATURES__RED_ALIAS_0_DATA 15:15
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#define NV_FUSE_OPT_IST_DISABLE_DEBUG_FEATURES__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_PADCTL_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_PADCTL_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_PMGR_PADCTL_WR_SECURE__PRI_ALIAS_0_DATA 16:16
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#define NV_FUSE_OPT_SECURE_PMGR_PADCTL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_PADCTL_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PMGR_PADCTL_WR_SECURE__RED_ALIAS_0_DATA 16:16
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#define NV_FUSE_OPT_SECURE_PMGR_PADCTL_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_PWR_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_PWR_WR_SECURE__PRI_ALIAS_0 0x00000002
|
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#define NV_FUSE_OPT_SECURE_PMGR_PWR_WR_SECURE__PRI_ALIAS_0_DATA 17:17
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#define NV_FUSE_OPT_SECURE_PMGR_PWR_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_PWR_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PMGR_PWR_WR_SECURE__RED_ALIAS_0_DATA 17:17
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#define NV_FUSE_OPT_SECURE_PMGR_PWR_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE__PRI_ALIAS_0_DATA 18:18
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#define NV_FUSE_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE__RED_ALIAS_0 0x00000003
|
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#define NV_FUSE_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE__RED_ALIAS_0_DATA 18:18
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#define NV_FUSE_OPT_SECURE_HOST_FB_TIMEOUT_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_ROM_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_ROM_WR_SECURE__PRI_ALIAS_0 0x00000002
|
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#define NV_FUSE_OPT_SECURE_PMGR_ROM_WR_SECURE__PRI_ALIAS_0_DATA 19:19
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#define NV_FUSE_OPT_SECURE_PMGR_ROM_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_ROM_WR_SECURE__RED_ALIAS_0 0x00000003
|
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#define NV_FUSE_OPT_SECURE_PMGR_ROM_WR_SECURE__RED_ALIAS_0_DATA 19:19
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#define NV_FUSE_OPT_SECURE_PMGR_ROM_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SM_TTU_EN__WIDTH 1
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#define NV_FUSE_OPT_SM_TTU_EN__PRI_ALIAS_0 0x00000002
|
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#define NV_FUSE_OPT_SM_TTU_EN__PRI_ALIAS_0_DATA 20:20
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#define NV_FUSE_OPT_SM_TTU_EN__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SM_TTU_EN__RED_ALIAS_0 0x00000003
|
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#define NV_FUSE_OPT_SM_TTU_EN__RED_ALIAS_0_DATA 20:20
|
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#define NV_FUSE_OPT_SM_TTU_EN__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SM_TTU_EN_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_SM_TTU_EN_CONTROL__PRI_ALIAS_0 0x00000002
|
|
#define NV_FUSE_OPT_SM_TTU_EN_CONTROL__PRI_ALIAS_0_DATA 21:21
|
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#define NV_FUSE_OPT_SM_TTU_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_SM_TTU_EN_CONTROL__RED_ALIAS_0 0x00000003
|
|
#define NV_FUSE_OPT_SM_TTU_EN_CONTROL__RED_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_SM_TTU_EN_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_WR_SECURE__PRI_ALIAS_0 0x00000002
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_WR_SECURE__PRI_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_WR_SECURE__RED_ALIAS_0 0x00000003
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_WR_SECURE__RED_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PJTAG_ACCESS_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PJTAG_ACCESS_WR_SECURE__PRI_ALIAS_0 0x00000002
|
|
#define NV_FUSE_OPT_SECURE_PJTAG_ACCESS_WR_SECURE__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_SECURE_PJTAG_ACCESS_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PJTAG_ACCESS_WR_SECURE__RED_ALIAS_0 0x00000003
|
|
#define NV_FUSE_OPT_SECURE_PJTAG_ACCESS_WR_SECURE__RED_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_SECURE_PJTAG_ACCESS_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_RST_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_RST_WR_SECURE__PRI_ALIAS_0 0x00000002
|
|
#define NV_FUSE_OPT_SECURE_PMU_RST_WR_SECURE__PRI_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_SECURE_PMU_RST_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_RST_WR_SECURE__RED_ALIAS_0 0x00000003
|
|
#define NV_FUSE_OPT_SECURE_PMU_RST_WR_SECURE__RED_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_SECURE_PMU_RST_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FUSE_UCODE_NVENC_REV__WIDTH 4
|
|
#define NV_FUSE_OPT_FUSE_UCODE_NVENC_REV__PRI_ALIAS_0 0x00000002
|
|
#define NV_FUSE_OPT_FUSE_UCODE_NVENC_REV__PRI_ALIAS_0_DATA 28:25
|
|
#define NV_FUSE_OPT_FUSE_UCODE_NVENC_REV__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FUSE_UCODE_NVENC_REV__RED_ALIAS_0 0x00000003
|
|
#define NV_FUSE_OPT_FUSE_UCODE_NVENC_REV__RED_ALIAS_0_DATA 28:25
|
|
#define NV_FUSE_OPT_FUSE_UCODE_NVENC_REV__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE__PRI_ALIAS_0 0x00000002
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE__PRI_ALIAS_0_DATA 29:29
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE__RED_ALIAS_0_DATA 29:29
|
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#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_ECC_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_THERM_FANTACH_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_THERM_FANTACH_WR_SECURE__PRI_ALIAS_0 0x00000002
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#define NV_FUSE_OPT_SECURE_THERM_FANTACH_WR_SECURE__PRI_ALIAS_0_DATA 30:30
|
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#define NV_FUSE_OPT_SECURE_THERM_FANTACH_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_THERM_FANTACH_WR_SECURE__RED_ALIAS_0 0x00000003
|
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#define NV_FUSE_OPT_SECURE_THERM_FANTACH_WR_SECURE__RED_ALIAS_0_DATA 30:30
|
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#define NV_FUSE_OPT_SECURE_THERM_FANTACH_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__WIDTH 3
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__PRI_ALIAS_0 0x00000002
|
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__PRI_ALIAS_0_DATA 31:31
|
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__PRI_ALIAS_1 0x00000004
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__PRI_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__PRI_ALIAS_1_WIDTH 2
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__RED_ALIAS_0 0x00000003
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__RED_ALIAS_0_DATA 31:31
|
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__RED_ALIAS_1 0x00000005
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__RED_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_SECURE_PRI_CONFIG_REG_WR_SECURE__RED_ALIAS_1_WIDTH 2
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#define NV_FUSE_OPT_SECURE_FBPA_ECC_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_FBPA_ECC_WR_SECURE__PRI_ALIAS_0 0x00000004
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#define NV_FUSE_OPT_SECURE_FBPA_ECC_WR_SECURE__PRI_ALIAS_0_DATA 2:2
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#define NV_FUSE_OPT_SECURE_FBPA_ECC_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_FBPA_ECC_WR_SECURE__RED_ALIAS_0 0x00000005
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#define NV_FUSE_OPT_SECURE_FBPA_ECC_WR_SECURE__RED_ALIAS_0_DATA 2:2
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#define NV_FUSE_OPT_SECURE_FBPA_ECC_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_MMU_PLM_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_MMU_PLM_WR_SECURE__PRI_ALIAS_0 0x00000004
|
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#define NV_FUSE_OPT_SECURE_MMU_PLM_WR_SECURE__PRI_ALIAS_0_DATA 3:3
|
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#define NV_FUSE_OPT_SECURE_MMU_PLM_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_MMU_PLM_WR_SECURE__RED_ALIAS_0 0x00000005
|
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#define NV_FUSE_OPT_SECURE_MMU_PLM_WR_SECURE__RED_ALIAS_0_DATA 3:3
|
|
#define NV_FUSE_OPT_SECURE_MMU_PLM_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE__WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE__PRI_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE__RED_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_SECURE_THERM_I2CSLAVE_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_INTRUPT_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_INTRUPT_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_THERM_INTRUPT_WR_SECURE__PRI_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_SECURE_THERM_INTRUPT_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_INTRUPT_WR_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_THERM_INTRUPT_WR_SECURE__RED_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_SECURE_THERM_INTRUPT_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_UPHY_CFG_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_UPHY_CFG_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_UPHY_CFG_WR_SECURE__PRI_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_UPHY_CFG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_UPHY_CFG_WR_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_UPHY_CFG_WR_SECURE__RED_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_UPHY_CFG_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_PP_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_PP_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_THERM_PP_WR_SECURE__PRI_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_SECURE_THERM_PP_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_THERM_PP_WR_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_THERM_PP_WR_SECURE__RED_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_SECURE_THERM_PP_WR_SECURE__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE__WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE__PRI_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE__RED_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_0_WR_SECURE__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE__PRI_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE__RED_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_SECURE_THERM_PWRGATE_1_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_RAM__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_RAM__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_RAM__PRI_ALIAS_0_DATA 10:10
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|
#define NV_FUSE_OPT_SECURE_GC6_BSI_RAM__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_GC6_BSI_RAM__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_RAM__RED_ALIAS_0_DATA 10:10
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|
#define NV_FUSE_OPT_SECURE_GC6_BSI_RAM__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE__WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE__PRI_ALIAS_0_DATA 11:11
|
|
#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE__RED_ALIAS_0 0x00000005
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|
#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE__RED_ALIAS_0_DATA 11:11
|
|
#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_0_WR_SECURE__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_GC6_BSI_DEBUG__WIDTH 2
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|
#define NV_FUSE_OPT_SECURE_GC6_BSI_DEBUG__PRI_ALIAS_0 0x00000004
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|
#define NV_FUSE_OPT_SECURE_GC6_BSI_DEBUG__PRI_ALIAS_0_DATA 13:12
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_DEBUG__PRI_ALIAS_0_WIDTH 2
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|
#define NV_FUSE_OPT_SECURE_GC6_BSI_DEBUG__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_DEBUG__RED_ALIAS_0_DATA 13:12
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_DEBUG__RED_ALIAS_0_WIDTH 2
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_FAN__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_FAN__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_FAN__PRI_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_FAN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_FAN__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_FAN__RED_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_FAN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_DEBUG__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_DEBUG__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_DEBUG__PRI_ALIAS_0_DATA 15:15
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_DEBUG__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_DEBUG__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_DEBUG__RED_ALIAS_0_DATA 15:15
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_DEBUG__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_SYSTEM__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_SYSTEM__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_SYSTEM__PRI_ALIAS_0_DATA 16:16
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_SYSTEM__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_SYSTEM__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_SYSTEM__RED_ALIAS_0_DATA 16:16
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_SYSTEM__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE__PRI_ALIAS_0_DATA 17:17
|
|
#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE__RED_ALIAS_0_DATA 17:17
|
|
#define NV_FUSE_OPT_SECURE_THERM_SLOWDOWN_1_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE__PRI_ALIAS_0_DATA 18:18
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE__RED_ALIAS_0_DATA 18:18
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_0_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE__PRI_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE__RED_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_OPT_SECURE_THERM_SMARTFAN_1_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE__PRI_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE__RED_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_LOW_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE__PRI_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE__RED_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_0_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE__PRI_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE__RED_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_SECURE_THERM_THERMAL_MED_HIGH_1_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_VIDCTRL_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_VIDCTRL_WR_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_THERM_VIDCTRL_WR_SECURE__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_SECURE_THERM_VIDCTRL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_THERM_VIDCTRL_WR_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_THERM_VIDCTRL_WR_SECURE__RED_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_SECURE_THERM_VIDCTRL_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ__PRI_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ__RED_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_PWR_SEQ__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_MAST_FSM__WIDTH 2
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_MAST_FSM__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_MAST_FSM__PRI_ALIAS_0_DATA 26:25
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_MAST_FSM__PRI_ALIAS_0_WIDTH 2
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_MAST_FSM__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_MAST_FSM__RED_ALIAS_0_DATA 26:25
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_MAST_FSM__RED_ALIAS_0_WIDTH 2
|
|
#define NV_FUSE_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE__PRI_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE__RED_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_SECURE_FUSE_KAPPAINFO_RD_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_INVALID_BITS_ATE__WIDTH 16
|
|
#define NV_FUSE_OPT_INVALID_BITS_ATE__PRI_ALIAS_0 0x00000004
|
|
#define NV_FUSE_OPT_INVALID_BITS_ATE__PRI_ALIAS_0_DATA 31:28
|
|
#define NV_FUSE_OPT_INVALID_BITS_ATE__PRI_ALIAS_0_WIDTH 4
|
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#define NV_FUSE_OPT_INVALID_BITS_ATE__PRI_ALIAS_1 0x00000006
|
|
#define NV_FUSE_OPT_INVALID_BITS_ATE__PRI_ALIAS_1_DATA 11:0
|
|
#define NV_FUSE_OPT_INVALID_BITS_ATE__PRI_ALIAS_1_WIDTH 12
|
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#define NV_FUSE_OPT_INVALID_BITS_ATE__RED_ALIAS_0 0x00000005
|
|
#define NV_FUSE_OPT_INVALID_BITS_ATE__RED_ALIAS_0_DATA 31:28
|
|
#define NV_FUSE_OPT_INVALID_BITS_ATE__RED_ALIAS_0_WIDTH 4
|
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#define NV_FUSE_OPT_INVALID_BITS_ATE__RED_ALIAS_1 0x00000007
|
|
#define NV_FUSE_OPT_INVALID_BITS_ATE__RED_ALIAS_1_DATA 11:0
|
|
#define NV_FUSE_OPT_INVALID_BITS_ATE__RED_ALIAS_1_WIDTH 12
|
|
#define NV_FUSE_OPT_OPENGL_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_OPENGL_EN__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_OPENGL_EN__PRI_ALIAS_0_DATA 12:12
|
|
#define NV_FUSE_OPT_OPENGL_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_OPENGL_EN__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_OPENGL_EN__RED_ALIAS_0_DATA 12:12
|
|
#define NV_FUSE_OPT_OPENGL_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_OPENGL_EN_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_OPENGL_EN_CONTROL__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_OPENGL_EN_CONTROL__PRI_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_OPT_OPENGL_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_OPENGL_EN_CONTROL__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_OPENGL_EN_CONTROL__RED_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_OPT_OPENGL_EN_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_MCHIP_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_MCHIP_EN__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_MCHIP_EN__PRI_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_OPT_MCHIP_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_MCHIP_EN__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_MCHIP_EN__RED_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_OPT_MCHIP_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_MCHIP_EN_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_MCHIP_EN_CONTROL__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_MCHIP_EN_CONTROL__PRI_ALIAS_0_DATA 15:15
|
|
#define NV_FUSE_OPT_MCHIP_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_MCHIP_EN_CONTROL__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_MCHIP_EN_CONTROL__RED_ALIAS_0_DATA 15:15
|
|
#define NV_FUSE_OPT_MCHIP_EN_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0_DATA 16:16
|
|
#define NV_FUSE_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE__RED_ALIAS_0_DATA 16:16
|
|
#define NV_FUSE_OPT_SECURE_TSENSE_CLK_PRIV_SECURE_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NOTEBOOK__WIDTH 1
|
|
#define NV_FUSE_OPT_NOTEBOOK__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_NOTEBOOK__PRI_ALIAS_0_DATA 17:17
|
|
#define NV_FUSE_OPT_NOTEBOOK__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NOTEBOOK__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_NOTEBOOK__RED_ALIAS_0_DATA 17:17
|
|
#define NV_FUSE_OPT_NOTEBOOK__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NOTEBOOK_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_NOTEBOOK_CONTROL__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_NOTEBOOK_CONTROL__PRI_ALIAS_0_DATA 18:18
|
|
#define NV_FUSE_OPT_NOTEBOOK_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NOTEBOOK_CONTROL__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_NOTEBOOK_CONTROL__RED_ALIAS_0_DATA 18:18
|
|
#define NV_FUSE_OPT_NOTEBOOK_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_JTAG2HOST_PRIV_SEC_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_JTAG2HOST_PRIV_SEC_EN__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_JTAG2HOST_PRIV_SEC_EN__PRI_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_OPT_JTAG2HOST_PRIV_SEC_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_JTAG2HOST_PRIV_SEC_EN__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_JTAG2HOST_PRIV_SEC_EN__RED_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_OPT_JTAG2HOST_PRIV_SEC_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP__WIDTH 1
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP__PRI_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP__RED_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP_CONTROL__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP_CONTROL__PRI_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP_CONTROL__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP_CONTROL__RED_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_SM_SPEED_SELECT_DP_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_ECC_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_ECC_EN__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_ECC_EN__PRI_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_ECC_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_ECC_EN__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_ECC_EN__RED_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_ECC_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_ECC_EN_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_ECC_EN_CONTROL__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_ECC_EN_CONTROL__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_ECC_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_ECC_EN_CONTROL__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_ECC_EN_CONTROL__RED_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_ECC_EN_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SCC_DIS__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SCC_DIS__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_SECURE_SCC_DIS__PRI_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_SECURE_SCC_DIS__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SCC_DIS__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_SECURE_SCC_DIS__RED_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_SECURE_SCC_DIS__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE__PRI_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE__RED_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_OPT_SECURE_HDCP_VPR_POLICY_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_VENDOR_CODE__WIDTH 4
|
|
#define NV_FUSE_OPT_VENDOR_CODE__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_VENDOR_CODE__PRI_ALIAS_0_DATA 29:26
|
|
#define NV_FUSE_OPT_VENDOR_CODE__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_VENDOR_CODE__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_VENDOR_CODE__RED_ALIAS_0_DATA 29:26
|
|
#define NV_FUSE_OPT_VENDOR_CODE__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FAB_CODE__WIDTH 6
|
|
#define NV_FUSE_OPT_FAB_CODE__PRI_ALIAS_0 0x00000006
|
|
#define NV_FUSE_OPT_FAB_CODE__PRI_ALIAS_0_DATA 31:30
|
|
#define NV_FUSE_OPT_FAB_CODE__PRI_ALIAS_0_WIDTH 2
|
|
#define NV_FUSE_OPT_FAB_CODE__PRI_ALIAS_1 0x00000008
|
|
#define NV_FUSE_OPT_FAB_CODE__PRI_ALIAS_1_DATA 3:0
|
|
#define NV_FUSE_OPT_FAB_CODE__PRI_ALIAS_1_WIDTH 4
|
|
#define NV_FUSE_OPT_FAB_CODE__RED_ALIAS_0 0x00000007
|
|
#define NV_FUSE_OPT_FAB_CODE__RED_ALIAS_0_DATA 31:30
|
|
#define NV_FUSE_OPT_FAB_CODE__RED_ALIAS_0_WIDTH 2
|
|
#define NV_FUSE_OPT_FAB_CODE__RED_ALIAS_1 0x00000009
|
|
#define NV_FUSE_OPT_FAB_CODE__RED_ALIAS_1_DATA 3:0
|
|
#define NV_FUSE_OPT_FAB_CODE__RED_ALIAS_1_WIDTH 4
|
|
#define NV_FUSE_OPT_LOT_CODE_0__WIDTH 32
|
|
#define NV_FUSE_OPT_LOT_CODE_0__PRI_ALIAS_0 0x00000008
|
|
#define NV_FUSE_OPT_LOT_CODE_0__PRI_ALIAS_0_DATA 31:4
|
|
#define NV_FUSE_OPT_LOT_CODE_0__PRI_ALIAS_0_WIDTH 28
|
|
#define NV_FUSE_OPT_LOT_CODE_0__PRI_ALIAS_1 0x0000000a
|
|
#define NV_FUSE_OPT_LOT_CODE_0__PRI_ALIAS_1_DATA 3:0
|
|
#define NV_FUSE_OPT_LOT_CODE_0__PRI_ALIAS_1_WIDTH 4
|
|
#define NV_FUSE_OPT_LOT_CODE_0__RED_ALIAS_0 0x00000009
|
|
#define NV_FUSE_OPT_LOT_CODE_0__RED_ALIAS_0_DATA 31:4
|
|
#define NV_FUSE_OPT_LOT_CODE_0__RED_ALIAS_0_WIDTH 28
|
|
#define NV_FUSE_OPT_LOT_CODE_0__RED_ALIAS_1 0x0000000b
|
|
#define NV_FUSE_OPT_LOT_CODE_0__RED_ALIAS_1_DATA 3:0
|
|
#define NV_FUSE_OPT_LOT_CODE_0__RED_ALIAS_1_WIDTH 4
|
|
#define NV_FUSE_OPT_LOT_CODE_1__WIDTH 28
|
|
#define NV_FUSE_OPT_LOT_CODE_1__PRI_ALIAS_0 0x0000000a
|
|
#define NV_FUSE_OPT_LOT_CODE_1__PRI_ALIAS_0_DATA 31:4
|
|
#define NV_FUSE_OPT_LOT_CODE_1__PRI_ALIAS_0_WIDTH 28
|
|
#define NV_FUSE_OPT_LOT_CODE_1__RED_ALIAS_0 0x0000000b
|
|
#define NV_FUSE_OPT_LOT_CODE_1__RED_ALIAS_0_DATA 31:4
|
|
#define NV_FUSE_OPT_LOT_CODE_1__RED_ALIAS_0_WIDTH 28
|
|
#define NV_FUSE_OPT_WAFER_ID__WIDTH 6
|
|
#define NV_FUSE_OPT_WAFER_ID__PRI_ALIAS_0 0x0000000c
|
|
#define NV_FUSE_OPT_WAFER_ID__PRI_ALIAS_0_DATA 5:0
|
|
#define NV_FUSE_OPT_WAFER_ID__PRI_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_WAFER_ID__RED_ALIAS_0 0x0000000d
|
|
#define NV_FUSE_OPT_WAFER_ID__RED_ALIAS_0_DATA 5:0
|
|
#define NV_FUSE_OPT_WAFER_ID__RED_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_X_COORDINATE__WIDTH 9
|
|
#define NV_FUSE_OPT_X_COORDINATE__PRI_ALIAS_0 0x0000000c
|
|
#define NV_FUSE_OPT_X_COORDINATE__PRI_ALIAS_0_DATA 14:6
|
|
#define NV_FUSE_OPT_X_COORDINATE__PRI_ALIAS_0_WIDTH 9
|
|
#define NV_FUSE_OPT_X_COORDINATE__RED_ALIAS_0 0x0000000d
|
|
#define NV_FUSE_OPT_X_COORDINATE__RED_ALIAS_0_DATA 14:6
|
|
#define NV_FUSE_OPT_X_COORDINATE__RED_ALIAS_0_WIDTH 9
|
|
#define NV_FUSE_OPT_Y_COORDINATE__WIDTH 9
|
|
#define NV_FUSE_OPT_Y_COORDINATE__PRI_ALIAS_0 0x0000000c
|
|
#define NV_FUSE_OPT_Y_COORDINATE__PRI_ALIAS_0_DATA 23:15
|
|
#define NV_FUSE_OPT_Y_COORDINATE__PRI_ALIAS_0_WIDTH 9
|
|
#define NV_FUSE_OPT_Y_COORDINATE__RED_ALIAS_0 0x0000000d
|
|
#define NV_FUSE_OPT_Y_COORDINATE__RED_ALIAS_0_DATA 23:15
|
|
#define NV_FUSE_OPT_Y_COORDINATE__RED_ALIAS_0_WIDTH 9
|
|
#define NV_FUSE_OPT_OPS_RESERVED__WIDTH 6
|
|
#define NV_FUSE_OPT_OPS_RESERVED__PRI_ALIAS_0 0x0000000c
|
|
#define NV_FUSE_OPT_OPS_RESERVED__PRI_ALIAS_0_DATA 29:24
|
|
#define NV_FUSE_OPT_OPS_RESERVED__PRI_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_OPS_RESERVED__RED_ALIAS_0 0x0000000d
|
|
#define NV_FUSE_OPT_OPS_RESERVED__RED_ALIAS_0_DATA 29:24
|
|
#define NV_FUSE_OPT_OPS_RESERVED__RED_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3__WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3__PRI_ALIAS_0 0x0000000c
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3__PRI_ALIAS_0_DATA 30:30
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3__RED_ALIAS_0 0x0000000d
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3__RED_ALIAS_0_DATA 30:30
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3_CONTROL__PRI_ALIAS_0 0x0000000c
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3_CONTROL__PRI_ALIAS_0_DATA 31:31
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3_CONTROL__RED_ALIAS_0 0x0000000d
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3_CONTROL__RED_ALIAS_0_DATA 31:31
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC3_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_INT_TS_VALID__WIDTH 1
|
|
#define NV_FUSE_OPT_INT_TS_VALID__PRI_ALIAS_0 0x0000000e
|
|
#define NV_FUSE_OPT_INT_TS_VALID__PRI_ALIAS_0_DATA 0:0
|
|
#define NV_FUSE_OPT_INT_TS_VALID__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_INT_TS_VALID__RED_ALIAS_0 0x0000000f
|
|
#define NV_FUSE_OPT_INT_TS_VALID__RED_ALIAS_0_DATA 0:0
|
|
#define NV_FUSE_OPT_INT_TS_VALID__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE__PRI_ALIAS_0 0x0000000e
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE__PRI_ALIAS_0_DATA 1:1
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE__RED_ALIAS_0 0x0000000f
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE__RED_ALIAS_0_DATA 1:1
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_REMAPPER_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE__PRI_ALIAS_0 0x0000000e
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE__PRI_ALIAS_0_DATA 2:2
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE__RED_ALIAS_0 0x0000000f
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE__RED_ALIAS_0_DATA 2:2
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE_CONTROL__PRI_ALIAS_0 0x0000000e
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE_CONTROL__PRI_ALIAS_0_DATA 3:3
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE_CONTROL__RED_ALIAS_0 0x0000000f
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE_CONTROL__RED_ALIAS_0_DATA 3:3
|
|
#define NV_FUSE_OPT_SW_SMC_DISABLE_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0 0x0000000e
|
|
#define NV_FUSE_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE__RED_ALIAS_0 0x0000000f
|
|
#define NV_FUSE_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE__RED_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_SECURE_TRIMMER_CTRL_PRIV_SECURE_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_TITAN_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_TITAN_EN__PRI_ALIAS_0 0x0000000e
|
|
#define NV_FUSE_OPT_TITAN_EN__PRI_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_TITAN_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_TITAN_EN__RED_ALIAS_0 0x0000000f
|
|
#define NV_FUSE_OPT_TITAN_EN__RED_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_TITAN_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_TITAN_EN_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_TITAN_EN_CONTROL__PRI_ALIAS_0 0x0000000e
|
|
#define NV_FUSE_OPT_TITAN_EN_CONTROL__PRI_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_TITAN_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_TITAN_EN_CONTROL__RED_ALIAS_0 0x0000000f
|
|
#define NV_FUSE_OPT_TITAN_EN_CONTROL__RED_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_TITAN_EN_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SRAM_REPAIR__WIDTH 8
|
|
#define NV_FUSE_OPT_SRAM_REPAIR__PRI_ALIAS_0 0x0000000e
|
|
#define NV_FUSE_OPT_SRAM_REPAIR__PRI_ALIAS_0_DATA 14:7
|
|
#define NV_FUSE_OPT_SRAM_REPAIR__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_SRAM_REPAIR__RED_ALIAS_0 0x0000000f
|
|
#define NV_FUSE_OPT_SRAM_REPAIR__RED_ALIAS_0_DATA 14:7
|
|
#define NV_FUSE_OPT_SRAM_REPAIR__RED_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_CP_BIN__WIDTH 4
|
|
#define NV_FUSE_OPT_CP_BIN__PRI_ALIAS_0 0x0000000e
|
|
#define NV_FUSE_OPT_CP_BIN__PRI_ALIAS_0_DATA 18:15
|
|
#define NV_FUSE_OPT_CP_BIN__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_CP_BIN__RED_ALIAS_0 0x0000000f
|
|
#define NV_FUSE_OPT_CP_BIN__RED_ALIAS_0_DATA 18:15
|
|
#define NV_FUSE_OPT_CP_BIN__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_DONE_MAP__WIDTH 8
|
|
#define NV_FUSE_OPT_DONE_MAP__PRI_ALIAS_0 0x0000000e
|
|
#define NV_FUSE_OPT_DONE_MAP__PRI_ALIAS_0_DATA 26:19
|
|
#define NV_FUSE_OPT_DONE_MAP__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_DONE_MAP__RED_ALIAS_0 0x0000000f
|
|
#define NV_FUSE_OPT_DONE_MAP__RED_ALIAS_0_DATA 26:19
|
|
#define NV_FUSE_OPT_DONE_MAP__RED_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE__PRI_ALIAS_0 0x0000000e
|
|
#define NV_FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE__PRI_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE__RED_ALIAS_0 0x0000000f
|
|
#define NV_FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE__RED_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_SECURE_SCANDEBUG_ACCESS_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_OFA_DEFECTIVE__WIDTH 1
|
|
#define NV_FUSE_OPT_OFA_DEFECTIVE__PRI_ALIAS_0 0x0000000e
|
|
#define NV_FUSE_OPT_OFA_DEFECTIVE__PRI_ALIAS_0_DATA 28:28
|
|
#define NV_FUSE_OPT_OFA_DEFECTIVE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_OFA_DEFECTIVE__RED_ALIAS_0 0x0000000f
|
|
#define NV_FUSE_OPT_OFA_DEFECTIVE__RED_ALIAS_0_DATA 28:28
|
|
#define NV_FUSE_OPT_OFA_DEFECTIVE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__WIDTH 4
|
|
#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__PRI_ALIAS_0 0x0000000e
|
|
#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__PRI_ALIAS_0_DATA 31:29
|
|
#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__PRI_ALIAS_0_WIDTH 3
|
|
#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__PRI_ALIAS_1 0x00000010
|
|
#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__RED_ALIAS_0 0x0000000f
|
|
#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__RED_ALIAS_0_DATA 31:29
|
|
#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__RED_ALIAS_0_WIDTH 3
|
|
#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__RED_ALIAS_1 0x00000011
|
|
#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__RED_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_FUSE_UCODE_OFA_REV__RED_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4__WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4__PRI_ALIAS_0_DATA 1:1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4__RED_ALIAS_0_DATA 1:1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4_CONTROL__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4_CONTROL__PRI_ALIAS_0_DATA 2:2
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4_CONTROL__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4_CONTROL__RED_ALIAS_0_DATA 2:2
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC4_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HDCP_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_HDCP_EN__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_HDCP_EN__PRI_ALIAS_0_DATA 3:3
|
|
#define NV_FUSE_OPT_HDCP_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HDCP_EN__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_HDCP_EN__RED_ALIAS_0_DATA 3:3
|
|
#define NV_FUSE_OPT_HDCP_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HDCP_EN_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_HDCP_EN_CONTROL__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_HDCP_EN_CONTROL__PRI_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_HDCP_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HDCP_EN_CONTROL__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_HDCP_EN_CONTROL__RED_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_HDCP_EN_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_WR_SECURE__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_WR_SECURE__PRI_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_WR_SECURE__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_WR_SECURE__RED_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_ISM_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_ISM_WR_SECURE__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_SECURE_ISM_WR_SECURE__PRI_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_ISM_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_ISM_WR_SECURE__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_SECURE_ISM_WR_SECURE__RED_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_ISM_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SAMPLE_BIN__WIDTH 3
|
|
#define NV_FUSE_OPT_SAMPLE_BIN__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_SAMPLE_BIN__PRI_ALIAS_0_DATA 9:7
|
|
#define NV_FUSE_OPT_SAMPLE_BIN__PRI_ALIAS_0_WIDTH 3
|
|
#define NV_FUSE_OPT_SAMPLE_BIN__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_SAMPLE_BIN__RED_ALIAS_0_DATA 9:7
|
|
#define NV_FUSE_OPT_SAMPLE_BIN__RED_ALIAS_0_WIDTH 3
|
|
#define NV_FUSE_OPT_SAMPLE_TYPE__WIDTH 3
|
|
#define NV_FUSE_OPT_SAMPLE_TYPE__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_SAMPLE_TYPE__PRI_ALIAS_0_DATA 12:10
|
|
#define NV_FUSE_OPT_SAMPLE_TYPE__PRI_ALIAS_0_WIDTH 3
|
|
#define NV_FUSE_OPT_SAMPLE_TYPE__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_SAMPLE_TYPE__RED_ALIAS_0_DATA 12:10
|
|
#define NV_FUSE_OPT_SAMPLE_TYPE__RED_ALIAS_0_WIDTH 3
|
|
#define NV_FUSE_OPT_SECURE_LOCAL_TRAP_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_LOCAL_TRAP_WR_SECURE__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_SECURE_LOCAL_TRAP_WR_SECURE__PRI_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_OPT_SECURE_LOCAL_TRAP_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_LOCAL_TRAP_WR_SECURE__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_SECURE_LOCAL_TRAP_WR_SECURE__RED_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_OPT_SECURE_LOCAL_TRAP_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PRI_SEQUENCER_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PRI_SEQUENCER_WR_SECURE__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_SECURE_PRI_SEQUENCER_WR_SECURE__PRI_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_OPT_SECURE_PRI_SEQUENCER_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PRI_SEQUENCER_WR_SECURE__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_SECURE_PRI_SEQUENCER_WR_SECURE__RED_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_OPT_SECURE_PRI_SEQUENCER_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SUBREVISION__WIDTH 4
|
|
#define NV_FUSE_OPT_SUBREVISION__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_SUBREVISION__PRI_ALIAS_0_DATA 18:15
|
|
#define NV_FUSE_OPT_SUBREVISION__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_SUBREVISION__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_SUBREVISION__RED_ALIAS_0_DATA 18:15
|
|
#define NV_FUSE_OPT_SUBREVISION__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_MEMORY_LOCKED_ENABLED__WIDTH 1
|
|
#define NV_FUSE_OPT_MEMORY_LOCKED_ENABLED__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_MEMORY_LOCKED_ENABLED__PRI_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_OPT_MEMORY_LOCKED_ENABLED__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_MEMORY_LOCKED_ENABLED__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_MEMORY_LOCKED_ENABLED__RED_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_OPT_MEMORY_LOCKED_ENABLED__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_IQ_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_IQ_WR_SECURE__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_SECURE_PLTS_IQ_WR_SECURE__PRI_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_OPT_SECURE_PLTS_IQ_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_IQ_WR_SECURE__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_SECURE_PLTS_IQ_WR_SECURE__RED_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_OPT_SECURE_PLTS_IQ_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_OVERT__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_OVERT__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_OVERT__PRI_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_OVERT__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_OVERT__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_OVERT__RED_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_SECURE_GC6_SCI_OVERT__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE__PRI_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE__RED_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_SECURE_GC6_BSI_FUSEPS18_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FUSE_CLK_SWITCH_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_FUSE_CLK_SWITCH_DISABLE__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_FUSE_CLK_SWITCH_DISABLE__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_FUSE_CLK_SWITCH_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FUSE_CLK_SWITCH_DISABLE__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_FUSE_CLK_SWITCH_DISABLE__RED_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_FUSE_CLK_SWITCH_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE__PRI_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE__RED_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_QUADRO_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN__PRI_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN__RED_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN_CONTROL__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN_CONTROL__PRI_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN_CONTROL__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN_CONTROL__RED_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_OPT_GLOBAL_POISON_EN_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_COH_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_COH_WR_SECURE__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_COH_WR_SECURE__PRI_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_COH_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_COH_WR_SECURE__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_COH_WR_SECURE__RED_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_COH_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_AUTO_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_AUTO_EN__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_AUTO_EN__PRI_ALIAS_0_DATA 28:28
|
|
#define NV_FUSE_OPT_AUTO_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_AUTO_EN__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_AUTO_EN__RED_ALIAS_0_DATA 28:28
|
|
#define NV_FUSE_OPT_AUTO_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_AUTO_EN_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_AUTO_EN_CONTROL__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_AUTO_EN_CONTROL__PRI_ALIAS_0_DATA 29:29
|
|
#define NV_FUSE_OPT_AUTO_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_AUTO_EN_CONTROL__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_AUTO_EN_CONTROL__RED_ALIAS_0_DATA 29:29
|
|
#define NV_FUSE_OPT_AUTO_EN_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SE_CONTROL_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SE_CONTROL_SECURE__PRI_ALIAS_0 0x00000010
|
|
#define NV_FUSE_OPT_SECURE_SE_CONTROL_SECURE__PRI_ALIAS_0_DATA 30:30
|
|
#define NV_FUSE_OPT_SECURE_SE_CONTROL_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SE_CONTROL_SECURE__RED_ALIAS_0 0x00000011
|
|
#define NV_FUSE_OPT_SECURE_SE_CONTROL_SECURE__RED_ALIAS_0_DATA 30:30
|
|
#define NV_FUSE_OPT_SECURE_SE_CONTROL_SECURE__RED_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE__WIDTH 1
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#define NV_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE__PRI_ALIAS_0 0x00000010
|
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#define NV_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE__PRI_ALIAS_0_DATA 31:31
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#define NV_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE__RED_ALIAS_0 0x00000011
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#define NV_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE__RED_ALIAS_0_DATA 31:31
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#define NV_FUSE_OPT_FEATURE_FUSES_OVERRIDE_DISABLE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_AMAP_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_AMAP_WR_SECURE__PRI_ALIAS_0 0x00000012
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#define NV_FUSE_OPT_SECURE_PFB_AMAP_WR_SECURE__PRI_ALIAS_0_DATA 0:0
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#define NV_FUSE_OPT_SECURE_PFB_AMAP_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_AMAP_WR_SECURE__RED_ALIAS_0 0x00000013
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#define NV_FUSE_OPT_SECURE_PFB_AMAP_WR_SECURE__RED_ALIAS_0_DATA 0:0
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#define NV_FUSE_OPT_SECURE_PFB_AMAP_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_CYA_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_CYA_WR_SECURE__PRI_ALIAS_0 0x00000012
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#define NV_FUSE_OPT_SECURE_PFB_CYA_WR_SECURE__PRI_ALIAS_0_DATA 1:1
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#define NV_FUSE_OPT_SECURE_PFB_CYA_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_CYA_WR_SECURE__RED_ALIAS_0 0x00000013
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#define NV_FUSE_OPT_SECURE_PFB_CYA_WR_SECURE__RED_ALIAS_0_DATA 1:1
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#define NV_FUSE_OPT_SECURE_PFB_CYA_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE__PRI_ALIAS_0 0x00000012
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#define NV_FUSE_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE__PRI_ALIAS_0_DATA 2:2
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#define NV_FUSE_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE__RED_ALIAS_0 0x00000013
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#define NV_FUSE_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE__RED_ALIAS_0_DATA 2:2
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#define NV_FUSE_OPT_SECURE_PFB_NISO_SCRUB_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE__PRI_ALIAS_0 0x00000012
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE__PRI_ALIAS_0_DATA 3:3
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE__RED_ALIAS_0 0x00000013
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE__RED_ALIAS_0_DATA 3:3
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_CYA_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE__PRI_ALIAS_0 0x00000012
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#define NV_FUSE_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE__PRI_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE__RED_ALIAS_0 0x00000013
|
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#define NV_FUSE_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE__RED_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_SECURE_FUSE_SRAM_VMIN_RD_SECURE__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE__PRI_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE__RED_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_DBG_WR_SECURE__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE__WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE__PRI_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE__RED_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_MSCG_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE__PRI_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE__RED_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_PERF_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE__PRI_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE__RED_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_LTC_CFG_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE__WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE__PRI_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE__RED_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_SECURE_PFB_HSHUB_NVL_CFG_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XBAR_CYA_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_XBAR_CYA_WR_SECURE__PRI_ALIAS_0 0x00000012
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|
#define NV_FUSE_OPT_SECURE_XBAR_CYA_WR_SECURE__PRI_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_OPT_SECURE_XBAR_CYA_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XBAR_CYA_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_XBAR_CYA_WR_SECURE__RED_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_OPT_SECURE_XBAR_CYA_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XBAR_PM_WR_SECURE__WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_XBAR_PM_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_XBAR_PM_WR_SECURE__PRI_ALIAS_0_DATA 11:11
|
|
#define NV_FUSE_OPT_SECURE_XBAR_PM_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XBAR_PM_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_XBAR_PM_WR_SECURE__RED_ALIAS_0_DATA 11:11
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|
#define NV_FUSE_OPT_SECURE_XBAR_PM_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PLTS_CBC_WR_SECURE__WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PLTS_CBC_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CBC_WR_SECURE__PRI_ALIAS_0_DATA 12:12
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CBC_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PLTS_CBC_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CBC_WR_SECURE__RED_ALIAS_0_DATA 12:12
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|
#define NV_FUSE_OPT_SECURE_PLTS_CBC_WR_SECURE__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_WR_SECURE__PRI_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_WR_SECURE__RED_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_WR_SECURE__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE__PRI_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE__RED_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_OPT_SECURE_PLTS_VPR_LEAKAGE_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_DSTG_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_DSTG_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_PLTS_DSTG_WR_SECURE__PRI_ALIAS_0_DATA 15:15
|
|
#define NV_FUSE_OPT_SECURE_PLTS_DSTG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_DSTG_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_PLTS_DSTG_WR_SECURE__RED_ALIAS_0_DATA 15:15
|
|
#define NV_FUSE_OPT_SECURE_PLTS_DSTG_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE__PRI_ALIAS_0_DATA 16:16
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE__RED_ALIAS_0_DATA 16:16
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_ECC_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_WR_SECURE__PRI_ALIAS_0_DATA 17:17
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CYA_WR_SECURE__RED_ALIAS_0_DATA 17:17
|
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#define NV_FUSE_OPT_SECURE_PLTS_CYA_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_TSTG_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_TSTG_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_PLTS_TSTG_WR_SECURE__PRI_ALIAS_0_DATA 18:18
|
|
#define NV_FUSE_OPT_SECURE_PLTS_TSTG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_TSTG_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_PLTS_TSTG_WR_SECURE__RED_ALIAS_0_DATA 18:18
|
|
#define NV_FUSE_OPT_SECURE_PLTS_TSTG_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CGATE_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CGATE_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CGATE_WR_SECURE__PRI_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CGATE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CGATE_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CGATE_WR_SECURE__RED_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_OPT_SECURE_PLTS_CGATE_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_WDATA_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_WDATA_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_FUSE_WDATA_WR_SECURE__PRI_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_OPT_SECURE_FUSE_WDATA_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_WDATA_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_FUSE_WDATA_WR_SECURE__RED_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_OPT_SECURE_FUSE_WDATA_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_RD_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_RD_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_RD_SECURE__PRI_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_RD_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_RD_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_RD_SECURE__RED_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_SECRET_RD_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE__PRI_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE__RED_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_SECURE_RAMCHAIN_CMD_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBPA_IOBIST_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBPA_IOBIST_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_FBPA_IOBIST_WR_SECURE__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_SECURE_FBPA_IOBIST_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBPA_IOBIST_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_FBPA_IOBIST_WR_SECURE__RED_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_SECURE_FBPA_IOBIST_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBPA_ILA_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBPA_ILA_WR_SECURE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_SECURE_FBPA_ILA_WR_SECURE__PRI_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_SECURE_FBPA_ILA_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBPA_ILA_WR_SECURE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_SECURE_FBPA_ILA_WR_SECURE__RED_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_SECURE_FBPA_ILA_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NNE_ID__WIDTH 1
|
|
#define NV_FUSE_OPT_NNE_ID__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_NNE_ID__PRI_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_OPT_NNE_ID__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NNE_ID__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_NNE_ID__RED_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_OPT_NNE_ID__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FT_DONE__WIDTH 10
|
|
#define NV_FUSE_OPT_FT_DONE__PRI_ALIAS_0 0x00000012
|
|
#define NV_FUSE_OPT_FT_DONE__PRI_ALIAS_0_DATA 31:26
|
|
#define NV_FUSE_OPT_FT_DONE__PRI_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_FT_DONE__PRI_ALIAS_1 0x00000014
|
|
#define NV_FUSE_OPT_FT_DONE__PRI_ALIAS_1_DATA 3:0
|
|
#define NV_FUSE_OPT_FT_DONE__PRI_ALIAS_1_WIDTH 4
|
|
#define NV_FUSE_OPT_FT_DONE__RED_ALIAS_0 0x00000013
|
|
#define NV_FUSE_OPT_FT_DONE__RED_ALIAS_0_DATA 31:26
|
|
#define NV_FUSE_OPT_FT_DONE__RED_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_FT_DONE__RED_ALIAS_1 0x00000015
|
|
#define NV_FUSE_OPT_FT_DONE__RED_ALIAS_1_DATA 3:0
|
|
#define NV_FUSE_OPT_FT_DONE__RED_ALIAS_1_WIDTH 4
|
|
#define NV_FUSE_OPT_NVS_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_NVS_EN__PRI_ALIAS_0 0x00000014
|
|
#define NV_FUSE_OPT_NVS_EN__PRI_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_NVS_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVS_EN__RED_ALIAS_0 0x00000015
|
|
#define NV_FUSE_OPT_NVS_EN__RED_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_NVS_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVS_EN_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_NVS_EN_CONTROL__PRI_ALIAS_0 0x00000014
|
|
#define NV_FUSE_OPT_NVS_EN_CONTROL__PRI_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_NVS_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVS_EN_CONTROL__RED_ALIAS_0 0x00000015
|
|
#define NV_FUSE_OPT_NVS_EN_CONTROL__RED_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_NVS_EN_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE__PRI_ALIAS_0 0x00000014
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE__PRI_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE__RED_ALIAS_0 0x00000015
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE__RED_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE_CONTROL__PRI_ALIAS_0 0x00000014
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE_CONTROL__PRI_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE_CONTROL__RED_ALIAS_0 0x00000015
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE_CONTROL__RED_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_VP8_VP9_DISABLE_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_TPC_GPC1_DEFECTIVE__WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC1_DEFECTIVE__PRI_ALIAS_0 0x00000014
|
|
#define NV_FUSE_OPT_TPC_GPC1_DEFECTIVE__PRI_ALIAS_0_DATA 13:8
|
|
#define NV_FUSE_OPT_TPC_GPC1_DEFECTIVE__PRI_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC1_DEFECTIVE__RED_ALIAS_0 0x00000015
|
|
#define NV_FUSE_OPT_TPC_GPC1_DEFECTIVE__RED_ALIAS_0_DATA 13:8
|
|
#define NV_FUSE_OPT_TPC_GPC1_DEFECTIVE__RED_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC2_DEFECTIVE__WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC2_DEFECTIVE__PRI_ALIAS_0 0x00000014
|
|
#define NV_FUSE_OPT_TPC_GPC2_DEFECTIVE__PRI_ALIAS_0_DATA 19:14
|
|
#define NV_FUSE_OPT_TPC_GPC2_DEFECTIVE__PRI_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC2_DEFECTIVE__RED_ALIAS_0 0x00000015
|
|
#define NV_FUSE_OPT_TPC_GPC2_DEFECTIVE__RED_ALIAS_0_DATA 19:14
|
|
#define NV_FUSE_OPT_TPC_GPC2_DEFECTIVE__RED_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_VGX_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_VGX_EN__PRI_ALIAS_0 0x00000014
|
|
#define NV_FUSE_OPT_VGX_EN__PRI_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_OPT_VGX_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_VGX_EN__RED_ALIAS_0 0x00000015
|
|
#define NV_FUSE_OPT_VGX_EN__RED_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_OPT_VGX_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_VGX_EN_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_VGX_EN_CONTROL__PRI_ALIAS_0 0x00000014
|
|
#define NV_FUSE_OPT_VGX_EN_CONTROL__PRI_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_VGX_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_VGX_EN_CONTROL__RED_ALIAS_0 0x00000015
|
|
#define NV_FUSE_OPT_VGX_EN_CONTROL__RED_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_VGX_EN_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_TPC_GPC3_DEFECTIVE__WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC3_DEFECTIVE__PRI_ALIAS_0 0x00000014
|
|
#define NV_FUSE_OPT_TPC_GPC3_DEFECTIVE__PRI_ALIAS_0_DATA 27:22
|
|
#define NV_FUSE_OPT_TPC_GPC3_DEFECTIVE__PRI_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC3_DEFECTIVE__RED_ALIAS_0 0x00000015
|
|
#define NV_FUSE_OPT_TPC_GPC3_DEFECTIVE__RED_ALIAS_0_DATA 27:22
|
|
#define NV_FUSE_OPT_TPC_GPC3_DEFECTIVE__RED_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_GC6_NVVDD_OK_THRESHOLD__WIDTH 4
|
|
#define NV_FUSE_OPT_GC6_NVVDD_OK_THRESHOLD__PRI_ALIAS_0 0x00000014
|
|
#define NV_FUSE_OPT_GC6_NVVDD_OK_THRESHOLD__PRI_ALIAS_0_DATA 31:28
|
|
#define NV_FUSE_OPT_GC6_NVVDD_OK_THRESHOLD__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_GC6_NVVDD_OK_THRESHOLD__RED_ALIAS_0 0x00000015
|
|
#define NV_FUSE_OPT_GC6_NVVDD_OK_THRESHOLD__RED_ALIAS_0_DATA 31:28
|
|
#define NV_FUSE_OPT_GC6_NVVDD_OK_THRESHOLD__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_CP1_DVS_COMPLETE__WIDTH 1
|
|
#define NV_FUSE_OPT_CP1_DVS_COMPLETE__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_CP1_DVS_COMPLETE__PRI_ALIAS_0_DATA 0:0
|
|
#define NV_FUSE_OPT_CP1_DVS_COMPLETE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_CP1_DVS_COMPLETE__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_CP1_DVS_COMPLETE__RED_ALIAS_0_DATA 0:0
|
|
#define NV_FUSE_OPT_CP1_DVS_COMPLETE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_CP2_DVS_COMPLETE__WIDTH 1
|
|
#define NV_FUSE_OPT_CP2_DVS_COMPLETE__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_CP2_DVS_COMPLETE__PRI_ALIAS_0_DATA 1:1
|
|
#define NV_FUSE_OPT_CP2_DVS_COMPLETE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_CP2_DVS_COMPLETE__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_CP2_DVS_COMPLETE__RED_ALIAS_0_DATA 1:1
|
|
#define NV_FUSE_OPT_CP2_DVS_COMPLETE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_TPC_GPC4_DEFECTIVE__WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC4_DEFECTIVE__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_TPC_GPC4_DEFECTIVE__PRI_ALIAS_0_DATA 7:2
|
|
#define NV_FUSE_OPT_TPC_GPC4_DEFECTIVE__PRI_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC4_DEFECTIVE__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_TPC_GPC4_DEFECTIVE__RED_ALIAS_0_DATA 7:2
|
|
#define NV_FUSE_OPT_TPC_GPC4_DEFECTIVE__RED_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_CP1_COMPLETE__WIDTH 1
|
|
#define NV_FUSE_OPT_CP1_COMPLETE__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_CP1_COMPLETE__PRI_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_CP1_COMPLETE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_CP1_COMPLETE__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_CP1_COMPLETE__RED_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_CP1_COMPLETE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_CP2_COMPLETE__WIDTH 1
|
|
#define NV_FUSE_OPT_CP2_COMPLETE__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_CP2_COMPLETE__PRI_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_CP2_COMPLETE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_CP2_COMPLETE__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_CP2_COMPLETE__RED_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_CP2_COMPLETE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_DEVID_SW_OVERRIDE_DIS__WIDTH 1
|
|
#define NV_FUSE_OPT_DEVID_SW_OVERRIDE_DIS__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_DEVID_SW_OVERRIDE_DIS__PRI_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_OPT_DEVID_SW_OVERRIDE_DIS__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_DEVID_SW_OVERRIDE_DIS__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_DEVID_SW_OVERRIDE_DIS__RED_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_OPT_DEVID_SW_OVERRIDE_DIS__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE__PRI_ALIAS_0_DATA 11:11
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE__RED_ALIAS_0_DATA 11:11
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE_CONTROL__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE_CONTROL__PRI_ALIAS_0_DATA 12:12
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE_CONTROL__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE_CONTROL__RED_ALIAS_0_DATA 12:12
|
|
#define NV_FUSE_OPT_ASSR_STICKY_DISABLE_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE__PRI_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE__RED_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_OPT_SECURE_FUSE_FLOORSWEEP_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_BA_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_BA_WR_SECURE__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_SECURE_BA_WR_SECURE__PRI_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_OPT_SECURE_BA_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_BA_WR_SECURE__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_SECURE_BA_WR_SECURE__RED_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_OPT_SECURE_BA_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_TPC_GPC5_DEFECTIVE__WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC5_DEFECTIVE__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_TPC_GPC5_DEFECTIVE__PRI_ALIAS_0_DATA 20:15
|
|
#define NV_FUSE_OPT_TPC_GPC5_DEFECTIVE__PRI_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC5_DEFECTIVE__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_TPC_GPC5_DEFECTIVE__RED_ALIAS_0_DATA 20:15
|
|
#define NV_FUSE_OPT_TPC_GPC5_DEFECTIVE__RED_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CTRL_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CTRL_WR_SECURE__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CTRL_WR_SECURE__PRI_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CTRL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CTRL_WR_SECURE__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CTRL_WR_SECURE__RED_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CTRL_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE__PRI_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE__RED_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_SECURE_FUSE_IDDQINFO_RD_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVJPG_DEFECTIVE__WIDTH 1
|
|
#define NV_FUSE_OPT_NVJPG_DEFECTIVE__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_NVJPG_DEFECTIVE__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_NVJPG_DEFECTIVE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVJPG_DEFECTIVE__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_NVJPG_DEFECTIVE__RED_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_NVJPG_DEFECTIVE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_GPC_DEFECTIVE__WIDTH 8
|
|
#define NV_FUSE_OPT_GPC_DEFECTIVE__PRI_ALIAS_0 0x00000016
|
|
#define NV_FUSE_OPT_GPC_DEFECTIVE__PRI_ALIAS_0_DATA 31:24
|
|
#define NV_FUSE_OPT_GPC_DEFECTIVE__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_GPC_DEFECTIVE__RED_ALIAS_0 0x00000017
|
|
#define NV_FUSE_OPT_GPC_DEFECTIVE__RED_ALIAS_0_DATA 31:24
|
|
#define NV_FUSE_OPT_GPC_DEFECTIVE__RED_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_TPC_GPC0_DEFECTIVE__WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC0_DEFECTIVE__PRI_ALIAS_0 0x00000018
|
|
#define NV_FUSE_OPT_TPC_GPC0_DEFECTIVE__PRI_ALIAS_0_DATA 5:0
|
|
#define NV_FUSE_OPT_TPC_GPC0_DEFECTIVE__PRI_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC0_DEFECTIVE__RED_ALIAS_0 0x00000019
|
|
#define NV_FUSE_OPT_TPC_GPC0_DEFECTIVE__RED_ALIAS_0_DATA 5:0
|
|
#define NV_FUSE_OPT_TPC_GPC0_DEFECTIVE__RED_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_FBP_DEFECTIVE__WIDTH 6
|
|
#define NV_FUSE_OPT_FBP_DEFECTIVE__PRI_ALIAS_0 0x00000018
|
|
#define NV_FUSE_OPT_FBP_DEFECTIVE__PRI_ALIAS_0_DATA 11:6
|
|
#define NV_FUSE_OPT_FBP_DEFECTIVE__PRI_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_FBP_DEFECTIVE__RED_ALIAS_0 0x00000019
|
|
#define NV_FUSE_OPT_FBP_DEFECTIVE__RED_ALIAS_0_DATA 11:6
|
|
#define NV_FUSE_OPT_FBP_DEFECTIVE__RED_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_FBIO_DEFECTIVE__WIDTH 6
|
|
#define NV_FUSE_OPT_FBIO_DEFECTIVE__PRI_ALIAS_0 0x00000018
|
|
#define NV_FUSE_OPT_FBIO_DEFECTIVE__PRI_ALIAS_0_DATA 17:12
|
|
#define NV_FUSE_OPT_FBIO_DEFECTIVE__PRI_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_FBIO_DEFECTIVE__RED_ALIAS_0 0x00000019
|
|
#define NV_FUSE_OPT_FBIO_DEFECTIVE__RED_ALIAS_0_DATA 17:12
|
|
#define NV_FUSE_OPT_FBIO_DEFECTIVE__RED_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_DISPLAY_DEFECTIVE__WIDTH 1
|
|
#define NV_FUSE_OPT_DISPLAY_DEFECTIVE__PRI_ALIAS_0 0x00000018
|
|
#define NV_FUSE_OPT_DISPLAY_DEFECTIVE__PRI_ALIAS_0_DATA 18:18
|
|
#define NV_FUSE_OPT_DISPLAY_DEFECTIVE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_DISPLAY_DEFECTIVE__RED_ALIAS_0 0x00000019
|
|
#define NV_FUSE_OPT_DISPLAY_DEFECTIVE__RED_ALIAS_0_DATA 18:18
|
|
#define NV_FUSE_OPT_DISPLAY_DEFECTIVE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVENC_DEFECTIVE__WIDTH 1
|
|
#define NV_FUSE_OPT_NVENC_DEFECTIVE__PRI_ALIAS_0 0x00000018
|
|
#define NV_FUSE_OPT_NVENC_DEFECTIVE__PRI_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_OPT_NVENC_DEFECTIVE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVENC_DEFECTIVE__RED_ALIAS_0 0x00000019
|
|
#define NV_FUSE_OPT_NVENC_DEFECTIVE__RED_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_OPT_NVENC_DEFECTIVE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVDEC_DEFECTIVE__WIDTH 2
|
|
#define NV_FUSE_OPT_NVDEC_DEFECTIVE__PRI_ALIAS_0 0x00000018
|
|
#define NV_FUSE_OPT_NVDEC_DEFECTIVE__PRI_ALIAS_0_DATA 21:20
|
|
#define NV_FUSE_OPT_NVDEC_DEFECTIVE__PRI_ALIAS_0_WIDTH 2
|
|
#define NV_FUSE_OPT_NVDEC_DEFECTIVE__RED_ALIAS_0 0x00000019
|
|
#define NV_FUSE_OPT_NVDEC_DEFECTIVE__RED_ALIAS_0_DATA 21:20
|
|
#define NV_FUSE_OPT_NVDEC_DEFECTIVE__RED_ALIAS_0_WIDTH 2
|
|
#define NV_FUSE_OPT_PCIE_LANE_DEFECTIVE__WIDTH 2
|
|
#define NV_FUSE_OPT_PCIE_LANE_DEFECTIVE__PRI_ALIAS_0 0x00000018
|
|
#define NV_FUSE_OPT_PCIE_LANE_DEFECTIVE__PRI_ALIAS_0_DATA 23:22
|
|
#define NV_FUSE_OPT_PCIE_LANE_DEFECTIVE__PRI_ALIAS_0_WIDTH 2
|
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#define NV_FUSE_OPT_PCIE_LANE_DEFECTIVE__RED_ALIAS_0 0x00000019
|
|
#define NV_FUSE_OPT_PCIE_LANE_DEFECTIVE__RED_ALIAS_0_DATA 23:22
|
|
#define NV_FUSE_OPT_PCIE_LANE_DEFECTIVE__RED_ALIAS_0_WIDTH 2
|
|
#define NV_FUSE_OPT_LTC_DEFECTIVE__WIDTH 12
|
|
#define NV_FUSE_OPT_LTC_DEFECTIVE__PRI_ALIAS_0 0x00000018
|
|
#define NV_FUSE_OPT_LTC_DEFECTIVE__PRI_ALIAS_0_DATA 31:24
|
|
#define NV_FUSE_OPT_LTC_DEFECTIVE__PRI_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_LTC_DEFECTIVE__PRI_ALIAS_1 0x0000001a
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|
#define NV_FUSE_OPT_LTC_DEFECTIVE__PRI_ALIAS_1_DATA 3:0
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|
#define NV_FUSE_OPT_LTC_DEFECTIVE__PRI_ALIAS_1_WIDTH 4
|
|
#define NV_FUSE_OPT_LTC_DEFECTIVE__RED_ALIAS_0 0x00000019
|
|
#define NV_FUSE_OPT_LTC_DEFECTIVE__RED_ALIAS_0_DATA 31:24
|
|
#define NV_FUSE_OPT_LTC_DEFECTIVE__RED_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_LTC_DEFECTIVE__RED_ALIAS_1 0x0000001b
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#define NV_FUSE_OPT_LTC_DEFECTIVE__RED_ALIAS_1_DATA 3:0
|
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#define NV_FUSE_OPT_LTC_DEFECTIVE__RED_ALIAS_1_WIDTH 4
|
|
#define NV_FUSE_OPT_WPR_ENABLED__WIDTH 1
|
|
#define NV_FUSE_OPT_WPR_ENABLED__PRI_ALIAS_0 0x0000001a
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|
#define NV_FUSE_OPT_WPR_ENABLED__PRI_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_WPR_ENABLED__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_WPR_ENABLED__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_WPR_ENABLED__RED_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_WPR_ENABLED__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SUB_REGION_NO_OVERRIDE__WIDTH 1
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|
#define NV_FUSE_OPT_SUB_REGION_NO_OVERRIDE__PRI_ALIAS_0 0x0000001a
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#define NV_FUSE_OPT_SUB_REGION_NO_OVERRIDE__PRI_ALIAS_0_DATA 5:5
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#define NV_FUSE_OPT_SUB_REGION_NO_OVERRIDE__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SUB_REGION_NO_OVERRIDE__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_SUB_REGION_NO_OVERRIDE__RED_ALIAS_0_DATA 5:5
|
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#define NV_FUSE_OPT_SUB_REGION_NO_OVERRIDE__RED_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_FBPA_I1500_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBPA_I1500_WR_SECURE__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_SECURE_FBPA_I1500_WR_SECURE__PRI_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_FBPA_I1500_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBPA_I1500_WR_SECURE__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_SECURE_FBPA_I1500_WR_SECURE__RED_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_FBPA_I1500_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_DECODE_TRAP_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_DECODE_TRAP_WR_SECURE__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_SECURE_DECODE_TRAP_WR_SECURE__PRI_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_SECURE_DECODE_TRAP_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_DECODE_TRAP_WR_SECURE__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_SECURE_DECODE_TRAP_WR_SECURE__RED_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_SECURE_DECODE_TRAP_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE__PRI_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE__RED_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_SECURE_PMC_HOST_GRP0_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE__PRI_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE__RED_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_SECURE_RING_PRIV_LEVEL_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE__PRI_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE__RED_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_OPT_SECURE_RING_RESET_PRIV_LEVEL_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_TARGET_MASK_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_TARGET_MASK_WR_SECURE__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_SECURE_TARGET_MASK_WR_SECURE__PRI_ALIAS_0_DATA 11:11
|
|
#define NV_FUSE_OPT_SECURE_TARGET_MASK_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_TARGET_MASK_WR_SECURE__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_SECURE_TARGET_MASK_WR_SECURE__RED_ALIAS_0_DATA 11:11
|
|
#define NV_FUSE_OPT_SECURE_TARGET_MASK_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBPA_MEM_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBPA_MEM_WR_SECURE__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_SECURE_FBPA_MEM_WR_SECURE__PRI_ALIAS_0_DATA 12:12
|
|
#define NV_FUSE_OPT_SECURE_FBPA_MEM_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBPA_MEM_WR_SECURE__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_SECURE_FBPA_MEM_WR_SECURE__RED_ALIAS_0_DATA 12:12
|
|
#define NV_FUSE_OPT_SECURE_FBPA_MEM_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBIO_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBIO_WR_SECURE__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_SECURE_FBIO_WR_SECURE__PRI_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_OPT_SECURE_FBIO_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FBIO_WR_SECURE__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_SECURE_FBIO_WR_SECURE__RED_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_OPT_SECURE_FBIO_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_RD_SECURE__WIDTH 5
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_RD_SECURE__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_RD_SECURE__PRI_ALIAS_0_DATA 18:14
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_RD_SECURE__PRI_ALIAS_0_WIDTH 5
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_RD_SECURE__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_RD_SECURE__RED_ALIAS_0_DATA 18:14
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_RD_SECURE__RED_ALIAS_0_WIDTH 5
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_WR_SECURE__WIDTH 7
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_WR_SECURE__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_WR_SECURE__PRI_ALIAS_0_DATA 25:19
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_WR_SECURE__PRI_ALIAS_0_WIDTH 7
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_WR_SECURE__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_WR_SECURE__RED_ALIAS_0_DATA 25:19
|
|
#define NV_FUSE_OPT_SECURE_FB_FALCON_FUNCTION_WR_SECURE__RED_ALIAS_0_WIDTH 7
|
|
#define NV_FUSE_OPT_ENABLE_CR_JTAG_SECURITY__WIDTH 1
|
|
#define NV_FUSE_OPT_ENABLE_CR_JTAG_SECURITY__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_ENABLE_CR_JTAG_SECURITY__PRI_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_OPT_ENABLE_CR_JTAG_SECURITY__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_ENABLE_CR_JTAG_SECURITY__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_ENABLE_CR_JTAG_SECURITY__RED_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_OPT_ENABLE_CR_JTAG_SECURITY__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE__PRI_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE__RED_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_SECURE_FUSE_SPEEDOINFO_RD_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_REFURBISHED__WIDTH 1
|
|
#define NV_FUSE_OPT_REFURBISHED__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_REFURBISHED__PRI_ALIAS_0_DATA 28:28
|
|
#define NV_FUSE_OPT_REFURBISHED__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_REFURBISHED__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_REFURBISHED__RED_ALIAS_0_DATA 28:28
|
|
#define NV_FUSE_OPT_REFURBISHED__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_JTAG_SECUREID_VALID__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_JTAG_SECUREID_VALID__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_SECURE_JTAG_SECUREID_VALID__PRI_ALIAS_0_DATA 29:29
|
|
#define NV_FUSE_OPT_SECURE_JTAG_SECUREID_VALID__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_JTAG_SECUREID_VALID__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_SECURE_JTAG_SECUREID_VALID__RED_ALIAS_0_DATA 29:29
|
|
#define NV_FUSE_OPT_SECURE_JTAG_SECUREID_VALID__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1__WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1__PRI_ALIAS_0_DATA 30:30
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1__RED_ALIAS_0_DATA 30:30
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1_CONTROL__PRI_ALIAS_0 0x0000001a
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1_CONTROL__PRI_ALIAS_0_DATA 31:31
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1_CONTROL__RED_ALIAS_0 0x0000001b
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1_CONTROL__RED_ALIAS_0_DATA 31:31
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC1_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2__WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2__PRI_ALIAS_0 0x0000001c
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2__PRI_ALIAS_0_DATA 0:0
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2__RED_ALIAS_0 0x0000001d
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2__RED_ALIAS_0_DATA 0:0
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2_CONTROL__PRI_ALIAS_0 0x0000001c
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2_CONTROL__PRI_ALIAS_0_DATA 1:1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2_CONTROL__RED_ALIAS_0 0x0000001d
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2_CONTROL__RED_ALIAS_0_DATA 1:1
|
|
#define NV_FUSE_OPT_HS_DIS_NVDEC2_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FB_FALCON_PRI_ACCESS_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_FB_FALCON_PRI_ACCESS_DISABLE__PRI_ALIAS_0 0x0000001c
|
|
#define NV_FUSE_OPT_FB_FALCON_PRI_ACCESS_DISABLE__PRI_ALIAS_0_DATA 2:2
|
|
#define NV_FUSE_OPT_FB_FALCON_PRI_ACCESS_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FB_FALCON_PRI_ACCESS_DISABLE__RED_ALIAS_0 0x0000001d
|
|
#define NV_FUSE_OPT_FB_FALCON_PRI_ACCESS_DISABLE__RED_ALIAS_0_DATA 2:2
|
|
#define NV_FUSE_OPT_FB_FALCON_PRI_ACCESS_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0 0x0000001c
|
|
#define NV_FUSE_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0_DATA 3:3
|
|
#define NV_FUSE_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE__RED_ALIAS_0 0x0000001d
|
|
#define NV_FUSE_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE__RED_ALIAS_0_DATA 3:3
|
|
#define NV_FUSE_OPT_SECURE_UTILSCLK_PRIV_SECURE_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE__PRI_ALIAS_0 0x0000001c
|
|
#define NV_FUSE_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE__PRI_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE__RED_ALIAS_0 0x0000001d
|
|
#define NV_FUSE_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE__RED_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_SECURE_CLOCKS_POISON_PILL_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_VPR_ENABLED__WIDTH 1
|
|
#define NV_FUSE_OPT_VPR_ENABLED__PRI_ALIAS_0 0x0000001c
|
|
#define NV_FUSE_OPT_VPR_ENABLED__PRI_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_VPR_ENABLED__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_VPR_ENABLED__RED_ALIAS_0 0x0000001d
|
|
#define NV_FUSE_OPT_VPR_ENABLED__RED_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_VPR_ENABLED__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_CTRL_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_CTRL_WR_SECURE__PRI_ALIAS_0 0x0000001c
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_CTRL_WR_SECURE__PRI_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_CTRL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_CTRL_WR_SECURE__RED_ALIAS_0 0x0000001d
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_CTRL_WR_SECURE__RED_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_HDCP22_CTRL_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVLINK_DEFECTIVE__WIDTH 3
|
|
#define NV_FUSE_OPT_NVLINK_DEFECTIVE__PRI_ALIAS_0 0x0000001c
|
|
#define NV_FUSE_OPT_NVLINK_DEFECTIVE__PRI_ALIAS_0_DATA 9:7
|
|
#define NV_FUSE_OPT_NVLINK_DEFECTIVE__PRI_ALIAS_0_WIDTH 3
|
|
#define NV_FUSE_OPT_NVLINK_DEFECTIVE__RED_ALIAS_0 0x0000001d
|
|
#define NV_FUSE_OPT_NVLINK_DEFECTIVE__RED_ALIAS_0_DATA 9:7
|
|
#define NV_FUSE_OPT_NVLINK_DEFECTIVE__RED_ALIAS_0_WIDTH 3
|
|
#define NV_FUSE_OPT_PES_DEFECTIVE__WIDTH 21
|
|
#define NV_FUSE_OPT_PES_DEFECTIVE__PRI_ALIAS_0 0x0000001c
|
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#define NV_FUSE_OPT_PES_DEFECTIVE__PRI_ALIAS_0_DATA 30:10
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#define NV_FUSE_OPT_PES_DEFECTIVE__PRI_ALIAS_0_WIDTH 21
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#define NV_FUSE_OPT_PES_DEFECTIVE__RED_ALIAS_0 0x0000001d
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#define NV_FUSE_OPT_PES_DEFECTIVE__RED_ALIAS_0_DATA 30:10
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#define NV_FUSE_OPT_PES_DEFECTIVE__RED_ALIAS_0_WIDTH 21
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__WIDTH 24
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__PRI_ALIAS_0 0x0000001c
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__PRI_ALIAS_0_DATA 31:31
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__PRI_ALIAS_1 0x0000001e
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__PRI_ALIAS_1_DATA 22:0
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__PRI_ALIAS_1_WIDTH 23
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__RED_ALIAS_0 0x0000001d
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__RED_ALIAS_0_DATA 31:31
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__RED_ALIAS_1 0x0000001f
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__RED_ALIAS_1_DATA 22:0
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_INPUT_CNTL_WR_SECURE__RED_ALIAS_1_WIDTH 23
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#define NV_FUSE_OPT_HDA_LPBK_DISABLE__WIDTH 1
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#define NV_FUSE_OPT_HDA_LPBK_DISABLE__PRI_ALIAS_0 0x0000001e
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#define NV_FUSE_OPT_HDA_LPBK_DISABLE__PRI_ALIAS_0_DATA 23:23
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#define NV_FUSE_OPT_HDA_LPBK_DISABLE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_HDA_LPBK_DISABLE__RED_ALIAS_0 0x0000001f
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#define NV_FUSE_OPT_HDA_LPBK_DISABLE__RED_ALIAS_0_DATA 23:23
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#define NV_FUSE_OPT_HDA_LPBK_DISABLE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SW_VPR_ENABLED__WIDTH 1
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#define NV_FUSE_OPT_SW_VPR_ENABLED__PRI_ALIAS_0 0x0000001e
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#define NV_FUSE_OPT_SW_VPR_ENABLED__PRI_ALIAS_0_DATA 24:24
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#define NV_FUSE_OPT_SW_VPR_ENABLED__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SW_VPR_ENABLED__RED_ALIAS_0 0x0000001f
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#define NV_FUSE_OPT_SW_VPR_ENABLED__RED_ALIAS_0_DATA 24:24
|
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#define NV_FUSE_OPT_SW_VPR_ENABLED__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__WIDTH 8
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#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__PRI_ALIAS_0 0x0000001e
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#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__PRI_ALIAS_0_DATA 31:25
|
|
#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__PRI_ALIAS_0_WIDTH 7
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#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__PRI_ALIAS_1 0x00000020
|
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#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__PRI_ALIAS_1_DATA 0:0
|
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#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__RED_ALIAS_0 0x0000001f
|
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#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__RED_ALIAS_0_DATA 31:25
|
|
#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__RED_ALIAS_0_WIDTH 7
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#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__RED_ALIAS_1 0x00000021
|
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#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__RED_ALIAS_1_DATA 0:0
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|
#define NV_FUSE_OPT_SECURE_NVLINK_MASK_WR_SECURE__RED_ALIAS_1_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE__PRI_ALIAS_0_DATA 1:1
|
|
#define NV_FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE__RED_ALIAS_0_DATA 1:1
|
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#define NV_FUSE_OPT_SECURE_NVLINK_BUFFER_READY_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE__PRI_ALIAS_0_DATA 2:2
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE__RED_ALIAS_0_DATA 2:2
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_BOUNDARY_SCAN_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_PKC_PK_SELECTION__WIDTH 1
|
|
#define NV_FUSE_OPT_PKC_PK_SELECTION__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_PKC_PK_SELECTION__PRI_ALIAS_0_DATA 3:3
|
|
#define NV_FUSE_OPT_PKC_PK_SELECTION__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_PKC_PK_SELECTION__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_PKC_PK_SELECTION__RED_ALIAS_0_DATA 3:3
|
|
#define NV_FUSE_OPT_PKC_PK_SELECTION__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_SHA2_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_SHA2_EN__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_SHA2_EN__PRI_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_SHA2_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_SHA2_EN__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_SHA2_EN__RED_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_SHA2_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE__PRI_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE__RED_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_SECURE_HOST_PBUS_ACCESS_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_STANDARD_MODE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_STANDARD_MODE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_STANDARD_MODE__PRI_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_STANDARD_MODE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_STANDARD_MODE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_STANDARD_MODE__RED_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_HOST2JTAG_STANDARD_MODE__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_XUSB_REG_SECURE_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_XUSB_REG_SECURE_EN__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_XUSB_REG_SECURE_EN__PRI_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_XUSB_REG_SECURE_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_XUSB_REG_SECURE_EN__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_XUSB_REG_SECURE_EN__RED_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_XUSB_REG_SECURE_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_PPC_EXT_REG_ACCESS_DIS__WIDTH 1
|
|
#define NV_FUSE_OPT_PPC_EXT_REG_ACCESS_DIS__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_PPC_EXT_REG_ACCESS_DIS__PRI_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_PPC_EXT_REG_ACCESS_DIS__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_PPC_EXT_REG_ACCESS_DIS__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_PPC_EXT_REG_ACCESS_DIS__RED_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_PPC_EXT_REG_ACCESS_DIS__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE__PRI_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE__RED_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_SECURE_PMU_SW_CLIENT_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE__PRI_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE__RED_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_OPT_SECURE_PMU_ELPG_DBG_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE__WIDTH 1
|
|
#define NV_FUSE_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE__PRI_ALIAS_0_DATA 11:11
|
|
#define NV_FUSE_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE__RED_ALIAS_0_DATA 11:11
|
|
#define NV_FUSE_OPT_CTRL_BLOCK_FUSE_RESET_JTAG_OVERRIDE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE__PRI_ALIAS_0_DATA 12:12
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE__RED_ALIAS_0_DATA 12:12
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE_CONTROL__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE_CONTROL__PRI_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE_CONTROL__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE_CONTROL__RED_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_OPT_NVJTAG_PROTECTION_ENABLE_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE__PRI_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE__RED_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_OPT_SECURE_FUSE_DEBUGCTRL_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_TPC_GPC6_DEFECTIVE__WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC6_DEFECTIVE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_TPC_GPC6_DEFECTIVE__PRI_ALIAS_0_DATA 20:15
|
|
#define NV_FUSE_OPT_TPC_GPC6_DEFECTIVE__PRI_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_TPC_GPC6_DEFECTIVE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_TPC_GPC6_DEFECTIVE__RED_ALIAS_0_DATA 20:15
|
|
#define NV_FUSE_OPT_TPC_GPC6_DEFECTIVE__RED_ALIAS_0_WIDTH 6
|
|
#define NV_FUSE_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_SECURE_GPCPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_SECURE_NVLINKS_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE__RED_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_SECURE_XTAL4X_PRIV_SECURE_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE__RED_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_SECURE_SPPLL1_PRIV_SECURE_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE__RED_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_OPT_SECURE_SPPLL0_PRIV_SECURE_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0 0x00000021
|
|
#define NV_FUSE_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_OPT_SECURE_VPLLS_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0 0x00000020
|
|
#define NV_FUSE_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0 0x00000021
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#define NV_FUSE_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_DATA 27:27
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#define NV_FUSE_OPT_SECURE_XBARPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0 0x00000020
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#define NV_FUSE_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_DATA 28:28
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#define NV_FUSE_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0 0x00000021
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#define NV_FUSE_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_DATA 28:28
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#define NV_FUSE_OPT_SECURE_SYSPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0 0x00000020
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#define NV_FUSE_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_DATA 29:29
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#define NV_FUSE_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0 0x00000021
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#define NV_FUSE_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_DATA 29:29
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#define NV_FUSE_OPT_SECURE_NVDPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0 0x00000020
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#define NV_FUSE_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_DATA 30:30
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#define NV_FUSE_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0 0x00000021
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#define NV_FUSE_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_DATA 30:30
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#define NV_FUSE_OPT_SECURE_DISPPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_CLOCKS_FMON_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_CLOCKS_FMON_WR_SECURE__PRI_ALIAS_0 0x00000020
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#define NV_FUSE_OPT_SECURE_CLOCKS_FMON_WR_SECURE__PRI_ALIAS_0_DATA 31:31
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#define NV_FUSE_OPT_SECURE_CLOCKS_FMON_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_CLOCKS_FMON_WR_SECURE__RED_ALIAS_0 0x00000021
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#define NV_FUSE_OPT_SECURE_CLOCKS_FMON_WR_SECURE__RED_ALIAS_0_DATA 31:31
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#define NV_FUSE_OPT_SECURE_CLOCKS_FMON_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE__WIDTH 1
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE__PRI_ALIAS_0_DATA 0:0
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE__RED_ALIAS_0_DATA 0:0
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE_CONTROL__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE_CONTROL__PRI_ALIAS_0_DATA 1:1
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE_CONTROL__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE_CONTROL__RED_ALIAS_0_DATA 1:1
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#define NV_FUSE_OPT_HEVC_ENC_DISABLE_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE__WIDTH 1
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE__PRI_ALIAS_0_DATA 2:2
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE__RED_ALIAS_0_DATA 2:2
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE_CONTROL__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE_CONTROL__PRI_ALIAS_0_DATA 3:3
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE_CONTROL__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE_CONTROL__RED_ALIAS_0_DATA 3:3
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#define NV_FUSE_OPT_HEVC_DEC_DISABLE_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE__PRI_ALIAS_0_DATA 4:4
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE__RED_ALIAS_0_DATA 4:4
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#define NV_FUSE_OPT_SECURE_GC6_SCI_SMBUS_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_TSENSE_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_TSENSE_WR_SECURE__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_SECURE_TSENSE_WR_SECURE__PRI_ALIAS_0_DATA 5:5
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#define NV_FUSE_OPT_SECURE_TSENSE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_TSENSE_WR_SECURE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_SECURE_TSENSE_WR_SECURE__RED_ALIAS_0_DATA 5:5
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#define NV_FUSE_OPT_SECURE_TSENSE_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_ROW_REMAPPER_EN__WIDTH 1
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#define NV_FUSE_OPT_ROW_REMAPPER_EN__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_ROW_REMAPPER_EN__PRI_ALIAS_0_DATA 6:6
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#define NV_FUSE_OPT_ROW_REMAPPER_EN__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_ROW_REMAPPER_EN__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_ROW_REMAPPER_EN__RED_ALIAS_0_DATA 6:6
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#define NV_FUSE_OPT_ROW_REMAPPER_EN__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_NV_P2P_PLM_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_NV_P2P_PLM_WR_SECURE__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_SECURE_NV_P2P_PLM_WR_SECURE__PRI_ALIAS_0_DATA 7:7
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#define NV_FUSE_OPT_SECURE_NV_P2P_PLM_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_NV_P2P_PLM_WR_SECURE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_SECURE_NV_P2P_PLM_WR_SECURE__RED_ALIAS_0_DATA 7:7
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#define NV_FUSE_OPT_SECURE_NV_P2P_PLM_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE__PRI_ALIAS_0_DATA 8:8
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#define NV_FUSE_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE__RED_ALIAS_0_DATA 8:8
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#define NV_FUSE_OPT_SECURE_XVE_RESET_CTRL_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE__PRI_ALIAS_0_DATA 9:9
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#define NV_FUSE_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE__RED_ALIAS_0_DATA 9:9
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#define NV_FUSE_OPT_SECURE_XVE_DEFAULT_SECURE_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_CWD_CYA_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_CWD_CYA_WR_SECURE__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_SECURE_CWD_CYA_WR_SECURE__PRI_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_SECURE_CWD_CYA_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_CWD_CYA_WR_SECURE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_SECURE_CWD_CYA_WR_SECURE__RED_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_SECURE_CWD_CYA_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_GCC_DBG_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_GCC_DBG_WR_SECURE__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_SECURE_GCC_DBG_WR_SECURE__PRI_ALIAS_0_DATA 11:11
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#define NV_FUSE_OPT_SECURE_GCC_DBG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_GCC_DBG_WR_SECURE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_SECURE_GCC_DBG_WR_SECURE__RED_ALIAS_0_DATA 11:11
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#define NV_FUSE_OPT_SECURE_GCC_DBG_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE__PRI_ALIAS_0_DATA 12:12
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#define NV_FUSE_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE__RED_ALIAS_0_DATA 12:12
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#define NV_FUSE_OPT_SECURE_CLOCKS_PWRCLK_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_FAN_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_FAN_WR_SECURE__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_SECURE_PMGR_FAN_WR_SECURE__PRI_ALIAS_0_DATA 13:13
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#define NV_FUSE_OPT_SECURE_PMGR_FAN_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_FAN_WR_SECURE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_SECURE_PMGR_FAN_WR_SECURE__RED_ALIAS_0_DATA 13:13
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#define NV_FUSE_OPT_SECURE_PMGR_FAN_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__PRI_ALIAS_0_DATA 14:14
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__RED_ALIAS_0_DATA 14:14
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__PRI_ALIAS_0 0x00000022
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__PRI_ALIAS_0_DATA 15:15
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__RED_ALIAS_0 0x00000023
|
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__RED_ALIAS_0_DATA 15:15
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE__PRI_ALIAS_0 0x00000022
|
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE__PRI_ALIAS_0_DATA 16:16
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE__RED_ALIAS_0_DATA 16:16
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#define NV_FUSE_OPT_SECURE_XVE_PROTECT_DROPOFF_OTHERS_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__PRI_ALIAS_0 0x00000022
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__PRI_ALIAS_0_DATA 17:17
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__RED_ALIAS_0 0x00000023
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__RED_ALIAS_0_DATA 17:17
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_CYA_GRP_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__PRI_ALIAS_0 0x00000022
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__PRI_ALIAS_0_DATA 18:18
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__RED_ALIAS_0 0x00000023
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__RED_ALIAS_0_DATA 18:18
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_NON_CYA_GRP_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE__PRI_ALIAS_0 0x00000022
|
|
#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE__PRI_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE__RED_ALIAS_0 0x00000023
|
|
#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE__RED_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_OPT_SECURE_XP_PROTECT_DROPOFF_OTHERS_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE__PRI_ALIAS_0 0x00000022
|
|
#define NV_FUSE_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE__PRI_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE__RED_ALIAS_0 0x00000023
|
|
#define NV_FUSE_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE__RED_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_OPT_SECURE_RESHIFT_GPC_RAIL_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_SPI_CLK_DIV_SET_SEL__WIDTH 2
|
|
#define NV_FUSE_OPT_SPI_CLK_DIV_SET_SEL__PRI_ALIAS_0 0x00000022
|
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#define NV_FUSE_OPT_SPI_CLK_DIV_SET_SEL__PRI_ALIAS_0_DATA 22:21
|
|
#define NV_FUSE_OPT_SPI_CLK_DIV_SET_SEL__PRI_ALIAS_0_WIDTH 2
|
|
#define NV_FUSE_OPT_SPI_CLK_DIV_SET_SEL__RED_ALIAS_0 0x00000023
|
|
#define NV_FUSE_OPT_SPI_CLK_DIV_SET_SEL__RED_ALIAS_0_DATA 22:21
|
|
#define NV_FUSE_OPT_SPI_CLK_DIV_SET_SEL__RED_ALIAS_0_WIDTH 2
|
|
#define NV_FUSE_OPT_ROP_DEFECTIVE__WIDTH 14
|
|
#define NV_FUSE_OPT_ROP_DEFECTIVE__PRI_ALIAS_0 0x00000022
|
|
#define NV_FUSE_OPT_ROP_DEFECTIVE__PRI_ALIAS_0_DATA 31:23
|
|
#define NV_FUSE_OPT_ROP_DEFECTIVE__PRI_ALIAS_0_WIDTH 9
|
|
#define NV_FUSE_OPT_ROP_DEFECTIVE__PRI_ALIAS_1 0x00000024
|
|
#define NV_FUSE_OPT_ROP_DEFECTIVE__PRI_ALIAS_1_DATA 4:0
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#define NV_FUSE_OPT_ROP_DEFECTIVE__PRI_ALIAS_1_WIDTH 5
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#define NV_FUSE_OPT_ROP_DEFECTIVE__RED_ALIAS_0 0x00000023
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#define NV_FUSE_OPT_ROP_DEFECTIVE__RED_ALIAS_0_DATA 31:23
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#define NV_FUSE_OPT_ROP_DEFECTIVE__RED_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_ROP_DEFECTIVE__RED_ALIAS_1 0x00000025
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#define NV_FUSE_OPT_ROP_DEFECTIVE__RED_ALIAS_1_DATA 4:0
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#define NV_FUSE_OPT_ROP_DEFECTIVE__RED_ALIAS_1_WIDTH 5
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#define NV_FUSE_OPT_SECURE_SKED_CYA_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_SKED_CYA_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_SKED_CYA_WR_SECURE__PRI_ALIAS_0_DATA 5:5
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#define NV_FUSE_OPT_SECURE_SKED_CYA_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_SKED_CYA_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_SKED_CYA_WR_SECURE__RED_ALIAS_0_DATA 5:5
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#define NV_FUSE_OPT_SECURE_SKED_CYA_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_SKED_DEBUG_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_SKED_DEBUG_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_SKED_DEBUG_WR_SECURE__PRI_ALIAS_0_DATA 6:6
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#define NV_FUSE_OPT_SECURE_SKED_DEBUG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_SKED_DEBUG_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_SKED_DEBUG_WR_SECURE__RED_ALIAS_0_DATA 6:6
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#define NV_FUSE_OPT_SECURE_SKED_DEBUG_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE__PRI_ALIAS_0_DATA 7:7
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE__RED_ALIAS_0_DATA 7:7
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_0_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE__PRI_ALIAS_0_DATA 8:8
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE__RED_ALIAS_0_DATA 8:8
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_1_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE__PRI_ALIAS_0_DATA 9:9
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE__RED_ALIAS_0_DATA 9:9
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_2_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE__PRI_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE__RED_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_3_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE__PRI_ALIAS_0_DATA 11:11
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE__RED_ALIAS_0_DATA 11:11
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_4_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE__PRI_ALIAS_0_DATA 12:12
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE__RED_ALIAS_0_DATA 12:12
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_5_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE__PRI_ALIAS_0_DATA 13:13
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE__RED_ALIAS_0_DATA 13:13
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_6_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE__PRI_ALIAS_0_DATA 14:14
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE__RED_ALIAS_0_DATA 14:14
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_7_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE__PRI_ALIAS_0_DATA 15:15
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE__RED_ALIAS_0_DATA 15:15
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_8_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE__PRI_ALIAS_0_DATA 16:16
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE__RED_ALIAS_0_DATA 16:16
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_9_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE__PRI_ALIAS_0_DATA 17:17
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE__RED_ALIAS_0_DATA 17:17
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_10_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE__PRI_ALIAS_0_DATA 18:18
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE__RED_ALIAS_0_DATA 18:18
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_11_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE__PRI_ALIAS_0_DATA 19:19
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE__RED_ALIAS_0_DATA 19:19
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_12_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE__PRI_ALIAS_0_DATA 20:20
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE__RED_ALIAS_0_DATA 20:20
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_13_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE__PRI_ALIAS_0_DATA 21:21
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE__RED_ALIAS_0_DATA 21:21
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_14_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE__PRI_ALIAS_0_DATA 22:22
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE__RED_ALIAS_0_DATA 22:22
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_15_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE__PRI_ALIAS_0_DATA 23:23
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE__RED_ALIAS_0_DATA 23:23
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_16_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE__PRI_ALIAS_0_DATA 24:24
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE__RED_ALIAS_0_DATA 24:24
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_17_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE__PRI_ALIAS_0_DATA 25:25
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE__RED_ALIAS_0_DATA 25:25
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_18_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE__PRI_ALIAS_0_DATA 26:26
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE__RED_ALIAS_0 0x00000025
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE__RED_ALIAS_0_DATA 26:26
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_19_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE__PRI_ALIAS_0 0x00000024
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE__PRI_ALIAS_0_DATA 27:27
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE__RED_ALIAS_0 0x00000025
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE__RED_ALIAS_0_DATA 27:27
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_20_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE__PRI_ALIAS_0 0x00000024
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE__PRI_ALIAS_0_DATA 28:28
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE__RED_ALIAS_0 0x00000025
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE__RED_ALIAS_0_DATA 28:28
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_21_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE__PRI_ALIAS_0 0x00000024
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE__PRI_ALIAS_0_DATA 29:29
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE__RED_ALIAS_0 0x00000025
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE__RED_ALIAS_0_DATA 29:29
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_22_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE__PRI_ALIAS_0 0x00000024
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE__PRI_ALIAS_0_DATA 30:30
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE__RED_ALIAS_0 0x00000025
|
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE__RED_ALIAS_0_DATA 30:30
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_23_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE__PRI_ALIAS_0 0x00000024
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE__PRI_ALIAS_0_DATA 31:31
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE__RED_ALIAS_0 0x00000025
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE__RED_ALIAS_0_DATA 31:31
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_24_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE__PRI_ALIAS_0_DATA 0:0
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE__RED_ALIAS_0_DATA 0:0
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_25_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE__PRI_ALIAS_0_DATA 1:1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE__RED_ALIAS_0_DATA 1:1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_26_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE__PRI_ALIAS_0_DATA 2:2
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE__RED_ALIAS_0_DATA 2:2
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_27_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE__PRI_ALIAS_0_DATA 3:3
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE__RED_ALIAS_0_DATA 3:3
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_28_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE__PRI_ALIAS_0_DATA 4:4
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE__RED_ALIAS_0_DATA 4:4
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_29_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE__PRI_ALIAS_0_DATA 5:5
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE__RED_ALIAS_0_DATA 5:5
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_30_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE__PRI_ALIAS_0_DATA 6:6
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE__RED_ALIAS_0_DATA 6:6
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_31_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE__PRI_ALIAS_0_DATA 7:7
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE__RED_ALIAS_0_DATA 7:7
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_32_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE__PRI_ALIAS_0_DATA 8:8
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE__RED_ALIAS_0_DATA 8:8
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_33_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE__PRI_ALIAS_0_DATA 9:9
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE__RED_ALIAS_0_DATA 9:9
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_34_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE__PRI_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE__RED_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_35_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE__PRI_ALIAS_0_DATA 11:11
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE__RED_ALIAS_0_DATA 11:11
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_36_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE__PRI_ALIAS_0_DATA 12:12
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE__RED_ALIAS_0_DATA 12:12
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_37_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE__PRI_ALIAS_0_DATA 13:13
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE__RED_ALIAS_0_DATA 13:13
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_38_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE__PRI_ALIAS_0_DATA 14:14
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE__RED_ALIAS_0_DATA 14:14
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#define NV_FUSE_OPT_SECURE_PMGR_GPIO_OUT_39_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_THERM_DLPPE_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_THERM_DLPPE_WR_SECURE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_THERM_DLPPE_WR_SECURE__PRI_ALIAS_0_DATA 15:15
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#define NV_FUSE_OPT_SECURE_THERM_DLPPE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_THERM_DLPPE_WR_SECURE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_THERM_DLPPE_WR_SECURE__RED_ALIAS_0_DATA 15:15
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#define NV_FUSE_OPT_SECURE_THERM_DLPPE_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_UCODE_DRIVER_FUB_REV__WIDTH 8
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#define NV_FUSE_OPT_FPF_UCODE_DRIVER_FUB_REV__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_FPF_UCODE_DRIVER_FUB_REV__PRI_ALIAS_0_DATA 23:16
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#define NV_FUSE_OPT_FPF_UCODE_DRIVER_FUB_REV__PRI_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_FPF_UCODE_DRIVER_FUB_REV__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_FPF_UCODE_DRIVER_FUB_REV__RED_ALIAS_0_DATA 23:16
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#define NV_FUSE_OPT_FPF_UCODE_DRIVER_FUB_REV__RED_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE__PRI_ALIAS_0_DATA 24:24
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE__RED_ALIAS_0_DATA 24:24
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE_CONTROL__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE_CONTROL__PRI_ALIAS_0_DATA 25:25
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE_CONTROL__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE_CONTROL__RED_ALIAS_0_DATA 25:25
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#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_MODE_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__WIDTH 8
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__PRI_ALIAS_0 0x00000026
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__PRI_ALIAS_0_DATA 31:26
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__PRI_ALIAS_0_WIDTH 6
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__PRI_ALIAS_1 0x00000028
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__PRI_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__PRI_ALIAS_1_WIDTH 2
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__RED_ALIAS_0 0x00000027
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__RED_ALIAS_0_DATA 31:26
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__RED_ALIAS_0_WIDTH 6
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__RED_ALIAS_1 0x00000029
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__RED_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_L2SLICE_FBP0_DEFECTIVE__RED_ALIAS_1_WIDTH 2
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#define NV_FUSE_OPT_L2SLICE_FBP1_DEFECTIVE__WIDTH 8
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#define NV_FUSE_OPT_L2SLICE_FBP1_DEFECTIVE__PRI_ALIAS_0 0x00000028
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#define NV_FUSE_OPT_L2SLICE_FBP1_DEFECTIVE__PRI_ALIAS_0_DATA 9:2
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#define NV_FUSE_OPT_L2SLICE_FBP1_DEFECTIVE__PRI_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_L2SLICE_FBP1_DEFECTIVE__RED_ALIAS_0 0x00000029
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#define NV_FUSE_OPT_L2SLICE_FBP1_DEFECTIVE__RED_ALIAS_0_DATA 9:2
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#define NV_FUSE_OPT_L2SLICE_FBP1_DEFECTIVE__RED_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_L2SLICE_FBP2_DEFECTIVE__WIDTH 8
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#define NV_FUSE_OPT_L2SLICE_FBP2_DEFECTIVE__PRI_ALIAS_0 0x00000028
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#define NV_FUSE_OPT_L2SLICE_FBP2_DEFECTIVE__PRI_ALIAS_0_DATA 17:10
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#define NV_FUSE_OPT_L2SLICE_FBP2_DEFECTIVE__PRI_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_L2SLICE_FBP2_DEFECTIVE__RED_ALIAS_0 0x00000029
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#define NV_FUSE_OPT_L2SLICE_FBP2_DEFECTIVE__RED_ALIAS_0_DATA 17:10
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#define NV_FUSE_OPT_L2SLICE_FBP2_DEFECTIVE__RED_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_L2SLICE_FBP3_DEFECTIVE__WIDTH 8
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#define NV_FUSE_OPT_L2SLICE_FBP3_DEFECTIVE__PRI_ALIAS_0 0x00000028
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#define NV_FUSE_OPT_L2SLICE_FBP3_DEFECTIVE__PRI_ALIAS_0_DATA 25:18
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#define NV_FUSE_OPT_L2SLICE_FBP3_DEFECTIVE__PRI_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_L2SLICE_FBP3_DEFECTIVE__RED_ALIAS_0 0x00000029
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#define NV_FUSE_OPT_L2SLICE_FBP3_DEFECTIVE__RED_ALIAS_0_DATA 25:18
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#define NV_FUSE_OPT_L2SLICE_FBP3_DEFECTIVE__RED_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__WIDTH 8
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__PRI_ALIAS_0 0x00000028
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__PRI_ALIAS_0_DATA 31:26
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__PRI_ALIAS_0_WIDTH 6
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__PRI_ALIAS_1 0x0000002a
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__PRI_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__PRI_ALIAS_1_WIDTH 2
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__RED_ALIAS_0 0x00000029
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__RED_ALIAS_0_DATA 31:26
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__RED_ALIAS_0_WIDTH 6
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__RED_ALIAS_1 0x0000002b
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__RED_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_L2SLICE_FBP4_DEFECTIVE__RED_ALIAS_1_WIDTH 2
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#define NV_FUSE_OPT_L2SLICE_FBP5_DEFECTIVE__WIDTH 8
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#define NV_FUSE_OPT_L2SLICE_FBP5_DEFECTIVE__PRI_ALIAS_0 0x0000002a
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#define NV_FUSE_OPT_L2SLICE_FBP5_DEFECTIVE__PRI_ALIAS_0_DATA 9:2
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#define NV_FUSE_OPT_L2SLICE_FBP5_DEFECTIVE__PRI_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_L2SLICE_FBP5_DEFECTIVE__RED_ALIAS_0 0x0000002b
|
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#define NV_FUSE_OPT_L2SLICE_FBP5_DEFECTIVE__RED_ALIAS_0_DATA 9:2
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#define NV_FUSE_OPT_L2SLICE_FBP5_DEFECTIVE__RED_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL__PRI_ALIAS_0 0x0000002a
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL__PRI_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL__RED_ALIAS_0 0x0000002b
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL__RED_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL_CONTROL__PRI_ALIAS_0 0x0000002a
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL_CONTROL__PRI_ALIAS_0_DATA 11:11
|
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL_CONTROL__RED_ALIAS_0 0x0000002b
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL_CONTROL__RED_ALIAS_0_DATA 11:11
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#define NV_FUSE_OPT_LANE_MARGINING_CONTROL_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_GPCRR_ENABLE__WIDTH 7
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#define NV_FUSE_OPT_GPCRR_ENABLE__PRI_ALIAS_0 0x0000002a
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#define NV_FUSE_OPT_GPCRR_ENABLE__PRI_ALIAS_0_DATA 18:12
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#define NV_FUSE_OPT_GPCRR_ENABLE__PRI_ALIAS_0_WIDTH 7
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#define NV_FUSE_OPT_GPCRR_ENABLE__RED_ALIAS_0 0x0000002b
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#define NV_FUSE_OPT_GPCRR_ENABLE__RED_ALIAS_0_DATA 18:12
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#define NV_FUSE_OPT_GPCRR_ENABLE__RED_ALIAS_0_WIDTH 7
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#define NV_FUSE_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0 0x0000002a
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#define NV_FUSE_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_DATA 19:19
|
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#define NV_FUSE_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0 0x0000002b
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#define NV_FUSE_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_DATA 19:19
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#define NV_FUSE_OPT_SECURE_DISPHUBPLL_PHYSICAL_DAMAGE_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SPEEDO_ADJ__WIDTH 1
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#define NV_FUSE_OPT_SPEEDO_ADJ__PRI_ALIAS_0 0x0000002a
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#define NV_FUSE_OPT_SPEEDO_ADJ__PRI_ALIAS_0_DATA 20:20
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#define NV_FUSE_OPT_SPEEDO_ADJ__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SPEEDO_ADJ__RED_ALIAS_0 0x0000002b
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#define NV_FUSE_OPT_SPEEDO_ADJ__RED_ALIAS_0_DATA 20:20
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#define NV_FUSE_OPT_SPEEDO_ADJ__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_ISFI_DISABLE__WIDTH 1
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#define NV_FUSE_OPT_ISFI_DISABLE__PRI_ALIAS_0 0x0000002a
|
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#define NV_FUSE_OPT_ISFI_DISABLE__PRI_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_ISFI_DISABLE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_ISFI_DISABLE__RED_ALIAS_0 0x0000002b
|
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#define NV_FUSE_OPT_ISFI_DISABLE__RED_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_ISFI_DISABLE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_ISENSE_ADC_FUSE_TESTSTAGE__WIDTH 3
|
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#define NV_FUSE_OPT_ISENSE_ADC_FUSE_TESTSTAGE__PRI_ALIAS_0 0x0000002a
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|
#define NV_FUSE_OPT_ISENSE_ADC_FUSE_TESTSTAGE__PRI_ALIAS_0_DATA 24:22
|
|
#define NV_FUSE_OPT_ISENSE_ADC_FUSE_TESTSTAGE__PRI_ALIAS_0_WIDTH 3
|
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#define NV_FUSE_OPT_ISENSE_ADC_FUSE_TESTSTAGE__RED_ALIAS_0 0x0000002b
|
|
#define NV_FUSE_OPT_ISENSE_ADC_FUSE_TESTSTAGE__RED_ALIAS_0_DATA 24:22
|
|
#define NV_FUSE_OPT_ISENSE_ADC_FUSE_TESTSTAGE__RED_ALIAS_0_WIDTH 3
|
|
#define NV_FUSE_OPT_SECURE_KFUSE_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_KFUSE_WR_SECURE__PRI_ALIAS_0 0x0000002a
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|
#define NV_FUSE_OPT_SECURE_KFUSE_WR_SECURE__PRI_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_OPT_SECURE_KFUSE_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_KFUSE_WR_SECURE__RED_ALIAS_0 0x0000002b
|
|
#define NV_FUSE_OPT_SECURE_KFUSE_WR_SECURE__RED_ALIAS_0_DATA 25:25
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|
#define NV_FUSE_OPT_SECURE_KFUSE_WR_SECURE__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN__PRI_ALIAS_0 0x0000002a
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|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN__PRI_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN__RED_ALIAS_0 0x0000002b
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN__RED_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_OPT_SECURE_FUSE_CLK_SCPM_SEC_FAULT_EN__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_FUSE_POD_SEC_FAULT_EN__WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_FUSE_POD_SEC_FAULT_EN__PRI_ALIAS_0 0x0000002a
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|
#define NV_FUSE_OPT_SECURE_FUSE_POD_SEC_FAULT_EN__PRI_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_SECURE_FUSE_POD_SEC_FAULT_EN__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_FUSE_POD_SEC_FAULT_EN__RED_ALIAS_0 0x0000002b
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|
#define NV_FUSE_OPT_SECURE_FUSE_POD_SEC_FAULT_EN__RED_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_SECURE_FUSE_POD_SEC_FAULT_EN__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN__WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN__PRI_ALIAS_0 0x0000002a
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|
#define NV_FUSE_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN__PRI_ALIAS_0_DATA 28:28
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|
#define NV_FUSE_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN__RED_ALIAS_0 0x0000002b
|
|
#define NV_FUSE_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN__RED_ALIAS_0_DATA 28:28
|
|
#define NV_FUSE_OPT_SECURE_NVDCLK_SCPM_SEC_FAULT_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE__PRI_ALIAS_0 0x0000002a
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|
#define NV_FUSE_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE__PRI_ALIAS_0_DATA 29:29
|
|
#define NV_FUSE_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE__RED_ALIAS_0 0x0000002b
|
|
#define NV_FUSE_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE__RED_ALIAS_0_DATA 29:29
|
|
#define NV_FUSE_OPT_SECURE_PMU_IDLE_COUNT_WR_SECURE__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE__WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE__PRI_ALIAS_0 0x0000002a
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|
#define NV_FUSE_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE__PRI_ALIAS_0_DATA 30:30
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE__RED_ALIAS_0 0x0000002b
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|
#define NV_FUSE_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE__RED_ALIAS_0_DATA 30:30
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPC_DEGLITCH_CFG_WR_SECURE__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PMU_INTR_1_WR_SECURE__WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PMU_INTR_1_WR_SECURE__PRI_ALIAS_0 0x0000002a
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|
#define NV_FUSE_OPT_SECURE_PMU_INTR_1_WR_SECURE__PRI_ALIAS_0_DATA 31:31
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#define NV_FUSE_OPT_SECURE_PMU_INTR_1_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_PMU_INTR_1_WR_SECURE__RED_ALIAS_0 0x0000002b
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#define NV_FUSE_OPT_SECURE_PMU_INTR_1_WR_SECURE__RED_ALIAS_0_DATA 31:31
|
|
#define NV_FUSE_OPT_SECURE_PMU_INTR_1_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_INTR_0_WR_SECURE__WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PMU_INTR_0_WR_SECURE__PRI_ALIAS_0 0x0000002c
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|
#define NV_FUSE_OPT_SECURE_PMU_INTR_0_WR_SECURE__PRI_ALIAS_0_DATA 0:0
|
|
#define NV_FUSE_OPT_SECURE_PMU_INTR_0_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_INTR_0_WR_SECURE__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_SECURE_PMU_INTR_0_WR_SECURE__RED_ALIAS_0_DATA 0:0
|
|
#define NV_FUSE_OPT_SECURE_PMU_INTR_0_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE__WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE__PRI_ALIAS_0 0x0000002c
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE__PRI_ALIAS_0_DATA 1:1
|
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#define NV_FUSE_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE__RED_ALIAS_0_DATA 1:1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPIO_OUTPUT_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE__PRI_ALIAS_0 0x0000002c
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE__PRI_ALIAS_0_DATA 2:2
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE__RED_ALIAS_0_DATA 2:2
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPIO_GENERAL_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE__PRI_ALIAS_0 0x0000002c
|
|
#define NV_FUSE_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE__PRI_ALIAS_0_DATA 3:3
|
|
#define NV_FUSE_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE__RED_ALIAS_0_DATA 3:3
|
|
#define NV_FUSE_OPT_SECURE_PMU_CMD_HEAD_INTR_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE__PRI_ALIAS_0 0x0000002c
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE__PRI_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE__RED_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_CTRL_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE__PRI_ALIAS_0 0x0000002c
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE__PRI_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE__RED_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_INTERLOCK_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE__PRI_ALIAS_0 0x0000002c
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE__PRI_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE__RED_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_GPC_PRI_ERR_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE__PRI_ALIAS_0 0x0000002c
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE__PRI_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE__RED_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_SECURE_PMU_GPCRG_SECURE_RESET_CTRL_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN__PRI_ALIAS_0 0x0000002c
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN__PRI_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN__RED_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_BOOT_FROM_HS_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN__PRI_ALIAS_0 0x0000002c
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN__PRI_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN__RED_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_NVDEC_FALCON_MOD_EN_AES_RO_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_RESET_EN__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_RESET_EN__PRI_ALIAS_0 0x0000002c
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_RESET_EN__PRI_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_RESET_EN__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_RESET_EN__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_RESET_EN__RED_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_RESET_EN__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_GC6_BSI_RAM_RPG_ENABLE__WIDTH 4
|
|
#define NV_FUSE_OPT_GC6_BSI_RAM_RPG_ENABLE__PRI_ALIAS_0 0x0000002c
|
|
#define NV_FUSE_OPT_GC6_BSI_RAM_RPG_ENABLE__PRI_ALIAS_0_DATA 14:11
|
|
#define NV_FUSE_OPT_GC6_BSI_RAM_RPG_ENABLE__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_GC6_BSI_RAM_RPG_ENABLE__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_GC6_BSI_RAM_RPG_ENABLE__RED_ALIAS_0_DATA 14:11
|
|
#define NV_FUSE_OPT_GC6_BSI_RAM_RPG_ENABLE__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE__PRI_ALIAS_0 0x0000002c
|
|
#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE__PRI_ALIAS_0_DATA 15:15
|
|
#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE__RED_ALIAS_0_DATA 15:15
|
|
#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE__RED_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE_CONTROL__PRI_ALIAS_0 0x0000002c
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#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE_CONTROL__PRI_ALIAS_0_DATA 16:16
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#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE_CONTROL__RED_ALIAS_0 0x0000002d
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#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE_CONTROL__RED_ALIAS_0_DATA 16:16
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#define NV_FUSE_OPT_DECODE_TRAP_READ_PROTECTION_DISABLE_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_EN__WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_EN__PRI_ALIAS_0 0x0000002c
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#define NV_FUSE_OPT_RISCV_DCLS_EN__PRI_ALIAS_0_DATA 17:17
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#define NV_FUSE_OPT_RISCV_DCLS_EN__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_EN__RED_ALIAS_0 0x0000002d
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#define NV_FUSE_OPT_RISCV_DCLS_EN__RED_ALIAS_0_DATA 17:17
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#define NV_FUSE_OPT_RISCV_DCLS_EN__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_EN_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_EN_CONTROL__PRI_ALIAS_0 0x0000002c
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#define NV_FUSE_OPT_RISCV_DCLS_EN_CONTROL__PRI_ALIAS_0_DATA 18:18
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#define NV_FUSE_OPT_RISCV_DCLS_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_EN_CONTROL__RED_ALIAS_0 0x0000002d
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#define NV_FUSE_OPT_RISCV_DCLS_EN_CONTROL__RED_ALIAS_0_DATA 18:18
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#define NV_FUSE_OPT_RISCV_DCLS_EN_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_ISFI_WR_SECURE__WIDTH 1
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#define NV_FUSE_OPT_SECURE_ISFI_WR_SECURE__PRI_ALIAS_0 0x0000002c
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#define NV_FUSE_OPT_SECURE_ISFI_WR_SECURE__PRI_ALIAS_0_DATA 19:19
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#define NV_FUSE_OPT_SECURE_ISFI_WR_SECURE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_ISFI_WR_SECURE__RED_ALIAS_0 0x0000002d
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#define NV_FUSE_OPT_SECURE_ISFI_WR_SECURE__RED_ALIAS_0_DATA 19:19
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#define NV_FUSE_OPT_SECURE_ISFI_WR_SECURE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_GSP_FALCON_BOOT_FROM_HS_EN__WIDTH 1
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#define NV_FUSE_OPT_GSP_FALCON_BOOT_FROM_HS_EN__PRI_ALIAS_0 0x0000002c
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#define NV_FUSE_OPT_GSP_FALCON_BOOT_FROM_HS_EN__PRI_ALIAS_0_DATA 20:20
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#define NV_FUSE_OPT_GSP_FALCON_BOOT_FROM_HS_EN__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_GSP_FALCON_BOOT_FROM_HS_EN__RED_ALIAS_0 0x0000002d
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#define NV_FUSE_OPT_GSP_FALCON_BOOT_FROM_HS_EN__RED_ALIAS_0_DATA 20:20
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#define NV_FUSE_OPT_GSP_FALCON_BOOT_FROM_HS_EN__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_GSP_FALCON_MOD_EN_AES_RO_EN__WIDTH 1
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#define NV_FUSE_OPT_GSP_FALCON_MOD_EN_AES_RO_EN__PRI_ALIAS_0 0x0000002c
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|
#define NV_FUSE_OPT_GSP_FALCON_MOD_EN_AES_RO_EN__PRI_ALIAS_0_DATA 21:21
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|
#define NV_FUSE_OPT_GSP_FALCON_MOD_EN_AES_RO_EN__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_GSP_FALCON_MOD_EN_AES_RO_EN__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_GSP_FALCON_MOD_EN_AES_RO_EN__RED_ALIAS_0_DATA 21:21
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#define NV_FUSE_OPT_GSP_FALCON_MOD_EN_AES_RO_EN__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SEC_FALCON_BOOT_FROM_HS_EN__WIDTH 1
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#define NV_FUSE_OPT_SEC_FALCON_BOOT_FROM_HS_EN__PRI_ALIAS_0 0x0000002c
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|
#define NV_FUSE_OPT_SEC_FALCON_BOOT_FROM_HS_EN__PRI_ALIAS_0_DATA 22:22
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#define NV_FUSE_OPT_SEC_FALCON_BOOT_FROM_HS_EN__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SEC_FALCON_BOOT_FROM_HS_EN__RED_ALIAS_0 0x0000002d
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#define NV_FUSE_OPT_SEC_FALCON_BOOT_FROM_HS_EN__RED_ALIAS_0_DATA 22:22
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#define NV_FUSE_OPT_SEC_FALCON_BOOT_FROM_HS_EN__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SEC_FALCON_MOD_EN_AES_RO_EN__WIDTH 1
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|
#define NV_FUSE_OPT_SEC_FALCON_MOD_EN_AES_RO_EN__PRI_ALIAS_0 0x0000002c
|
|
#define NV_FUSE_OPT_SEC_FALCON_MOD_EN_AES_RO_EN__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_SEC_FALCON_MOD_EN_AES_RO_EN__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SEC_FALCON_MOD_EN_AES_RO_EN__RED_ALIAS_0 0x0000002d
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|
#define NV_FUSE_OPT_SEC_FALCON_MOD_EN_AES_RO_EN__RED_ALIAS_0_DATA 23:23
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|
#define NV_FUSE_OPT_SEC_FALCON_MOD_EN_AES_RO_EN__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_PMU_FALCON_BOOT_FROM_HS_EN__WIDTH 1
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|
#define NV_FUSE_OPT_PMU_FALCON_BOOT_FROM_HS_EN__PRI_ALIAS_0 0x0000002c
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|
#define NV_FUSE_OPT_PMU_FALCON_BOOT_FROM_HS_EN__PRI_ALIAS_0_DATA 24:24
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#define NV_FUSE_OPT_PMU_FALCON_BOOT_FROM_HS_EN__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_PMU_FALCON_BOOT_FROM_HS_EN__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_PMU_FALCON_BOOT_FROM_HS_EN__RED_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_PMU_FALCON_BOOT_FROM_HS_EN__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_PMU_FALCON_MOD_EN_AES_RO_EN__WIDTH 1
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|
#define NV_FUSE_OPT_PMU_FALCON_MOD_EN_AES_RO_EN__PRI_ALIAS_0 0x0000002c
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|
#define NV_FUSE_OPT_PMU_FALCON_MOD_EN_AES_RO_EN__PRI_ALIAS_0_DATA 25:25
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#define NV_FUSE_OPT_PMU_FALCON_MOD_EN_AES_RO_EN__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_PMU_FALCON_MOD_EN_AES_RO_EN__RED_ALIAS_0 0x0000002d
|
|
#define NV_FUSE_OPT_PMU_FALCON_MOD_EN_AES_RO_EN__RED_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_OPT_PMU_FALCON_MOD_EN_AES_RO_EN__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_GSP_RISCV_DEV_DIS__WIDTH 1
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|
#define NV_FUSE_OPT_GSP_RISCV_DEV_DIS__PRI_ALIAS_0 0x0000002c
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|
#define NV_FUSE_OPT_GSP_RISCV_DEV_DIS__PRI_ALIAS_0_DATA 26:26
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|
#define NV_FUSE_OPT_GSP_RISCV_DEV_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_GSP_RISCV_DEV_DIS__RED_ALIAS_0 0x0000002d
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|
#define NV_FUSE_OPT_GSP_RISCV_DEV_DIS__RED_ALIAS_0_DATA 26:26
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|
#define NV_FUSE_OPT_GSP_RISCV_DEV_DIS__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SEC_RISCV_DEV_DIS__WIDTH 1
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|
#define NV_FUSE_OPT_SEC_RISCV_DEV_DIS__PRI_ALIAS_0 0x0000002c
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|
#define NV_FUSE_OPT_SEC_RISCV_DEV_DIS__PRI_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_SEC_RISCV_DEV_DIS__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_SEC_RISCV_DEV_DIS__RED_ALIAS_0 0x0000002d
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|
#define NV_FUSE_OPT_SEC_RISCV_DEV_DIS__RED_ALIAS_0_DATA 27:27
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|
#define NV_FUSE_OPT_SEC_RISCV_DEV_DIS__RED_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_OPT_PMU_RISCV_DEV_DIS__WIDTH 1
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#define NV_FUSE_OPT_PMU_RISCV_DEV_DIS__PRI_ALIAS_0 0x0000002c
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|
#define NV_FUSE_OPT_PMU_RISCV_DEV_DIS__PRI_ALIAS_0_DATA 28:28
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#define NV_FUSE_OPT_PMU_RISCV_DEV_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_PMU_RISCV_DEV_DIS__RED_ALIAS_0 0x0000002d
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|
#define NV_FUSE_OPT_PMU_RISCV_DEV_DIS__RED_ALIAS_0_DATA 28:28
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#define NV_FUSE_OPT_PMU_RISCV_DEV_DIS__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT__WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT__PRI_ALIAS_0 0x0000002c
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT__PRI_ALIAS_0_DATA 29:29
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT__RED_ALIAS_0 0x0000002d
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT__RED_ALIAS_0_DATA 29:29
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT_CONTROL__PRI_ALIAS_0 0x0000002c
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT_CONTROL__PRI_ALIAS_0_DATA 30:30
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT_CONTROL__RED_ALIAS_0 0x0000002d
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT_CONTROL__RED_ALIAS_0_DATA 30:30
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_HALT_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT__WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT__PRI_ALIAS_0 0x0000002c
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT__PRI_ALIAS_0_DATA 31:31
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT__RED_ALIAS_0 0x0000002d
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT__RED_ALIAS_0_DATA 31:31
|
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT_CONTROL__PRI_ALIAS_0 0x0000002e
|
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT_CONTROL__PRI_ALIAS_0_DATA 0:0
|
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT_CONTROL__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT_CONTROL__RED_ALIAS_0 0x0000002f
|
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT_CONTROL__RED_ALIAS_0_DATA 0:0
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_ASSERT_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT__WIDTH 1
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|
#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT__PRI_ALIAS_0_DATA 1:1
|
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT__RED_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT__RED_ALIAS_0_DATA 1:1
|
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT__RED_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT_CONTROL__WIDTH 1
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|
#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT_CONTROL__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT_CONTROL__PRI_ALIAS_0_DATA 2:2
|
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT_CONTROL__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT_CONTROL__RED_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT_CONTROL__RED_ALIAS_0_DATA 2:2
|
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#define NV_FUSE_OPT_RISCV_DCLS_SECURITY_ACTION_INTERRUPT_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE__WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE__PRI_ALIAS_0_DATA 3:3
|
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#define NV_FUSE_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE__RED_ALIAS_0 0x0000002f
|
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#define NV_FUSE_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE__RED_ALIAS_0_DATA 3:3
|
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#define NV_FUSE_OPT_SECURE_CLOCKS_CORE_CLOCKS_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_SECURE_CLOCKS_MCLK_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_CLOCKS_MCLK_WR_SECURE__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_OPT_SECURE_CLOCKS_MCLK_WR_SECURE__PRI_ALIAS_0_DATA 4:4
|
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#define NV_FUSE_OPT_SECURE_CLOCKS_MCLK_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_CLOCKS_MCLK_WR_SECURE__RED_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_OPT_SECURE_CLOCKS_MCLK_WR_SECURE__RED_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_OPT_SECURE_CLOCKS_MCLK_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SEC_DEFAULT_CORE_SELECT__WIDTH 1
|
|
#define NV_FUSE_OPT_SEC_DEFAULT_CORE_SELECT__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_OPT_SEC_DEFAULT_CORE_SELECT__PRI_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_SEC_DEFAULT_CORE_SELECT__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SEC_DEFAULT_CORE_SELECT__RED_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_OPT_SEC_DEFAULT_CORE_SELECT__RED_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_OPT_SEC_DEFAULT_CORE_SELECT__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_PMU_DEFAULT_CORE_SELECT__WIDTH 1
|
|
#define NV_FUSE_OPT_PMU_DEFAULT_CORE_SELECT__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_OPT_PMU_DEFAULT_CORE_SELECT__PRI_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_PMU_DEFAULT_CORE_SELECT__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_PMU_DEFAULT_CORE_SELECT__RED_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_OPT_PMU_DEFAULT_CORE_SELECT__RED_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_OPT_PMU_DEFAULT_CORE_SELECT__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_GSP_DEFAULT_CORE_SELECT__WIDTH 1
|
|
#define NV_FUSE_OPT_GSP_DEFAULT_CORE_SELECT__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_OPT_GSP_DEFAULT_CORE_SELECT__PRI_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_GSP_DEFAULT_CORE_SELECT__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_GSP_DEFAULT_CORE_SELECT__RED_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_OPT_GSP_DEFAULT_CORE_SELECT__RED_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_OPT_GSP_DEFAULT_CORE_SELECT__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE__PRI_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE__RED_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE__RED_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_SECURE_HDCP_DEBUG_CRC_RD_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE__PRI_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE__RED_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE__RED_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_OPT_SECURE_SEC_FAULT_CONFIG_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE__WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE__PRI_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE__RED_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE__RED_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_OPT_SECURE_FEATURE_OVERRIDE_MEMQUAL_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_0__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_0__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_0__PRI_ALIAS_0_DATA 11:11
|
|
#define NV_FUSE_SPARE_BIT_0__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_1__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_1__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_1__PRI_ALIAS_0_DATA 12:12
|
|
#define NV_FUSE_SPARE_BIT_1__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_2__WIDTH 1
|
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#define NV_FUSE_SPARE_BIT_2__PRI_ALIAS_0 0x0000002e
|
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#define NV_FUSE_SPARE_BIT_2__PRI_ALIAS_0_DATA 13:13
|
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#define NV_FUSE_SPARE_BIT_2__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_SPARE_BIT_3__WIDTH 1
|
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#define NV_FUSE_SPARE_BIT_3__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_3__PRI_ALIAS_0_DATA 14:14
|
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#define NV_FUSE_SPARE_BIT_3__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_SPARE_BIT_4__WIDTH 1
|
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#define NV_FUSE_SPARE_BIT_4__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_4__PRI_ALIAS_0_DATA 15:15
|
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#define NV_FUSE_SPARE_BIT_4__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_SPARE_BIT_5__WIDTH 1
|
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#define NV_FUSE_SPARE_BIT_5__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_5__PRI_ALIAS_0_DATA 16:16
|
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#define NV_FUSE_SPARE_BIT_5__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_6__WIDTH 1
|
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#define NV_FUSE_SPARE_BIT_6__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_6__PRI_ALIAS_0_DATA 17:17
|
|
#define NV_FUSE_SPARE_BIT_6__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_SPARE_BIT_7__WIDTH 1
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#define NV_FUSE_SPARE_BIT_7__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_7__PRI_ALIAS_0_DATA 18:18
|
|
#define NV_FUSE_SPARE_BIT_7__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_SPARE_BIT_8__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_8__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_8__PRI_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_SPARE_BIT_8__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_SPARE_BIT_9__WIDTH 1
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#define NV_FUSE_SPARE_BIT_9__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_9__PRI_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_SPARE_BIT_9__PRI_ALIAS_0_WIDTH 1
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|
#define NV_FUSE_SPARE_BIT_10__WIDTH 1
|
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#define NV_FUSE_SPARE_BIT_10__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_10__PRI_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_SPARE_BIT_10__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_11__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_11__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_11__PRI_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_SPARE_BIT_11__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_SPARE_BIT_12__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_12__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_12__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_SPARE_BIT_12__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_13__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_13__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_13__PRI_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_SPARE_BIT_13__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_14__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_14__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_14__PRI_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_SPARE_BIT_14__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_15__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_15__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_15__PRI_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_SPARE_BIT_15__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_16__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_16__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_16__PRI_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_SPARE_BIT_16__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_17__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_17__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_17__PRI_ALIAS_0_DATA 28:28
|
|
#define NV_FUSE_SPARE_BIT_17__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_18__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_18__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_18__PRI_ALIAS_0_DATA 29:29
|
|
#define NV_FUSE_SPARE_BIT_18__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_19__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_19__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_19__PRI_ALIAS_0_DATA 30:30
|
|
#define NV_FUSE_SPARE_BIT_19__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_20__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_20__PRI_ALIAS_0 0x0000002e
|
|
#define NV_FUSE_SPARE_BIT_20__PRI_ALIAS_0_DATA 31:31
|
|
#define NV_FUSE_SPARE_BIT_20__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_21__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_21__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_21__PRI_ALIAS_0_DATA 11:11
|
|
#define NV_FUSE_SPARE_BIT_21__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_22__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_22__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_22__PRI_ALIAS_0_DATA 12:12
|
|
#define NV_FUSE_SPARE_BIT_22__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_23__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_23__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_23__PRI_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_SPARE_BIT_23__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_24__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_24__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_24__PRI_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_SPARE_BIT_24__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_25__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_25__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_25__PRI_ALIAS_0_DATA 15:15
|
|
#define NV_FUSE_SPARE_BIT_25__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_26__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_26__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_26__PRI_ALIAS_0_DATA 16:16
|
|
#define NV_FUSE_SPARE_BIT_26__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_27__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_27__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_27__PRI_ALIAS_0_DATA 17:17
|
|
#define NV_FUSE_SPARE_BIT_27__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_28__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_28__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_28__PRI_ALIAS_0_DATA 18:18
|
|
#define NV_FUSE_SPARE_BIT_28__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_29__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_29__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_29__PRI_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_SPARE_BIT_29__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_30__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_30__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_30__PRI_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_SPARE_BIT_30__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_31__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_31__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_31__PRI_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_SPARE_BIT_31__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_32__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_32__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_32__PRI_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_SPARE_BIT_32__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_33__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_33__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_33__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_SPARE_BIT_33__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_34__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_34__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_34__PRI_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_SPARE_BIT_34__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_35__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_35__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_35__PRI_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_SPARE_BIT_35__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_36__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_36__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_36__PRI_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_SPARE_BIT_36__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_37__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_37__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_37__PRI_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_SPARE_BIT_37__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_38__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_38__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_38__PRI_ALIAS_0_DATA 28:28
|
|
#define NV_FUSE_SPARE_BIT_38__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_39__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_39__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_39__PRI_ALIAS_0_DATA 29:29
|
|
#define NV_FUSE_SPARE_BIT_39__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_40__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_40__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_40__PRI_ALIAS_0_DATA 30:30
|
|
#define NV_FUSE_SPARE_BIT_40__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_41__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_41__PRI_ALIAS_0 0x0000002f
|
|
#define NV_FUSE_SPARE_BIT_41__PRI_ALIAS_0_DATA 31:31
|
|
#define NV_FUSE_SPARE_BIT_41__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_0__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_0__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_0__PRI_ALIAS_0_DATA 0:0
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_0__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_0_CONTROL__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_0_CONTROL__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_0_CONTROL__PRI_ALIAS_0_DATA 1:1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_0_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_1__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_1__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_1__PRI_ALIAS_0_DATA 2:2
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_1__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_1_CONTROL__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_1_CONTROL__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_1_CONTROL__PRI_ALIAS_0_DATA 3:3
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_1_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2__PRI_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2_CONTROL__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2_CONTROL__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2_CONTROL__PRI_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_2_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3__PRI_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3_CONTROL__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3_CONTROL__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3_CONTROL__PRI_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_3_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_4__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_4__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_4__PRI_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_4__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_4_CONTROL__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_4_CONTROL__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_4_CONTROL__PRI_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_SPARE_BIT_ENDIS_4_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_42__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_42__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_42__PRI_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_SPARE_BIT_42__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_43__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_43__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_43__PRI_ALIAS_0_DATA 11:11
|
|
#define NV_FUSE_SPARE_BIT_43__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_44__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_44__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_44__PRI_ALIAS_0_DATA 12:12
|
|
#define NV_FUSE_SPARE_BIT_44__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_45__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_45__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_45__PRI_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_SPARE_BIT_45__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_46__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_46__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_46__PRI_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_SPARE_BIT_46__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_47__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_47__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_47__PRI_ALIAS_0_DATA 15:15
|
|
#define NV_FUSE_SPARE_BIT_47__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_48__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_48__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_48__PRI_ALIAS_0_DATA 16:16
|
|
#define NV_FUSE_SPARE_BIT_48__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_49__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_49__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_49__PRI_ALIAS_0_DATA 17:17
|
|
#define NV_FUSE_SPARE_BIT_49__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_50__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_50__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_50__PRI_ALIAS_0_DATA 18:18
|
|
#define NV_FUSE_SPARE_BIT_50__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_51__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_51__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_51__PRI_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_SPARE_BIT_51__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_52__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_52__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_52__PRI_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_SPARE_BIT_52__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_53__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_53__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_53__PRI_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_SPARE_BIT_53__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_54__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_54__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_54__PRI_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_SPARE_BIT_54__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_55__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_55__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_55__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_SPARE_BIT_55__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_56__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_56__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_56__PRI_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_SPARE_BIT_56__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_57__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_57__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_57__PRI_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_SPARE_BIT_57__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_58__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_58__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_58__PRI_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_SPARE_BIT_58__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_59__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_59__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_59__PRI_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_SPARE_BIT_59__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_60__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_60__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_60__PRI_ALIAS_0_DATA 28:28
|
|
#define NV_FUSE_SPARE_BIT_60__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_61__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_61__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_61__PRI_ALIAS_0_DATA 29:29
|
|
#define NV_FUSE_SPARE_BIT_61__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_62__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_62__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_62__PRI_ALIAS_0_DATA 30:30
|
|
#define NV_FUSE_SPARE_BIT_62__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_63__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_63__PRI_ALIAS_0 0x00000030
|
|
#define NV_FUSE_SPARE_BIT_63__PRI_ALIAS_0_DATA 31:31
|
|
#define NV_FUSE_SPARE_BIT_63__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_FLW0__WIDTH 1
|
|
#define NV_FUSE_FLW0__PRI_ALIAS_0 0x00000031
|
|
#define NV_FUSE_FLW0__PRI_ALIAS_0_DATA 0:0
|
|
#define NV_FUSE_FLW0__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_0__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_0__PRI_ALIAS_0 0x00000031
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_0__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_0__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_0__PRI_ALIAS_1 0x00000032
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_0__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_0__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_1__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_1__PRI_ALIAS_0 0x00000032
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_1__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_1__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_1__PRI_ALIAS_1 0x00000033
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_1__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_1__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_2__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_2__PRI_ALIAS_0 0x00000033
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_2__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_2__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_2__PRI_ALIAS_1 0x00000034
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_2__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_2__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_3__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_3__PRI_ALIAS_0 0x00000034
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_3__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_3__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_3__PRI_ALIAS_1 0x00000035
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_3__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_PROTECTINFO_PLAINTEXT_3__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_0__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_0__PRI_ALIAS_0 0x00000035
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_0__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_0__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_0__PRI_ALIAS_1 0x00000036
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_0__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_0__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_1__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_1__PRI_ALIAS_0 0x00000036
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_1__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_1__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_1__PRI_ALIAS_1 0x00000037
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_1__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_1__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_2__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_2__PRI_ALIAS_0 0x00000037
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_2__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_2__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_2__PRI_ALIAS_1 0x00000038
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_2__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_2__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_3__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_3__PRI_ALIAS_0 0x00000038
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_3__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_3__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_3__PRI_ALIAS_1 0x00000039
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_3__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_SIGNATURE_3__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_HEADER_PLAINTEXT__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_HEADER_PLAINTEXT__PRI_ALIAS_0 0x00000039
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_HEADER_PLAINTEXT__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_HEADER_PLAINTEXT__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_HEADER_PLAINTEXT__PRI_ALIAS_1 0x0000003a
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_HEADER_PLAINTEXT__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_HEADER_PLAINTEXT__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_0__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_0__PRI_ALIAS_0 0x0000003a
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_0__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_0__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_0__PRI_ALIAS_1 0x0000003b
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_0__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_0__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_1__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_1__PRI_ALIAS_0 0x0000003b
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_1__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_1__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_1__PRI_ALIAS_1 0x0000003c
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_1__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_1__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_2__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_2__PRI_ALIAS_0 0x0000003c
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_2__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_2__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_2__PRI_ALIAS_1 0x0000003d
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_2__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_2__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_3__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_3__PRI_ALIAS_0 0x0000003d
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_3__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_3__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_3__PRI_ALIAS_1 0x0000003e
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_3__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_3__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_4__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_4__PRI_ALIAS_0 0x0000003e
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_4__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_4__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_4__PRI_ALIAS_1 0x0000003f
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_4__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_4__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_5__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_5__PRI_ALIAS_0 0x0000003f
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_5__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_5__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_5__PRI_ALIAS_1 0x00000040
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_5__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_5__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_6__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_6__PRI_ALIAS_0 0x00000040
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_6__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_6__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_6__PRI_ALIAS_1 0x00000041
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_6__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_6__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_7__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_7__PRI_ALIAS_0 0x00000041
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_7__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_7__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_7__PRI_ALIAS_1 0x00000042
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_7__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_7__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_8__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_8__PRI_ALIAS_0 0x00000042
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_8__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_8__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_8__PRI_ALIAS_1 0x00000043
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_8__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_8__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_9__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_9__PRI_ALIAS_0 0x00000043
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_9__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_9__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_9__PRI_ALIAS_1 0x00000044
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_9__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_9__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_10__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_10__PRI_ALIAS_0 0x00000044
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_10__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_10__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_10__PRI_ALIAS_1 0x00000045
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_10__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_10__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_11__WIDTH 32
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_11__PRI_ALIAS_0 0x00000045
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_11__PRI_ALIAS_0_DATA 31:1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_11__PRI_ALIAS_0_WIDTH 31
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_11__PRI_ALIAS_1 0x00000046
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_11__PRI_ALIAS_1_DATA 0:0
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_11__PRI_ALIAS_1_WIDTH 1
|
|
#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_12__WIDTH 32
|
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_12__PRI_ALIAS_0 0x00000046
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_12__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_12__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_12__PRI_ALIAS_1 0x00000047
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_12__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_12__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_13__WIDTH 32
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_13__PRI_ALIAS_0 0x00000047
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_13__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_13__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_13__PRI_ALIAS_1 0x00000048
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_13__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_13__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_14__WIDTH 32
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_14__PRI_ALIAS_0 0x00000048
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_14__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_14__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_14__PRI_ALIAS_1 0x00000049
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_14__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_14__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_15__WIDTH 32
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_15__PRI_ALIAS_0 0x00000049
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_15__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_15__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_15__PRI_ALIAS_1 0x0000004a
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_15__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_15__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_16__WIDTH 32
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_16__PRI_ALIAS_0 0x0000004a
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_16__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_16__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_16__PRI_ALIAS_1 0x0000004b
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_16__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_16__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_17__WIDTH 32
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_17__PRI_ALIAS_0 0x0000004b
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_17__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_17__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_17__PRI_ALIAS_1 0x0000004c
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_17__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_17__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_18__WIDTH 32
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_18__PRI_ALIAS_0 0x0000004c
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_18__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_18__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_18__PRI_ALIAS_1 0x0000004d
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_18__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_18__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_19__WIDTH 32
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_19__PRI_ALIAS_0 0x0000004d
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_19__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_19__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_19__PRI_ALIAS_1 0x0000004e
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_19__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_ENC_FUSE_KEY_PAYLOAD_KEYS_CIPHERTEXT_19__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_H0__WIDTH 32
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#define NV_FUSE_H0__PRI_ALIAS_0 0x0000004e
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#define NV_FUSE_H0__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_H0__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_H0__PRI_ALIAS_1 0x0000004f
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#define NV_FUSE_H0__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_H0__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_OPT_PRIV_SFK_0__WIDTH 32
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#define NV_FUSE_OPT_PRIV_SFK_0__PRI_ALIAS_0 0x0000004f
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#define NV_FUSE_OPT_PRIV_SFK_0__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_PRIV_SFK_0__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_PRIV_SFK_0__PRI_ALIAS_1 0x00000050
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#define NV_FUSE_OPT_PRIV_SFK_0__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_PRIV_SFK_0__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_OPT_PRIV_SFK_1__WIDTH 32
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#define NV_FUSE_OPT_PRIV_SFK_1__PRI_ALIAS_0 0x00000050
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#define NV_FUSE_OPT_PRIV_SFK_1__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_PRIV_SFK_1__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_PRIV_SFK_1__PRI_ALIAS_1 0x00000051
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#define NV_FUSE_OPT_PRIV_SFK_1__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_PRIV_SFK_1__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_OPT_PRIV_SFK_2__WIDTH 32
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#define NV_FUSE_OPT_PRIV_SFK_2__PRI_ALIAS_0 0x00000051
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#define NV_FUSE_OPT_PRIV_SFK_2__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_PRIV_SFK_2__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_PRIV_SFK_2__PRI_ALIAS_1 0x00000052
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#define NV_FUSE_OPT_PRIV_SFK_2__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_PRIV_SFK_2__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_OPT_PRIV_SFK_3__WIDTH 32
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#define NV_FUSE_OPT_PRIV_SFK_3__PRI_ALIAS_0 0x00000052
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#define NV_FUSE_OPT_PRIV_SFK_3__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_PRIV_SFK_3__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_PRIV_SFK_3__PRI_ALIAS_1 0x00000053
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#define NV_FUSE_OPT_PRIV_SFK_3__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_PRIV_SFK_3__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_OPT_PDI_0__WIDTH 32
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#define NV_FUSE_OPT_PDI_0__PRI_ALIAS_0 0x00000053
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#define NV_FUSE_OPT_PDI_0__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_PDI_0__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_PDI_0__PRI_ALIAS_1 0x00000054
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#define NV_FUSE_OPT_PDI_0__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_PDI_0__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_OPT_PDI_1__WIDTH 32
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#define NV_FUSE_OPT_PDI_1__PRI_ALIAS_0 0x00000054
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#define NV_FUSE_OPT_PDI_1__PRI_ALIAS_0_DATA 31:1
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#define NV_FUSE_OPT_PDI_1__PRI_ALIAS_0_WIDTH 31
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#define NV_FUSE_OPT_PDI_1__PRI_ALIAS_1 0x00000055
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#define NV_FUSE_OPT_PDI_1__PRI_ALIAS_1_DATA 0:0
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#define NV_FUSE_OPT_PDI_1__PRI_ALIAS_1_WIDTH 1
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#define NV_FUSE_FLW1__WIDTH 1
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#define NV_FUSE_FLW1__PRI_ALIAS_0 0x00000055
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#define NV_FUSE_FLW1__PRI_ALIAS_0_DATA 1:1
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#define NV_FUSE_FLW1__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_PKC_PK_0__WIDTH 32
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#define NV_FUSE_OPT_PKC_PK_0__PRI_ALIAS_0 0x00000055
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#define NV_FUSE_OPT_PKC_PK_0__PRI_ALIAS_0_DATA 31:2
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#define NV_FUSE_OPT_PKC_PK_0__PRI_ALIAS_0_WIDTH 30
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#define NV_FUSE_OPT_PKC_PK_0__PRI_ALIAS_1 0x00000056
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#define NV_FUSE_OPT_PKC_PK_0__PRI_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_PKC_PK_0__PRI_ALIAS_1_WIDTH 2
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#define NV_FUSE_OPT_PKC_PK_1__WIDTH 32
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#define NV_FUSE_OPT_PKC_PK_1__PRI_ALIAS_0 0x00000056
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#define NV_FUSE_OPT_PKC_PK_1__PRI_ALIAS_0_DATA 31:2
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#define NV_FUSE_OPT_PKC_PK_1__PRI_ALIAS_0_WIDTH 30
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#define NV_FUSE_OPT_PKC_PK_1__PRI_ALIAS_1 0x00000057
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#define NV_FUSE_OPT_PKC_PK_1__PRI_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_PKC_PK_1__PRI_ALIAS_1_WIDTH 2
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#define NV_FUSE_OPT_PKC_PK_2__WIDTH 32
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#define NV_FUSE_OPT_PKC_PK_2__PRI_ALIAS_0 0x00000057
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#define NV_FUSE_OPT_PKC_PK_2__PRI_ALIAS_0_DATA 31:2
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#define NV_FUSE_OPT_PKC_PK_2__PRI_ALIAS_0_WIDTH 30
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#define NV_FUSE_OPT_PKC_PK_2__PRI_ALIAS_1 0x00000058
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#define NV_FUSE_OPT_PKC_PK_2__PRI_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_PKC_PK_2__PRI_ALIAS_1_WIDTH 2
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#define NV_FUSE_OPT_PKC_PK_3__WIDTH 32
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#define NV_FUSE_OPT_PKC_PK_3__PRI_ALIAS_0 0x00000058
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#define NV_FUSE_OPT_PKC_PK_3__PRI_ALIAS_0_DATA 31:2
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#define NV_FUSE_OPT_PKC_PK_3__PRI_ALIAS_0_WIDTH 30
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#define NV_FUSE_OPT_PKC_PK_3__PRI_ALIAS_1 0x00000059
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#define NV_FUSE_OPT_PKC_PK_3__PRI_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_PKC_PK_3__PRI_ALIAS_1_WIDTH 2
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#define NV_FUSE_OPT_PKC_PK_4__WIDTH 32
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#define NV_FUSE_OPT_PKC_PK_4__PRI_ALIAS_0 0x00000059
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#define NV_FUSE_OPT_PKC_PK_4__PRI_ALIAS_0_DATA 31:2
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#define NV_FUSE_OPT_PKC_PK_4__PRI_ALIAS_0_WIDTH 30
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#define NV_FUSE_OPT_PKC_PK_4__PRI_ALIAS_1 0x0000005a
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#define NV_FUSE_OPT_PKC_PK_4__PRI_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_PKC_PK_4__PRI_ALIAS_1_WIDTH 2
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#define NV_FUSE_OPT_PKC_PK_5__WIDTH 32
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#define NV_FUSE_OPT_PKC_PK_5__PRI_ALIAS_0 0x0000005a
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#define NV_FUSE_OPT_PKC_PK_5__PRI_ALIAS_0_DATA 31:2
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#define NV_FUSE_OPT_PKC_PK_5__PRI_ALIAS_0_WIDTH 30
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#define NV_FUSE_OPT_PKC_PK_5__PRI_ALIAS_1 0x0000005b
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#define NV_FUSE_OPT_PKC_PK_5__PRI_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_PKC_PK_5__PRI_ALIAS_1_WIDTH 2
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#define NV_FUSE_OPT_PKC_PK_6__WIDTH 32
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#define NV_FUSE_OPT_PKC_PK_6__PRI_ALIAS_0 0x0000005b
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#define NV_FUSE_OPT_PKC_PK_6__PRI_ALIAS_0_DATA 31:2
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#define NV_FUSE_OPT_PKC_PK_6__PRI_ALIAS_0_WIDTH 30
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#define NV_FUSE_OPT_PKC_PK_6__PRI_ALIAS_1 0x0000005c
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#define NV_FUSE_OPT_PKC_PK_6__PRI_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_PKC_PK_6__PRI_ALIAS_1_WIDTH 2
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#define NV_FUSE_OPT_PKC_PK_7__WIDTH 32
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#define NV_FUSE_OPT_PKC_PK_7__PRI_ALIAS_0 0x0000005c
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#define NV_FUSE_OPT_PKC_PK_7__PRI_ALIAS_0_DATA 31:2
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#define NV_FUSE_OPT_PKC_PK_7__PRI_ALIAS_0_WIDTH 30
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#define NV_FUSE_OPT_PKC_PK_7__PRI_ALIAS_1 0x0000005d
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#define NV_FUSE_OPT_PKC_PK_7__PRI_ALIAS_1_DATA 1:0
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#define NV_FUSE_OPT_PKC_PK_7__PRI_ALIAS_1_WIDTH 2
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#define NV_FUSE_H1__WIDTH 32
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#define NV_FUSE_H1__PRI_ALIAS_0 0x0000005d
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#define NV_FUSE_H1__PRI_ALIAS_0_DATA 31:2
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#define NV_FUSE_H1__PRI_ALIAS_0_WIDTH 30
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#define NV_FUSE_H1__PRI_ALIAS_1 0x0000005e
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#define NV_FUSE_H1__PRI_ALIAS_1_DATA 1:0
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#define NV_FUSE_H1__PRI_ALIAS_1_WIDTH 2
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#define NV_FUSE_FLW2__WIDTH 1
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#define NV_FUSE_FLW2__PRI_ALIAS_0 0x0000005e
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#define NV_FUSE_FLW2__PRI_ALIAS_0_DATA 2:2
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#define NV_FUSE_FLW2__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_HDCP22_LC128_0__WIDTH 32
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#define NV_FUSE_OPT_HDCP22_LC128_0__PRI_ALIAS_0 0x0000005e
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#define NV_FUSE_OPT_HDCP22_LC128_0__PRI_ALIAS_0_DATA 31:3
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#define NV_FUSE_OPT_HDCP22_LC128_0__PRI_ALIAS_0_WIDTH 29
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#define NV_FUSE_OPT_HDCP22_LC128_0__PRI_ALIAS_1 0x0000005f
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#define NV_FUSE_OPT_HDCP22_LC128_0__PRI_ALIAS_1_DATA 2:0
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#define NV_FUSE_OPT_HDCP22_LC128_0__PRI_ALIAS_1_WIDTH 3
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#define NV_FUSE_OPT_HDCP22_LC128_1__WIDTH 32
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#define NV_FUSE_OPT_HDCP22_LC128_1__PRI_ALIAS_0 0x0000005f
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#define NV_FUSE_OPT_HDCP22_LC128_1__PRI_ALIAS_0_DATA 31:3
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#define NV_FUSE_OPT_HDCP22_LC128_1__PRI_ALIAS_0_WIDTH 29
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#define NV_FUSE_OPT_HDCP22_LC128_1__PRI_ALIAS_1 0x00000060
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#define NV_FUSE_OPT_HDCP22_LC128_1__PRI_ALIAS_1_DATA 2:0
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#define NV_FUSE_OPT_HDCP22_LC128_1__PRI_ALIAS_1_WIDTH 3
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#define NV_FUSE_OPT_HDCP22_LC128_2__WIDTH 32
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#define NV_FUSE_OPT_HDCP22_LC128_2__PRI_ALIAS_0 0x00000060
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#define NV_FUSE_OPT_HDCP22_LC128_2__PRI_ALIAS_0_DATA 31:3
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#define NV_FUSE_OPT_HDCP22_LC128_2__PRI_ALIAS_0_WIDTH 29
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#define NV_FUSE_OPT_HDCP22_LC128_2__PRI_ALIAS_1 0x00000061
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#define NV_FUSE_OPT_HDCP22_LC128_2__PRI_ALIAS_1_DATA 2:0
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#define NV_FUSE_OPT_HDCP22_LC128_2__PRI_ALIAS_1_WIDTH 3
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#define NV_FUSE_OPT_HDCP22_LC128_3__WIDTH 32
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#define NV_FUSE_OPT_HDCP22_LC128_3__PRI_ALIAS_0 0x00000061
|
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#define NV_FUSE_OPT_HDCP22_LC128_3__PRI_ALIAS_0_DATA 31:3
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#define NV_FUSE_OPT_HDCP22_LC128_3__PRI_ALIAS_0_WIDTH 29
|
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#define NV_FUSE_OPT_HDCP22_LC128_3__PRI_ALIAS_1 0x00000062
|
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#define NV_FUSE_OPT_HDCP22_LC128_3__PRI_ALIAS_1_DATA 2:0
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#define NV_FUSE_OPT_HDCP22_LC128_3__PRI_ALIAS_1_WIDTH 3
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#define NV_FUSE_H2__WIDTH 32
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|
#define NV_FUSE_H2__PRI_ALIAS_0 0x00000062
|
|
#define NV_FUSE_H2__PRI_ALIAS_0_DATA 31:3
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#define NV_FUSE_H2__PRI_ALIAS_0_WIDTH 29
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|
#define NV_FUSE_H2__PRI_ALIAS_1 0x00000063
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#define NV_FUSE_H2__PRI_ALIAS_1_DATA 2:0
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#define NV_FUSE_H2__PRI_ALIAS_1_WIDTH 3
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#define NV_FUSE_FLW3__WIDTH 1
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#define NV_FUSE_FLW3__PRI_ALIAS_0 0x00000063
|
|
#define NV_FUSE_FLW3__PRI_ALIAS_0_DATA 3:3
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#define NV_FUSE_FLW3__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_H3__WIDTH 32
|
|
#define NV_FUSE_H3__PRI_ALIAS_0 0x00000063
|
|
#define NV_FUSE_H3__PRI_ALIAS_0_DATA 31:4
|
|
#define NV_FUSE_H3__PRI_ALIAS_0_WIDTH 28
|
|
#define NV_FUSE_H3__PRI_ALIAS_1 0x00000064
|
|
#define NV_FUSE_H3__PRI_ALIAS_1_DATA 3:0
|
|
#define NV_FUSE_H3__PRI_ALIAS_1_WIDTH 4
|
|
#define NV_FUSE_SPARE_BIT_64__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_64__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_64__PRI_ALIAS_0_DATA 4:4
|
|
#define NV_FUSE_SPARE_BIT_64__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_65__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_65__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_65__PRI_ALIAS_0_DATA 5:5
|
|
#define NV_FUSE_SPARE_BIT_65__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_66__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_66__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_66__PRI_ALIAS_0_DATA 6:6
|
|
#define NV_FUSE_SPARE_BIT_66__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_67__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_67__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_67__PRI_ALIAS_0_DATA 7:7
|
|
#define NV_FUSE_SPARE_BIT_67__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_68__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_68__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_68__PRI_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_SPARE_BIT_68__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_69__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_69__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_69__PRI_ALIAS_0_DATA 9:9
|
|
#define NV_FUSE_SPARE_BIT_69__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_70__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_70__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_70__PRI_ALIAS_0_DATA 10:10
|
|
#define NV_FUSE_SPARE_BIT_70__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_71__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_71__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_71__PRI_ALIAS_0_DATA 11:11
|
|
#define NV_FUSE_SPARE_BIT_71__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_72__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_72__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_72__PRI_ALIAS_0_DATA 12:12
|
|
#define NV_FUSE_SPARE_BIT_72__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_73__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_73__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_73__PRI_ALIAS_0_DATA 13:13
|
|
#define NV_FUSE_SPARE_BIT_73__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_74__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_74__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_74__PRI_ALIAS_0_DATA 14:14
|
|
#define NV_FUSE_SPARE_BIT_74__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_75__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_75__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_75__PRI_ALIAS_0_DATA 15:15
|
|
#define NV_FUSE_SPARE_BIT_75__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_76__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_76__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_76__PRI_ALIAS_0_DATA 16:16
|
|
#define NV_FUSE_SPARE_BIT_76__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_77__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_77__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_77__PRI_ALIAS_0_DATA 17:17
|
|
#define NV_FUSE_SPARE_BIT_77__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_78__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_78__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_78__PRI_ALIAS_0_DATA 18:18
|
|
#define NV_FUSE_SPARE_BIT_78__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_79__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_79__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_79__PRI_ALIAS_0_DATA 19:19
|
|
#define NV_FUSE_SPARE_BIT_79__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_80__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_80__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_80__PRI_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_SPARE_BIT_80__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_81__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_81__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_81__PRI_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_SPARE_BIT_81__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_82__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_82__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_82__PRI_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_SPARE_BIT_82__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_83__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_83__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_83__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_SPARE_BIT_83__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_84__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_84__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_84__PRI_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_SPARE_BIT_84__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_85__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_85__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_85__PRI_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_SPARE_BIT_85__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_86__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_86__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_86__PRI_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_SPARE_BIT_86__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_87__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_87__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_87__PRI_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_SPARE_BIT_87__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_88__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_88__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_88__PRI_ALIAS_0_DATA 28:28
|
|
#define NV_FUSE_SPARE_BIT_88__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_89__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_89__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_89__PRI_ALIAS_0_DATA 29:29
|
|
#define NV_FUSE_SPARE_BIT_89__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_90__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_90__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_90__PRI_ALIAS_0_DATA 30:30
|
|
#define NV_FUSE_SPARE_BIT_90__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_91__WIDTH 1
|
|
#define NV_FUSE_SPARE_BIT_91__PRI_ALIAS_0 0x00000064
|
|
#define NV_FUSE_SPARE_BIT_91__PRI_ALIAS_0_DATA 31:31
|
|
#define NV_FUSE_SPARE_BIT_91__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION__PRI_ALIAS_0 0x00000065
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION__RED_ALIAS_0 0x00000066
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION__PRI_ALIAS_0 0x00000065
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION__RED_ALIAS_0 0x00000066
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE2_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION__PRI_ALIAS_0 0x00000067
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION__RED_ALIAS_0 0x00000068
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE3_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION__PRI_ALIAS_0 0x00000067
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION__RED_ALIAS_0 0x00000068
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE4_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION__PRI_ALIAS_0 0x00000069
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION__RED_ALIAS_0 0x0000006a
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE5_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION__PRI_ALIAS_0 0x00000069
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION__RED_ALIAS_0 0x0000006a
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE6_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION__PRI_ALIAS_0 0x0000006b
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION__RED_ALIAS_0 0x0000006c
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE7_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION__PRI_ALIAS_0 0x0000006b
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION__RED_ALIAS_0 0x0000006c
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE8_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION__PRI_ALIAS_0 0x0000006d
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION__RED_ALIAS_0 0x0000006e
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE9_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION__PRI_ALIAS_0 0x0000006d
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION__RED_ALIAS_0 0x0000006e
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE10_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION__PRI_ALIAS_0 0x0000006f
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION__RED_ALIAS_0 0x00000070
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE11_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION__PRI_ALIAS_0 0x0000006f
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION__RED_ALIAS_0 0x00000070
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE12_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION__PRI_ALIAS_0 0x00000071
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION__RED_ALIAS_0 0x00000072
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE13_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION__PRI_ALIAS_0 0x00000071
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION__RED_ALIAS_0 0x00000072
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE14_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION__PRI_ALIAS_0 0x00000073
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION__RED_ALIAS_0 0x00000074
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE15_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION__PRI_ALIAS_0 0x00000073
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION__RED_ALIAS_0 0x00000074
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_NVDEC_UCODE16_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION__PRI_ALIAS_0 0x00000075
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION__RED_ALIAS_0 0x00000076
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION__PRI_ALIAS_0 0x00000075
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION__RED_ALIAS_0 0x00000076
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE2_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION__PRI_ALIAS_0 0x00000077
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION__RED_ALIAS_0 0x00000078
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE3_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION__PRI_ALIAS_0 0x00000077
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION__RED_ALIAS_0 0x00000078
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE4_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION__PRI_ALIAS_0 0x00000079
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION__RED_ALIAS_0 0x0000007a
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE5_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION__PRI_ALIAS_0 0x00000079
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION__RED_ALIAS_0 0x0000007a
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE6_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION__PRI_ALIAS_0 0x0000007b
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION__RED_ALIAS_0 0x0000007c
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE7_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION__PRI_ALIAS_0 0x0000007b
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION__RED_ALIAS_0 0x0000007c
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE8_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION__PRI_ALIAS_0 0x0000007d
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION__RED_ALIAS_0 0x0000007e
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE9_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION__PRI_ALIAS_0 0x0000007d
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION__RED_ALIAS_0 0x0000007e
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE10_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION__PRI_ALIAS_0 0x0000007f
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION__RED_ALIAS_0 0x00000080
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE11_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION__PRI_ALIAS_0 0x0000007f
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION__RED_ALIAS_0 0x00000080
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE12_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION__PRI_ALIAS_0 0x00000081
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION__RED_ALIAS_0 0x00000082
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE13_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION__PRI_ALIAS_0 0x00000081
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION__RED_ALIAS_0 0x00000082
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE14_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION__PRI_ALIAS_0 0x00000083
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION__RED_ALIAS_0 0x00000084
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE15_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION__PRI_ALIAS_0 0x00000083
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION__RED_ALIAS_0 0x00000084
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_SEC2_UCODE16_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE1_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE1_VERSION__PRI_ALIAS_0 0x00000085
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE1_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE1_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE1_VERSION__RED_ALIAS_0 0x00000086
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE1_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE1_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE2_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE2_VERSION__PRI_ALIAS_0 0x00000085
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE2_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE2_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE2_VERSION__RED_ALIAS_0 0x00000086
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE2_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE2_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE3_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE3_VERSION__PRI_ALIAS_0 0x00000087
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE3_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE3_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE3_VERSION__RED_ALIAS_0 0x00000088
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE3_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE3_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE4_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE4_VERSION__PRI_ALIAS_0 0x00000087
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE4_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE4_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE4_VERSION__RED_ALIAS_0 0x00000088
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE4_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE4_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE5_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE5_VERSION__PRI_ALIAS_0 0x00000089
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE5_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE5_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE5_VERSION__RED_ALIAS_0 0x0000008a
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE5_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE5_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE6_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE6_VERSION__PRI_ALIAS_0 0x00000089
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE6_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE6_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE6_VERSION__RED_ALIAS_0 0x0000008a
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE6_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE6_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE7_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE7_VERSION__PRI_ALIAS_0 0x0000008b
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE7_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE7_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE7_VERSION__RED_ALIAS_0 0x0000008c
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE7_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE7_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE8_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE8_VERSION__PRI_ALIAS_0 0x0000008b
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE8_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE8_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE8_VERSION__RED_ALIAS_0 0x0000008c
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE8_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE8_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE9_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE9_VERSION__PRI_ALIAS_0 0x0000008d
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE9_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE9_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE9_VERSION__RED_ALIAS_0 0x0000008e
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE9_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE9_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE10_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE10_VERSION__PRI_ALIAS_0 0x0000008d
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE10_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE10_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE10_VERSION__RED_ALIAS_0 0x0000008e
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE10_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE10_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE11_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE11_VERSION__PRI_ALIAS_0 0x0000008f
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE11_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE11_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE11_VERSION__RED_ALIAS_0 0x00000090
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE11_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE11_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE12_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE12_VERSION__PRI_ALIAS_0 0x0000008f
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE12_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE12_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE12_VERSION__RED_ALIAS_0 0x00000090
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE12_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE12_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE13_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE13_VERSION__PRI_ALIAS_0 0x00000091
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE13_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE13_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE13_VERSION__RED_ALIAS_0 0x00000092
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE13_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE13_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE14_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE14_VERSION__PRI_ALIAS_0 0x00000091
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE14_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE14_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE14_VERSION__RED_ALIAS_0 0x00000092
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE14_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE14_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE15_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE15_VERSION__PRI_ALIAS_0 0x00000093
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE15_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE15_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE15_VERSION__RED_ALIAS_0 0x00000094
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE15_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE15_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE16_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE16_VERSION__PRI_ALIAS_0 0x00000093
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE16_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE16_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE16_VERSION__RED_ALIAS_0 0x00000094
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE16_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_PMU_UCODE16_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION__PRI_ALIAS_0 0x00000095
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION__RED_ALIAS_0 0x00000096
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION__PRI_ALIAS_0 0x00000095
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION__RED_ALIAS_0 0x00000096
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE2_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION__PRI_ALIAS_0 0x00000097
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION__RED_ALIAS_0 0x00000098
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE3_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION__PRI_ALIAS_0 0x00000097
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION__RED_ALIAS_0 0x00000098
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE4_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION__PRI_ALIAS_0 0x00000099
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION__RED_ALIAS_0 0x0000009a
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE5_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION__PRI_ALIAS_0 0x00000099
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION__RED_ALIAS_0 0x0000009a
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE6_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION__PRI_ALIAS_0 0x0000009b
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION__RED_ALIAS_0 0x0000009c
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE7_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION__PRI_ALIAS_0 0x0000009b
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION__RED_ALIAS_0 0x0000009c
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE8_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION__PRI_ALIAS_0 0x0000009d
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION__RED_ALIAS_0 0x0000009e
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE9_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION__PRI_ALIAS_0 0x0000009d
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION__RED_ALIAS_0 0x0000009e
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE10_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION__PRI_ALIAS_0 0x0000009f
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION__RED_ALIAS_0 0x000000a0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE11_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION__PRI_ALIAS_0 0x0000009f
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION__RED_ALIAS_0 0x000000a0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE12_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION__PRI_ALIAS_0 0x000000a1
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION__RED_ALIAS_0 0x000000a2
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE13_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION__PRI_ALIAS_0 0x000000a1
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION__RED_ALIAS_0 0x000000a2
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE14_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION__PRI_ALIAS_0 0x000000a3
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION__RED_ALIAS_0 0x000000a4
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE15_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION__PRI_ALIAS_0 0x000000a3
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION__RED_ALIAS_0 0x000000a4
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_GSP_UCODE16_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE1_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE1_VERSION__PRI_ALIAS_0 0x000000a5
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE1_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE1_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE1_VERSION__RED_ALIAS_0 0x000000a6
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE1_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE1_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE2_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE2_VERSION__PRI_ALIAS_0 0x000000a5
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE2_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE2_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE2_VERSION__RED_ALIAS_0 0x000000a6
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE2_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE2_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE3_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE3_VERSION__PRI_ALIAS_0 0x000000a7
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE3_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE3_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE3_VERSION__RED_ALIAS_0 0x000000a8
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE3_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE3_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE4_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE4_VERSION__PRI_ALIAS_0 0x000000a7
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE4_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE4_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE4_VERSION__RED_ALIAS_0 0x000000a8
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE4_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE4_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE5_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE5_VERSION__PRI_ALIAS_0 0x000000a9
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE5_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE5_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE5_VERSION__RED_ALIAS_0 0x000000aa
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE5_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE5_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE6_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE6_VERSION__PRI_ALIAS_0 0x000000a9
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE6_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE6_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE6_VERSION__RED_ALIAS_0 0x000000aa
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE6_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE6_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE7_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE7_VERSION__PRI_ALIAS_0 0x000000ab
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE7_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE7_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE7_VERSION__RED_ALIAS_0 0x000000ac
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE7_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE7_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE8_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE8_VERSION__PRI_ALIAS_0 0x000000ab
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE8_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE8_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE8_VERSION__RED_ALIAS_0 0x000000ac
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE8_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_XUSB_UCODE8_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE1_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE1_VERSION__PRI_ALIAS_0 0x000000ad
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE1_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE1_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE1_VERSION__RED_ALIAS_0 0x000000ae
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE1_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE1_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE2_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE2_VERSION__PRI_ALIAS_0 0x000000ad
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE2_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE2_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE2_VERSION__RED_ALIAS_0 0x000000ae
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE2_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE2_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE3_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE3_VERSION__PRI_ALIAS_0 0x000000af
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE3_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE3_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE3_VERSION__RED_ALIAS_0 0x000000b0
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE3_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE3_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE4_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE4_VERSION__PRI_ALIAS_0 0x000000af
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE4_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE4_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE4_VERSION__RED_ALIAS_0 0x000000b0
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE4_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE4_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE5_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE5_VERSION__PRI_ALIAS_0 0x000000b1
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE5_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE5_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE5_VERSION__RED_ALIAS_0 0x000000b2
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE5_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE5_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE6_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE6_VERSION__PRI_ALIAS_0 0x000000b1
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE6_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE6_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE6_VERSION__RED_ALIAS_0 0x000000b2
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE6_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE6_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE7_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE7_VERSION__PRI_ALIAS_0 0x000000b3
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE7_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE7_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE7_VERSION__RED_ALIAS_0 0x000000b4
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE7_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE7_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE8_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE8_VERSION__PRI_ALIAS_0 0x000000b3
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE8_VERSION__PRI_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE8_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE8_VERSION__RED_ALIAS_0 0x000000b4
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE8_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE8_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_CTKID__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_CTKID__PRI_ALIAS_0 0x000000b5
|
|
#define NV_FUSE_OPT_FPF_CTKID__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_CTKID__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_CTKID__RED_ALIAS_0 0x000000b6
|
|
#define NV_FUSE_OPT_FPF_CTKID__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_CTKID__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_UCODE_SCRUBBER_BIN_REV__WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_SCRUBBER_BIN_REV__PRI_ALIAS_0 0x000000b5
|
|
#define NV_FUSE_OPT_FPF_UCODE_SCRUBBER_BIN_REV__PRI_ALIAS_0_DATA 23:16
|
|
#define NV_FUSE_OPT_FPF_UCODE_SCRUBBER_BIN_REV__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_SCRUBBER_BIN_REV__RED_ALIAS_0 0x000000b6
|
|
#define NV_FUSE_OPT_FPF_UCODE_SCRUBBER_BIN_REV__RED_ALIAS_0_DATA 23:16
|
|
#define NV_FUSE_OPT_FPF_UCODE_SCRUBBER_BIN_REV__RED_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_SEC2_REV__WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_SEC2_REV__PRI_ALIAS_0 0x000000b5
|
|
#define NV_FUSE_OPT_FPF_UCODE_SEC2_REV__PRI_ALIAS_0_DATA 31:24
|
|
#define NV_FUSE_OPT_FPF_UCODE_SEC2_REV__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_SEC2_REV__RED_ALIAS_0 0x000000b6
|
|
#define NV_FUSE_OPT_FPF_UCODE_SEC2_REV__RED_ALIAS_0_DATA 31:24
|
|
#define NV_FUSE_OPT_FPF_UCODE_SEC2_REV__RED_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_PR_VPR_REV__WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_PR_VPR_REV__PRI_ALIAS_0 0x000000b7
|
|
#define NV_FUSE_OPT_FPF_UCODE_PR_VPR_REV__PRI_ALIAS_0_DATA 7:0
|
|
#define NV_FUSE_OPT_FPF_UCODE_PR_VPR_REV__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_PR_VPR_REV__RED_ALIAS_0 0x000000b8
|
|
#define NV_FUSE_OPT_FPF_UCODE_PR_VPR_REV__RED_ALIAS_0_DATA 7:0
|
|
#define NV_FUSE_OPT_FPF_UCODE_PR_VPR_REV__RED_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_ACR_HS_REV__WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_ACR_HS_REV__PRI_ALIAS_0 0x000000b7
|
|
#define NV_FUSE_OPT_FPF_UCODE_ACR_HS_REV__PRI_ALIAS_0_DATA 15:8
|
|
#define NV_FUSE_OPT_FPF_UCODE_ACR_HS_REV__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_ACR_HS_REV__RED_ALIAS_0 0x000000b8
|
|
#define NV_FUSE_OPT_FPF_UCODE_ACR_HS_REV__RED_ALIAS_0_DATA 15:8
|
|
#define NV_FUSE_OPT_FPF_UCODE_ACR_HS_REV__RED_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_GFW_REV__WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_GFW_REV__PRI_ALIAS_0 0x000000b7
|
|
#define NV_FUSE_OPT_FPF_UCODE_GFW_REV__PRI_ALIAS_0_DATA 23:16
|
|
#define NV_FUSE_OPT_FPF_UCODE_GFW_REV__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_GFW_REV__RED_ALIAS_0 0x000000b8
|
|
#define NV_FUSE_OPT_FPF_UCODE_GFW_REV__RED_ALIAS_0_DATA 23:16
|
|
#define NV_FUSE_OPT_FPF_UCODE_GFW_REV__RED_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_ROM_FLASH_REV__WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_ROM_FLASH_REV__PRI_ALIAS_0 0x000000b7
|
|
#define NV_FUSE_OPT_FPF_UCODE_ROM_FLASH_REV__PRI_ALIAS_0_DATA 31:24
|
|
#define NV_FUSE_OPT_FPF_UCODE_ROM_FLASH_REV__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_ROM_FLASH_REV__RED_ALIAS_0 0x000000b8
|
|
#define NV_FUSE_OPT_FPF_UCODE_ROM_FLASH_REV__RED_ALIAS_0_DATA 31:24
|
|
#define NV_FUSE_OPT_FPF_UCODE_ROM_FLASH_REV__RED_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_NVDEC_REV__WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_NVDEC_REV__PRI_ALIAS_0 0x000000b9
|
|
#define NV_FUSE_OPT_FPF_UCODE_NVDEC_REV__PRI_ALIAS_0_DATA 7:0
|
|
#define NV_FUSE_OPT_FPF_UCODE_NVDEC_REV__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_NVDEC_REV__RED_ALIAS_0 0x000000ba
|
|
#define NV_FUSE_OPT_FPF_UCODE_NVDEC_REV__RED_ALIAS_0_DATA 7:0
|
|
#define NV_FUSE_OPT_FPF_UCODE_NVDEC_REV__RED_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_CTXSW_REV__WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_CTXSW_REV__PRI_ALIAS_0 0x000000b9
|
|
#define NV_FUSE_OPT_FPF_UCODE_CTXSW_REV__PRI_ALIAS_0_DATA 15:8
|
|
#define NV_FUSE_OPT_FPF_UCODE_CTXSW_REV__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_CTXSW_REV__RED_ALIAS_0 0x000000ba
|
|
#define NV_FUSE_OPT_FPF_UCODE_CTXSW_REV__RED_ALIAS_0_DATA 15:8
|
|
#define NV_FUSE_OPT_FPF_UCODE_CTXSW_REV__RED_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_FBFALCON_REV__WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_FBFALCON_REV__PRI_ALIAS_0 0x000000b9
|
|
#define NV_FUSE_OPT_FPF_UCODE_FBFALCON_REV__PRI_ALIAS_0_DATA 23:16
|
|
#define NV_FUSE_OPT_FPF_UCODE_FBFALCON_REV__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_FBFALCON_REV__RED_ALIAS_0 0x000000ba
|
|
#define NV_FUSE_OPT_FPF_UCODE_FBFALCON_REV__RED_ALIAS_0_DATA 23:16
|
|
#define NV_FUSE_OPT_FPF_UCODE_FBFALCON_REV__RED_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_GSP_REV__WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_GSP_REV__PRI_ALIAS_0 0x000000b9
|
|
#define NV_FUSE_OPT_FPF_UCODE_GSP_REV__PRI_ALIAS_0_DATA 31:24
|
|
#define NV_FUSE_OPT_FPF_UCODE_GSP_REV__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_GSP_REV__RED_ALIAS_0 0x000000ba
|
|
#define NV_FUSE_OPT_FPF_UCODE_GSP_REV__RED_ALIAS_0_DATA 31:24
|
|
#define NV_FUSE_OPT_FPF_UCODE_GSP_REV__RED_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_0__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_0__PRI_ALIAS_0 0x000000bb
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_0__PRI_ALIAS_0_DATA 3:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_0__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_0__RED_ALIAS_0 0x000000bc
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_0__RED_ALIAS_0_DATA 3:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_0__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_1__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_1__PRI_ALIAS_0 0x000000bb
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_1__PRI_ALIAS_0_DATA 7:4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_1__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_1__RED_ALIAS_0 0x000000bc
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_1__RED_ALIAS_0_DATA 7:4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_1__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_2__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_2__PRI_ALIAS_0 0x000000bb
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_2__PRI_ALIAS_0_DATA 11:8
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_2__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_2__RED_ALIAS_0 0x000000bc
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_2__RED_ALIAS_0_DATA 11:8
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_2__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_3__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_3__PRI_ALIAS_0 0x000000bb
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_3__PRI_ALIAS_0_DATA 15:12
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_3__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_3__RED_ALIAS_0 0x000000bc
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_3__RED_ALIAS_0_DATA 15:12
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_3__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_4__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_4__PRI_ALIAS_0 0x000000bb
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_4__PRI_ALIAS_0_DATA 19:16
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_4__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_4__RED_ALIAS_0 0x000000bc
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_4__RED_ALIAS_0_DATA 19:16
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_4__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_5__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_5__PRI_ALIAS_0 0x000000bb
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_5__PRI_ALIAS_0_DATA 23:20
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_5__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_5__RED_ALIAS_0 0x000000bc
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_5__RED_ALIAS_0_DATA 23:20
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_5__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_6__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_6__PRI_ALIAS_0 0x000000bb
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_6__PRI_ALIAS_0_DATA 27:24
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_6__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_6__RED_ALIAS_0 0x000000bc
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_6__RED_ALIAS_0_DATA 27:24
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_6__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_7__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_7__PRI_ALIAS_0 0x000000bb
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_7__PRI_ALIAS_0_DATA 31:28
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_7__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_7__RED_ALIAS_0 0x000000bc
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_7__RED_ALIAS_0_DATA 31:28
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_7__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_8__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_8__PRI_ALIAS_0 0x000000bd
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_8__PRI_ALIAS_0_DATA 3:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_8__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_8__RED_ALIAS_0 0x000000be
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_8__RED_ALIAS_0_DATA 3:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_8__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_9__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_9__PRI_ALIAS_0 0x000000bd
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_9__PRI_ALIAS_0_DATA 7:4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_9__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_9__RED_ALIAS_0 0x000000be
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_9__RED_ALIAS_0_DATA 7:4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_9__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_10__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_10__PRI_ALIAS_0 0x000000bd
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_10__PRI_ALIAS_0_DATA 11:8
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_10__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_10__RED_ALIAS_0 0x000000be
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_10__RED_ALIAS_0_DATA 11:8
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_10__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_11__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_11__PRI_ALIAS_0 0x000000bd
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_11__PRI_ALIAS_0_DATA 15:12
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_11__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_11__RED_ALIAS_0 0x000000be
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_11__RED_ALIAS_0_DATA 15:12
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_11__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_12__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_12__PRI_ALIAS_0 0x000000bd
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_12__PRI_ALIAS_0_DATA 19:16
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_12__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_12__RED_ALIAS_0 0x000000be
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_12__RED_ALIAS_0_DATA 19:16
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_12__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_13__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_13__PRI_ALIAS_0 0x000000bd
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_13__PRI_ALIAS_0_DATA 23:20
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_13__PRI_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_13__RED_ALIAS_0 0x000000be
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_13__RED_ALIAS_0_DATA 23:20
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_13__RED_ALIAS_0_WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_14__WIDTH 4
|
|
#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_14__PRI_ALIAS_0 0x000000bd
|
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_14__PRI_ALIAS_0_DATA 27:24
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_14__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_14__RED_ALIAS_0 0x000000be
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_14__RED_ALIAS_0_DATA 27:24
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_14__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_15__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_15__PRI_ALIAS_0 0x000000bd
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_15__PRI_ALIAS_0_DATA 31:28
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_15__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_15__RED_ALIAS_0 0x000000be
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_15__RED_ALIAS_0_DATA 31:28
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_15__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_16__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_16__PRI_ALIAS_0 0x000000bf
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_16__PRI_ALIAS_0_DATA 3:0
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_16__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_16__RED_ALIAS_0 0x000000c0
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_16__RED_ALIAS_0_DATA 3:0
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_16__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_17__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_17__PRI_ALIAS_0 0x000000bf
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_17__PRI_ALIAS_0_DATA 7:4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_17__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_17__RED_ALIAS_0 0x000000c0
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_17__RED_ALIAS_0_DATA 7:4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_17__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_18__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_18__PRI_ALIAS_0 0x000000bf
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_18__PRI_ALIAS_0_DATA 11:8
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_18__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_18__RED_ALIAS_0 0x000000c0
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_18__RED_ALIAS_0_DATA 11:8
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_18__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_19__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_19__PRI_ALIAS_0 0x000000bf
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_19__PRI_ALIAS_0_DATA 15:12
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_19__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_19__RED_ALIAS_0 0x000000c0
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_19__RED_ALIAS_0_DATA 15:12
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_19__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_20__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_20__PRI_ALIAS_0 0x000000bf
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_20__PRI_ALIAS_0_DATA 19:16
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_20__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_20__RED_ALIAS_0 0x000000c0
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_20__RED_ALIAS_0_DATA 19:16
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_20__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_21__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_21__PRI_ALIAS_0 0x000000bf
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_21__PRI_ALIAS_0_DATA 23:20
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_21__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_21__RED_ALIAS_0 0x000000c0
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_21__RED_ALIAS_0_DATA 23:20
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_21__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_22__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_22__PRI_ALIAS_0 0x000000bf
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_22__PRI_ALIAS_0_DATA 27:24
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_22__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_22__RED_ALIAS_0 0x000000c0
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_22__RED_ALIAS_0_DATA 27:24
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_22__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_23__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_23__PRI_ALIAS_0 0x000000bf
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_23__PRI_ALIAS_0_DATA 31:28
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_23__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_23__RED_ALIAS_0 0x000000c0
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_23__RED_ALIAS_0_DATA 31:28
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_23__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_24__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_24__PRI_ALIAS_0 0x000000c1
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_24__PRI_ALIAS_0_DATA 3:0
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_24__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_24__RED_ALIAS_0 0x000000c2
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_24__RED_ALIAS_0_DATA 3:0
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_24__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_25__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_25__PRI_ALIAS_0 0x000000c1
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_25__PRI_ALIAS_0_DATA 7:4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_25__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_25__RED_ALIAS_0 0x000000c2
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_25__RED_ALIAS_0_DATA 7:4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_25__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_26__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_26__PRI_ALIAS_0 0x000000c1
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_26__PRI_ALIAS_0_DATA 11:8
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_26__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_26__RED_ALIAS_0 0x000000c2
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_26__RED_ALIAS_0_DATA 11:8
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_26__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_27__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_27__PRI_ALIAS_0 0x000000c1
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_27__PRI_ALIAS_0_DATA 15:12
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_27__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_27__RED_ALIAS_0 0x000000c2
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_27__RED_ALIAS_0_DATA 15:12
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_27__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_28__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_28__PRI_ALIAS_0 0x000000c1
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_28__PRI_ALIAS_0_DATA 19:16
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_28__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_28__RED_ALIAS_0 0x000000c2
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_28__RED_ALIAS_0_DATA 19:16
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_28__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_29__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_29__PRI_ALIAS_0 0x000000c1
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_29__PRI_ALIAS_0_DATA 23:20
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_29__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_29__RED_ALIAS_0 0x000000c2
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_29__RED_ALIAS_0_DATA 23:20
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_29__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_30__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_30__PRI_ALIAS_0 0x000000c1
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_30__PRI_ALIAS_0_DATA 27:24
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_30__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_30__RED_ALIAS_0 0x000000c2
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_30__RED_ALIAS_0_DATA 27:24
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_30__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_31__WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_31__PRI_ALIAS_0 0x000000c1
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_31__PRI_ALIAS_0_DATA 31:28
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_31__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_31__RED_ALIAS_0 0x000000c2
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_31__RED_ALIAS_0_DATA 31:28
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#define NV_FUSE_OPT_FPF_FIELD_FEATURE_CONTROL_31__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_SKU_CONVERSION__WIDTH 16
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#define NV_FUSE_OPT_FPF_SKU_CONVERSION__PRI_ALIAS_0 0x000000c3
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#define NV_FUSE_OPT_FPF_SKU_CONVERSION__PRI_ALIAS_0_DATA 15:0
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#define NV_FUSE_OPT_FPF_SKU_CONVERSION__PRI_ALIAS_0_WIDTH 16
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#define NV_FUSE_OPT_FPF_SKU_CONVERSION__RED_ALIAS_0 0x000000c4
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#define NV_FUSE_OPT_FPF_SKU_CONVERSION__RED_ALIAS_0_DATA 15:0
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#define NV_FUSE_OPT_FPF_SKU_CONVERSION__RED_ALIAS_0_WIDTH 16
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT0__WIDTH 8
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT0__PRI_ALIAS_0 0x000000c3
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT0__PRI_ALIAS_0_DATA 23:16
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT0__PRI_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT0__RED_ALIAS_0 0x000000c4
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT0__RED_ALIAS_0_DATA 23:16
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT0__RED_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT1__WIDTH 8
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT1__PRI_ALIAS_0 0x000000c3
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT1__PRI_ALIAS_0_DATA 31:24
|
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT1__PRI_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT1__RED_ALIAS_0 0x000000c4
|
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT1__RED_ALIAS_0_DATA 31:24
|
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#define NV_FUSE_OPT_FPF_TPC_ENABLED_COUNT1__RED_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_FPF_OVERLOCK_INFO__WIDTH 4
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#define NV_FUSE_OPT_FPF_OVERLOCK_INFO__PRI_ALIAS_0 0x000000c5
|
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#define NV_FUSE_OPT_FPF_OVERLOCK_INFO__PRI_ALIAS_0_DATA 3:0
|
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#define NV_FUSE_OPT_FPF_OVERLOCK_INFO__PRI_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_OVERLOCK_INFO__RED_ALIAS_0 0x000000c6
|
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#define NV_FUSE_OPT_FPF_OVERLOCK_INFO__RED_ALIAS_0_DATA 3:0
|
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#define NV_FUSE_OPT_FPF_OVERLOCK_INFO__RED_ALIAS_0_WIDTH 4
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_0__WIDTH 3
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_0__PRI_ALIAS_0 0x000000c5
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_0__PRI_ALIAS_0_DATA 6:4
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_0__PRI_ALIAS_0_WIDTH 3
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_0__RED_ALIAS_0 0x000000c6
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_0__RED_ALIAS_0_DATA 6:4
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_0__RED_ALIAS_0_WIDTH 3
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_1__WIDTH 8
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_1__PRI_ALIAS_0 0x000000c5
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_1__PRI_ALIAS_0_DATA 14:7
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_1__PRI_ALIAS_0_WIDTH 8
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_1__RED_ALIAS_0 0x000000c6
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_1__RED_ALIAS_0_DATA 14:7
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_1__RED_ALIAS_0_WIDTH 8
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_2__WIDTH 8
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_2__PRI_ALIAS_0 0x000000c5
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_2__PRI_ALIAS_0_DATA 22:15
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_2__PRI_ALIAS_0_WIDTH 8
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_2__RED_ALIAS_0 0x000000c6
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_2__RED_ALIAS_0_DATA 22:15
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_2__RED_ALIAS_0_WIDTH 8
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__WIDTH 32
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__PRI_ALIAS_0 0x000000c5
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__PRI_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__PRI_ALIAS_0_WIDTH 9
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__PRI_ALIAS_1 0x000000c7
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__PRI_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__PRI_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__RED_ALIAS_0 0x000000c6
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__RED_ALIAS_0_DATA 31:23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__RED_ALIAS_0_WIDTH 9
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__RED_ALIAS_1 0x000000c8
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__RED_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_3__RED_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__WIDTH 32
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__PRI_ALIAS_0 0x000000c7
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__PRI_ALIAS_0_DATA 31:23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__PRI_ALIAS_0_WIDTH 9
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__PRI_ALIAS_1 0x000000c9
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__PRI_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__PRI_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__RED_ALIAS_0 0x000000c8
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__RED_ALIAS_0_DATA 31:23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__RED_ALIAS_0_WIDTH 9
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__RED_ALIAS_1 0x000000ca
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__RED_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_4__RED_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__WIDTH 32
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__PRI_ALIAS_0 0x000000c9
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__PRI_ALIAS_0_DATA 31:23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__PRI_ALIAS_0_WIDTH 9
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__PRI_ALIAS_1 0x000000cb
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__PRI_ALIAS_1_DATA 22:0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__PRI_ALIAS_1_WIDTH 23
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__RED_ALIAS_0 0x000000ca
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__RED_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__RED_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__RED_ALIAS_1 0x000000cc
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__RED_ALIAS_1_DATA 22:0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_5__RED_ALIAS_1_WIDTH 23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__WIDTH 32
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__PRI_ALIAS_0 0x000000cb
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__PRI_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__PRI_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__PRI_ALIAS_1 0x000000cd
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__PRI_ALIAS_1_DATA 22:0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__PRI_ALIAS_1_WIDTH 23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__RED_ALIAS_0 0x000000cc
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__RED_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__RED_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__RED_ALIAS_1 0x000000ce
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__RED_ALIAS_1_DATA 22:0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_6__RED_ALIAS_1_WIDTH 23
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__WIDTH 32
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__PRI_ALIAS_0 0x000000cd
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__PRI_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__PRI_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__PRI_ALIAS_1 0x000000cf
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__PRI_ALIAS_1_DATA 22:0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__PRI_ALIAS_1_WIDTH 23
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__RED_ALIAS_0 0x000000ce
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__RED_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__RED_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__RED_ALIAS_1 0x000000d0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__RED_ALIAS_1_DATA 22:0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_7__RED_ALIAS_1_WIDTH 23
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__WIDTH 32
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__PRI_ALIAS_0 0x000000cf
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__PRI_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__PRI_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__PRI_ALIAS_1 0x000000d1
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__PRI_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__PRI_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__RED_ALIAS_0 0x000000d0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__RED_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__RED_ALIAS_0_WIDTH 9
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__RED_ALIAS_1 0x000000d2
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__RED_ALIAS_1_DATA 22:0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_8__RED_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__WIDTH 32
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__PRI_ALIAS_0 0x000000d1
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__PRI_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__PRI_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__PRI_ALIAS_1 0x000000d3
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__PRI_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__PRI_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__RED_ALIAS_0 0x000000d2
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__RED_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__RED_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__RED_ALIAS_1 0x000000d4
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__RED_ALIAS_1_DATA 22:0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_9__RED_ALIAS_1_WIDTH 23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__WIDTH 32
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__PRI_ALIAS_0 0x000000d3
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__PRI_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__PRI_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__PRI_ALIAS_1 0x000000d5
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__PRI_ALIAS_1_DATA 22:0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__PRI_ALIAS_1_WIDTH 23
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|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__RED_ALIAS_0 0x000000d4
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__RED_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__RED_ALIAS_0_WIDTH 9
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|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__RED_ALIAS_1 0x000000d6
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__RED_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_10__RED_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__WIDTH 32
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__PRI_ALIAS_0 0x000000d5
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__PRI_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__PRI_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__PRI_ALIAS_1 0x000000d7
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__PRI_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__PRI_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__RED_ALIAS_0 0x000000d6
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__RED_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__RED_ALIAS_0_WIDTH 9
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__RED_ALIAS_1 0x000000d8
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__RED_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_11__RED_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__WIDTH 32
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__PRI_ALIAS_0 0x000000d7
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__PRI_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__PRI_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__PRI_ALIAS_1 0x000000d9
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__PRI_ALIAS_1_DATA 22:0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__PRI_ALIAS_1_WIDTH 23
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__RED_ALIAS_0 0x000000d8
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__RED_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__RED_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__RED_ALIAS_1 0x000000da
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__RED_ALIAS_1_DATA 22:0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_12__RED_ALIAS_1_WIDTH 23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__WIDTH 32
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__PRI_ALIAS_0 0x000000d9
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__PRI_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__PRI_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__PRI_ALIAS_1 0x000000db
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__PRI_ALIAS_1_DATA 22:0
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__PRI_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__RED_ALIAS_0 0x000000da
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__RED_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__RED_ALIAS_0_WIDTH 9
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|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__RED_ALIAS_1 0x000000dc
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__RED_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_13__RED_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__WIDTH 32
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__PRI_ALIAS_0 0x000000db
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__PRI_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__PRI_ALIAS_0_WIDTH 9
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__PRI_ALIAS_1 0x000000dd
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__PRI_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__PRI_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__RED_ALIAS_0 0x000000dc
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__RED_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__RED_ALIAS_0_WIDTH 9
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__RED_ALIAS_1 0x000000de
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__RED_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_14__RED_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__WIDTH 32
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__PRI_ALIAS_0 0x000000dd
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__PRI_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__PRI_ALIAS_0_WIDTH 9
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__PRI_ALIAS_1 0x000000df
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__PRI_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__PRI_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__RED_ALIAS_0 0x000000de
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__RED_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__RED_ALIAS_0_WIDTH 9
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__RED_ALIAS_1 0x000000e0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__RED_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_15__RED_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__WIDTH 32
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__PRI_ALIAS_0 0x000000df
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__PRI_ALIAS_0_DATA 31:23
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__PRI_ALIAS_0_WIDTH 9
|
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#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__PRI_ALIAS_1 0x000000e1
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__PRI_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__PRI_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__RED_ALIAS_0 0x000000e0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__RED_ALIAS_0_DATA 31:23
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__RED_ALIAS_0_WIDTH 9
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__RED_ALIAS_1 0x000000e2
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__RED_ALIAS_1_DATA 22:0
|
|
#define NV_FUSE_OPT_FPF_FIELD_SPARE_FUSES_16__RED_ALIAS_1_WIDTH 23
|
|
#define NV_FUSE_OPT_FPF_SEC_RISCV_PL3_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_SEC_RISCV_PL3_DISABLE__PRI_ALIAS_0 0x000000e1
|
|
#define NV_FUSE_OPT_FPF_SEC_RISCV_PL3_DISABLE__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_FPF_SEC_RISCV_PL3_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_SEC_RISCV_PL3_DISABLE__RED_ALIAS_0 0x000000e2
|
|
#define NV_FUSE_OPT_FPF_SEC_RISCV_PL3_DISABLE__RED_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_FPF_SEC_RISCV_PL3_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_PMU_RISCV_PL3_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_PMU_RISCV_PL3_DISABLE__PRI_ALIAS_0 0x000000e1
|
|
#define NV_FUSE_OPT_FPF_PMU_RISCV_PL3_DISABLE__PRI_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_FPF_PMU_RISCV_PL3_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_PMU_RISCV_PL3_DISABLE__RED_ALIAS_0 0x000000e2
|
|
#define NV_FUSE_OPT_FPF_PMU_RISCV_PL3_DISABLE__RED_ALIAS_0_DATA 24:24
|
|
#define NV_FUSE_OPT_FPF_PMU_RISCV_PL3_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_GSP_RISCV_PL3_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_GSP_RISCV_PL3_DISABLE__PRI_ALIAS_0 0x000000e1
|
|
#define NV_FUSE_OPT_FPF_GSP_RISCV_PL3_DISABLE__PRI_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_OPT_FPF_GSP_RISCV_PL3_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_GSP_RISCV_PL3_DISABLE__RED_ALIAS_0 0x000000e2
|
|
#define NV_FUSE_OPT_FPF_GSP_RISCV_PL3_DISABLE__RED_ALIAS_0_DATA 25:25
|
|
#define NV_FUSE_OPT_FPF_GSP_RISCV_PL3_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE__PRI_ALIAS_0 0x000000e1
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE__PRI_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE__RED_ALIAS_0 0x000000e2
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE__RED_ALIAS_0_DATA 26:26
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE_CONTROL__PRI_ALIAS_0 0x000000e1
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE_CONTROL__PRI_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE_CONTROL__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE_CONTROL__RED_ALIAS_0 0x000000e2
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE_CONTROL__RED_ALIAS_0_DATA 27:27
|
|
#define NV_FUSE_OPT_FPF_SEC_FALCON_DISABLE_CONTROL__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE__PRI_ALIAS_0 0x000000e1
|
|
#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE__PRI_ALIAS_0_DATA 28:28
|
|
#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE__RED_ALIAS_0 0x000000e2
|
|
#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE__RED_ALIAS_0_DATA 28:28
|
|
#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE_CONTROL__WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE_CONTROL__PRI_ALIAS_0 0x000000e1
|
|
#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE_CONTROL__PRI_ALIAS_0_DATA 29:29
|
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#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE_CONTROL__RED_ALIAS_0 0x000000e2
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#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE_CONTROL__RED_ALIAS_0_DATA 29:29
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#define NV_FUSE_OPT_FPF_PMU_FALCON_DISABLE_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE__WIDTH 1
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE__PRI_ALIAS_0 0x000000e1
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE__PRI_ALIAS_0_DATA 30:30
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE__RED_ALIAS_0 0x000000e2
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE__RED_ALIAS_0_DATA 30:30
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE_CONTROL__PRI_ALIAS_0 0x000000e1
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE_CONTROL__PRI_ALIAS_0_DATA 31:31
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE_CONTROL__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE_CONTROL__RED_ALIAS_0 0x000000e2
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE_CONTROL__RED_ALIAS_0_DATA 31:31
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#define NV_FUSE_OPT_FPF_GSP_FALCON_DISABLE_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_MINION_UCODE9_VERSION__WIDTH 16
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#define NV_FUSE_OPT_FPF_MINION_UCODE9_VERSION__PRI_ALIAS_0 0x000000e3
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#define NV_FUSE_OPT_FPF_MINION_UCODE9_VERSION__PRI_ALIAS_0_DATA 15:0
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#define NV_FUSE_OPT_FPF_MINION_UCODE9_VERSION__PRI_ALIAS_0_WIDTH 16
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#define NV_FUSE_OPT_FPF_MINION_UCODE9_VERSION__RED_ALIAS_0 0x000000e4
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#define NV_FUSE_OPT_FPF_MINION_UCODE9_VERSION__RED_ALIAS_0_DATA 15:0
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#define NV_FUSE_OPT_FPF_MINION_UCODE9_VERSION__RED_ALIAS_0_WIDTH 16
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#define NV_FUSE_OPT_FPF_MINION_UCODE10_VERSION__WIDTH 16
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#define NV_FUSE_OPT_FPF_MINION_UCODE10_VERSION__PRI_ALIAS_0 0x000000e3
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#define NV_FUSE_OPT_FPF_MINION_UCODE10_VERSION__PRI_ALIAS_0_DATA 31:16
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#define NV_FUSE_OPT_FPF_MINION_UCODE10_VERSION__PRI_ALIAS_0_WIDTH 16
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#define NV_FUSE_OPT_FPF_MINION_UCODE10_VERSION__RED_ALIAS_0 0x000000e4
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#define NV_FUSE_OPT_FPF_MINION_UCODE10_VERSION__RED_ALIAS_0_DATA 31:16
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#define NV_FUSE_OPT_FPF_MINION_UCODE10_VERSION__RED_ALIAS_0_WIDTH 16
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#define NV_FUSE_OPT_FPF_MINION_UCODE11_VERSION__WIDTH 16
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#define NV_FUSE_OPT_FPF_MINION_UCODE11_VERSION__PRI_ALIAS_0 0x000000e5
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE11_VERSION__PRI_ALIAS_0_DATA 15:0
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#define NV_FUSE_OPT_FPF_MINION_UCODE11_VERSION__PRI_ALIAS_0_WIDTH 16
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE11_VERSION__RED_ALIAS_0 0x000000e6
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE11_VERSION__RED_ALIAS_0_DATA 15:0
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#define NV_FUSE_OPT_FPF_MINION_UCODE11_VERSION__RED_ALIAS_0_WIDTH 16
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE12_VERSION__WIDTH 16
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#define NV_FUSE_OPT_FPF_MINION_UCODE12_VERSION__PRI_ALIAS_0 0x000000e5
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE12_VERSION__PRI_ALIAS_0_DATA 31:16
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE12_VERSION__PRI_ALIAS_0_WIDTH 16
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE12_VERSION__RED_ALIAS_0 0x000000e6
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE12_VERSION__RED_ALIAS_0_DATA 31:16
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#define NV_FUSE_OPT_FPF_MINION_UCODE12_VERSION__RED_ALIAS_0_WIDTH 16
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#define NV_FUSE_OPT_FPF_MINION_UCODE13_VERSION__WIDTH 16
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#define NV_FUSE_OPT_FPF_MINION_UCODE13_VERSION__PRI_ALIAS_0 0x000000e7
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE13_VERSION__PRI_ALIAS_0_DATA 15:0
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#define NV_FUSE_OPT_FPF_MINION_UCODE13_VERSION__PRI_ALIAS_0_WIDTH 16
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE13_VERSION__RED_ALIAS_0 0x000000e8
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE13_VERSION__RED_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE13_VERSION__RED_ALIAS_0_WIDTH 16
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE14_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE14_VERSION__PRI_ALIAS_0 0x000000e7
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE14_VERSION__PRI_ALIAS_0_DATA 31:16
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE14_VERSION__PRI_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE14_VERSION__RED_ALIAS_0 0x000000e8
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE14_VERSION__RED_ALIAS_0_DATA 31:16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE14_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE15_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE15_VERSION__PRI_ALIAS_0 0x000000e9
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE15_VERSION__PRI_ALIAS_0_DATA 15:0
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE15_VERSION__PRI_ALIAS_0_WIDTH 16
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE15_VERSION__RED_ALIAS_0 0x000000ea
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE15_VERSION__RED_ALIAS_0_DATA 15:0
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE15_VERSION__RED_ALIAS_0_WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE16_VERSION__WIDTH 16
|
|
#define NV_FUSE_OPT_FPF_MINION_UCODE16_VERSION__PRI_ALIAS_0 0x000000e9
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE16_VERSION__PRI_ALIAS_0_DATA 31:16
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE16_VERSION__PRI_ALIAS_0_WIDTH 16
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE16_VERSION__RED_ALIAS_0 0x000000ea
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE16_VERSION__RED_ALIAS_0_DATA 31:16
|
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#define NV_FUSE_OPT_FPF_MINION_UCODE16_VERSION__RED_ALIAS_0_WIDTH 16
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#define NV_FUSE_OPT_FPF_UCODE_MINION_REV__WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_MINION_REV__PRI_ALIAS_0 0x000000eb
|
|
#define NV_FUSE_OPT_FPF_UCODE_MINION_REV__PRI_ALIAS_0_DATA 7:0
|
|
#define NV_FUSE_OPT_FPF_UCODE_MINION_REV__PRI_ALIAS_0_WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_MINION_REV__RED_ALIAS_0 0x000000ec
|
|
#define NV_FUSE_OPT_FPF_UCODE_MINION_REV__RED_ALIAS_0_DATA 7:0
|
|
#define NV_FUSE_OPT_FPF_UCODE_MINION_REV__RED_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS__WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS__PRI_ALIAS_0 0x000000eb
|
|
#define NV_FUSE_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS__PRI_ALIAS_0_DATA 8:8
|
|
#define NV_FUSE_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS__RED_ALIAS_0 0x000000ec
|
|
#define NV_FUSE_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS__RED_ALIAS_0_DATA 8:8
|
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#define NV_FUSE_OPT_FPF_NVDEC_FALCON_BR_VHR_DIS__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_GSP_FALCON_BR_VHR_DIS__WIDTH 1
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#define NV_FUSE_OPT_FPF_GSP_FALCON_BR_VHR_DIS__PRI_ALIAS_0 0x000000eb
|
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#define NV_FUSE_OPT_FPF_GSP_FALCON_BR_VHR_DIS__PRI_ALIAS_0_DATA 9:9
|
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#define NV_FUSE_OPT_FPF_GSP_FALCON_BR_VHR_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_GSP_FALCON_BR_VHR_DIS__RED_ALIAS_0 0x000000ec
|
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#define NV_FUSE_OPT_FPF_GSP_FALCON_BR_VHR_DIS__RED_ALIAS_0_DATA 9:9
|
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#define NV_FUSE_OPT_FPF_GSP_FALCON_BR_VHR_DIS__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_SEC_FALCON_BR_VHR_DIS__WIDTH 1
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#define NV_FUSE_OPT_FPF_SEC_FALCON_BR_VHR_DIS__PRI_ALIAS_0 0x000000eb
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#define NV_FUSE_OPT_FPF_SEC_FALCON_BR_VHR_DIS__PRI_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_FPF_SEC_FALCON_BR_VHR_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_SEC_FALCON_BR_VHR_DIS__RED_ALIAS_0 0x000000ec
|
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#define NV_FUSE_OPT_FPF_SEC_FALCON_BR_VHR_DIS__RED_ALIAS_0_DATA 10:10
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#define NV_FUSE_OPT_FPF_SEC_FALCON_BR_VHR_DIS__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_PMU_FALCON_BR_VHR_DIS__WIDTH 1
|
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#define NV_FUSE_OPT_FPF_PMU_FALCON_BR_VHR_DIS__PRI_ALIAS_0 0x000000eb
|
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#define NV_FUSE_OPT_FPF_PMU_FALCON_BR_VHR_DIS__PRI_ALIAS_0_DATA 11:11
|
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#define NV_FUSE_OPT_FPF_PMU_FALCON_BR_VHR_DIS__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_PMU_FALCON_BR_VHR_DIS__RED_ALIAS_0 0x000000ec
|
|
#define NV_FUSE_OPT_FPF_PMU_FALCON_BR_VHR_DIS__RED_ALIAS_0_DATA 11:11
|
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#define NV_FUSE_OPT_FPF_PMU_FALCON_BR_VHR_DIS__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN__WIDTH 1
|
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN__PRI_ALIAS_0 0x000000eb
|
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN__PRI_ALIAS_0_DATA 12:12
|
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN__PRI_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN__RED_ALIAS_0 0x000000ec
|
|
#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN__RED_ALIAS_0_DATA 12:12
|
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN_CONTROL__WIDTH 1
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN_CONTROL__PRI_ALIAS_0 0x000000eb
|
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN_CONTROL__PRI_ALIAS_0_DATA 13:13
|
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN_CONTROL__RED_ALIAS_0 0x000000ec
|
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN_CONTROL__RED_ALIAS_0_DATA 13:13
|
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#define NV_FUSE_OPT_FPF_GSP_RISCV_BR_ERROR_INFO_EN_CONTROL__RED_ALIAS_0_WIDTH 1
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN__WIDTH 1
|
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN__PRI_ALIAS_0 0x000000eb
|
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN__PRI_ALIAS_0_DATA 14:14
|
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN__RED_ALIAS_0 0x000000ec
|
|
#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN__RED_ALIAS_0_DATA 14:14
|
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN__RED_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN_CONTROL__WIDTH 1
|
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN_CONTROL__PRI_ALIAS_0 0x000000eb
|
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN_CONTROL__PRI_ALIAS_0_DATA 15:15
|
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN_CONTROL__RED_ALIAS_0 0x000000ec
|
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN_CONTROL__RED_ALIAS_0_DATA 15:15
|
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#define NV_FUSE_OPT_FPF_SEC_RISCV_BR_ERROR_INFO_EN_CONTROL__RED_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN__WIDTH 1
|
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN__PRI_ALIAS_0 0x000000eb
|
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN__PRI_ALIAS_0_DATA 16:16
|
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN__RED_ALIAS_0 0x000000ec
|
|
#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN__RED_ALIAS_0_DATA 16:16
|
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN__RED_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN_CONTROL__WIDTH 1
|
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN_CONTROL__PRI_ALIAS_0 0x000000eb
|
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN_CONTROL__PRI_ALIAS_0_DATA 17:17
|
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN_CONTROL__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN_CONTROL__RED_ALIAS_0 0x000000ec
|
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN_CONTROL__RED_ALIAS_0_DATA 17:17
|
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#define NV_FUSE_OPT_FPF_PMU_RISCV_BR_ERROR_INFO_EN_CONTROL__RED_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_FPF_PRI_FILLER_WR_SECURE__WIDTH 1
|
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#define NV_FUSE_OPT_FPF_PRI_FILLER_WR_SECURE__PRI_ALIAS_0 0x000000eb
|
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#define NV_FUSE_OPT_FPF_PRI_FILLER_WR_SECURE__PRI_ALIAS_0_DATA 18:18
|
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#define NV_FUSE_OPT_FPF_PRI_FILLER_WR_SECURE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_PRI_FILLER_WR_SECURE__RED_ALIAS_0 0x000000ec
|
|
#define NV_FUSE_OPT_FPF_PRI_FILLER_WR_SECURE__RED_ALIAS_0_DATA 18:18
|
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#define NV_FUSE_OPT_FPF_PRI_FILLER_WR_SECURE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_UNLOCK__WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_UNLOCK__PRI_ALIAS_0 0x000000eb
|
|
#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_UNLOCK__PRI_ALIAS_0_DATA 19:19
|
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_UNLOCK__PRI_ALIAS_0_WIDTH 1
|
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_UNLOCK__RED_ALIAS_0 0x000000ec
|
|
#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_UNLOCK__RED_ALIAS_0_DATA 19:19
|
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_UNLOCK__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_LOCK__WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_LOCK__PRI_ALIAS_0 0x000000eb
|
|
#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_LOCK__PRI_ALIAS_0_DATA 20:20
|
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#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_LOCK__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_LOCK__RED_ALIAS_0 0x000000ec
|
|
#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_LOCK__RED_ALIAS_0_DATA 20:20
|
|
#define NV_FUSE_OPT_FPF_RMA_PRI_FILLER_LOCK__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_IST_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_IST_DISABLE__PRI_ALIAS_0 0x000000eb
|
|
#define NV_FUSE_OPT_FPF_IST_DISABLE__PRI_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_FPF_IST_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_IST_DISABLE__RED_ALIAS_0 0x000000ec
|
|
#define NV_FUSE_OPT_FPF_IST_DISABLE__RED_ALIAS_0_DATA 21:21
|
|
#define NV_FUSE_OPT_FPF_IST_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_ENABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_ENABLE__PRI_ALIAS_0 0x000000eb
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_ENABLE__PRI_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_ENABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_ENABLE__RED_ALIAS_0 0x000000ec
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_ENABLE__RED_ALIAS_0_DATA 22:22
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_ENABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_DISABLE__WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_DISABLE__PRI_ALIAS_0 0x000000eb
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_DISABLE__PRI_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_DISABLE__PRI_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_DISABLE__RED_ALIAS_0 0x000000ec
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_DISABLE__RED_ALIAS_0_DATA 23:23
|
|
#define NV_FUSE_OPT_FPF_RMA_IST_DISABLE__RED_ALIAS_0_WIDTH 1
|
|
#define NV_FUSE_OPT_FPF_UCODE_LSPMU_REV__WIDTH 8
|
|
#define NV_FUSE_OPT_FPF_UCODE_LSPMU_REV__PRI_ALIAS_0 0x000000eb
|
|
#define NV_FUSE_OPT_FPF_UCODE_LSPMU_REV__PRI_ALIAS_0_DATA 31:24
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#define NV_FUSE_OPT_FPF_UCODE_LSPMU_REV__PRI_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_FPF_UCODE_LSPMU_REV__RED_ALIAS_0 0x000000ec
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#define NV_FUSE_OPT_FPF_UCODE_LSPMU_REV__RED_ALIAS_0_DATA 31:24
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#define NV_FUSE_OPT_FPF_UCODE_LSPMU_REV__RED_ALIAS_0_WIDTH 8
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#define NV_FUSE_OPT_TPC_DISABLE_GPC(i) (0x00820760+(i)*4) /* */
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#define NV_FUSE_OPT_TPC_DISABLE_GPC__SIZE_1 8 /* */
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#define NV_FUSE_OPT_TPC_DISABLE_GPC_DATA 31:0 /* */
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#define NV_FUSE_OPT_TPC_DISABLE_GPC_DATA_INIT 0x00000000 /* */
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#define NV_FUSE_OPT_TPC_DISABLE_GPC_IDX(j) (j):(j) /* */
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#define NV_FUSE_OPT_TPC_DISABLE_GPC_IDX__SIZE_1 32 /* */
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#define NV_FUSE_OPT_TPC_DISABLE_GPC_IDX_ENABLE 0x00000000 /* */
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#define NV_FUSE_OPT_TPC_DISABLE_GPC_IDX_DISABLE 0x00000001 /* */
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#define NV_FUSE_OPT_ADC_CAL(i) (0x0082130c+(i)*4) /* */
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#define NV_FUSE_OPT_ADC_CAL__SIZE_1 9 /* */
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#define NV_FUSE_OPT_ADC_CAL_OFFSET_CALIBRATIONDATA 6:0 /* */
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#define NV_FUSE_OPT_ADC_CAL_GAIN_CALIBRATION_DATA 11:7 /* */
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#define NV_FUSE_OPT_ADC_CAL_OFFSET_COARSE_CALIBRATION_DATA 15:12 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT(i) (0x00821354+(i)*4) /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT__SIZE_1 9 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_LT_CODE_DELTA_DATA 9:6 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT(i) (0x0082139C+(i)*4) /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT__SIZE_1 9 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_CODE_ERROR_DATA 5:0 /* */
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#define NV_FUSE_OPT_ADC_CODE_ERR_HT_CODE_DELTA_DATA 9:6 /* */
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#endif // __ga102_dev_fuse_h__
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