1685 lines
139 KiB
C
1685 lines
139 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
|
|
*
|
|
* Copyright 2015 by NVIDIA Corporation. All rights reserved. All
|
|
* information contained herein is proprietary and confidential to NVIDIA
|
|
* Corporation. Any use, reproduction, or disclosure without the written
|
|
* permission of NVIDIA Corporation is prohibited.
|
|
*
|
|
* _NVRM_COPYRIGHT_END_
|
|
*/
|
|
|
|
//
|
|
// DO NOT EDIT - this file automatically generated by ref2h-fbpa.pl
|
|
//
|
|
|
|
#ifndef __ga102_dev_fbpa_off_h__
|
|
#define __ga102_dev_fbpa_off_h__
|
|
|
|
//
|
|
// Register Offsets in range 'NV_PFB_FBPA' :
|
|
// #define NV_PFB_FBPA 0x009A3FFF:0x009A0000 /* RW--D */
|
|
//
|
|
#define NV_PFB_FBPA_OFFSET_MEM_PRIV_LEVEL_MASK 0x00000168 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HISEC_PRIV_LEVEL_MASK 0x00000148 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HISECTESTCMD_PRIV_LEVEL_MASK 0x0000014C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_PRIV_LEVEL_MASK 0x00000170 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_PM_PRIV_LEVEL_MASK 0x000001B0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CG_PRIV_LEVEL_MASK 0x000001B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CSTATUS_PRIV_LEVEL_MASK 0x00002578 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ROW_REMAP_PRIV_LEVEL_MASK 0x0000000C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_MEM_DRAMID_PRIV_LEVEL_MASK 0x00002250 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DRAMID_PRIV_LEVEL_MASK 0x0000086C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SPARE 0x00000050 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SPARE2 0x000000CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FALCON_MONITOR 0x00000054 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FALCON_CTRL_VER 0x00000064 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_CFG_PWRD 0x00000060 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_0 0x00000080 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_1 0x00000084 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_2 0x00002340 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_SUBPIDLE(i) (0x00002344+(i)*4) /* R--4A */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_SUBPIDLE__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_PAIDLE 0x0000234C /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_CTRL_0 0x00002350 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_CTRL_1 0x00002354 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_COUNT_LO_BASE 0x00002358 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_COUNT_HI_BASE 0x0000235C /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_COUNT_LO_0 0x00002360 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_COUNT_HI_0 0x00002364 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_COUNT_LO_1 0x00002368 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_COUNT_HI_1 0x0000236C /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_COUNT_LO_2 0x00002370 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_COUNT_HI_2 0x00002374 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_COUNT_LO_3 0x00002378 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DEBUG_COUNT_HI_3 0x0000237C /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_ROW_REMAP 0x000001DC /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_ROW_REMAP_RD(i) (0x000001F0+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_ROW_REMAP_RD__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ROW_REMAP_WR(i) (0x000001F8+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_ROW_REMAP_WR__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TESTCMD 0x00000090 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TESTCMD_EXT 0x00000094 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TESTCMD_EXT_1 0x00000154 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SWIZZLE_BIT_SUBP0BYTE0 0x000000A0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SWIZZLE_BIT_SUBP0BYTE1 0x000000A4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SWIZZLE_BIT_SUBP0BYTE2 0x000000A8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SWIZZLE_BIT_SUBP0BYTE3 0x000000AC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SWIZZLE_BIT_SUBP1BYTE0 0x000000B0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SWIZZLE_BIT_SUBP1BYTE1 0x000000B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SWIZZLE_BIT_SUBP1BYTE2 0x000000B8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SWIZZLE_BIT_SUBP1BYTE3 0x000000BC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SWIZZLE_DBI 0x000000C0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SWIZZLE_ECC 0x000000C8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SWIZZLE_BYTE 0x000000C4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_PM 0x00000100 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_PM_SUBP(i) (0x000001E0+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_PM_SUBP__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_PM_CAPTURE(i) (0x00000180+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_PM_CAPTURE__SIZE_1 12 /* */
|
|
#define NV_PFB_FBPA_OFFSET_PM_CAPTURE_HI(i) (0x00002500+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_PM_CAPTURE_HI__SIZE_1 12 /* */
|
|
#define NV_PFB_FBPA_OFFSET_PM_CAPTURE_WINDOW(i) (0x000001D0+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_PM_CAPTURE_WINDOW__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_PM_CAPTURE_CTL 0x000001D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_PM_BUCKET(i) (0x00002530+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_PM_BUCKET__SIZE_1 11 /* */
|
|
#define NV_PFB_FBPA_OFFSET_PM_BUCKET_CTL 0x0000255C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_PM_CTL 0x00002560 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_REG_CTL 0x00002564 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASR_NUM(i) (0x00000110+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASR_NUM__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASR_CYCCNT(i) (0x00000118+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASR_CYCCNT__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASR_MAXCYC(i) (0x00000120+(i)*4) /* R--4A */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASR_MAXCYC__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASR_MINCYC(i) (0x00000128+(i)*4) /* R--4A */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASR_MINCYC__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASRSTALL_CYCCNT(i) (0x00000130+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASRSTALL_CYCCNT__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASRSTALL_MAXCYC(i) (0x00000138+(i)*4) /* R--4A */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASRSTALL_MAXCYC__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASRSTALL_MINCYC(i) (0x00000140+(i)*4) /* R--4A */
|
|
#define NV_PFB_FBPA_OFFSET_PM_ASRSTALL_MINCYC__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ASRCTRL_NONISO 0x00000150 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_MISC_CTRL 0x00000160 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_NUM_ACTIVE_FBPS 0x00000164 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_NUM_ACTIVE_LTCS 0x0000016C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_WPRE0 0x00000174 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_WPRE1 0x00000178 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_WPRE2 0x0000017C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_WPOST0 0x000001B8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_WPOST1 0x000001BC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_WPOST2 0x000001C0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CFG0 0x00000200 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CFG1 0x00000204 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CSTATUS 0x0000020C /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_CSTATUS_OVERRIDE 0x0000257C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_REFCTRL 0x00000210 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ZQ 0x00000214 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_PIN 0x00000218 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_PAD 0x0000021C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING 0x000003F4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING0 0x00000220 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING1 0x00000224 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING2 0x00000228 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING3 0x0000022C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING4 0x00000230 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING5 0x00000234 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING6 0x00000238 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING7 0x0000023C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING8 0x00000240 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING9 0x00000244 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING10 0x00000248 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING11 0x0000024C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING12 0x00000250 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING13 0x00000254 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING14 0x00000258 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING15 0x0000025C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING16 0x00000260 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING17 0x00000264 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING18 0x00000268 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING19 0x0000026C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING20 0x0000028C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING21 0x00000390 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING22 0x00000394 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING23 0x0000039C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING24 0x000003E0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING25 0x000003EC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING26 0x000024E0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING27 0x000024E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING28 0x000024E8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING29 0x000024EC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING30 0x000024FC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING31 0x000024F8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_POWER_0 0x000024F0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_POWER_1 0x000024F4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ASR_CTRL0 0x00002300 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ASR_CTRL1 0x00002304 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ASR_CTRL2 0x00002308 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ASR_CTRL3 0x0000230C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ASR_CTRL4 0x00002310 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ASR_CTRL5 0x00002314 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ASR_CTRL6 0x00002318 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ASR_CTRL7 0x0000231C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ACPD_CTRL0 0x00002320 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ACPD_CTRL1 0x00002324 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ACPD_CTRL2 0x00002328 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ACPD_CTRL3 0x0000232C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ACPD_CTRL4 0x00002330 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ACPD_CTRL5 0x00002334 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ACPD_CTRL6 0x00002338 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ACPD_CTRL7 0x0000233C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DQR_CTRL 0x00002444 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DQR_STATUS_DQ_IC0_SUBP0 0x000024C0 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DQR_STATUS_DQ_IC0_SUBP1 0x000024C4 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DQR_STATUS_DQ_IC1_SUBP0 0x000024C8 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DQR_STATUS_DQ_IC1_SUBP1 0x000024CC /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_DQR_STATUS_VLD 0x000024D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFIG0 0x00000290 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFIG1 0x00000294 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFIG2 0x00000298 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFIG3 0x0000029C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFIG4 0x000002A0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFIG5 0x000002A4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFIG6 0x000002A8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFIG7 0x000002AC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFIG8 0x000002CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFIG9 0x000002E8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFIG10 0x000002F4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFIG11 0x000003E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFIG12 0x0000015C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING0_GEN 0x000002B0 /* R-I4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING1_GEN 0x000002B4 /* R-I4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING2_GEN 0x000002B8 /* R-I4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING3_GEN 0x000002BC /* R-I4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING4_GEN 0x000002C0 /* R-I4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING5_GEN 0x000002C4 /* R-I4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING6_GEN 0x000002C8 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING7_GEN 0x000002D0 /* R-I4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING8_GEN 0x000002D4 /* R-I4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING9_GEN 0x000002D8 /* R-I4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING15_GEN 0x000002DC /* R-I4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING16_GEN 0x000002E0 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING17_GEN 0x000002E4 /* R-I4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING18_GEN 0x000002EC /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING19_GEN 0x000002F0 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING20_GEN 0x00000288 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING22_GEN 0x000003F8 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_TIMING24_GEN 0x000003E8 /* R-I4R */
|
|
#define NV_PFB_FBPA_OFFSET_PTR_RESET 0x00000158 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ASR_STALL_WKUP 0x00000384 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ASR_WAKEUP 0x000002F8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DRAM_ASR 0x000002FC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS 0x00000300 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_EMRS 0x00000304 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS_EXT 0x00000308 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_EMRS_EXT 0x0000030C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_REF 0x00000310 /* -W-4R */
|
|
#define NV_PFB_FBPA_OFFSET_PRE 0x00000314 /* -W-4R */
|
|
#define NV_PFB_FBPA_OFFSET_NOP 0x00000318 /* -W-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SELF_REF 0x0000031C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_EMRS2 0x00000320 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_EMRS3 0x00000324 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_EMRS2_EXT 0x00000328 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_EMRS3_EXT 0x0000032C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS1 0x00000330 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS2 0x00000334 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS3 0x00000338 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS4 0x0000033C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS5 0x00000340 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS6 0x00000344 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS7 0x00000348 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS8 0x00000354 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS9 0x00000358 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS10 0x00002200 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS11 0x00002204 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS12 0x00002208 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS13 0x0000220C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS14 0x0000035C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS15 0x0000034C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS16 0x00002210 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS17 0x00002214 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS18 0x00002218 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS19 0x0000221C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS20 0x00002220 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS22 0x00002224 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS23 0x00002228 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS24 0x0000222C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS25 0x00002230 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS32 0x00002234 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS40 0x00002238 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_MRR 0x0000223C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_MPC 0x00002240 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_MISC_DRAMC 0x00000350 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_IC_CTRL 0x00000208 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_STALL_CMD_FIFO 0x000023FC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS6_SUBP0 0x00000360 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS6_SUBP1 0x00000364 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS9_SUBP0 0x00000368 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS9_SUBP1 0x0000036C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS14_SUBP0 0x00000370 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS14_SUBP1 0x00000374 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS4_EXT 0x00000378 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS5_EXT 0x0000037C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_GENERIC_MRS6_EXT 0x00000380 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CG1 0x00000280 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CG2 0x00000284 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_READ_FT_CFG 0x00000400 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_WRITE_FT_CFG 0x00000410 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_READ_BANKQ_CFG 0x00000420 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_WRITE_BANKQ_CFG 0x00000430 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DIR_ARB_CFG0 0x00000440 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DIR_ARB_CFG1 0x00000444 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DIR_ARB_CFG2 0x00000448 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DIR_ARB_CFG3 0x0000046C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DIR_ARB_CFG4 0x000004BC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DIR_ARB_CFG5 0x00002580 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DIR_ARB_CFG6 0x00002584 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DIR_ARB_CFG7 0x00002588 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_WRITE_ARB_CFG 0x00000450 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_READ_ARB_CFG 0x00000454 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ACT_ARB_CFG 0x00000460 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ACT_ARB_CFG1 0x00000464 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ACT_ARB_CFG2 0x00000468 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ACT_ARB_CFG3 0x000004C8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ACT_ARB_CFG4 0x000004D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FIFO_DEPTH 0x000004D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_WINDOW 0x000004D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_WINDOW_ACPD_ASR 0x00000458 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_SECTORS_WR 0x000004DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_SECTORS_VC0 0x000004F0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_SECTORS_VC1 0x000004F4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_SECTORS_VC2 0x000004F8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_SECTORS_ACPD_ASR 0x000004FC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_WR 0x000004E0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_VC0 0x000004E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_VC1 0x000004E8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_VC1_ECC 0x0000045C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_VC2 0x000004EC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_ACPD 0x000004B0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BW_TRACKER_ASR 0x0000044C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_CONTROL 0x00000470 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_INTR_CTRL 0x00000474 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_STATUS(i) (0x00000478+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_STATUS__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_SEC_COUNT(i) (0x00000480+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_SEC_COUNT__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_DED_COUNT(i) (0x00000488+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_DED_COUNT__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_DIAG(i) (0x00000490+(i)*4) /* RWI4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_DIAG__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ERR_INJECTION_ADDR(i) (0x00000498+(i)*4) /* RWI4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ERR_INJECTION_ADDR__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ERR_INJECTION_ADDR_EXT(i) (0x000024B8+(i)*4) /* RWI4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ERR_INJECTION_ADDR_EXT__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR(i) (0x000004A0+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT(i) (0x000004A8+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT2(i) (0x00002498+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT2__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_DED(i) (0x00002448+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_DED__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT_DED(i) (0x00002450+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT_DED__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT2_DED(i) (0x000024A0+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT2_DED__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_SEC(i) (0x00002458+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_SEC__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT_SEC(i) (0x00002460+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT_SEC__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT2_SEC(i) (0x000024A8+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT2_SEC__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_POISON(i) (0x00002468+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_POISON__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT_POISON(i) (0x00002470+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT_POISON__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT2_POISON(i) (0x000024B0+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT2_POISON__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_ADDRERR(i) (0x00002480+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_ADDRERR__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT_ADDRERR(i) (0x00002488+(i)*4) /* R-I4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDR_EXT_ADDRERR__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDRERR_COUNT(i) (0x00002490+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_ECC_ADDRERR_COUNT__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_BANK_SWIZZLE 0x000004B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CONFLICT_RESOLUTION 0x000004B8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_LTC_BANDWIDTH_LIMITER 0x000004C0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO2PA_RESYNC_FIFO 0x000004C4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_READSCHEDULE_FIFO 0x000004CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRIGGER_CNTRL 0x00000500 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAP0 0x0000050C /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_PARITY 0x00000510 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BLK_ACTIVITY_PRIV_LEVEL_MASK 0x00000554 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BA_WT0 0x00000514 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BA_WT1 0x00000518 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BA_WT2 0x0000051C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BA_WT3 0x00000520 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BA_WT4 0x00000524 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BA_WT5 0x00000528 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_BA 0x00000550 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_RD 0x00000558 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_WR 0x0000055C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_TRIGGER 0x00000560 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_DATA0 0x00000564 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_DATA1 0x00000568 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_DATA2 0x0000056C /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_ERROR_RATE 0x00000570 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_TICK 0x00000574 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_ERROR_MAX_DELTA 0x00000578 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_REPLAY_RETRY_SUBP0 0x000000D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_REPLAY_RETRY_SUBP1 0x000000D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_REPLAY_CYCLES_SUBP0 0x000000D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_REPLAY_CYCLES_SUBP1 0x000000DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CRC 0x00000580 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_INTERRUPT 0x00000584 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_DEBUG 0x00000588 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_ERROR_COUNT_RD_BYTE(i) (0x00002400+(i)*4) /* RWI4A */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_ERROR_COUNT_RD_BYTE__SIZE_1 8 /* */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_ERROR_COUNT_WR_BYTE(i) (0x00002420+(i)*4) /* RWI4A */
|
|
#define NV_PFB_FBPA_OFFSET_CRC_ERROR_COUNT_WR_BYTE__SIZE_1 8 /* */
|
|
#define NV_PFB_FBPA_OFFSET_REPLAY_DEBUG 0x00002440 /* RWI4R */
|
|
#define NV_PFB_FBPA_OFFSET_RR_FIFOERR(i) (0x000024D4+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_RR_FIFOERR__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_REFCTRL3 0x000024DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_ISO_LATENCY 0x0000058C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_INTR_STATUS 0x00000398 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_OOR 0x000003A8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CFG0 0x0000038C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_ARB_CFG 0x000003A0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_ARB_CFG1 0x000003A4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CHAR 0x000003AC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CHAR_COUNTER_MASK_DQ_DW0 0x000003B0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CHAR_COUNTER_MASK_DQ_DW1 0x000003B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CHAR_COUNTER_MASK_DQ_DW2 0x000003B8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CHAR_COUNTER_MASK_DQ_DW3 0x000003BC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW0 0x000003C0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW1 0x000003C4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW2 0x000003C8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CHAR_COUNTER_MASK_DQ_INVERT_DW3 0x000003CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CHAR_COUNTER_MASK_DBI 0x000003D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CHAR_COUNTER_MASK_ECC 0x000003D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CHAR_COUNTER_MAX 0x000003D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_HBM_CHAR_COUNTER_THRESHOLD 0x000003DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_RR_CTRL 0x000003FC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_PRIV_LEVEL_MASK 0x000008FC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_BROADCAST 0x00000590 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CONFIG_DBI 0x00000594 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CHANNELCFG 0x00000598 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_BROADCAST1 0x0000059C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CONFIG5 0x00000604 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SPARE 0x0000060C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CFG_BRICK_VAUXGEN 0x00000610 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CFG_VTTGEN_VAUXGEN 0x00000614 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_ASR 0x0000061C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DDLLCAL_CTRL 0x00000670 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_DDLLCAL_STATUS 0x00000674 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_DDLLCAL_STATUS 0x00000678 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DDLL_CTRL 0x0000067C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_ADR_DDLL 0x00000694 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_WCK_DDLL 0x00000698 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_WCK_DDLL 0x0000069C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_IB_DDLL 0x000006A0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_IB_DDLL 0x000006A4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_OB_DDLL 0x000006A8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_OB_DDLL 0x000006AC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_DQDQS_DDLL 0x000006B0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_DQDQS_DDLL 0x000006B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_QUSE_DDLL 0x000006B8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_QUSE_DDLL 0x000006BC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_QUSE_DDLL_RANK1 0x00000ED8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_QUSE_DDLL_RANK1 0x00000EDC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_BYTE_VREF_MODE 0x00000700 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DELAY_BROADCAST_DDLL 0x00000704 /* -W-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DELAY_BROADCAST_MISC 0x00000708 /* -W-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DELAY_BROADCAST_MISC1 0x0000070C /* -W-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DELAY_BROADCAST_MISC2_SUBP0 0x00000710 /* -W-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DELAY_BROADCAST_MISC2_SUBP1 0x00000714 /* -W-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DELAY_BROADCAST_MISC3 0x00000718 /* -W-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CML_CLK 0x00000650 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DELAY 0x0000065C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_DELAY 0x000008E0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CFG_WCK_TAPER 0x000008E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CML_WCK 0x0000066C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CAL 0x00000504 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_TRNG_ARB 0x00000508 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CAL_BYP_DRVR 0x00000720 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CAL_BYP_DRVF 0x00000724 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CAL_BYP_DRVT 0x00000728 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CAL_BYP_SLWR 0x00000730 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CAL_BYP_CS 0x00000738 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_ADR_DRV_SEL0 0x000007D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_ADR_DRV_SEL1 0x000007D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_ADR_DRV_SEL2 0x000007D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_ADR_DRV_SEL3 0x000007E8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CALCFG 0x000007E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVR_SUBP0_DAT 0x00001EC8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVR_SUBP1_DAT 0x00001ECC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVR_SUBP0_DQS 0x00001ED0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVR_SUBP1_DQS 0x00001ED4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVR_SUBP0_WDQS 0x00001ED8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVR_SUBP1_WDQS 0x00001EDC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVF_SUBP0_DAT 0x00001EE0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVF_SUBP1_DAT 0x00001EE4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVF_SUBP0_DQS 0x00001EE8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVF_SUBP1_DQS 0x00001EEC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVF_SUBP0_WDQS 0x00001EF0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVF_SUBP1_WDQS 0x00001EF4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVT_SUBP0_DAT 0x00001EF8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVT_SUBP1_DAT 0x00001EFC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVT_SUBP0_DQS 0x00001F00 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVT_SUBP1_DQS 0x00001F04 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVT_SUBP0_WDQS 0x00001F08 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVT_SUBP1_WDQS 0x00001F0C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_CMD_DRVR_SUBP0 0x00001F10 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_CMD_DRVF_SUBP0 0x00001F14 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_CMD_DRVR_SUBP1 0x00001F18 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_CMD_DRVF_SUBP1 0x00001F1C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVDN_SUBP0_RX 0x00001F20 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_CAL_SLV_DELTA_DRVDN_SUBP1_RX 0x00001F24 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CAL_CLK 0x00001F28 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CAL_CLK_VML 0x00001F34 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CAL_WCK 0x00001F2C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CAL_WCK_VML 0x00001F38 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_PRI_FBPA_CG 0x00000000 /* RWE4R */
|
|
#define NV_PFB_FBPA_OFFSET_PRI_FBPA_CG1 0x00000004 /* RWE4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CFG8 0x00000800 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CFG10 0x00000808 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_BRLSHFT 0x00000820 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CFG_PWRD 0x00000824 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CFG11 0x00000828 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CFG12 0x0000082C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CFG1 0x00000830 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SPARE2 0x00000834 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VEND_ID_C0 0x00000838 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VEND_ID_C1 0x0000083C /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMOS_CLK 0x00000860 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_CMOS_WCK 0x00000864 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_CMOS_WCK 0x00000868 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_RCV_CTRL 0x00000870 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CFG7 0x00000874 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_PWR_CTRL 0x00000890 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_BLCG_CTRL 0x00000894 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_PWR_CTRL1 0x00000898 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_BYTE_CONFIG_L 0x000008C8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_BYTE_CONFIG_H 0x000008CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CLK_CTRL 0x000008D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_LOOPBK_TRIM 0x000008D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_PARITY 0x000008D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_PARITY 0x000008DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DRAMPLL_CFG 0x00000E00 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DRAMPLL_COEFF 0x00000E04 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DRAMPLL_CTRL 0x00000E08 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DRAMPLL_CFG2 0x00000E0C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DRAMPLL_DUAL_STATUS 0x00000E14 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_DRAMPLL_CFG3 0x00000E18 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_REFMPLL_CFG 0x00000E20 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_REFMPLL_COEFF 0x00000E24 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_REFMPLL_CTRL 0x00000E28 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_REFMPLL_CFG2 0x00000E2C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_REFMPLL_SSD0 0x00000E30 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_REFMPLL_SSD1 0x00000E34 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_MEM_TR_PRIV_LEVEL_MASK 0x00002030 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_MEM_TR_HISEC_PRIV_LEVEL_MASK 0x00002034 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_MEM_TR_CMD_PRIV_LEVEL_MASK 0x00002038 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_ADR(i) (0x00000900+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_ADR__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_CMD(i) (0x00000910+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_CMD__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DP(i) (0x00000918+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DP__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DP_CNTD(i) (0x00000920+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DP_CNTD__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_CTRL(i) (0x000009C0+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_CTRL__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_DQ0(i) (0x00000938+(i)*4) /* R--4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_DQ0__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_DQ1(i) (0x00000940+(i)*4) /* R--4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_DQ1__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_DQ2(i) (0x00000948+(i)*4) /* R--4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_DQ2__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_DQ3(i) (0x00000950+(i)*4) /* R--4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_DQ3__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_MISC0(i) (0x00000958+(i)*4) /* R--4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_MISC0__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_MISC1(i) (0x00000960+(i)*4) /* R--4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DEBUG_MISC1__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATTERN_PTR(i) (0x00000968+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATTERN_PTR__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_TIMING 0x00000970 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_TIMING2 0x000009C8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_TIMING3 0x00002050 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_PI_OFFSET_CTRL 0x00002054 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_STATUS 0x00000974 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_CTRL 0x00000978 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_LEGACY_CTRL 0x0000097C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_CTRL2 0x00002040 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_MISC_CTRL 0x00002070 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_TAG 0x00000A00 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATRAM 0x00000A04 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATRAM_SELECT 0x00000AE0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATRAM_SELECT2 0x00000AE4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATRAM_COUNTER 0x00000A08 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATRAM_COUNTER_MASK_LOWER(i) (0x00000AC0+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATRAM_COUNTER_MASK_LOWER__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATRAM_COUNTER_MASK_UPPER(i) (0x00000AC8+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATRAM_COUNTER_MASK_UPPER__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATRAM_COUNTER_MASK_MISC(i) (0x00000AD0+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATRAM_COUNTER_MASK_MISC__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_CHAR_CTRL 0x00000A0C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_CHAR_BURST 0x00000A10 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_CHAR_TURN 0x00000A14 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_CHAR_SWEEP_CTRL 0x00000A18 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_CHAR_BANK_CTRL 0x00000AD8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_CHAR_BANK_CTRL2 0x00000ADC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_ADDR_TADR_CTRL 0x000009CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_ADDR_CORS_CTRL 0x000009D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_ADDR_FINE_CTRL 0x000009D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_ADDR_CTRL 0x00000984 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_WCK_INTRPLTR_CTRL 0x00000988 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_WCK_INTRPLTR_VOTE_CTRL 0x000009D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_WCK_DDLL_CTRL 0x000009DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_WCK_TRIMMER_CTRL 0x000009E0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_WCK_INTRPLTR_CTRL_EXT 0x0000098C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_WCK_INTRPLTR_EXIT_CTRL 0x00000A1C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_WCK_EDC_LIMIT 0x00000990 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_QUSE_CORS_CTRL 0x000009F4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_QUSE_FINE_CTRL 0x000009F8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_QUSE_CTRL 0x000009FC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DLCELL_CTRL 0x00000AE8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DLCELL_CTRL2 0x00000AEC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_DLCELL_CTRL3 0x00000AFC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_CTRL_MPR 0x00000AF4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_CTRL_MPR_DATA 0x00000AF8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_LDFF_CTRL 0x00000994 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_BRLSHFT_CTRL 0x00000998 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_BRLSHFT_QUICK_CTRL 0x000009E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_CORS_INTRPLTR_CTRL 0x0000099C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_FINE_INTRPLTR_CTRL 0x000009A0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_CORS_DDLL_CTRL 0x000009E8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_FINE_DDLL_CTRL 0x000009EC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_TRIMMER_CTRL 0x000009A4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_VREF_CTRL 0x000009A8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_ERR_LIMIT 0x000009AC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_PERIODIC_CTRL 0x000009B0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_PERIODIC_DDLL_CTRL 0x000009F0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_PERIODIC_CTRL2 0x000009B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_PERIODIC_CTRL3 0x00002048 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_EDC_CTRL 0x0000204C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_WR_VREF_CTRL 0x00002044 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_IB_BYTE0(i) (0x00000A20+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_IB_BYTE0__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_IB_BYTE1(i) (0x00000A28+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_IB_BYTE1__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_IB_BYTE2(i) (0x00000A30+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_IB_BYTE2__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_IB_BYTE3(i) (0x00000A38+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_IB_BYTE3__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_IB_MISC(i) (0x00000A40+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_IB_MISC__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_OB_BYTE0(i) (0x00000A48+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_OB_BYTE0__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_OB_BYTE1(i) (0x00000A50+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_OB_BYTE1__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_OB_BYTE2(i) (0x00000A58+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_OB_BYTE2__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_OB_BYTE3(i) (0x00000A60+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_OB_BYTE3__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_OB_MISC(i) (0x00000A68+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_EYE_CENTER_OB_MISC__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_IB_BYTE0(i) (0x00000A70+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_IB_BYTE0__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_IB_BYTE1(i) (0x00000A78+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_IB_BYTE1__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_IB_BYTE2(i) (0x00000A80+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_IB_BYTE2__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_IB_BYTE3(i) (0x00000A88+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_IB_BYTE3__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_IB_MISC(i) (0x00000A90+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_IB_MISC__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_OB_BYTE0(i) (0x00000A98+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_OB_BYTE0__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_OB_BYTE1(i) (0x00000AA0+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_OB_BYTE1__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_OB_BYTE2(i) (0x00000AA8+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_OB_BYTE2__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_OB_BYTE3(i) (0x00000AB0+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_OB_BYTE3__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_OB_MISC(i) (0x00000AB8+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_RW_OFFSET_OB_MISC__SIZE_1 2 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATRAM_PRBS_SEED(i) (0x00002000+(i)*4) /* RW-4A */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PATRAM_PRBS_SEED__SIZE_1 8 /* */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PROFILE_CTRL 0x00002060 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PROFILE_FULL 0x00002064 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_PROFILE_PHASE 0x00002068 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_TRAINING_ARRAY_CTRL 0x00002074 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_SW_CONFIG 0x00002078 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_NOISE_CFG1 0x0000207C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_NOISE_CFG2 0x00002080 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_WCK 0x00000B04 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_WCKB 0x00000B14 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_WCK 0x00000B08 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_WCKB 0x00000B18 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_WCK_STEP_CTRL 0x00000EE0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_CTRL 0x00000B0C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_CTRL 0x00000B10 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_INTRPLTR_OFFSET 0x00000B00 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT1 0x00000B20 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT2 0x00000B24 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_IB_BRLSHFT3 0x00000B28 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT1 0x00000B2C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT2 0x00000B30 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_IB_BRLSHFT3 0x00000B34 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT1 0x00000B38 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT2 0x00000B3C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_IB_BRLSHFT3 0x00000B40 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT1 0x00000B44 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT2 0x00000B48 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_IB_BRLSHFT3 0x00000B4C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT1 0x00000B50 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT2 0x00000B54 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_IB_BRLSHFT3 0x00000B58 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT1 0x00000B5C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT2 0x00000B60 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_IB_BRLSHFT3 0x00000B64 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT1 0x00000B68 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT2 0x00000B6C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_IB_BRLSHFT3 0x00000B70 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT1 0x00000B74 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT2 0x00000B78 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_IB_BRLSHFT3 0x00000B7C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR1 0x00000BC0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR2 0x00000BC4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_IB_FINE_INTRPLTR3 0x00000BC8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR1 0x00000BCC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR2 0x00000BD0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_IB_FINE_INTRPLTR3 0x00000BD4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR1 0x00000BD8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR2 0x00000BDC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_IB_FINE_INTRPLTR3 0x00000BE0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR1 0x00000BE4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR2 0x00000BE8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_IB_FINE_INTRPLTR3 0x00000BEC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR1 0x00000BF0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR2 0x00000BF4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_IB_FINE_INTRPLTR3 0x00000BF8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR1 0x00000BFC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR2 0x00000C00 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_IB_FINE_INTRPLTR3 0x00000C04 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR1 0x00000C08 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR2 0x00000C0C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_IB_FINE_INTRPLTR3 0x00000C10 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR1 0x00000C14 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR2 0x00000C18 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_IB_FINE_INTRPLTR3 0x00000C1C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT1 0x00000C20 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT2 0x00000C24 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_OB_BRLSHFT3 0x00000C28 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT1 0x00000C2C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT2 0x00000C30 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_OB_BRLSHFT3 0x00000C34 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT1 0x00000C38 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT2 0x00000C3C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_OB_BRLSHFT3 0x00000C40 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT1 0x00000C44 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT2 0x00000C48 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_OB_BRLSHFT3 0x00000C4C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT1 0x00000C50 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT2 0x00000C54 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_OB_BRLSHFT3 0x00000C58 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT1 0x00000C5C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT2 0x00000C60 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_OB_BRLSHFT3 0x00000C64 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT1 0x00000C68 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT2 0x00000C6C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_OB_BRLSHFT3 0x00000C70 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT1 0x00000C74 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT2 0x00000C78 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_OB_BRLSHFT3 0x00000C7C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR1 0x00000CC0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR2 0x00000CC4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_OB_FINE_INTRPLTR3 0x00000CC8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR1 0x00000CCC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR2 0x00000CD0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_OB_FINE_INTRPLTR3 0x00000CD4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR1 0x00000CD8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR2 0x00000CDC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_OB_FINE_INTRPLTR3 0x00000CE0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR1 0x00000CE4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR2 0x00000CE8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_OB_FINE_INTRPLTR3 0x00000CEC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR1 0x00000CF0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR2 0x00000CF4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_OB_FINE_INTRPLTR3 0x00000CF8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR1 0x00000CFC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR2 0x00000D00 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_OB_FINE_INTRPLTR3 0x00000D04 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR1 0x00000D08 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR2 0x00000D0C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_OB_FINE_INTRPLTR3 0x00000D10 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR1 0x00000D14 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR2 0x00000D18 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_OB_FINE_INTRPLTR3 0x00000D1C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_CMD_INTRPLTR1 0x00000D70 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_CMD_INTRPLTR2 0x00000D74 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_CMD_INTRPLTR3 0x00000D78 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_CMD_INTRPLTR4 0x00000D7C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_CMD_INTRPLTR5 0x00000D80 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_CMD_INTRPLTR1 0x00000D84 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_CMD_INTRPLTR2 0x00000D88 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_CMD_INTRPLTR3 0x00000D8C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_CMD_INTRPLTR4 0x00000D90 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_CMD_INTRPLTR5 0x00000D94 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_CMD_BRLSHFT1 0x00000D98 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_CMD_BRLSHFT2 0x00000D9C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_CMD_BRLSHFT3 0x00000DA0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_CMD_BRLSHFT1 0x00000DA4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_CMD_BRLSHFT2 0x00000DA8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_CMD_BRLSHFT3 0x00000DAC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_QUSE_BRLSHFT 0x00000DB0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_QUSE_BRLSHFT 0x00000DB4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_QUSE_BRLSHFT_RANK1 0x00000EE4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_QUSE_BRLSHFT_RANK1 0x00000EE8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_PRIV_CMD 0x00000D28 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_PRIV_CMD 0x00000D2C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_PAD_CTRL 0x00000D30 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_WCK_CLK_PAD_CTRL 0x00000D34 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_BYTE_PAD_CTRL0 0x00000D38 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_BYTE_PAD_CTRL2 0x00000D40 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_RX_DFE1 0x00000DB8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_RX_DFE2 0x00000DBC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_RX_DFE1 0x00000DC0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_RX_DFE2 0x00000DC4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_RX_DFE1 0x00000DC8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_RX_DFE2 0x00000DCC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_RX_DFE1 0x00000DD0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_RX_DFE2 0x00000DD4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_RX_DFE1 0x00000DD8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_RX_DFE2 0x00000DDC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_RX_DFE1 0x00000DE0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_RX_DFE2 0x00000DE4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_RX_DFE1 0x00000DE8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_RX_DFE2 0x00000DEC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_RX_DFE1 0x00000DF0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_RX_DFE2 0x00000DF4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL1 0x000005A0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_TX_E_PREEMPH_LEVEL2 0x000005A4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL1 0x000005A8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_TX_E_PREEMPH_LEVEL2 0x000005AC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL1 0x000005B0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_TX_E_PREEMPH_LEVEL2 0x000005B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL1 0x000005B8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_TX_E_PREEMPH_LEVEL2 0x000005BC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL1 0x000005C0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_TX_E_PREEMPH_LEVEL2 0x000005C4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL1 0x000005C8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_TX_E_PREEMPH_LEVEL2 0x000005CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL1 0x000005D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_TX_E_PREEMPH_LEVEL2 0x000005D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL1 0x000005D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_TX_E_PREEMPH_LEVEL2 0x000005DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_BYTE_TX_E_PREEMPH_CTRL 0x000005E0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_TX_E_PREEMPH_CTRL 0x000005E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_PAD_CTRL_MISC 0x00000D44 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_PAD_CTRL_MISC1 0x00000D48 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_IREF_BYTE_RX_CTRL 0x00000EB0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_IREF_BYTE_INTERP_CTRL 0x00000EB4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_IREF_CMD_CTRL 0x00000EB8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_IREF_WCK_CTRL 0x00000EBC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_IREF_WCK_INTERP_CTRL 0x00000ED0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VTT_CNTL 0x00000EC4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VTT_CNTL2 0x00000EC8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VTT_CNTL3 0x00000EEC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VTT_CNTL4 0x00000EF0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VTT_CNTL5 0x00000EF4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_MDDLL_CNTL 0x00000EF8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_MISC_CONFIG 0x00000ECC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CML_CLK2 0x00000ED4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG0 0x00001004 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_SPARE_1 0x00001008 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_SPARE_2 0x0000100C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_PWR_CTRL 0x00001010 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_BLCG_CTRL 0x00001014 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CMD_CFG 0x00001018 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_FABRIC_PARITY 0x00001020 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CMD_FABRIC_PARITY 0x00001024 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD0 0x0000103C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD1 0x00001040 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL0_DWORD0_PWRD2 0x00001044 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD0 0x00001048 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD1 0x0000104C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL0_DWORD1_PWRD2 0x00001050 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD0 0x00001054 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD1 0x00001058 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL0_DWORD2_PWRD2 0x0000105C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD0 0x00001060 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD1 0x00001064 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL0_DWORD3_PWRD2 0x00001068 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD0 0x0000106C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD1 0x00001070 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL1_DWORD0_PWRD2 0x00001074 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD0 0x00001078 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD1 0x0000107C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL1_DWORD1_PWRD2 0x00001080 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD0 0x00001084 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD1 0x00001088 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL1_DWORD2_PWRD2 0x0000108C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD0 0x00001090 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD1 0x00001094 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL1_DWORD3_PWRD2 0x00001098 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD0 0x0000109C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD1 0x000010A0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD2 0x000010A4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG2_CHANNEL0_DWORD0_BRICK 0x000010A8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG2_CHANNEL0_DWORD1_BRICK 0x000010AC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG2_CHANNEL0_DWORD2_BRICK 0x000010B0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG2_CHANNEL0_DWORD3_BRICK 0x000010B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG2_CHANNEL1_DWORD0_BRICK 0x000010B8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG2_CHANNEL1_DWORD1_BRICK 0x000010BC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG2_CHANNEL1_DWORD2_BRICK 0x000010C0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG2_CHANNEL1_DWORD3_BRICK 0x000010C4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG2_CHANNEL_CMD_BRICK 0x000010C8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG3_BRICK_SPARE 0x000010CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG4_BRICK_SPARE 0x000010D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG5_BRICK_SPARE 0x000010D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD0_WL_DDLL 0x000010D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD0_TX_DDLL 0x000010DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD0_RX_DDLL 0x000010E0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD1_WL_DDLL 0x000010E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD1_TX_DDLL 0x000010E8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD1_RX_DDLL 0x000010EC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD2_WL_DDLL 0x000010F0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD2_TX_DDLL 0x000010F4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD2_RX_DDLL 0x000010F8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD3_WL_DDLL 0x000010FC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD3_TX_DDLL 0x00001100 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD3_RX_DDLL 0x00001104 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD0_WL_DDLL 0x00001108 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD0_TX_DDLL 0x0000110C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD0_RX_DDLL 0x00001110 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD1_WL_DDLL 0x00001114 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD1_TX_DDLL 0x00001118 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD1_RX_DDLL 0x0000111C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD2_WL_DDLL 0x00001120 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD2_TX_DDLL 0x00001124 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD2_RX_DDLL 0x00001128 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD3_WL_DDLL 0x0000112C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD3_TX_DDLL 0x00001130 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD3_RX_DDLL 0x00001134 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL_CMD_WL_DDLL 0x00001138 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL_CMD_TX_DDLL 0x0000113C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL_CMD_RX_DDLL 0x00001140 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD0_DDLLCAL 0x00001144 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD1_DDLLCAL 0x00001148 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD2_DDLLCAL 0x0000114C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD3_DDLLCAL 0x00001150 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL_CMD_DDLLCAL 0x00001154 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_DDLLCAL_CTRL 0x00001158 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_DDLLCAL_CTRL1 0x000011DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEUP 0x00001160 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEUP 0x00001164 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEUP 0x00001168 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEUP 0x0000116C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEUP 0x00001170 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEUP 0x00001174 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEUP 0x00001178 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEUP 0x0000117C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEUP 0x00001180 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL0_DWORD0_DRIVEDN 0x00001184 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL0_DWORD1_DRIVEDN 0x00001188 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL0_DWORD2_DRIVEDN 0x0000118C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL0_DWORD3_DRIVEDN 0x00001190 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL1_DWORD0_DRIVEDN 0x00001194 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL1_DWORD1_DRIVEDN 0x00001198 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL1_DWORD2_DRIVEDN 0x0000119C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL1_DWORD3_DRIVEDN 0x000011A0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CAL_CHANNEL_CMD_DRIVEDN 0x000011A4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALCFG 0x000011A8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD0 0x000011B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD1 0x000011B8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD2 0x000011BC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_LINK_REPAIR_CHANNEL0_DWORD3 0x000011C0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD0 0x000011C4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD1 0x000011C8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD2 0x000011CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_LINK_REPAIR_CHANNEL1_DWORD3 0x000011D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CMD_LINK_REPAIR 0x000011D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG1_CHANNEL_CMD_PWRD3 0x000011D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD0_DEBUG 0x000011FC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD1_DEBUG 0x00001200 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD2_DEBUG 0x00001204 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL0_DWORD3_DEBUG 0x00001208 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD0_DEBUG 0x0000120C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD1_DEBUG 0x00001210 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD2_DEBUG 0x00001214 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD3_DEBUG 0x00001218 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL_CMD_DEBUG 0x0000121C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_DELAY_BROADCAST_MISC0 0x00001224 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_DELAY_BROADCAST_MISC1 0x00001228 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_DONT_USE1 0x00001030 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_DONT_USE2 0x00001034 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_DONT_USE3 0x00001038 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD0_DDLLCAL 0x000012C4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD1_DDLLCAL 0x000012C8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD2_DDLLCAL 0x000012CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CHANNEL1_DWORD3_DDLLCAL 0x000012D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG6_BRICK_SPARE 0x000012D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG7_BRICK_SPARE 0x000012D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG8_BRICK_SPARE 0x000012DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG9_BRICK_SPARE 0x000012F4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG10_BRICK_SPARE 0x000012E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG11_BRICK_SPARE 0x000012E8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_VREF_CODE1 0x00001700 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_VREF_CODE2 0x00001704 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_VREF_CODE3 0x00001708 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_VREF_CODE1 0x0000170C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_VREF_CODE2 0x00001710 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_VREF_CODE3 0x00001714 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_VREF_CODE1 0x00001718 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_VREF_CODE2 0x0000171C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_VREF_CODE3 0x00001720 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_VREF_CODE1 0x00001724 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_VREF_CODE2 0x00001728 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_VREF_CODE3 0x0000172C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_VREF_CODE1 0x00001730 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_VREF_CODE2 0x00001734 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_VREF_CODE3 0x00001738 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_VREF_CODE1 0x0000173C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_VREF_CODE2 0x00001740 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_VREF_CODE3 0x00001744 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_VREF_CODE1 0x00001748 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_VREF_CODE2 0x0000174C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_VREF_CODE3 0x00001750 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_VREF_CODE1 0x00001754 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_VREF_CODE2 0x00001758 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_VREF_CODE3 0x0000175C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE1 0x00001760 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE2 0x00001764 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_VREF_MID_CODE3 0x00001768 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE1 0x0000176C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE2 0x00001770 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_VREF_MID_CODE3 0x00001774 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE1 0x00001778 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE2 0x0000177C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_VREF_MID_CODE3 0x00001780 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE1 0x00001784 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE2 0x00001788 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_VREF_MID_CODE3 0x0000178C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE1 0x00001790 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE2 0x00001794 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_VREF_MID_CODE3 0x00001798 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE1 0x0000179C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE2 0x000017A0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_VREF_MID_CODE3 0x000017A4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE1 0x000017A8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE2 0x000017AC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_VREF_MID_CODE3 0x000017B0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE1 0x000017B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE2 0x000017B8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_VREF_MID_CODE3 0x000017BC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE1 0x000017C0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE2 0x000017C4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_VREF_UPPER_CODE3 0x000017C8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE1 0x000017CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE2 0x000017D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_VREF_UPPER_CODE3 0x000017D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE1 0x000017D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE2 0x000017DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_VREF_UPPER_CODE3 0x000017E0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE1 0x000017E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE2 0x000017E8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_VREF_UPPER_CODE3 0x000017EC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE1 0x000017F0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE2 0x000017F4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_VREF_UPPER_CODE3 0x000017F8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE1 0x000017FC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE2 0x00001800 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_VREF_UPPER_CODE3 0x00001804 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE1 0x00001808 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE2 0x0000180C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_VREF_UPPER_CODE3 0x00001810 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE1 0x00001814 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE2 0x00001818 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_VREF_UPPER_CODE3 0x0000181C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OFFSET1 0x00001860 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OFFSET2 0x00001864 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OFFSET3 0x00001868 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OFFSET1 0x0000186C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OFFSET2 0x00001870 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OFFSET3 0x00001874 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OFFSET1 0x00001878 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OFFSET2 0x0000187C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OFFSET3 0x00001880 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OFFSET1 0x00001884 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OFFSET2 0x00001888 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OFFSET3 0x0000188C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OFFSET1 0x00001890 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OFFSET2 0x00001894 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OFFSET3 0x00001898 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OFFSET1 0x0000189C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OFFSET2 0x000018A0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OFFSET3 0x000018A4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OFFSET1 0x000018A8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OFFSET2 0x000018AC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OFFSET3 0x000018B0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OFFSET1 0x000018B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OFFSET2 0x000018B8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OFFSET3 0x000018BC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP1 0x000018D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP2 0x000018D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP3 0x000018D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP1 0x000018DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP2 0x000018E0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP3 0x000018E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP1 0x000018E8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP2 0x000018EC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP3 0x000018F0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP1 0x000018F4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP2 0x000018F8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP3 0x000018FC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP1 0x00001900 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP2 0x00001904 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP3 0x00001908 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP1 0x0000190C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP2 0x00001910 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP3 0x00001914 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP1 0x00001918 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP2 0x0000191C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP3 0x00001920 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP1 0x00001924 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP2 0x00001928 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP3 0x0000192C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN1 0x00001930 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN2 0x00001934 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN3 0x00001938 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN1 0x0000193C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN2 0x00001940 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN3 0x00001944 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN1 0x00001948 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN2 0x0000194C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN3 0x00001950 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN1 0x00001954 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN2 0x00001958 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN3 0x0000195C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN1 0x00001960 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN2 0x00001964 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN3 0x00001968 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN1 0x0000196C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN2 0x00001970 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN3 0x00001974 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN1 0x00001978 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN2 0x0000197C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN3 0x00001980 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN1 0x00001984 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN2 0x00001988 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN3 0x0000198C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD1 0x00002600 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD2 0x00002604 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETP_ODD3 0x00002608 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD1 0x0000260C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD2 0x00002610 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETP_ODD3 0x00002614 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD1 0x00002618 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD2 0x0000261C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETP_ODD3 0x00002620 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD1 0x00002624 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD2 0x00002628 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETP_ODD3 0x0000262C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD1 0x00002630 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD2 0x00002634 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETP_ODD3 0x00002638 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD1 0x0000263C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD2 0x00002640 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETP_ODD3 0x00002644 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD1 0x00002648 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD2 0x0000264C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETP_ODD3 0x00002650 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD1 0x00002654 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD2 0x00002658 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETP_ODD3 0x0000265C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD1 0x00002660 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD2 0x00002664 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETN_ODD3 0x00002668 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD1 0x0000266C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD2 0x00002670 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETN_ODD3 0x00002674 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD1 0x00002678 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD2 0x0000267C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETN_ODD3 0x00002680 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD1 0x00002684 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD2 0x00002688 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETN_ODD3 0x0000268C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD1 0x00002690 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD2 0x00002694 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETN_ODD3 0x00002698 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD1 0x0000269C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD2 0x000026A0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETN_ODD3 0x000026A4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD1 0x000026A8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD2 0x000026AC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETN_ODD3 0x000026B0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD1 0x000026B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD2 0x000026B8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETN_ODD3 0x000026BC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU1 0x000026C0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU2 0x000026C4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU3 0x000026C8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU1 0x000026CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU2 0x000026D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU3 0x000026D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU1 0x000026D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU2 0x000026DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU3 0x000026E0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU1 0x000026E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU2 0x000026E8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU3 0x000026EC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU1 0x000026F0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU2 0x000026F4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU3 0x000026F8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU1 0x000026FC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU2 0x00002700 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU3 0x00002704 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU1 0x00002708 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU2 0x0000270C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU3 0x00002710 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU1 0x00002714 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU2 0x00002718 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU3 0x0000271C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD1 0x00002720 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD2 0x00002724 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_OC_OFFSETU_ODD3 0x00002728 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD1 0x0000272C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD2 0x00002730 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_OC_OFFSETU_ODD3 0x00002734 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD1 0x00002738 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD2 0x0000273C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_OC_OFFSETU_ODD3 0x00002740 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD1 0x00002744 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD2 0x00002748 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_OC_OFFSETU_ODD3 0x0000274C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD1 0x00002750 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD2 0x00002754 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_OC_OFFSETU_ODD3 0x00002758 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD1 0x0000275C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD2 0x00002760 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_OC_OFFSETU_ODD3 0x00002764 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD1 0x00002768 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD2 0x0000276C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_OC_OFFSETU_ODD3 0x00002770 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD1 0x00002774 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD2 0x00002778 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_OC_OFFSETU_ODD3 0x0000277C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_WCK_DDLLCAL_LT 0x000027A0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_WCKB_DDLLCAL_LT 0x000027A4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_WCK_DDLLCAL_LT 0x000027A8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_WCKB_DDLLCAL_LT 0x000027AC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CK_DDLLCAL_LT 0x000027B0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_DFE_CTRL1 0x00001990 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_DFE_CTRL2 0x00001994 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_DFE_CTRL3 0x00001998 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_DFE_CTRL1 0x0000199C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_DFE_CTRL2 0x000019A0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_DFE_CTRL3 0x000019A4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_DFE_CTRL1 0x000019A8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_DFE_CTRL2 0x000019AC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_DFE_CTRL3 0x000019B0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_DFE_CTRL1 0x000019B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_DFE_CTRL2 0x000019B8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_DFE_CTRL3 0x000019BC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_DFE_CTRL1 0x000019C0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_DFE_CTRL2 0x000019C4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_DFE_CTRL3 0x000019C8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_DFE_CTRL1 0x000019CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_DFE_CTRL2 0x000019D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_DFE_CTRL3 0x000019D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_DFE_CTRL1 0x000019D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_DFE_CTRL2 0x000019DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_DFE_CTRL3 0x000019E0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_DFE_CTRL1 0x000019E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_DFE_CTRL2 0x000019E8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_DFE_CTRL3 0x000019EC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_LOWER_DFE_CTRL1 0x00001FC0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_LOWER_DFE_CTRL1 0x00001FC4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_LOWER_DFE_CTRL1 0x00001FC8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_LOWER_DFE_CTRL1 0x00001FCC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_LOWER_DFE_CTRL1 0x00001FD0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_LOWER_DFE_CTRL1 0x00001FD4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_LOWER_DFE_CTRL1 0x00001FD8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_LOWER_DFE_CTRL1 0x00001FDC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_MID_DFE_CTRL1 0x00001FE0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_MID_DFE_CTRL1 0x00001FE4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_MID_DFE_CTRL1 0x00001FE8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_MID_DFE_CTRL1 0x00001FEC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_MID_DFE_CTRL1 0x00001FF0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_MID_DFE_CTRL1 0x00001FF4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_MID_DFE_CTRL1 0x00001FF8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_MID_DFE_CTRL1 0x00001FFC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_UPPER_DFE_CTRL1 0x00001820 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_UPPER_DFE_CTRL1 0x00001824 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_UPPER_DFE_CTRL1 0x00001828 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_UPPER_DFE_CTRL1 0x0000182C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_UPPER_DFE_CTRL1 0x00001830 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_UPPER_DFE_CTRL1 0x00001834 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_UPPER_DFE_CTRL1 0x00001838 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_UPPER_DFE_CTRL1 0x0000183C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_OFFSET_CAL_CTRL 0x00001A00 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VREF_MISC_CTRL 0x00001A04 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_OFFSET_CAL_STATUS 0x00001A10 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_OFFSET_CAL_STATUS 0x00001A14 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_OFFSET_CAL_STATUS 0x00001A18 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_OFFSET_CAL_STATUS 0x00001A1C /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_OFFSET_CAL_STATUS 0x00001A20 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_OFFSET_CAL_STATUS 0x00001A24 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_OFFSET_CAL_STATUS 0x00001A28 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_OFFSET_CAL_STATUS 0x00001A2C /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_LSB 0x00001A30 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_RANK0_QUSE_DDLL_MSB 0x00001A34 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_LSB 0x00001A38 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_RANK1_QUSE_DDLL_MSB 0x00001A3C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_LSB 0x00001A40 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_RANK0_QUSE_DDLL_MSB 0x00001A44 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_LSB 0x00001A48 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_RANK1_QUSE_DDLL_MSB 0x00001A4C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_LSB 0x00001A50 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_RANK0_OB_DQS_DDLL_MSB 0x00001A54 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_LSB 0x00001A58 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_RANK1_OB_DQS_DDLL_MSB 0x00001A5C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_LSB 0x00001A60 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_RANK0_OB_DQS_DDLL_MSB 0x00001A64 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_LSB 0x00001A68 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_RANK1_OB_DQS_DDLL_MSB 0x00001A6C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_LSB 0x00001A70 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_RANK0_IB_DQS_DDLL_MSB 0x00001A74 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_LSB 0x00001A78 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_RANK1_IB_DQS_DDLL_MSB 0x00001A7C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_LSB 0x00001A80 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_RANK0_IB_DQS_DDLL_MSB 0x00001A84 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_LSB 0x00001A88 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_RANK1_IB_DQS_DDLL_MSB 0x00001A8C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_LSB 0x00001A90 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_LSB 0x00001A94 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_LSB 0x00001A98 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_LSB 0x00001A9C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_LSB 0x00001AA0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_LSB 0x00001AA4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_LSB 0x00001AA8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_LSB 0x00001AAC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_LSB 0x00001AB0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_LSB 0x00001AB4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_LSB 0x00001AB8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_LSB 0x00001ABC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_LSB 0x00001AC0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_LSB 0x00001AC4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_LSB 0x00001AC8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_LSB 0x00001ACC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_LSB 0x00001AD0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_LSB 0x00001AD4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_LSB 0x00001AD8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_LSB 0x00001ADC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_LSB 0x00001AE0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_LSB 0x00001AE4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_LSB 0x00001AE8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_LSB 0x00001AEC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_LSB 0x00001AF0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_LSB 0x00001AF4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_LSB 0x00001AF8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_LSB 0x00001AFC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_LSB 0x00001B00 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_LSB 0x00001B04 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_LSB 0x00001B08 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_LSB 0x00001B0C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_LSB 0x00001B10 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_LSB 0x00001B14 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_LSB 0x00001B18 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_LSB 0x00001B1C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_LSB 0x00001B20 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_LSB 0x00001B24 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_LSB 0x00001B28 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_LSB 0x00001B2C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_LSB 0x00001B30 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_LSB 0x00001B34 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_LSB 0x00001B38 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_LSB 0x00001B3C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_LSB 0x00001B40 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_LSB 0x00001B44 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_LSB 0x00001B48 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_LSB 0x00001B4C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL0_MSB 0x00001B50 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL1_MSB 0x00001B54 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK0_OB_DQ_DDLL2_MSB 0x00001B58 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL0_MSB 0x00001B5C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL1_MSB 0x00001B60 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK0_OB_DQ_DDLL2_MSB 0x00001B64 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL0_MSB 0x00001B68 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL1_MSB 0x00001B6C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK0_OB_DQ_DDLL2_MSB 0x00001B70 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL0_MSB 0x00001B74 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL1_MSB 0x00001B78 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK0_OB_DQ_DDLL2_MSB 0x00001B7C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL0_MSB 0x00001B80 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL1_MSB 0x00001B84 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK0_OB_DQ_DDLL2_MSB 0x00001B88 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL0_MSB 0x00001B8C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL1_MSB 0x00001B90 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK0_OB_DQ_DDLL2_MSB 0x00001B94 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL0_MSB 0x00001B98 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL1_MSB 0x00001B9C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK0_OB_DQ_DDLL2_MSB 0x00001BA0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL0_MSB 0x00001BA4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL1_MSB 0x00001BA8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK0_OB_DQ_DDLL2_MSB 0x00001BAC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL0_MSB 0x00001BB0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL1_MSB 0x00001BB4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_OB_DQ_DDLL2_MSB 0x00001BB8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL0_MSB 0x00001BBC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL1_MSB 0x00001BC0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_OB_DQ_DDLL2_MSB 0x00001BC4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL0_MSB 0x00001BC8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL1_MSB 0x00001BCC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_OB_DQ_DDLL2_MSB 0x00001BD0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL0_MSB 0x00001BD4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL1_MSB 0x00001BD8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_OB_DQ_DDLL2_MSB 0x00001BDC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL0_MSB 0x00001BE0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL1_MSB 0x00001BE4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_OB_DQ_DDLL2_MSB 0x00001BE8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL0_MSB 0x00001BEC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL1_MSB 0x00001BF0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_OB_DQ_DDLL2_MSB 0x00001BF4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL0_MSB 0x00001BF8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL1_MSB 0x00001BFC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_OB_DQ_DDLL2_MSB 0x00001C00 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL0_MSB 0x00001C04 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL1_MSB 0x00001C08 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_OB_DQ_DDLL2_MSB 0x00001C0C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_LSB 0x00001C10 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_LSB 0x00001C14 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_LSB 0x00001C18 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_LSB 0x00001C1C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_LSB 0x00001C20 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_LSB 0x00001C24 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_LSB 0x00001C28 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_LSB 0x00001C2C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_LSB 0x00001C30 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_LSB 0x00001C34 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_LSB 0x00001C38 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_LSB 0x00001C3C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_LSB 0x00001C40 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_LSB 0x00001C44 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_LSB 0x00001C48 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_LSB 0x00001C4C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_LSB 0x00001C50 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_LSB 0x00001C54 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_LSB 0x00001C58 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_LSB 0x00001C5C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_LSB 0x00001C60 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_LSB 0x00001C64 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_LSB 0x00001C68 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_LSB 0x00001C6C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_LSB 0x00001C70 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_LSB 0x00001C74 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_LSB 0x00001C78 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_LSB 0x00001C7C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_LSB 0x00001C80 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_LSB 0x00001C84 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_LSB 0x00001C88 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_LSB 0x00001C8C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_LSB 0x00001C90 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_LSB 0x00001C94 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_LSB 0x00001C98 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_LSB 0x00001C9C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_LSB 0x00001CA0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_LSB 0x00001CA4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_LSB 0x00001CA8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_LSB 0x00001CAC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_LSB 0x00001CB0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_LSB 0x00001CB4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_LSB 0x00001CB8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_LSB 0x00001CBC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_LSB 0x00001CC0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_LSB 0x00001CC4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_LSB 0x00001CC8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_LSB 0x00001CCC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL0_MSB 0x00001CD0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL1_MSB 0x00001CD4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK0_IB_DQ_DDLL2_MSB 0x00001CD8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL0_MSB 0x00001CDC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL1_MSB 0x00001CE0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK0_IB_DQ_DDLL2_MSB 0x00001CE4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL0_MSB 0x00001CE8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL1_MSB 0x00001CEC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK0_IB_DQ_DDLL2_MSB 0x00001CF0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL0_MSB 0x00001CF4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL1_MSB 0x00001CF8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK0_IB_DQ_DDLL2_MSB 0x00001CFC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL0_MSB 0x00001D00 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL1_MSB 0x00001D04 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK0_IB_DQ_DDLL2_MSB 0x00001D08 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL0_MSB 0x00001D0C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL1_MSB 0x00001D10 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK0_IB_DQ_DDLL2_MSB 0x00001D14 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL0_MSB 0x00001D18 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL1_MSB 0x00001D1C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK0_IB_DQ_DDLL2_MSB 0x00001D20 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL0_MSB 0x00001D24 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL1_MSB 0x00001D28 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK0_IB_DQ_DDLL2_MSB 0x00001D2C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL0_MSB 0x00001D30 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL1_MSB 0x00001D34 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_IB_DQ_DDLL2_MSB 0x00001D38 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL0_MSB 0x00001D3C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL1_MSB 0x00001D40 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_IB_DQ_DDLL2_MSB 0x00001D44 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL0_MSB 0x00001D48 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL1_MSB 0x00001D4C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_IB_DQ_DDLL2_MSB 0x00001D50 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL0_MSB 0x00001D54 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL1_MSB 0x00001D58 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_IB_DQ_DDLL2_MSB 0x00001D5C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL0_MSB 0x00001D60 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL1_MSB 0x00001D64 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_IB_DQ_DDLL2_MSB 0x00001D68 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL0_MSB 0x00001D6C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL1_MSB 0x00001D70 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_IB_DQ_DDLL2_MSB 0x00001D74 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL0_MSB 0x00001D78 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL1_MSB 0x00001D7C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_IB_DQ_DDLL2_MSB 0x00001D80 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL0_MSB 0x00001D84 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL1_MSB 0x00001D88 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_IB_DQ_DDLL2_MSB 0x00001D8C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT1 0x00001DA0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT2 0x00001DA4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE0_RANK1_OB_BRLSHFT3 0x00001DA8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT1 0x00001DAC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT2 0x00001DB0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE1_RANK1_OB_BRLSHFT3 0x00001DB4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT1 0x00001DB8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT2 0x00001DBC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE2_RANK1_OB_BRLSHFT3 0x00001DC0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT1 0x00001DC4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT2 0x00001DC8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0BYTE3_RANK1_OB_BRLSHFT3 0x00001DCC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT1 0x00001DD0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT2 0x00001DD4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE0_RANK1_OB_BRLSHFT3 0x00001DD8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT1 0x00001DDC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT2 0x00001DE0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE1_RANK1_OB_BRLSHFT3 0x00001DE4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT1 0x00001DE8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT2 0x00001DEC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE2_RANK1_OB_BRLSHFT3 0x00001DF0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT1 0x00001DF4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT2 0x00001DF8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1BYTE3_RANK1_OB_BRLSHFT3 0x00001DFC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE0_DDLLCAL 0x00001E00 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE1_DDLLCAL 0x00001E04 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE2_DDLLCAL 0x00001E08 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE3_DDLLCAL 0x00001E0C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE0_DDLLCAL 0x00001E10 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE1_DDLLCAL 0x00001E14 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE2_DDLLCAL 0x00001E18 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE3_DDLLCAL 0x00001E1C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_DDLLCAL_16FF 0x00001E20 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE0_DDLL_16FF 0x00001E24 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE1_DDLL_16FF 0x00001E28 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE2_DDLL_16FF 0x00001E2C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE3_DDLL_16FF 0x00001E30 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE0_DDLL_16FF 0x00001E34 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE1_DDLL_16FF 0x00001E38 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE2_DDLL_16FF 0x00001E3C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE3_DDLL_16FF 0x00001E40 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_DDLL_16FF 0x00001E44 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE0_E_PREMPH1 0x00001E48 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE0_E_PREMPH2 0x00001E4C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE1_E_PREMPH1 0x00001E50 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE1_E_PREMPH2 0x00001E54 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE2_E_PREMPH1 0x00001E58 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE2_E_PREMPH2 0x00001E5C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE3_E_PREMPH1 0x00001E60 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE3_E_PREMPH2 0x00001E64 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE0_E_PREMPH1 0x00001E68 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE0_E_PREMPH2 0x00001E6C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE1_E_PREMPH1 0x00001E70 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE1_E_PREMPH2 0x00001E74 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE2_E_PREMPH1 0x00001E78 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE2_E_PREMPH2 0x00001E7C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE3_E_PREMPH1 0x00001E80 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE3_E_PREMPH2 0x00001E84 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE0_E_TBB_PU 0x00001E88 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE1_E_TBB_PU 0x00001E8C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE2_E_TBB_PU 0x00001E90 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE3_E_TBB_PU 0x00001E94 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE0_E_TBB_PU 0x00001E98 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE1_E_TBB_PU 0x00001E9C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE2_E_TBB_PU 0x00001EA0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE3_E_TBB_PU 0x00001EA4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE0_E_TBB_PD 0x00001EA8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE1_E_TBB_PD 0x00001EAC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE2_E_TBB_PD 0x00001EB0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_BYTE3_E_TBB_PD 0x00001EB4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE0_E_TBB_PD 0x00001EB8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE1_E_TBB_PD 0x00001EBC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE2_E_TBB_PD 0x00001EC0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_BYTE3_E_TBB_PD 0x00001EC4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_BG_VTT 0x00001F30 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_WCK_CK2DQS_LSB 0x00001F4C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0_WCK_CK2DQS_MSB 0x00001F40 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_WCK_CK2DQS_LSB 0x00001F3C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1_WCK_CK2DQS_MSB 0x00001F44 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CK_CK2DQS 0x00001F48 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DDLLCAL_CTRL1 0x00001F50 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_DDLL_MSB_SUBP0_0 0x00002780 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_DDLL_MSB_SUBP0_1 0x00002784 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_DDLL_MSB_SUBP0_2 0x00002788 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_DDLL_MSB_SUBP0_3 0x0000278C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_DDLL_MSB_SUBP1_0 0x00002790 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_DDLL_MSB_SUBP1_1 0x00002794 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_DDLL_MSB_SUBP1_2 0x00002798 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_DDLL_MSB_SUBP1_3 0x0000279C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_EDC_TRACKING 0x00001F54 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VREF_TRACKING 0x00001F58 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VREF_TRACKING2 0x000027B4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VREF_TRACKING_READ1 0x000027B8 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VREF_TRACKING_READ2 0x000027BC /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW1 0x000027C8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_TRACKING_SHADOW2 0x000027CC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW1 0x000027D0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_TRACKING_SHADOW2 0x000027D4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW1 0x000027D8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_TRACKING_SHADOW2 0x000027DC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW1 0x000027E0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_TRACKING_SHADOW2 0x000027E4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW1 0x000027E8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_TRACKING_SHADOW2 0x000027EC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW1 0x000027F0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_TRACKING_SHADOW2 0x000027F4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW1 0x000027F8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_TRACKING_SHADOW2 0x000027FC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW1 0x00002800 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_TRACKING_SHADOW2 0x00002804 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_EDC_TRACKING_DEBUG 0x00001F5C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_EDC_TRACKING_DEBUG1 0x00001F60 /* R--4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE0_VREF_TRACKING1 0x00001F64 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE1_VREF_TRACKING1 0x00001F68 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE2_VREF_TRACKING1 0x00001F6C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP0BYTE3_VREF_TRACKING1 0x00001F70 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE0_VREF_TRACKING1 0x00001F74 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE1_VREF_TRACKING1 0x00001F78 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE2_VREF_TRACKING1 0x00001F7C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SUBP1BYTE3_VREF_TRACKING1 0x00001F80 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CFG14 0x00001F84 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HSDAC 0x00001F8C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_HSDAC0 0x000027C0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CMD_HSDAC1 0x000027C4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_BYTE_PAD_CTRL3_SUBP0 0x00001F90 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_BYTE_PAD_CTRL3_SUBP1 0x00001F94 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_WCK_CTRL_SDDRDQS 0x00001F98 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_INTERP_2UI 0x00001F9C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_CMD_INTRPLTR6 0x00001FA0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_CMD_INTRPLTR7 0x00001FA4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_CMD_INTRPLTR6 0x00001FA8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_CMD_INTRPLTR7 0x00001FAC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP0_CMD_BRLSHFT4 0x00001FB0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIOTRNG_SUBP1_CMD_BRLSHFT4 0x00001FB4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_EDC_TRACKING1 0x00001FB8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_SERIAL_PRIV_LEVEL_MASK 0x00003C7C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBMPLL_CFG 0x00003C90 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBMPLL_CTRL 0x00003C94 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBMPLL_COEFF 0x00003C98 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_TEST_MACRO 0x00003C9C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_BRICK_TEST 0x00003CA0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_BRICK_TEST_CFG 0x00003CA4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_BRICK_TEST_CFG1 0x00003CA8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_BRICK_TEST_PWRD1 0x00003CAC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_BRICK_TEST_PWRD2 0x00003CB0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG12_BRICK_SPARE 0x00003CCC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CFG13_BRICK_SPARE 0x00003CD0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_COMP_BRICK_CFG 0x00003CD4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_COMP_BRICK_CFG1 0x00003CD8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_COMP_BRICK_CFG2 0x00003CDC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBMPLL_CFG1 0x00003CE0 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_HBMCDB_CFG0 0x00003CE4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_HBMCDB_CFG1 0x00003CE8 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_COMP_CFG0 0x00003CEC /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBMPLL_CFG2 0x00003CF4 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_CFG 0x00003C00 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_CLAMP_MIN 0x00003C04 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_CLAMP_MAX 0x00003C08 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_SW_CTRL 0x00003C0C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_RB 0x00003C10 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_RB2 0x00003C14 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_RB3 0x00003C18 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_RB4 0x00003C1C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_RB5 0x00003C20 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_SLOPE_DRVR 0x00003C30 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_SLOPE_DRVR2 0x00003C34 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_SLOPE_DRVF 0x00003C38 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_SLOPE_DRVF2 0x00003C3C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_SLOPE_DRVT 0x00003C40 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_SLOPE_SLWR 0x00003C44 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_SLOPE_SLWF 0x00003C48 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_OFFSET_DRVR 0x00003C4C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_OFFSET_DRVR2 0x00003C50 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_OFFSET_DRVF 0x00003C54 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_OFFSET_DRVF2 0x00003C58 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_OFFSET_DRVT 0x00003C5C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_OFFSET_SLWR 0x00003C60 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_OFFSET_SLWF 0x00003C64 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_CFG2 0x00003C68 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_HBM_CALMASTER_CFG3 0x00003C6C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_REFMPLL_CONFIG 0x00003D00 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_REFMPLL_CTRL 0x00003D04 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_REFMPLL_CFG2 0x00003D08 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DRAMPLL_CONFIG 0x00003D20 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DRAMPLL_CTRL 0x00003D24 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_DRAMPLL_CFG2 0x00003D28 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VTT_CTRL0 0x00003D40 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VTT_CTRL1 0x00003D44 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CDBCTRL 0x00003D48 /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_CTRL_SER_PRIV 0x00003D4C /* RW-4R */
|
|
#define NV_PFB_FBPA_OFFSET_FBIO_VTT_CTRL2 0x00003D50 /* RW-4R */
|
|
|
|
|
|
#endif // __ga102_dev_fbpa_off_h__
|