229 lines
27 KiB
C
229 lines
27 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_fbif_v4_h__
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#define __ga102_dev_fbif_v4_h__
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/* This file is autogenerated. Do not edit */
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#define NV_FALCON_NVDEC_BASE 0x00848000
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#define NV_FALCON_NVDEC0_BASE 0x00848000
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#define NV_FALCON_NVDEC1_BASE 0x0084c000
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#define NV_FALCON_MSVLD_BASE 0x00084000
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#define NV_FALCON_MSPDEC_BASE 0x00085000
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#define NV_FALCON_MSPPP_BASE 0x00086000
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#define NV_FALCON_PWR_BASE 0x0010a000
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#define NV_FALCON_CE0_BASE 0x00104000
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#define NV_FALCON_CE1_BASE 0x00105000
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#define NV_FALCON_NVENC_BASE 0x001c8000
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK 0x00000070 /* RWI4R */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PFALCON_FBIF_TRANSCFG(i) (0x00000000+(i)*4) /* RW-4A */
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#define NV_PFALCON_FBIF_TRANSCFG__SIZE_1 8 /* */
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#define NV_PFALCON_FBIF_TRANSCFG__PRIV_LEVEL_MASK 0x00000070 /* */
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#define NV_PFALCON_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */
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#define NV_PFALCON_FBIF_TRANSCFG_TARGET_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_TRANSCFG_TARGET_LOCAL_FB 0x00000000 /* R---V */
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#define NV_PFALCON_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
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#define NV_PFALCON_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */
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#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
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#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0x00000000 /* R---V */
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#define NV_PFALCON_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
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#define NV_PFALCON_FBIF_TRANSCFG_L2C_WR 5:4 /* RWIVF */
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#define NV_PFALCON_FBIF_TRANSCFG_L2C_WR_INIT 0x00000001 /* RWI-V */
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#define NV_PFALCON_FBIF_TRANSCFG_L2C_WR_L2_EVICT_FIRST 0x00000000 /* R---V */
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#define NV_PFALCON_FBIF_TRANSCFG_L2C_WR_L2_EVICT_NORMAL 0x00000001 /* R---V */
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#define NV_PFALCON_FBIF_TRANSCFG_L2C_WR_L2_EVICT_LAST 0x00000002 /* R---V */
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#define NV_PFALCON_FBIF_TRANSCFG_L2C_RD 9:8 /* RWIVF */
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#define NV_PFALCON_FBIF_TRANSCFG_L2C_RD_INIT 0x00000001 /* RWI-V */
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#define NV_PFALCON_FBIF_TRANSCFG_L2C_RD_L2_EVICT_FIRST 0x00000000 /* R---V */
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#define NV_PFALCON_FBIF_TRANSCFG_L2C_RD_L2_EVICT_NORMAL 0x00000001 /* R---V */
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#define NV_PFALCON_FBIF_TRANSCFG_L2C_RD_L2_EVICT_LAST 0x00000002 /* R---V */
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#define NV_PFALCON_FBIF_TRANSCFG_WACHK0 12:12 /* RWIVF */
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#define NV_PFALCON_FBIF_TRANSCFG_WACHK0_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_TRANSCFG_WACHK0_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_TRANSCFG_WACHK0_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_TRANSCFG_WACHK1 13:13 /* RWIVF */
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#define NV_PFALCON_FBIF_TRANSCFG_WACHK1_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_TRANSCFG_WACHK1_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_TRANSCFG_WACHK1_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_TRANSCFG_RACHK0 14:14 /* RWIVF */
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#define NV_PFALCON_FBIF_TRANSCFG_RACHK0_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_TRANSCFG_RACHK0_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_TRANSCFG_RACHK0_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_TRANSCFG_RACHK1 15:15 /* RWIVF */
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#define NV_PFALCON_FBIF_TRANSCFG_RACHK1_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_TRANSCFG_RACHK1_ENABLE 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_TRANSCFG_RACHK1_DISABLE 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_TRANSCFG_ENGINE_ID_FLAG 16:16 /* RWIVF */
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#define NV_PFALCON_FBIF_TRANSCFG_ENGINE_ID_FLAG_BAR2_FN0 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_TRANSCFG_ENGINE_ID_FLAG_OWN 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_INSTBLK 0x00000020 /* R--4R */
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#define NV_PFALCON_FBIF_INSTBLK_PTR 27:0 /* R--VF */
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#define NV_PFALCON_FBIF_INSTBLK_TARGET 29:28 /* R--VF */
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#define NV_PFALCON_FBIF_INSTBLK_TARGET_LOCAL_FB 0x00000000 /* R---V */
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#define NV_PFALCON_FBIF_INSTBLK_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
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#define NV_PFALCON_FBIF_INSTBLK_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */
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#define NV_PFALCON_FBIF_BIND_STATUS 0x00000028 /* R--4R */
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#define NV_PFALCON_FBIF_BIND_STATUS_STATUS 1:0 /* R-IVF */
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#define NV_PFALCON_FBIF_BIND_STATUS_STATUS_NOT_BIND 0x00000000 /* R-I-V */
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#define NV_PFALCON_FBIF_BIND_STATUS_STATUS_BOUND 0x00000002 /* R---V */
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#define NV_PFALCON_FBIF_BIND_STATUS_GFID 9:4 /* R--VF */
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#define NV_PFALCON_FBIF_BIND_STATUS_GFID_INIT 0x00000000 /* R---V */
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#define NV_PFALCON_FBIF_BIND_STATUS_ENGINE_ID 23:16 /* R--VF */
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#define NV_PFALCON_FBIF_CTL 0x00000024 /* RW-4R */
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#define NV_PFALCON_FBIF_CTL_FLUSH 0:0 /* RW-VF */
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#define NV_PFALCON_FBIF_CTL_FLUSH_SET 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_FLUSH_CLEAR 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_INVAL_CONTEXT 2:2 /* RW-VF */
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#define NV_PFALCON_FBIF_CTL_INVAL_CONTEXT_SET 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_INVAL_CONTEXT_CLEAR 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_CLR_BWCOUNT 3:3 /* RW-VF */
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#define NV_PFALCON_FBIF_CTL_CLR_BWCOUNT_SET 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_CLR_BWCOUNT_CLEAR 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_ENABLE 4:4 /* RWIVF */
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#define NV_PFALCON_FBIF_CTL_ENABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PFALCON_FBIF_CTL_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_CLR_IDLEWDERR 5:5 /* RW-VF */
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#define NV_PFALCON_FBIF_CTL_CLR_IDLEWDERR_SET 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_CLR_IDLEWDERR_CLEAR 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_RESET 6:6 /* RW-VF */
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#define NV_PFALCON_FBIF_CTL_RESET_SET 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_RESET_CLEAR 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
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#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_DISALLOW 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_IDLE 8:8 /* R--VF */
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#define NV_PFALCON_FBIF_CTL_IDLE_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FBIF_CTL_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FBIF_CTL_IDLEWDERR 9:9 /* R--VF */
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#define NV_PFALCON_FBIF_CTL_IDLEWDERR_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FBIF_CTL_IDLEWDERR_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FBIF_CTL_SRTOUT 10:10 /* R--VF */
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#define NV_PFALCON_FBIF_CTL_SRTOUT_TRUE 0x00000001 /* R---V */
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#define NV_PFALCON_FBIF_CTL_SRTOUT_FALSE 0x00000000 /* R---V */
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#define NV_PFALCON_FBIF_CTL_CLR_SRTOUT 11:11 /* RW-VF */
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#define NV_PFALCON_FBIF_CTL_CLR_SRTOUT_SET 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_CLR_SRTOUT_CLEAR 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_CTL_SRTOVAL 19:16 /* RWIVF */
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#define NV_PFALCON_FBIF_CTL_SRTOVAL_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_THROTTLE 0x0000002c /* RW-4R */
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#define NV_PFALCON_FBIF_THROTTLE_BUCKET_SIZE 11:0 /* RWIVF */
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#define NV_PFALCON_FBIF_THROTTLE_BUCKET_SIZE_INIT 0x00000064 /* RWI-V */
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#define NV_PFALCON_FBIF_THROTTLE_LEAK_COUNT 27:16 /* RWIVF */
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#define NV_PFALCON_FBIF_THROTTLE_LEAK_COUNT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_THROTTLE_LEAK_SIZE 31:30 /* RWIVF */
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#define NV_PFALCON_FBIF_THROTTLE_LEAK_SIZE_16B 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_THROTTLE_LEAK_SIZE_32B 0x00000001 /* RW--V */
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#define NV_PFALCON_FBIF_THROTTLE_LEAK_SIZE_64B 0x00000002 /* RWI-V */
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#define NV_PFALCON_FBIF_THROTTLE_LEAK_SIZE_128B 0x00000003 /* RW--V */
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#define NV_PFALCON_FBIF_REGIONCFG 0x0000006c /* RW-4R */
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#define NV_PFALCON_FBIF_REGIONCFG__PRIV_LEVEL_MASK 0x00000070 /* */
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#define NV_PFALCON_FBIF_REGIONCFG_T0 3:0 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_T0_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_REGIONCFG_T1 7:4 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_T1_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_REGIONCFG_T2 11:8 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_T2_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_REGIONCFG_T3 15:12 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_T3_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_REGIONCFG_T4 19:16 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_T4_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_REGIONCFG_T5 23:20 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_T5_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_REGIONCFG_T6 27:24 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_T6_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_REGIONCFG_T7 31:28 /* RWIVF */
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#define NV_PFALCON_FBIF_REGIONCFG_T7_INIT 0x00000000 /* RWI-V */
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#define NV_PFALCON_FBIF_CG1 0x00000074 /* RW-4R */
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#define NV_PFALCON_FBIF_CG1_SLCG 3:0 /* */
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#define NV_PFALCON_FBIF_CG1_SLCG_ENABLED 0 /* */
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#define NV_PFALCON_FBIF_CG1_SLCG_DISABLED 0xF /* */
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#define NV_PFALCON_FBIF_CG1_SLCG__PROD 0x0 /* */
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#define NV_PFALCON_FBIF_CG1_SLCG_MSD0 0:0 /* RWIVF */
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#define NV_PFALCON_FBIF_CG1_SLCG_MSD0_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_CG1_SLCG_MSD0_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FBIF_CG1_SLCG_MSD1 1:1 /* RWIVF */
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#define NV_PFALCON_FBIF_CG1_SLCG_MSD1_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_CG1_SLCG_MSD1_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FBIF_CG1_SLCG_FB0 2:2 /* RWIVF */
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#define NV_PFALCON_FBIF_CG1_SLCG_FB0_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_CG1_SLCG_FB0_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FBIF_CG1_SLCG_FB1 3:3 /* RWIVF */
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#define NV_PFALCON_FBIF_CG1_SLCG_FB1_ENABLED 0x00000000 /* RW--V */
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#define NV_PFALCON_FBIF_CG1_SLCG_FB1_DISABLED 0x00000001 /* RWI-V */
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#define NV_PFALCON_FBIF_ACHK_BLK(i) (0x00000030+(i)*8) /* RW-4A */
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#define NV_PFALCON_FBIF_ACHK_BLK__SIZE_1 2 /* */
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#define NV_PFALCON_FBIF_ACHK_BLK_ADDR 31:0 /* RW-VF */
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#define NV_PFALCON_FBIF_ACHK_CTL(i) (0x00000034+(i)*8) /* RW-4A */
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#define NV_PFALCON_FBIF_ACHK_CTL__SIZE_1 2 /* */
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#define NV_PFALCON_FBIF_ACHK_CTL_SIZE 4:0 /* RW-VF */
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#define NV_PFALCON_FBIF_ACHK_CTL_TYPE 6:6 /* RW-VF */
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#define NV_PFALCON_FBIF_ACHK_CTL_TYPE_INSIDE 0x00000000 /* R---V */
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#define NV_PFALCON_FBIF_ACHK_CTL_TYPE_OUTSIDE 0x00000001 /* R---V */
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#define NV_PFALCON_FBIF_ACHK_CTL_STATE 7:7 /* RW-VF */
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#define NV_PFALCON_FBIF_ACHK_CTL_STATE_DISABLE 0x00000000 /* R---V */
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#define NV_PFALCON_FBIF_ACHK_CTL_STATE_ENABLE 0x00000001 /* R---V */
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#define NV_PFALCON_FBIF_ACHK_CTL_COUNT 31:16 /* RW-VF */
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#define NV_PFALCON_FBIF_BW_ALLOC 0x0000004c /* RW-4R */
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#define NV_PFALCON_FBIF_BW_ALLOC_VAL 31:0 /* */
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#define NV_PFALCON_FBIF_BW_ALLOC_INT_RD 7:0 /* RW-VF */
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#define NV_PFALCON_FBIF_BW_ALLOC_INT_WR 15:8 /* RW-VF */
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#define NV_PFALCON_FBIF_BW_ALLOC_EXT_RD 23:16 /* RW-VF */
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#define NV_PFALCON_FBIF_BW_ALLOC_REQ_T 31:24 /* RW-VF */
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#endif // __ga102_dev_fbif_v4_h__
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