14867 lines
1.6 MiB
14867 lines
1.6 MiB
#define NV_PDISP_FE 0x00615FFF:0x00610000 /* RW--D */
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#define NV_PDISP_HEADS 8 /* */
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#define NV_PDISP_SORS 8 /* */
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#define NV_PDISP_DSIS 4 /* */
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#define NV_PDISP_MAX_HEAD 4 /* */
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#define NV_PDISP_MAX_DAC 0 /* */
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#define NV_PDISP_MAX_SOR 4 /* */
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#define NV_PDISP_MAX_PIOR 0 /* */
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#define NV_PDISP_CHANNELS 84 /* */
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#define NV_PDISP_CHN_NUM_CORE 0 /* */
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#define NV_PDISP_CHN_NUM_WIN(i) (1+(i)) /* */
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#define NV_PDISP_CHN_NUM_WIN__SIZE_1 32 /* */
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#define NV_PDISP_CHN_NUM_WINIM(i) (33+(i)) /* */
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#define NV_PDISP_CHN_NUM_WINIM__SIZE_1 32 /* */
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#define NV_PDISP_CHN_NUM_CURS(i) (73+(i)) /* */
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#define NV_PDISP_CHN_NUM_CURS__SIZE_1 8 /* */
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#define NV_PDISP_CHN_NUM_PCALC 82 /* */
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#define NV_PDISP_CHN_NUM_SUPERVISOR 83 /* */
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#define NV_PDISP_EXCEPT_CHN_NUM_CORE 0 /* */
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#define NV_PDISP_EXCEPT_CHN_NUM_WIN(i) (1+(i)) /* */
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#define NV_PDISP_EXCEPT_CHN_NUM_WIN__SIZE_1 32 /* */
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#define NV_PDISP_FE_CLASSES 0x00610000 /* R--4R */
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#define NV_PDISP_FE_CLASSES_HW_REV 3:0 /* R--UF */
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#define NV_PDISP_FE_CLASSES_API_REV 7:4 /* R--UF */
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#define NV_PDISP_FE_CLASSES_CLASS_REV 15:8 /* R--UF */
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#define NV_PDISP_FE_CLASSES_CLASS_ID 31:16 /* R--UF */
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#define NV_PDISP_FE_CLASSES_0 3329229840 /* */
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#define NV_PDISP_FE_INST_MEM0 0x00610010 /* RW-4R */
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#define NV_PDISP_FE_INST_MEM0_TARGET 1:0 /* RWIVF */
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#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_NVM 0x00000001 /* RW--V */
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#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_PCI 0x00000002 /* RW--V */
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#define NV_PDISP_FE_INST_MEM0_TARGET_PHYS_PCI_COHERENT 0x00000003 /* RW--V */
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#define NV_PDISP_FE_INST_MEM0_STATUS 3:3 /* RWIVF */
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#define NV_PDISP_FE_INST_MEM0_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_INST_MEM0_STATUS_INVALID 0x00000000 /* RW--V */
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#define NV_PDISP_FE_INST_MEM0_STATUS_VALID 0x00000001 /* RW--V */
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#define NV_PDISP_FE_INST_MEM1 0x00610014 /* RW-4R */
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#define NV_PDISP_FE_INST_MEM1_ADDR 30:0 /* RWIUF */
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#define NV_PDISP_FE_INST_MEM1_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_IP_VER 0x00610018 /* R--4R */
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#define NV_PDISP_FE_IP_VER_DEV 7:0 /* R--UF */
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#define NV_PDISP_FE_IP_VER_ECO 15:8 /* R--UF */
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#define NV_PDISP_FE_IP_VER_MINOR 23:16 /* R--UF */
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#define NV_PDISP_FE_IP_VER_MAJOR 31:24 /* R--UF */
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#define NV_PDISP_FE_IP_VER_0 67174400 /* */
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#define NV_PDISP_FE_ACQ_DELAY 0x00610040 /* RW-4R */
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#define NV_PDISP_FE_ACQ_DELAY_SEMA 7:0 /* RWIUF */
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#define NV_PDISP_FE_ACQ_DELAY_SEMA_INIT 0x0000000a /* RWI-V */
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#define NV_PDISP_FE_ACQ_DELAY_SEMA_10US 0x0000000a /* RW--V */
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#define NV_PDISP_FE_ACQ_DELAY_SYNCPT 15:8 /* RWIUF */
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#define NV_PDISP_FE_ACQ_DELAY_SYNCPT_INIT 0x0000000a /* RWI-V */
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#define NV_PDISP_FE_ACQ_DELAY_SYNCPT_10US 0x0000000a /* RW--V */
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#define NV_PDISP_FE_HW_SYS_CAP 0x00610060 /* R--4R */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD0_EXISTS 0:0 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD1_EXISTS 1:1 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD2_EXISTS 2:2 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD3_EXISTS 3:3 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD4_EXISTS 4:4 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD5_EXISTS 5:5 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD6_EXISTS 6:6 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD7_EXISTS 7:7 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR0_EXISTS 8:8 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR1_EXISTS 9:9 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR2_EXISTS 10:10 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR3_EXISTS 11:11 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR4_EXISTS 12:12 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR5_EXISTS 13:13 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR6_EXISTS 14:14 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR7_EXISTS 15:15 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB 0x00610064 /* R--4R */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW0_EXISTS 0:0 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW1_EXISTS 1:1 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW2_EXISTS 2:2 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW3_EXISTS 3:3 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW4_EXISTS 4:4 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW5_EXISTS 5:5 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW6_EXISTS 6:6 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW7_EXISTS 7:7 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW8_EXISTS 8:8 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW9_EXISTS 9:9 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW10_EXISTS 10:10 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW11_EXISTS 11:11 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW12_EXISTS 12:12 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW13_EXISTS 13:13 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW14_EXISTS 14:14 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW15_EXISTS 15:15 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW16_EXISTS 16:16 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW17_EXISTS 17:17 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW18_EXISTS 18:18 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW19_EXISTS 19:19 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW20_EXISTS 20:20 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW21_EXISTS 21:21 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW22_EXISTS 22:22 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW23_EXISTS 23:23 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW24_EXISTS 24:24 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW25_EXISTS 25:25 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW26_EXISTS 26:26 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW27_EXISTS 27:27 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW28_EXISTS 28:28 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW29_EXISTS 29:29 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW30_EXISTS 30:30 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW31_EXISTS 31:31 /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* R--VF */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_HW_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_HW_LOCK_PIN_CAP 0x00610068 /* R--4R */
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#define NV_PDISP_FE_HW_LOCK_PIN_CAP_FLIP_LOCK_PINS 3:0 /* R--UF */
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#define NV_PDISP_FE_HW_LOCK_PIN_CAP_SCAN_LOCK_PINS 7:4 /* R--UF */
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#define NV_PDISP_FE_HW_LOCK_PIN_CAP_STEREO_PINS 11:8 /* R--UF */
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#define NV_PDISP_FE_MISC_CONFIGA 0x00610074 /* R--4R */
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#define NV_PDISP_FE_MISC_CONFIGA_NUM_HEADS 3:0 /* R--UF */
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#define NV_PDISP_FE_MISC_CONFIGA_NUM_SORS 11:8 /* R--UF */
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#define NV_PDISP_FE_MISC_CONFIGA_NUM_WINDOWS 25:20 /* R--UF */
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#define NV_PDISP_FE_LOCK_CAPS 0x00610078 /* RWI4R */
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#define NV_PDISP_FE_LOCK_CAPS_LOCK 0:0 /* RWIVF */
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#define NV_PDISP_FE_LOCK_CAPS_LOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_LOCK_CAPS_LOCK_UNLOCKED 0x00000000 /* RW--V */
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#define NV_PDISP_FE_LOCK_CAPS_LOCK_LOCKED 0x00000001 /* RW--V */
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#define NV_PDISP_FE_TRAP(i) (0x00610360+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_TRAP__SIZE_1 32 /* */
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#define NV_PDISP_FE_TRAP_METHOD 13:2 /* RWIUF */
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#define NV_PDISP_FE_TRAP_METHOD_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_TRAP_CHN_NUM 22:16 /* RWIUF */
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#define NV_PDISP_FE_TRAP_CHN_NUM_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_TRAP_CHN_TYPE 22:16 /* RWIUF */
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#define NV_PDISP_FE_TRAP_CHN_TYPE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_TRAP_CHN_TYPE_CORE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_TRAP_CHN_TYPE_WIN 0x00000001 /* RW--V */
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#define NV_PDISP_FE_TRAP_CHN_TYPE_WRBK 0x00000002 /* RW--V */
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#define NV_PDISP_FE_TRAP_MODE 30:28 /* RWIVF */
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#define NV_PDISP_FE_TRAP_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_TRAP_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_TRAP_MODE_METHOD_CHANNEL 0x00000001 /* RW--V */
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#define NV_PDISP_FE_TRAP_MODE_METHOD_CHANNEL_TYPE 0x00000002 /* RW--V */
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#define NV_PDISP_FE_TRAP_MODE_ALL_CHANNEL 0x00000003 /* RW--V */
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#define NV_PDISP_FE_TRAP_MODE_ALL_CHANNEL_TYPE 0x00000004 /* RW--V */
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#define NV_PDISP_FE_ERRMASK(i) (0x006103E0+(i)*8) /* RW-4A */
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#define NV_PDISP_FE_ERRMASK__SIZE_1 32 /* */
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#define NV_PDISP_FE_ERRMASK_METHOD 13:2 /* RWIUF */
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#define NV_PDISP_FE_ERRMASK_METHOD_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_ERRMASK_CHN_MODE 16:16 /* RWIUF */
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#define NV_PDISP_FE_ERRMASK_CHN_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_ERRMASK_CHN_MODE_INSTANCE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_ERRMASK_CHN_MODE_TYPE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_ERRMASK_CHN_NUM 26:20 /* RWIUF */
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#define NV_PDISP_FE_ERRMASK_CHN_NUM_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_ERRMASK_CHN_TYPE 26:20 /* RWIUF */
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#define NV_PDISP_FE_ERRMASK_CHN_TYPE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_ERRMASK_CHN_TYPE_CORE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_ERRMASK_CHN_TYPE_WIN 0x00000001 /* RW--V */
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#define NV_PDISP_FE_ERRMASK_CHN_TYPE_WRBK 0x00000002 /* RW--V */
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#define NV_PDISP_FE_ERRMASK_MODE 31:29 /* RWIVF */
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#define NV_PDISP_FE_ERRMASK_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_ERRMASK_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_ERRMASK_MODE_ALL 0x00000001 /* RW--V */
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#define NV_PDISP_FE_ERRMASK_MODE_ALL_ARG 0x00000002 /* RW--V */
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#define NV_PDISP_FE_ERRMASK_MODE_ALL_STATE 0x00000003 /* RW--V */
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#define NV_PDISP_FE_ERRMASK_MODE_METHOD_ARG 0x00000004 /* RW--V */
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#define NV_PDISP_FE_ERRMASK_MODE_STATE_CODE 0x00000005 /* RW--V */
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#define NV_PDISP_FE_ERRMASKCODE(i) (0x006103E4+(i)*8) /* RW-4A */
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#define NV_PDISP_FE_ERRMASKCODE__SIZE_1 32 /* */
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#define NV_PDISP_FE_ERRMASKCODE_CODE 23:0 /* RWIUF */
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#define NV_PDISP_FE_ERRMASKCODE_CODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_ERRMASKCODE_CODE_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_ERRMASKCODE_MASK_SIZE 28:24 /* RWIUF */
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#define NV_PDISP_FE_ERRMASKCODE_MASK_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CORE 0x006104E0 /* RW-4R */
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#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION 0:0 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION_DEALLOCATE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_CONNECTION 1:1 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CORE_CONNECTION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CORE_CONNECTION_DISCONNECT 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_CONNECTION_CONNECT 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE 4:4 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_EFI 5:5 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CORE_EFI_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CORE_EFI_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_EFI_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF 9:9 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_SKIP_NOTIF_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_SKIP_SEMA 10:10 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CORE_SKIP_SEMA_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CORE_SKIP_SEMA_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_SKIP_SEMA_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK 11:11 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_ERRCHECK_WHEN_DISCONNECTED 12:12 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CORE_ERRCHECK_WHEN_DISCONNECTED_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CORE_ERRCHECK_WHEN_DISCONNECTED_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_ERRCHECK_WHEN_DISCONNECTED_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE 14:13 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN 15:15 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CORE_INTR_DURING_SHTDWN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN(i) (0x006104E4+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_CHNCTL_WIN__SIZE_1 32 /* */
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#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION 0:0 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION_DEALLOCATE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION 1:1 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_DISCONNECT 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_CONNECTION_CONNECT 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_IN_ORDER 2:2 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WIN_IN_ORDER_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WIN_IN_ORDER_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_IN_ORDER_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE 4:4 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT 6:6 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SYNCPOINT_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP 7:7 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_TIMESTAMP_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI 8:8 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_PI_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF 9:9 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_SKIP_NOTIF_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA 10:10 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_SKIP_SEMA_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK 11:11 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE 14:13 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WIN_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WINIM(i) (0x00610564+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_CHNCTL_WINIM__SIZE_1 32 /* */
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#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION 0:0 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION_DEALLOCATE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WINIM_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WINIM_CONNECTION 1:1 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WINIM_CONNECTION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WINIM_CONNECTION_DISCONNECT 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WINIM_CONNECTION_CONNECT 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE 4:4 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WINIM_PUTPTR_WRITE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK 11:11 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WINIM_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE 14:13 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_WINIM_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CURS(i) (0x00610604+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_CHNCTL_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION 0:0 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION_DEALLOCATE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CURS_ALLOCATION_ALLOCATE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO 4:4 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CURS_LOCK_PIO_FIFO_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK 11:11 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CURS_IGNORE_INTERLOCK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE 14:13 /* RWIVF */
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#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_ONLY 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CHNCTL_CURS_TRASH_MODE_TRASH_AND_ABORT 0x00000002 /* RW--V */
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#define NV_PDISP_FE_CHNSTATUS_CORE 0x00610630 /* R--4R */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE 3:0 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_READ_METHOD 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_REQ_METHOD_INFO 0x00000002 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_CHK_METHOD_INFO 0x00000003 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_CHK_CTXDMA 0x00000004 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_CTX_DMA_LOOKUP 0x00000005 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_WAIT_FOR_STG2 0x00000006 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_WAIT_FOR_UPD 0x00000007 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG1_STATE_EXCEPTION 0x00000008 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE 7:4 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_PUBLIC 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_MISC 0x00000002 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_LIMIT 0x00000003 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_BASE 0x00000004 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STG2_STATE_SEND_SETPARAMSCRSR 0x00000005 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE 20:16 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_DEALLOC_LIMBO 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT1 0x00000002 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_INIT2 0x00000003 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_VBIOS_OPERATION 0x00000004 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT1 0x00000005 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_INIT2 0x00000006 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_EFI_OPERATION 0x00000007 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_UNCONNECTED 0x00000008 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT1 0x00000009 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_INIT2 0x0000000A /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_IDLE 0x0000000B /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_BUSY 0x0000000C /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN1 0x0000000D /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATE_SHUTDOWN2 0x0000000E /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_FIRSTTIME 24:24 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CORE_FIRSTTIME_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_FIRSTTIME_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_FIRSTTIME_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_FIFO 25:25 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_FIFO_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_FIFO_EMPTY 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_FIFO_NOTEMPTY 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_READ_PENDING 26:26 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_READ_PENDING_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_READ_PENDING_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_READ_PENDING_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_NOTIF_WRITE_PENDING 27:27 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_NOTIF_WRITE_PENDING_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_NOTIF_WRITE_PENDING_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_NOTIF_WRITE_PENDING_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_SUBDEVICE_STATUS 29:29 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CORE_SUBDEVICE_STATUS_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_SUBDEVICE_STATUS_INACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_SUBDEVICE_STATUS_ACTIVE 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_QUIESCENT 30:30 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_QUIESCENT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_QUIESCENT_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_QUIESCENT_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_EXEC 31:31 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_EXEC_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_EXEC_IDLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CORE_STATUS_METHOD_EXEC_RUNNING 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN(i) (0x00610664+(i)*4) /* R--4A */
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#define NV_PDISP_FE_CHNSTATUS_WIN__SIZE_1 32 /* */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE 3:0 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_READ_METHOD 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_REQ_METHOD_INFO 0x00000002 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_CHK_METHOD_INFO 0x00000003 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_CHK_CTXDMA 0x00000004 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_CTX_DMA_LOOKUP 0x00000005 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_WAIT_FOR_STG2 0x00000006 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_WAIT_FOR_UPD 0x00000007 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG1_STATE_EXCEPTION 0x00000008 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE 7:4 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_PUBLIC 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_MISC 0x00000002 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_LIMIT 0x00000003 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_BASE 0x00000004 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STG2_STATE_SEND_WIN_SETCONFIG 0x00000005 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE 11:8 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_IDLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_BLOCK 0x00000002 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_MPI 0x00000003 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_ILK_PH_1 0x00000004 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_STATE_ERRCHK 0x00000005 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_RDY_TO_FLIP 0x00000006 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_ILK_PH_2 0x00000007 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_CHECK_PEND_LOADV 0x00000008 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_SEND_UPD 0x00000009 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_PRM 0x0000000a /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_EXCEPTION 0x0000000b /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_UPD_STATE_WAIT_ILK_ABORT 0x0000000c /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATE 19:16 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_DEALLOC 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_UNCONNECTED 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT1 0x00000002 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_INIT2 0x00000003 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_IDLE 0x00000004 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_BUSY 0x00000005 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN1 0x00000006 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATE_SHUTDOWN2 0x00000007 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_FIRSTTIME 24:24 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WIN_FIRSTTIME_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_FIRSTTIME_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_FIRSTTIME_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_FIFO 25:25 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_FIFO_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_FIFO_EMPTY 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_FIFO_NOTEMPTY 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_READ_PENDING 26:26 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_READ_PENDING_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_READ_PENDING_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_READ_PENDING_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_WRITE_PENDING 27:27 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_WRITE_PENDING_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_WRITE_PENDING_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_WRITE_PENDING_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_SUBDEVICE_STATUS 29:29 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WIN_SUBDEVICE_STATUS_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_SUBDEVICE_STATUS_INACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_SUBDEVICE_STATUS_ACTIVE 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_QUIESCENT 30:30 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_QUIESCENT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_QUIESCENT_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_QUIESCENT_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC 31:31 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC_IDLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WIN_STATUS_METHOD_EXEC_RUNNING 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM(i) (0x006106E4+(i)*4) /* R--4A */
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#define NV_PDISP_FE_CHNSTATUS_WINIM__SIZE_1 32 /* */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE 3:0 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_EXCEPT 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_SEND_PUBLIC 0x00000002 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_ILK1 0x00000003 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_FLIP 0x00000004 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_ILK2 0x00000005 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_LOADV 0x00000006 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_SEND_UPDATE 0x00000007 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_PRM 0x00000008 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_ILK_ABORT 0x00000009 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_MP_STATE_WAIT_BLOCK 0x0000000a /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE 19:16 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_DEALLOC 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_UNCONNECTED 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT1 0x00000002 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_INIT2 0x00000003 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_IDLE 0x00000004 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_BUSY 0x00000005 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN1 0x00000006 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATE_SHUTDOWN2 0x00000007 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_FIRSTTIME 24:24 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_FIRSTTIME_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_FIRSTTIME_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_FIRSTTIME_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_FIFO 25:25 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_FIFO_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_FIFO_EMPTY 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_FIFO_NOTEMPTY 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_READ_PENDING 26:26 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_READ_PENDING_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_READ_PENDING_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_READ_PENDING_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_WRITE_PENDING 27:27 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_WRITE_PENDING_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_WRITE_PENDING_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_WRITE_PENDING_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_SUBDEVICE_STATUS 29:29 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_SUBDEVICE_STATUS_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_SUBDEVICE_STATUS_INACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_SUBDEVICE_STATUS_ACTIVE 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_QUIESCENT 30:30 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_QUIESCENT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_QUIESCENT_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_QUIESCENT_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_EXEC 31:31 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_EXEC_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_EXEC_IDLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_WINIM_STATUS_METHOD_EXEC_RUNNING 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS(i) (0x00610784+(i)*4) /* R--4A */
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#define NV_PDISP_FE_CHNSTATUS_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE 3:0 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_PBERR 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_RSVD 0x00000002 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_SND_PUBLIC 0x00000003 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_WAIT_PUBLIC 0x00000004 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_ILK1_START 0x00000005 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_ILK1_WAIT 0x00000006 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_ILK2_START 0x00000007 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_ILK2_WAIT 0x00000008 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_CHECK_PEND_LOADV 0x00000009 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_SEND_UPD 0x0000000a /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_MP_STATE_WAIT_PRM 0x0000000b /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_FIRSTTIME 24:24 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CURS_FIRSTTIME_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_FIRSTTIME_NO 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_FIRSTTIME_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_STATE 18:16 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_DEALLOC 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_INIT1 0x00000002 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_IDLE 0x00000004 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_STATE_BUSY 0x00000005 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_STATUS_METHOD_EXEC 31:31 /* R-IVF */
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#define NV_PDISP_FE_CHNSTATUS_CURS_STATUS_METHOD_EXEC_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_STATUS_METHOD_EXEC_IDLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CHNSTATUS_CURS_STATUS_METHOD_EXEC_RUNNING 0x00000001 /* R---V */
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#define NV_PDISP_FE_SUPERVISOR_MAIN 0x006107A8 /* RW-4R */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_MODE_SWITCH 4:4 /* R--VF */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_MODE_SWITCH_NOT_IN_PROGRESS 0x00000000 /* R---V */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_MODE_SWITCH_IN_PROGRESS 0x00000001 /* R---V */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_SECOND_INT 24:24 /* RWIVF */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_SECOND_INT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_SECOND_INT_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_SECOND_INT_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_THIRD_INT 25:25 /* RWIVF */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_THIRD_INT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_THIRD_INT_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_SKIP_THIRD_INT_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART 31:31 /* RWIVF */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART_DONE 0x00000000 /* R---V */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_SUPERVISOR_MAIN_RESTART_TRIGGER 0x00000001 /* -W--V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD(i) (0x006107AC+(i)*4) /* RW-4A */
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|
#define NV_PDISP_FE_SUPERVISOR_HEAD__SIZE_1 8 /* */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_BLANK 8:8 /* R-IVF */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_BLANK_INIT 0x00000000 /* R-I-V */
|
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#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_BLANK_NO 0x00000000 /* R---V */
|
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#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_BLANK_YES 0x00000001 /* R---V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_BLANK 9:9 /* RWIVF */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_BLANK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_BLANK_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_BLANK_YES 0x00000001 /* RW--V */
|
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK 10:10 /* RWIVF */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_SHUTDOWN 12:12 /* R-IVF */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_SHUTDOWN_INIT 0x00000000 /* R-I-V */
|
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#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_SHUTDOWN_NO 0x00000000 /* R---V */
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|
#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_SHUTDOWN_YES 0x00000001 /* R---V */
|
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_SHUTDOWN 13:13 /* RWIVF */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_SHUTDOWN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_SHUTDOWN_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_SHUTDOWN_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOSHUTDOWN 14:14 /* RWIVF */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOSHUTDOWN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOSHUTDOWN_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOSHUTDOWN_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_CHANGE_VPLL 16:16 /* R-IVF */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_CHANGE_VPLL_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_CHANGE_VPLL_NO 0x00000000 /* R---V */
|
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#define NV_PDISP_FE_SUPERVISOR_HEAD_WILL_CHANGE_VPLL_YES 0x00000001 /* R---V */
|
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_CHANGE_VPLL 17:17 /* RWIVF */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_CHANGE_VPLL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_CHANGE_VPLL_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_CHANGE_VPLL_YES 0x00000001 /* RW--V */
|
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOCHANGE_VPLL 18:18 /* RWIVF */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOCHANGE_VPLL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOCHANGE_VPLL_NO 0x00000000 /* RW--V */
|
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOCHANGE_VPLL_YES 0x00000001 /* RW--V */
|
|
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_WAKEUP 20:20 /* RWIVF */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_WAKEUP_INIT 0x00000000 /* RWI-V */
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|
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_WAKEUP_NO 0x00000000 /* RW--V */
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|
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_WAKEUP_YES 0x00000001 /* RW--V */
|
|
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_SHUTDOWN 21:21 /* RWIVF */
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|
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_SHUTDOWN_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_SHUTDOWN_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SUPERVISOR_HEAD_FORCE_NOBLANK_SHUTDOWN_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PBBASEHI_REGBASE 0x00000b20 /* */
|
|
#define NV_PDISP_FE_PBBASE_REGBASE 0x00000b24 /* */
|
|
#define NV_PDISP_FE_PBSUBDEV_REGBASE 0x00000b28 /* */
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#define NV_PDISP_FE_PBCLIENT_REGBASE 0x00000b2c /* */
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#define NV_PDISP_FE_PBBASEHI(i) (0x00610B20+(i)*16) /* RW-4A */
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#define NV_PDISP_FE_PBBASEHI__SIZE_1 73 /* */
|
|
#define NV_PDISP_FE_PBBASEHI_PUSHBUFFER_ADDR 6:0 /* RWIUF */
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#define NV_PDISP_FE_PBBASEHI_PUSHBUFFER_ADDR_INIT 0x00000000 /* RWI-V */
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|
#define NV_PDISP_FE_PBBASE(i) (0x00610B24+(i)*16) /* RW-4A */
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|
#define NV_PDISP_FE_PBBASE__SIZE_1 73 /* */
|
|
#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET 1:0 /* RWIVF */
|
|
#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET_PHYS_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET_PHYS_NVM 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET_PHYS_PCI 0x00000002 /* RW--V */
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#define NV_PDISP_FE_PBBASE_PUSHBUFFER_TARGET_PHYS_PCI_COHERENT 0x00000003 /* RW--V */
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|
#define NV_PDISP_FE_PBBASE_PUSHBUFFER_ADDR 31:4 /* RWIUF */
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#define NV_PDISP_FE_PBBASE_PUSHBUFFER_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PBSUBDEV(i) (0x00610B28+(i)*16) /* RW-4A */
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|
#define NV_PDISP_FE_PBSUBDEV__SIZE_1 73 /* */
|
|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID 11:0 /* RWIVF */
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|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_INIT 0x00000001 /* RWI-V */
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|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_0 0x00000001 /* RW--V */
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|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_1 0x00000002 /* RW--V */
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|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_2 0x00000004 /* RW--V */
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|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_3 0x00000008 /* RW--V */
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|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_4 0x00000010 /* RW--V */
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|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_5 0x00000020 /* RW--V */
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|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_6 0x00000040 /* RW--V */
|
|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_7 0x00000080 /* RW--V */
|
|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_8 0x00000100 /* RW--V */
|
|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_9 0x00000200 /* RW--V */
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|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_10 0x00000400 /* RW--V */
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|
#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_11 0x00000800 /* RW--V */
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#define NV_PDISP_FE_PBSUBDEV_SUBDEVICE_ID_ALL 0x00000FFF /* RW--V */
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#define NV_PDISP_FE_PBCLIENT(i) (0x00610B2C+(i)*16) /* RW-4A */
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|
#define NV_PDISP_FE_PBCLIENT__SIZE_1 73 /* */
|
|
#define NV_PDISP_FE_PBCLIENT_CLIENT_ID 13:0 /* RWIUF */
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|
#define NV_PDISP_FE_PBCLIENT_CLIENT_ID_INIT 0x00000000 /* RWI-V */
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|
#define NV_PDISP_FE_PBBASEHI_CORE (0x00610B20+0*16) /* */
|
|
#define NV_PDISP_FE_PBBASE_CORE (0x00610B24+0*16) /* */
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#define NV_PDISP_FE_PBSUBDEV_CORE (0x00610B28+0*16) /* */
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#define NV_PDISP_FE_PBCLIENT_CORE (0x00610B2C+0*16) /* */
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#define NV_PDISP_FE_PBBASEHI_WIN(i) (0x00610B20+(1+(i))*16) /* */
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#define NV_PDISP_FE_PBBASEHI_WIN__SIZE_1 32 /* */
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|
#define NV_PDISP_FE_PBBASE_WIN(i) (0x00610B24+(1+(i))*16) /* */
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#define NV_PDISP_FE_PBBASE_WIN__SIZE_1 32 /* */
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#define NV_PDISP_FE_PBSUBDEV_WIN(i) (0x00610B28+(1+(i))*16) /* */
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#define NV_PDISP_FE_PBSUBDEV_WIN__SIZE_1 32 /* */
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#define NV_PDISP_FE_PBCLIENT_WIN(i) (0x00610B2C+(1+(i))*16) /* */
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#define NV_PDISP_FE_PBCLIENT_WIN__SIZE_1 32 /* */
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|
#define NV_PDISP_FE_PBBASEHI_WINIM(i) (0x00610B20+(33+(i))*16) /* */
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#define NV_PDISP_FE_PBBASEHI_WINIM__SIZE_1 32 /* */
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|
#define NV_PDISP_FE_PBBASE_WINIM(i) (0x00610B24+(33+(i))*16) /* */
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#define NV_PDISP_FE_PBBASE_WINIM__SIZE_1 32 /* */
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#define NV_PDISP_FE_PBSUBDEV_WINIM(i) (0x00610B28+(33+(i))*16) /* */
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#define NV_PDISP_FE_PBSUBDEV_WINIM__SIZE_1 32 /* */
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#define NV_PDISP_FE_PBCLIENT_WINIM(i) (0x00610B2C+(33+(i))*16) /* */
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#define NV_PDISP_FE_PBCLIENT_WINIM__SIZE_1 32 /* */
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#define NV_PDISP_FE_PBBASEHI_WRBK(i) (0x00610B20+(65+(i))*16) /* */
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#define NV_PDISP_FE_PBBASEHI_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_PBBASE_WRBK(i) (0x00610B24+(65+(i))*16) /* */
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#define NV_PDISP_FE_PBBASE_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_PBSUBDEV_WRBK(i) (0x00610B28+(65+(i))*16) /* */
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#define NV_PDISP_FE_PBSUBDEV_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_PBCLIENT_WRBK(i) (0x00610B2C+(65+(i))*16) /* */
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#define NV_PDISP_FE_PBCLIENT_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_EXCEPT(i) (0x00611020+(i)*12) /* RW-4A */
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#define NV_PDISP_FE_EXCEPT__SIZE_1 81 /* */
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#define NV_PDISP_FE_EXCEPT_METHOD_OFFSET 11:0 /* R--VF */
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#define NV_PDISP_FE_EXCEPT_METHOD_OFFSET_PBERR_INVALOP 0x00000000 /* R---V */
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#define NV_PDISP_FE_EXCEPT_METHOD_OFFSET_PBERR_PROTFAULT 0x00000000 /* R---V */
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#define NV_PDISP_FE_EXCEPT_REASON 14:12 /* R--VF */
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#define NV_PDISP_FE_EXCEPT_REASON_NONE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EXCEPT_REASON_PUSHBUFFER_ERR 0x00000001 /* R---V */
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#define NV_PDISP_FE_EXCEPT_REASON_TRAP 0x00000002 /* R---V */
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#define NV_PDISP_FE_EXCEPT_REASON_RESERVED_METHOD 0x00000003 /* R---V */
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#define NV_PDISP_FE_EXCEPT_REASON_INVALID_ARG 0x00000004 /* R---V */
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#define NV_PDISP_FE_EXCEPT_REASON_INVALID_STATE 0x00000005 /* R---V */
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#define NV_PDISP_FE_EXCEPT_REASON_UNRESOLVABLE_HANDLE 0x00000007 /* R---V */
|
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#define NV_PDISP_FE_EXCEPT_RESTART_MODE 29:28 /* RWIVF */
|
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#define NV_PDISP_FE_EXCEPT_RESTART_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_EXCEPT_RESTART_MODE_RESUME 0x00000000 /* RW--V */
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#define NV_PDISP_FE_EXCEPT_RESTART_MODE_SKIP 0x00000001 /* RW--V */
|
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#define NV_PDISP_FE_EXCEPT_RESTART_MODE_REPLAY 0x00000002 /* RW--V */
|
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#define NV_PDISP_FE_EXCEPT_RESTART 31:31 /* RWIVF */
|
|
#define NV_PDISP_FE_EXCEPT_RESTART_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_EXCEPT_RESTART_DONE 0x00000000 /* R---V */
|
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#define NV_PDISP_FE_EXCEPT_RESTART_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_EXCEPT_RESTART_TRIGGER 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_EXCEPTARG(i) (0x00611024+(i)*12) /* RW-4A */
|
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#define NV_PDISP_FE_EXCEPTARG__SIZE_1 41 /* */
|
|
#define NV_PDISP_FE_EXCEPTARG_RDARG 31:0 /* RWIVF */
|
|
#define NV_PDISP_FE_EXCEPTARG_RDARG_INIT 0x00000000 /* R-I-V */
|
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#define NV_PDISP_FE_EXCEPTARG_RDARG_PBERR_INVALOP 0x00000000 /* R---V */
|
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#define NV_PDISP_FE_EXCEPTARG_RDARG_PBERR_PROTFAULT 0x00000400 /* R---V */
|
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#define NV_PDISP_FE_EXCEPTARG_WRARG 31:0 /* -W-VF */
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#define NV_PDISP_FE_EXCEPTERR(i) (0x00611028+(i)*12) /* R--4A */
|
|
#define NV_PDISP_FE_EXCEPTERR__SIZE_1 41 /* */
|
|
#define NV_PDISP_FE_EXCEPTERR_CODE 23:0 /* R-IVF */
|
|
#define NV_PDISP_FE_EXCEPTERR_CODE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_EXCEPTERR_CODE_NONE 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_TIMEOUT 0x00611400 /* RW-4R */
|
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#define NV_PDISP_FE_TIMEOUT_BB_VALUE 7:0 /* RWIVF */
|
|
#define NV_PDISP_FE_TIMEOUT_BB_VALUE_INIT 0x00000064 /* RWI-V */
|
|
#define NV_PDISP_FE_TIMEOUT_BB_SCALE 11:8 /* RWIVF */
|
|
#define NV_PDISP_FE_TIMEOUT_BB_SCALE_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0 0x00611408 /* RW-4R */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_FE 0:0 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_FE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_FE_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_FE_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_FE_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB 1:1 /* RWIVF */
|
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#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_IHUB_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA 2:2 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_VGA_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC 3:3 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_SEC_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0 8:8 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD0_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1 9:9 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD1_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2 10:10 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD2_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3 11:11 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD3_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4 12:12 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD4_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5 13:13 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD5_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6 14:14 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD6_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7 15:15 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD7_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD(i) (8+(i)):(8+(i)) /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD__SIZE_1 8 /* */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_HEAD_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0 16:16 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR0_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1 17:17 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR1_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2 18:18 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR2_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3 19:19 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR3_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4 20:20 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR4_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5 21:21 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR5_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6 22:22 /* RWIVF */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6_INIT 0x00000000 /* R-I-V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR6_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7 23:23 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR7_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR(i) (16+(i)):(16+(i)) /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR__SIZE_1 8 /* */
|
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT0_SOR_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1 0x0061140C /* RW-4R */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0 0:0 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN0_UNLOCK 0x00000001 /* -W--V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1 1:1 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN1_UNLOCK 0x00000001 /* -W--V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2 2:2 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2_LOCKED 0x00000001 /* R---V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN2_UNLOCK 0x00000001 /* -W--V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3 3:3 /* RWIVF */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3_INIT 0x00000000 /* R-I-V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3_LOCKED 0x00000001 /* R---V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN3_UNLOCK 0x00000001 /* -W--V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4 4:4 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4_INIT 0x00000000 /* R-I-V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4_NORMAL 0x00000000 /* R---V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4_LOCKED 0x00000001 /* R---V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN4_UNLOCK 0x00000001 /* -W--V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5 5:5 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5_NORMAL 0x00000000 /* R---V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5_LOCKED 0x00000001 /* R---V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN5_UNLOCK 0x00000001 /* -W--V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6 6:6 /* RWIVF */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6_INIT 0x00000000 /* R-I-V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6_NORMAL 0x00000000 /* R---V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6_LOCKED 0x00000001 /* R---V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN6_UNLOCK 0x00000001 /* -W--V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7 7:7 /* RWIVF */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7_INIT 0x00000000 /* R-I-V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7_NORMAL 0x00000000 /* R---V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7_LOCKED 0x00000001 /* R---V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN7_UNLOCK 0x00000001 /* -W--V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8 8:8 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8_INIT 0x00000000 /* R-I-V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN8_UNLOCK 0x00000001 /* -W--V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9 9:9 /* RWIVF */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9_INIT 0x00000000 /* R-I-V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9_NORMAL 0x00000000 /* R---V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9_LOCKED 0x00000001 /* R---V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN9_UNLOCK 0x00000001 /* -W--V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10 10:10 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN10_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11 11:11 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN11_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12 12:12 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN12_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13 13:13 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN13_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14 14:14 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN14_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15 15:15 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN15_UNLOCK 0x00000001 /* -W--V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16 16:16 /* RWIVF */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16_LOCKED 0x00000001 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN16_UNLOCK 0x00000001 /* -W--V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17 17:17 /* RWIVF */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17_LOCKED 0x00000001 /* R---V */
|
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN17_UNLOCK 0x00000001 /* -W--V */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18 18:18 /* RWIVF */
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|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18_LOCKED 0x00000001 /* R---V */
|
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN18_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19 19:19 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19_NORMAL 0x00000000 /* R---V */
|
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#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN19_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20 20:20 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN20_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21 21:21 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN21_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22 22:22 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN22_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23 23:23 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN23_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24 24:24 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN24_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25 25:25 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN25_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26 26:26 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN26_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27 27:27 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN27_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28 28:28 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN28_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29 29:29 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN29_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30 30:30 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN30_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31 31:31 /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN31_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN(i) (0+(i)):(0+(i)) /* RWIVF */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN__SIZE_1 32 /* */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN_INIT 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN_NORMAL 0x00000000 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN_LOCKED 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_BB_BLOCK_STAT1_WIN_UNLOCK 0x00000001 /* -W--V */
|
|
#define NV_PDISP_FE_CMGR_LOCK_DELAY 0x00611704 /* RW-4R */
|
|
#define NV_PDISP_FE_CMGR_LOCK_DELAY_VPLL 15:0 /* RWIUF */
|
|
#define NV_PDISP_FE_CMGR_LOCK_DELAY_VPLL_INIT 0x00000064 /* RWI-V */
|
|
#define NV_PDISP_FE_CMGR_LOCK_DELAY_VPLL_100US 0x00000064 /* RW--V */
|
|
#define NV_PDISP_FE_CMGR_LOCK_DELAY_MACROPLL 31:16 /* RWIUF */
|
|
#define NV_PDISP_FE_CMGR_LOCK_DELAY_MACROPLL_INIT 0x000003E8 /* RWI-V */
|
|
#define NV_PDISP_FE_CMGR_LOCK_DELAY_MACROPLL_200US 0x000000C8 /* RW--V */
|
|
#define NV_PDISP_FE_CMGR_LOCK_DELAY_MACROPLL_1MS 0x000003E8 /* RW--V */
|
|
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING(i) (0x00611800+(i)*4) /* RW-4A */
|
|
#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LOADV_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_LAST_DATA_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VBLANK_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_STALL_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_A_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_LINE_B_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_SEC_POLICY_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_4_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_5_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_HEAD_TIMING_RG_SEM_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP 0x00611848 /* RW-4R */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_4_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_5_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_6_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_7_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_UNDERFLOW_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_4_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_5_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_6_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_7_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_CRC_MISMATCH_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_BUNDLE_TIMEOUT_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_0 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_1 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_2 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_3 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_4 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_4_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_5 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_5_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_6 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_6_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_7 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_7_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW(i) (18+(i)):(18+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_SF_DPOVERFLOW_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_SEM_SKIPPED 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_SEM_SKIPPED_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_SEM_SKIPPED_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_SEM_SKIPPED_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_RG_SEM_SKIPPED_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_ERROR 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_ERROR_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_ERROR_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_ERROR_DISP_REG_ERROR_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN 0x0061184C /* RW-4R */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_4_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_5_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_6_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_7_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_8_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_9_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_10_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_11_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_12_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_13_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_14_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_15_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_16_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_17_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_18_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_19_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_20_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_21_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_22_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_23_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_24_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_25_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_26_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_27_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_28_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_29_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_30_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_31_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_WIN_CH_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM 0x00611850 /* RW-4R */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_4_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_5_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_6_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_7_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_8_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_9_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_10_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_11_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_12_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_13_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_14_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_15_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_16_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_17_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_18_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_19_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_20_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_21_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_22_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_23_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_24_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_25_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_26_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_27_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_28_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_29_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_30_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_31_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_WINIM_CH_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER 0x00611854 /* RW-4R */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CORE_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_4_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_5_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_6_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_7_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_WRBK_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_4_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_5_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_6_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_7_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_EXC_OTHER_CURS_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN 0x00611858 /* RW-4R */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_4_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_5_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_6_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_7_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_8_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_9_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_10_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_11_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_12_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_13_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_14_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_15_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_16_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_17_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_18_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_19_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_20_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_21_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_22_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_23_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_24_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_25_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_26_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_27_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_28_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_29_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_30_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_31_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_WIN_CH_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER 0x0061185C /* RW-4R */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_CORE_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_4_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_5_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_6_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_7_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_SEM_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_4_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_5_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_6_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_7_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_AWAKEN_OTHER_WRBK_NTF_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP 0x00611860 /* RW-4R */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SUPERVISOR_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_VBIOS_RELEASE_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_A_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_SW_GENERIC_B_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_CTRL_DISP_MSF_PIN_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_OR 0x00611864 /* RW-4R */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_4_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_5_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_6_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_7_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_OR_SOR_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_OR_DSI_OP_DONE_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN 0x00611868 /* RW-4R */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_0_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_1_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_2_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_3_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_4_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_5_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_6_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_7_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_8_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_8_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_8_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_8_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_9_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_9_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_9_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_9_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_10_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_10_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_10_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_10_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_11_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_11_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_11_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_11_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_12_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_12_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_12_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_12_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_13_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_13_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_13_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_13_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_14_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_14_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_14_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_14_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_15_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_15_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_15_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_15_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_16_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_16_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_16_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_16_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_17_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_17_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_17_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_17_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_18_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_18_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_18_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_18_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_19_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_19_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_19_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_19_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_20_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_20_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_20_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_20_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_21_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_21_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_21_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_21_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_22_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_22_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_22_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_22_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_23_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_23_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_23_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_23_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_24_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_24_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_24_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_24_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_25_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_25_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_25_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_25_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_26_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_26_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_26_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_26_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_27_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_27_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_27_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_27_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_28_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_28_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_28_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_28_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_29_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_29_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_29_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_29_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_30_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_30_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_30_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_30_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_31_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_31_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_31_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_31_RESET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_STAT_SEM_WIN_CH_RESET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING(i) (0x00611900+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_LOADV 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_LOADV_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_LOADV_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_LOADV_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_LOADV_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_LAST_DATA_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_LAST_DATA_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_VBLANK 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_VBLANK_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_VBLANK_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_VBLANK_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_VBLANK_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_VACTIVE_SPACE_VBLANK_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_VACTIVE_SPACE_VBLANK_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_VACTIVE_SPACE_VBLANK_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_STALL_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_STALL_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_STALL_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_STALL_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_LINE_A_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_LINE_A_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_LINE_A_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_LINE_A_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_LINE_B_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_LINE_B_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_LINE_B_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_LINE_B_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_SEC_POLICY_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_SEC_POLICY_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_SEC_POLICY_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_SEC_POLICY_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_4_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_5_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_HEAD_TIMING_RG_SEM_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP 0x00611948 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_4_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_5_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_6_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_7_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_UNDERFLOW_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_4_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_5_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_6_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_7_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_CRC_MISMATCH_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_BUNDLE_TIMEOUT_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_0 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_1 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_2 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_3 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_4 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_4_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_5 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_5_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_6 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_6_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_7 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_7_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW(i) (18+(i)):(18+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_SF_DPOVERFLOW_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_SEM_SKIPPED 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_SEM_SKIPPED_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_SEM_SKIPPED_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_SEM_SKIPPED_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_RG_SEM_SKIPPED_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_ERROR 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_ERROR_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_ERROR_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_ERROR_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_ERROR_DISP_REG_ERROR_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN 0x0061194C /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_4_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_5_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_6_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_7_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_8_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_8_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_8_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_8_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_9_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_9_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_9_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_9_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_10_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_10_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_10_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_10_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_11_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_11_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_11_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_11_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_12_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_12_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_12_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_12_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_13_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_13_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_13_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_13_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_14_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_14_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_14_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_14_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_15_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_15_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_15_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_15_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_16_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_16_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_16_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_16_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_17_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_17_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_17_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_17_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_18_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_18_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_18_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_18_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_19_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_19_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_19_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_19_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_20_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_20_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_20_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_20_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_21_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_21_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_21_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_21_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_22_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_22_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_22_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_22_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_23_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_23_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_23_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_23_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_24_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_24_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_24_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_24_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_25_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_25_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_25_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_25_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_26_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_26_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_26_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_26_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_27_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_27_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_27_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_27_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_28_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_28_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_28_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_28_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_29_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_29_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_29_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_29_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_30_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_30_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_30_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_30_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_31_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_31_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_31_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_31_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WIN_CH_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM 0x00611950 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_4_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_5_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_6_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_7_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_8_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_8_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_8_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_8_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_9_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_9_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_9_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_9_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_10_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_10_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_10_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_10_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_11_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_11_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_11_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_11_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_12_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_12_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_12_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_12_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_13_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_13_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_13_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_13_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_14_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_14_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_14_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_14_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_15_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_15_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_15_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_15_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_16_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_16_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_16_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_16_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_17_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_17_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_17_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_17_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_18_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_18_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_18_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_18_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_19_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_19_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_19_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_19_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_20_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_20_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_20_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_20_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_21_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_21_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_21_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_21_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_22_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_22_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_22_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_22_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_23_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_23_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_23_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_23_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_24_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_24_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_24_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_24_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_25_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_25_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_25_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_25_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_26_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_26_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_26_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_26_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_27_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_27_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_27_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_27_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_28_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_28_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_28_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_28_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_29_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_29_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_29_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_29_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_30_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_30_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_30_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_30_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_31_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_31_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_31_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_31_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_WINIM_CH_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER 0x00611954 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CORE_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CORE_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CORE_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CORE_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_4_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_5_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_6_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_7_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_WRBK_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_4_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_5_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_6_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_7_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_EXC_OTHER_CURS_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN 0x00611958 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_4_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_5_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_6_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_7_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_8_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_8_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_8_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_8_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_9_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_9_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_9_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_9_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_10_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_10_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_10_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_10_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_11_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_11_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_11_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_11_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_12_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_12_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_12_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_12_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_13_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_13_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_13_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_13_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_14_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_14_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_14_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_14_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_15_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_15_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_15_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_15_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_16_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_16_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_16_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_16_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_17_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_17_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_17_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_17_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_18_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_18_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_18_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_18_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_19_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_19_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_19_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_19_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_20_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_20_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_20_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_20_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_21_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_21_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_21_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_21_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_22_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_22_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_22_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_22_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_23_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_23_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_23_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_23_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_24_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_24_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_24_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_24_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_25_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_25_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_25_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_25_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_26_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_26_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_26_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_26_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_27_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_27_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_27_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_27_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_28_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_28_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_28_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_28_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_29_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_29_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_29_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_29_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_30_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_30_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_30_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_30_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_31_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_31_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_31_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_31_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_WIN_CH_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER 0x0061195C /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_CORE_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_CORE_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_CORE_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_CORE_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_4_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_5_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_6_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_7_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_SEM_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_4_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_5_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_6_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_7_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_AWAKEN_OTHER_WRBK_NTF_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP 0x00611960 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SUPERVISOR_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_VBIOS_RELEASE_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_VBIOS_RELEASE_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_VBIOS_RELEASE_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SW_GENERIC_A_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SW_GENERIC_A_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SW_GENERIC_A_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SW_GENERIC_A_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SW_GENERIC_B_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SW_GENERIC_B_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SW_GENERIC_B_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_SW_GENERIC_B_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_MSF_PIN_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_MSF_PIN_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_MSF_PIN_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_CTRL_DISP_MSF_PIN_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR 0x00611964 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_4_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_5_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_6_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_7_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_SOR_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_OR_DSI_OP_DONE_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN 0x00611968 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_0_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_1_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_2_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_3_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_4_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_5_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_6_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_7_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_8_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_8_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_8_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_8_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_9_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_9_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_9_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_9_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_10_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_10_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_10_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_10_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_11_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_11_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_11_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_11_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_12_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_12_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_12_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_12_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_13_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_13_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_13_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_13_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_14_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_14_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_14_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_14_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_15_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_15_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_15_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_15_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_16_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_16_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_16_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_16_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_17_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_17_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_17_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_17_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_18_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_18_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_18_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_18_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_19_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_19_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_19_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_19_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_20_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_20_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_20_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_20_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_21_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_21_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_21_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_21_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_22_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_22_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_22_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_22_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_23_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_23_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_23_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_23_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_24_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_24_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_24_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_24_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_25_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_25_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_25_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_25_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_26_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_26_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_26_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_26_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_27_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_27_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_27_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_27_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_28_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_28_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_28_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_28_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_29_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_29_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_29_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_29_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_30_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_30_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_30_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_30_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_31_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_31_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_31_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_31_CLEAR 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_CLR_SEM_WIN_CH_CLEAR 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING(i) (0x00611980+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING__SIZE_1 8 /* */
|
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_LOADV 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_LOADV_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_LOADV_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_LOADV_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_LOADV_SET 0x00000001 /* -W--V */
|
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_LAST_DATA_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_LAST_DATA_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_VBLANK 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_VBLANK_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_VBLANK_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_VBLANK_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_VBLANK_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_VACTIVE_SPACE_VBLANK_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_VACTIVE_SPACE_VBLANK_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_VACTIVE_SPACE_VBLANK_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_STALL_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_STALL_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_STALL_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_STALL_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_LINE_A_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_LINE_A_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_LINE_A_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_LINE_A_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_LINE_B_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_LINE_B_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_LINE_B_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_LINE_B_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_SEC_POLICY_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_SEC_POLICY_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_SEC_POLICY_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_SEC_POLICY_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_4_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_5_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_HEAD_TIMING_RG_SEM_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP 0x006119C8 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_4_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_5_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_6_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_7_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_UNDERFLOW_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_4_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_5_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_6_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_7_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_CRC_MISMATCH_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_BUNDLE_TIMEOUT_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_0 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_1 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_2 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_3 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_4 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_4_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_5 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_5_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_6 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_6_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_7 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_7_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW(i) (18+(i)):(18+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_SF_DPOVERFLOW_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_SEM_SKIPPED 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_SEM_SKIPPED_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_SEM_SKIPPED_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_SEM_SKIPPED_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_RG_SEM_SKIPPED_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_ERROR 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_ERROR_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_ERROR_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_ERROR_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_ERROR_DISP_REG_ERROR_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN 0x006119CC /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_4_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_5_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_6_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_7_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_8_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_8_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_8_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_8_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_9_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_9_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_9_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_9_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_10_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_10_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_10_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_10_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_11_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_11_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_11_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_11_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_12_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_12_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_12_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_12_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_13_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_13_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_13_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_13_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_14_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_14_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_14_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_14_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_15_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_15_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_15_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_15_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_16_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_16_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_16_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_16_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_17_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_17_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_17_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_17_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_18_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_18_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_18_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_18_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_19_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_19_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_19_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_19_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_20_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_20_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_20_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_20_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_21_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_21_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_21_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_21_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_22_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_22_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_22_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_22_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_23_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_23_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_23_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_23_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_24_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_24_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_24_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_24_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_25_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_25_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_25_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_25_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_26_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_26_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_26_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_26_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_27_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_27_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_27_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_27_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_28_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_28_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_28_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_28_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_29_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_29_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_29_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_29_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_30_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_30_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_30_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_30_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_31_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_31_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_31_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_31_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WIN_CH_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM 0x006119D0 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_4_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_5_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_6_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_7_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_8_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_8_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_8_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_8_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_9_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_9_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_9_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_9_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_10_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_10_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_10_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_10_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_11_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_11_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_11_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_11_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_12_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_12_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_12_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_12_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_13_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_13_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_13_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_13_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_14_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_14_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_14_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_14_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_15_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_15_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_15_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_15_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_16_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_16_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_16_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_16_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_17_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_17_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_17_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_17_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_18_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_18_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_18_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_18_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_19_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_19_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_19_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_19_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_20_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_20_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_20_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_20_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_21_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_21_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_21_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_21_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_22_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_22_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_22_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_22_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_23_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_23_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_23_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_23_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_24_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_24_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_24_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_24_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_25_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_25_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_25_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_25_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_26_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_26_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_26_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_26_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_27_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_27_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_27_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_27_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_28_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_28_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_28_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_28_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_29_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_29_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_29_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_29_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_30_INIT 0x00000001 /* R-I-V */
|
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_30_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_30_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_30_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_31_INIT 0x00000001 /* R-I-V */
|
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_31_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_31_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_31_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH__SIZE_1 32 /* */
|
|
#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_INIT 0x00000001 /* */
|
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_DISABLE 0x00000000 /* */
|
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_WINIM_CH_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER 0x006119D4 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CORE_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CORE_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CORE_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CORE_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_4_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_5_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_6_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_7_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_WRBK_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_4_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_5_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_6_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_7_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_EXC_OTHER_CURS_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN 0x006119D8 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_4_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_5_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_6_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_7_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_8_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_8_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_8_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_8_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_9_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_9_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_9_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_9_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_10_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_10_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_10_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_10_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_11_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_11_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_11_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_11_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_12_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_12_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_12_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_12_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_13_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_13_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_13_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_13_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_14_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_14_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_14_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_14_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_15_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_15_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_15_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_15_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_16_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_16_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_16_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_16_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_17_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_17_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_17_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_17_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_18_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_18_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_18_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_18_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_19_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_19_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_19_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_19_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_20_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_20_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_20_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_20_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_21_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_21_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_21_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_21_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_22_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_22_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_22_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_22_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_23_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_23_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_23_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_23_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_24_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_24_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_24_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_24_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_25_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_25_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_25_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_25_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_26_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_26_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_26_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_26_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_27_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_27_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_27_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_27_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_28_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_28_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_28_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_28_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_29_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_29_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_29_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_29_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_30_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_30_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_30_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_30_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_31_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_31_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_31_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_31_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_WIN_CH_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER 0x006119DC /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_CORE_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_CORE_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_CORE_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_CORE_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_4_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_5_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_6_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_7_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_SEM_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_4_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_5_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_6_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_7_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_AWAKEN_OTHER_WRBK_NTF_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP 0x006119E0 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SUPERVISOR_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_VBIOS_RELEASE_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_VBIOS_RELEASE_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_VBIOS_RELEASE_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SW_GENERIC_A_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SW_GENERIC_A_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SW_GENERIC_A_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SW_GENERIC_A_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SW_GENERIC_B_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SW_GENERIC_B_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SW_GENERIC_B_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_SW_GENERIC_B_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_MSF_PIN_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_MSF_PIN_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_MSF_PIN_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_CTRL_DISP_MSF_PIN_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_OR 0x006119E4 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_4_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_5_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_6_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_7_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_OR_SOR_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_OR_DSI_OP_DONE_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN 0x006119E8 /* RW-4R */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_0_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_0_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_0_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_0_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_1_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_1_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_1_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_1_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_2_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_2_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_2_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_2_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_3_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_3_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_3_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_3_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_4_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_4_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_4_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_4_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_5_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_5_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_5_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_5_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_6_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_6_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_6_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_6_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_7_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_7_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_7_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_7_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_8_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_8_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_8_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_8_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_9_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_9_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_9_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_9_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_10_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_10_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_10_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_10_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_11_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_11_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_11_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_11_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_12_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_12_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_12_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_12_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_13_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_13_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_13_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_13_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_14_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_14_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_14_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_14_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_15_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_15_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_15_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_15_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_16_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_16_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_16_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_16_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_17_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_17_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_17_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_17_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_18_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_18_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_18_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_18_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_19_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_19_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_19_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_19_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_20_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_20_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_20_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_20_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_21_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_21_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_21_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_21_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_22_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_22_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_22_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_22_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_23_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_23_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_23_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_23_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_24_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_24_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_24_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_24_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_25_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_25_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_25_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_25_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_26_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_26_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_26_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_26_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_27_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_27_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_27_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_27_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_28_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_28_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_28_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_28_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_29_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_29_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_29_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_29_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_30_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_30_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_30_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_30_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_31_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_31_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_31_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_31_SET 0x00000001 /* -W--V */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_INIT 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_EVT_EN_SET_SEM_WIN_CH_SET 0x00000001 /* */
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#define NV_PDISP_FE_EVT_DISPATCH 0x00611A00 /* R--4R */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_0 0:0 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_1 1:1 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_2 2:2 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_3 3:3 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_4 4:4 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_5 5:5 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_6 6:6 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_7 7:7 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_EVT_DISPATCH_HEAD_TIMING_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DISP 18:18 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DISP_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_ERROR_DISP_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_EXC_WIN 19:19 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_EXC_WIN_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_EXC_WIN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_EXC_WINIM 20:20 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_EXC_WINIM_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_EXC_WINIM_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_EXC_OTHER 21:21 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_EXC_OTHER_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_EXC_OTHER_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_WIN 22:22 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_WIN_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_WIN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_OTHER 23:23 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_OTHER_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_AWAKEN_OTHER_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_CTRL_DISP 24:24 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_CTRL_DISP_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_CTRL_DISP_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_OR 25:25 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_OR_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_OR_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_SEM_WIN 26:26 /* R--VF */
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#define NV_PDISP_FE_EVT_DISPATCH_SEM_WIN_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_EVT_DISPATCH_SEM_WIN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING(i) (0x00611C00+(i)*4) /* R--4A */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_LOADV 0:0 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_LOADV_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_LOADV_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_LAST_DATA 1:1 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_LAST_DATA_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_LAST_DATA_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_VBLANK 2:2 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_VBLANK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_VBLANK_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_STALL 4:4 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_STALL_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_STALL_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_LINE_A 5:5 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_LINE_A_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_LINE_A_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_LINE_B 6:6 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_LINE_B_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_LINE_B_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_SEC_POLICY 8:8 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_SEC_POLICY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_SEC_POLICY_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_0 16:16 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_1 17:17 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_2 18:18 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_3 19:19 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_4 20:20 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_5 21:21 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_HEAD_TIMING_RG_SEM_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN 0x00611C24 /* R--4R */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_0 0:0 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_1 1:1 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_2 2:2 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_3 3:3 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_4 4:4 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_5 5:5 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_6 6:6 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_7 7:7 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_8 8:8 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_8_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_9 9:9 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_9_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_10 10:10 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_10_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_10_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_11 11:11 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_11_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_11_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_12 12:12 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_12_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_12_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_13 13:13 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_13_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_13_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_14 14:14 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_14_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_14_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_15 15:15 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_15_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_15_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_16 16:16 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_16_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_16_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_17 17:17 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_17_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_17_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_18 18:18 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_18_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_18_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_19 19:19 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_19_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_19_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_20 20:20 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_20_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_20_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_21 21:21 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_21_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_21_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_22 22:22 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_22_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_22_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_23 23:23 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_23_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_23_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_24 24:24 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_24_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_24_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_25 25:25 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_25_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_25_PENDING 0x00000001 /* R---V */
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|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_26 26:26 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_26_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_26_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_27 27:27 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_27_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_27_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_28 28:28 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_28_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_28_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_29 29:29 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_29_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_29_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_30 30:30 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_30_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_30_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_31 31:31 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_31_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_31_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WIN_CH_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM 0x00611C28 /* R--4R */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_0 0:0 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_1 1:1 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_2 2:2 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_3 3:3 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_4 4:4 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_5 5:5 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_6 6:6 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_7 7:7 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_8 8:8 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_8_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_9 9:9 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_9_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_10 10:10 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_10_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_10_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_11 11:11 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_11_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_11_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_12 12:12 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_12_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_12_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_13 13:13 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_13_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_13_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_14 14:14 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_14_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_14_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_15 15:15 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_15_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_15_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_16 16:16 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_16_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_16_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_17 17:17 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_17_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_17_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_18 18:18 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_18_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_18_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_19 19:19 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_19_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_19_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_20 20:20 /* R-IVF */
|
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_20_NOT_PENDING 0x00000000 /* R-I-V */
|
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_20_PENDING 0x00000001 /* R---V */
|
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_21 21:21 /* R-IVF */
|
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_21_NOT_PENDING 0x00000000 /* R-I-V */
|
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_21_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_22 22:22 /* R-IVF */
|
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_22_NOT_PENDING 0x00000000 /* R-I-V */
|
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_22_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_23 23:23 /* R-IVF */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_23_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_23_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_24 24:24 /* R-IVF */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_24_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_24_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_25 25:25 /* R-IVF */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_25_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_25_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_26 26:26 /* R-IVF */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_26_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_26_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_27 27:27 /* R-IVF */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_27_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_27_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_28 28:28 /* R-IVF */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_28_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_28_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_29 29:29 /* R-IVF */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_29_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_29_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_30 30:30 /* R-IVF */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_30_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_30_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_31 31:31 /* R-IVF */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_31_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_31_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_WINIM_CH_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER 0x00611C2C /* R--4R */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CORE 0:0 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CORE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CORE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_0 8:8 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_1 9:9 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_2 10:10 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_3 11:11 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_4 12:12 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_5 13:13 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_6 14:14 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_7 15:15 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_WRBK_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_0 16:16 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_1 17:17 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_2 18:18 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_3 19:19 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_4 20:20 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_5 21:21 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_6 22:22 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_7 23:23 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_EXC_OTHER_CURS_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP 0x00611C30 /* R--4R */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR1 0:0 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR2 1:1 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR3 2:2 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SUPERVISOR_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_VBIOS_RELEASE 3:3 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_VBIOS_RELEASE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_VBIOS_RELEASE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_A 4:4 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_A_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_A_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_B 5:5 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_B_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_SW_GENERIC_B_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_MSF_PIN 6:6 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_MSF_PIN_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_MSF_PIN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_ERROR 7:7 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_ERROR_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN 8:8 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_AWAKEN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WIN_SEM 9:9 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WIN_SEM_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WIN_SEM_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WRBK_SEM 10:10 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WRBK_SEM_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_CTRL_DISP_WRBK_SEM_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR 0x00611C34 /* R--4R */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_0 0:0 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_1 1:1 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_2 2:2 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_3 3:3 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_4 4:4 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_5 5:5 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_6 6:6 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_7 7:7 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_SOR_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_0 8:8 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_1 9:9 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_2 10:10 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_3 11:11 /* R-IVF */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_STAT_OR_DSI_OP_DONE_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING(i) (0x00611C40+(i)*4) /* R--4A */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_LOADV 0:0 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_LOADV_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_LOADV_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_LAST_DATA 1:1 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_LAST_DATA_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_LAST_DATA_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_VBLANK 2:2 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_VBLANK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_VBLANK_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_STALL 4:4 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_STALL_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_STALL_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_LINE_A 5:5 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_LINE_A_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_LINE_A_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_LINE_B 6:6 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_LINE_B_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_LINE_B_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_SEC_POLICY 8:8 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_SEC_POLICY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_SEC_POLICY_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_0 16:16 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_1 17:17 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_2 18:18 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_3 19:19 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_4 20:20 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_5 21:21 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_HEAD_TIMING_RG_SEM_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN 0x00611C64 /* R--4R */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_0 0:0 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_1 1:1 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_2 2:2 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_3 3:3 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_4 4:4 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_5 5:5 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_6 6:6 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_7 7:7 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_8 8:8 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_8_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_9 9:9 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_9_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_10 10:10 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_10_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_10_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_11 11:11 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_11_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_11_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_12 12:12 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_12_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_12_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_13 13:13 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_13_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_13_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_14 14:14 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_14_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_14_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_15 15:15 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_15_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_15_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_16 16:16 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_16_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_16_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_17 17:17 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_17_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_17_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_18 18:18 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_18_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_18_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_19 19:19 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_19_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_19_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_20 20:20 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_20_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_20_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_21 21:21 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_21_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_21_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_22 22:22 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_22_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_22_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_23 23:23 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_23_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_23_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_24 24:24 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_24_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_24_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_25 25:25 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_25_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_25_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_26 26:26 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_26_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_26_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_27 27:27 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_27_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_27_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_28 28:28 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_28_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_28_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_29 29:29 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_29_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_29_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_30 30:30 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_30_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_30_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_31 31:31 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_31_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_31_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WIN_CH_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM 0x00611C68 /* R--4R */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_0 0:0 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_1 1:1 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_2 2:2 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_3 3:3 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_4 4:4 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_5 5:5 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_6 6:6 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_7 7:7 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_8 8:8 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_8_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_9 9:9 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_9_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_10 10:10 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_10_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_10_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_11 11:11 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_11_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_11_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_12 12:12 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_12_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_12_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_13 13:13 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_13_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_13_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_14 14:14 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_14_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_14_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_15 15:15 /* R-IVF */
|
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_15_NOT_PENDING 0x00000000 /* R-I-V */
|
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_15_PENDING 0x00000001 /* R---V */
|
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_16 16:16 /* R-IVF */
|
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_16_NOT_PENDING 0x00000000 /* R-I-V */
|
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_16_PENDING 0x00000001 /* R---V */
|
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_17 17:17 /* R-IVF */
|
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_17_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_17_PENDING 0x00000001 /* R---V */
|
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_18 18:18 /* R-IVF */
|
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_18_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_18_PENDING 0x00000001 /* R---V */
|
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_19 19:19 /* R-IVF */
|
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_19_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_19_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_20 20:20 /* R-IVF */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_20_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_20_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_21 21:21 /* R-IVF */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_21_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_21_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_22 22:22 /* R-IVF */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_22_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_22_PENDING 0x00000001 /* R---V */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_23 23:23 /* R-IVF */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_23_NOT_PENDING 0x00000000 /* R-I-V */
|
|
#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_23_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_24 24:24 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_24_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_24_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_25 25:25 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_25_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_25_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_26 26:26 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_26_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_26_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_27 27:27 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_27_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_27_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_28 28:28 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_28_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_28_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_29 29:29 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_29_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_29_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_30 30:30 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_30_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_30_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_31 31:31 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_31_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_31_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_WINIM_CH_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER 0x00611C6C /* R--4R */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CORE 0:0 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CORE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CORE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_0 8:8 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_1 9:9 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_2 10:10 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_3 11:11 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_4 12:12 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_5 13:13 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_6 14:14 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_7 15:15 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_WRBK_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_0 16:16 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_1 17:17 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_2 18:18 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_3 19:19 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_4 20:20 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_5 21:21 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_6 22:22 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_7 23:23 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_EXC_OTHER_CURS_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP 0x00611C70 /* R--4R */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SUPERVISOR1 0:0 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SUPERVISOR1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SUPERVISOR1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SUPERVISOR2 1:1 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SUPERVISOR2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SUPERVISOR2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SUPERVISOR3 2:2 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SUPERVISOR3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SUPERVISOR3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SUPERVISOR_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SUPERVISOR_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_VBIOS_RELEASE 3:3 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_VBIOS_RELEASE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_VBIOS_RELEASE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SW_GENERIC_A 4:4 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SW_GENERIC_A_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SW_GENERIC_A_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SW_GENERIC_B 5:5 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SW_GENERIC_B_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_SW_GENERIC_B_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_MSF_PIN 6:6 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_MSF_PIN_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_MSF_PIN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_ERROR 7:7 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_ERROR_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_AWAKEN 8:8 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_AWAKEN_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_AWAKEN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_WIN_SEM 9:9 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_WIN_SEM_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_WIN_SEM_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_WRBK_SEM 10:10 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_WRBK_SEM_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_CTRL_DISP_WRBK_SEM_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR 0x00611C74 /* R--4R */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_0 0:0 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_1 1:1 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_2 2:2 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_3 3:3 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_4 4:4 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_5 5:5 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_6 6:6 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_7 7:7 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_SOR_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_0 8:8 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_1 9:9 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_2 10:10 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_3 11:11 /* R-IVF */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_STAT_OR_DSI_OP_DONE_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING(i) (0x00611C80+(i)*4) /* R--4A */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_LOADV 0:0 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_LOADV_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_LOADV_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_LAST_DATA 1:1 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_LAST_DATA_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_LAST_DATA_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_VBLANK 2:2 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_VBLANK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_VBLANK_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_VACTIVE_SPACE_VBLANK_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_STALL 4:4 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_STALL_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_STALL_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_LINE_A 5:5 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_LINE_A_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_LINE_A_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_LINE_B 6:6 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_LINE_B_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_LINE_B_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_SEC_POLICY 8:8 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_SEC_POLICY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_SEC_POLICY_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_0 16:16 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_1 17:17 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_2 18:18 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_3 19:19 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_4 20:20 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_5 21:21 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_HEAD_TIMING_RG_SEM_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN 0x00611CA4 /* R--4R */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_0 0:0 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_1 1:1 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_2 2:2 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_3 3:3 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_4 4:4 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_5 5:5 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_6 6:6 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_7 7:7 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_8 8:8 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_8_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_9 9:9 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_9_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_10 10:10 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_10_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_10_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_11 11:11 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_11_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_11_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_12 12:12 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_12_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_12_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_13 13:13 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_13_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_13_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_14 14:14 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_14_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_14_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_15 15:15 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_15_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_15_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_16 16:16 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_16_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_16_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_17 17:17 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_17_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_17_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_18 18:18 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_18_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_18_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_19 19:19 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_19_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_19_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_20 20:20 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_20_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_20_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_21 21:21 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_21_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_21_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_22 22:22 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_22_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_22_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_23 23:23 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_23_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_23_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_24 24:24 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_24_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_24_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_25 25:25 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_25_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_25_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_26 26:26 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_26_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_26_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_27 27:27 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_27_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_27_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_28 28:28 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_28_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_28_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_29 29:29 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_29_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_29_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_30 30:30 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_30_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_30_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_31 31:31 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_31_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_31_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WIN_CH_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM 0x00611CA8 /* R--4R */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_0 0:0 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_1 1:1 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_2 2:2 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_3 3:3 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_4 4:4 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_5 5:5 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_6 6:6 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_7 7:7 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_8 8:8 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_8_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_9 9:9 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_9_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_10 10:10 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_10_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_10_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_11 11:11 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_11_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_11_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_12 12:12 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_12_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_12_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_13 13:13 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_13_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_13_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_14 14:14 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_14_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_14_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_15 15:15 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_15_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_15_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_16 16:16 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_16_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_16_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_17 17:17 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_17_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_17_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_18 18:18 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_18_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_18_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_19 19:19 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_19_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_19_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_20 20:20 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_20_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_20_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_21 21:21 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_21_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_21_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_22 22:22 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_22_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_22_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_23 23:23 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_23_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_23_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_24 24:24 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_24_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_24_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_25 25:25 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_25_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_25_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_26 26:26 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_26_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_26_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_27 27:27 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_27_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_27_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_28 28:28 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_28_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_28_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_29 29:29 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_29_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_29_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_30 30:30 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_30_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_30_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_31 31:31 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_31_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_31_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_WINIM_CH_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER 0x00611CAC /* R--4R */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CORE 0:0 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CORE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CORE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_0 8:8 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_1 9:9 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_2 10:10 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_3 11:11 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_4 12:12 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_5 13:13 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_6 14:14 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_7 15:15 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_WRBK_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_0 16:16 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_1 17:17 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_2 18:18 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_3 19:19 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_4 20:20 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_5 21:21 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_6 22:22 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_7 23:23 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_EXC_OTHER_CURS_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP 0x00611CB0 /* R--4R */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SUPERVISOR1 0:0 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SUPERVISOR1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SUPERVISOR1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SUPERVISOR2 1:1 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SUPERVISOR2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SUPERVISOR2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SUPERVISOR3 2:2 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SUPERVISOR3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SUPERVISOR3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SUPERVISOR_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SUPERVISOR_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_VBIOS_RELEASE 3:3 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_VBIOS_RELEASE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_VBIOS_RELEASE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SW_GENERIC_A 4:4 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SW_GENERIC_A_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SW_GENERIC_A_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SW_GENERIC_B 5:5 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SW_GENERIC_B_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_SW_GENERIC_B_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_MSF_PIN 6:6 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_MSF_PIN_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_MSF_PIN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_ERROR 7:7 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_ERROR_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_AWAKEN 8:8 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_AWAKEN_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_AWAKEN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_WIN_SEM 9:9 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_WIN_SEM_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_WIN_SEM_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_WRBK_SEM 10:10 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_WRBK_SEM_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_CTRL_DISP_WRBK_SEM_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR 0x00611CB4 /* R--4R */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_0 0:0 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_1 1:1 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_2 2:2 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_3 3:3 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_4 4:4 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_5 5:5 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_6 6:6 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_7 7:7 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_SOR_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_0 8:8 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_1 9:9 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_2 10:10 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_3 11:11 /* R-IVF */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_STAT_OR_DSI_OP_DONE_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING(i) (0x00611CC0+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LOADV 0:0 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LOADV_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LOADV_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LOADV_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LAST_DATA_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VBLANK 2:2 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VBLANK_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VBLANK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VBLANK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_STALL_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_STALL_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_STALL_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_A_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_A_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_A_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_B_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_B_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_LINE_B_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SEC_POLICY_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SEC_POLICY_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_SEC_POLICY_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_0_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_1_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_2_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_3_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_4_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_5_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_INIT 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_HEAD_TIMING_RG_SEM_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN 0x00611CE4 /* RW-4R */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_0_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_1_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_2_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_3_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_4_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_5_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_6_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_7_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_8_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_8_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_8_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_9_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_9_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_9_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_10_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_10_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_10_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_11_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_11_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_11_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_12_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_12_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_12_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_13_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_13_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_13_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_14_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_14_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_14_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_15_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_15_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_15_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_16_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_16_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_16_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_17_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_17_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_17_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_18_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_18_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_18_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_19_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_19_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_19_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_20_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_20_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_20_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_21_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_21_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_21_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_22_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_22_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_22_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_23_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_23_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_23_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_24_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_24_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_24_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_25_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_25_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_25_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_26_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_26_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_26_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_27_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_27_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_27_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_28_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_28_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_28_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_29_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_29_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_29_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_30_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_30_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_30_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_31_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_31_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_31_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_INIT 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WIN_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM 0x00611CE8 /* RW-4R */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_0_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_1_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_2_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_3_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_4_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_5_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_6_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_7_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_8_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_8_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_8_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_9_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_9_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_9_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_10_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_10_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_10_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_11_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_11_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_11_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_12_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_12_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_12_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_13_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_13_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_13_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_14_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_14_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_14_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_15_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_15_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_15_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_16_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_16_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_16_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_17_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_17_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_17_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_18_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_18_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_18_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_19_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_19_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_19_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_20_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_20_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_20_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_21_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_21_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_21_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_22_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_22_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_22_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_23_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_23_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_23_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_24_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_24_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_24_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_25_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_25_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_25_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_26_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_26_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_26_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_27_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_27_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_27_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_28_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_28_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_28_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_29_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_29_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_29_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_30_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_30_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_30_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_31_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_31_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_31_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_INIT 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_WINIM_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER 0x00611CEC /* RW-4R */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CORE_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CORE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CORE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_0_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_1_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_2_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_3_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_4_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_5_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_6_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_7_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_INIT 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_WRBK_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_0_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_1_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_2_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_3_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_4_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_5_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_6_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_7_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_INIT 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_EXC_OTHER_CURS_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP 0x00611CF0 /* RW-4R */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR1_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR2_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR3_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR_INIT 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SUPERVISOR_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_A_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_A_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_A_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_B_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_B_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_SW_GENERIC_B_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_MSF_PIN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_MSF_PIN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_MSF_PIN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_ERROR 7:7 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_ERROR_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_AWAKEN 8:8 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_AWAKEN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_AWAKEN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_AWAKEN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_WIN_SEM 9:9 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_WIN_SEM_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_WIN_SEM_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_WIN_SEM_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_WRBK_SEM 10:10 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_WRBK_SEM_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_WRBK_SEM_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_CTRL_DISP_WRBK_SEM_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR 0x00611CF4 /* RW-4R */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_0_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_1_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_2_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_3_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_4_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_5_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_6_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_7_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_INIT 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_SOR_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_0_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_1_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_2_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_3_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_INIT 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_MSK_OR_DSI_OP_DONE_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING(i) (0x00611D00+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_LOADV 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_LOADV_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_LOADV_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_LOADV_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_VBLANK 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_VBLANK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_VBLANK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_VBLANK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_STALL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_STALL_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_STALL_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_LINE_A_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_LINE_A_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_LINE_A_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_LINE_B_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_LINE_B_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_LINE_B_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_SEC_POLICY_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_SEC_POLICY_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_SEC_POLICY_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_HEAD_TIMING_RG_SEM_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN 0x00611D24 /* RW-4R */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_8_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_8_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_8_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_9_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_9_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_9_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_10_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_10_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_10_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_11_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_11_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_11_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_12_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_12_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_12_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_13_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_13_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_13_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_14_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_14_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_14_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_15_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_15_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_15_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_16_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_16_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_16_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_17_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_17_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_17_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_18_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_18_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_18_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_19_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_19_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_19_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_20_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_20_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_20_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_21_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_21_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_21_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_22_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_22_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_22_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_23_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_23_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_23_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_24_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_24_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_24_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_25_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_25_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_25_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_26_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_26_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_26_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_27_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_27_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_27_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_28_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_28_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_28_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_29_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_29_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_29_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_30_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_30_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_30_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_31_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_31_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_31_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WIN_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM 0x00611D28 /* RW-4R */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_8_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_8_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_8_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_9_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_9_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_9_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_10_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_10_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_10_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_11_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_11_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_11_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_12_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_12_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_12_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_13_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_13_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_13_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_14_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_14_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_14_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_15_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_15_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_15_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_16_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_16_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_16_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_17_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_17_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_17_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_18_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_18_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_18_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_19_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_19_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_19_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_20_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_20_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_20_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_21_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_21_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_21_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_22_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_22_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_22_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_23_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_23_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_23_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_24_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_24_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_24_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_25_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_25_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_25_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_26_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_26_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_26_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_27_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_27_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_27_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_28_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_28_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_28_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_29_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_29_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_29_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_30_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_30_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_30_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_31_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_31_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_31_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_WINIM_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER 0x00611D2C /* RW-4R */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CORE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CORE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CORE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_WRBK_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_EXC_OTHER_CURS_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP 0x00611D30 /* RW-4R */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SUPERVISOR_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SW_GENERIC_A_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SW_GENERIC_A_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SW_GENERIC_A_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SW_GENERIC_B_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SW_GENERIC_B_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_SW_GENERIC_B_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_MSF_PIN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_MSF_PIN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_MSF_PIN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_ERROR 7:7 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_AWAKEN 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_AWAKEN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_AWAKEN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_AWAKEN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_WIN_SEM 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_WIN_SEM_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_WIN_SEM_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_WIN_SEM_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_WRBK_SEM 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_WRBK_SEM_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_WRBK_SEM_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_CTRL_DISP_WRBK_SEM_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR 0x00611D34 /* RW-4R */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_SOR_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_MSK_OR_DSI_OP_DONE_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING(i) (0x00611D40+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_LOADV 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_LOADV_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_LOADV_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_LOADV_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_VBLANK 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_VBLANK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_VBLANK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_VBLANK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_VACTIVE_SPACE_VBLANK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_STALL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_STALL_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_STALL_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_LINE_A_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_LINE_A_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_LINE_A_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_LINE_B_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_LINE_B_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_LINE_B_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_SEC_POLICY_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_SEC_POLICY_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_SEC_POLICY_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_HEAD_TIMING_RG_SEM_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN 0x00611D64 /* RW-4R */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_8_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_8_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_8_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_9_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_9_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_9_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_10_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_10_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_10_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_11_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_11_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_11_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_12_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_12_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_12_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_13_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_13_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_13_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_14_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_14_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_14_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_15_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_15_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_15_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_16_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_16_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_16_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_17_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_17_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_17_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_18_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_18_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_18_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_19_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_19_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_19_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_20_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_20_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_20_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_21_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_21_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_21_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_22_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_22_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_22_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_23_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_23_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_23_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_24_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_24_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_24_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_25_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_25_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_25_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_26_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_26_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_26_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_27_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_27_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_27_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_28_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_28_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_28_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_29_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_29_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_29_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_30_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_30_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_30_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_31_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_31_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_31_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WIN_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM 0x00611D68 /* RW-4R */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_8_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_8_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_8_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_9_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_9_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_9_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_10_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_10_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_10_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_11_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_11_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_11_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_12_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_12_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_12_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_13_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_13_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_13_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_14_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_14_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_14_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_15_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_15_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_15_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_16_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_16_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_16_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_17_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_17_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_17_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_18_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_18_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_18_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_19_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_19_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_19_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_20_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_20_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_20_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_21_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_21_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_21_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_22_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_22_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_22_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_23_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_23_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_23_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_24_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_24_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_24_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_25_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_25_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_25_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_26_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_26_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_26_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_27_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_27_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_27_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_28_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_28_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_28_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_29_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_29_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_29_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_30_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_30_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_30_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_31_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_31_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_31_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_WINIM_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER 0x00611D6C /* RW-4R */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CORE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CORE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CORE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_WRBK_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_EXC_OTHER_CURS_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP 0x00611D70 /* RW-4R */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SUPERVISOR_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_VBIOS_RELEASE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SW_GENERIC_A_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SW_GENERIC_A_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SW_GENERIC_A_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SW_GENERIC_B_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SW_GENERIC_B_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_SW_GENERIC_B_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_MSF_PIN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_MSF_PIN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_MSF_PIN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_ERROR 7:7 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_AWAKEN 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_AWAKEN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_AWAKEN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_AWAKEN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_WIN_SEM 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_WIN_SEM_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_WIN_SEM_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_WIN_SEM_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_WRBK_SEM 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_WRBK_SEM_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_WRBK_SEM_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_CTRL_DISP_WRBK_SEM_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR 0x00611D74 /* RW-4R */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_SOR_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_MSK_OR_DSI_OP_DONE_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING(i) (0x00611D80+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LOADV 0:0 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LOADV_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LOADV_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LOADV_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_LAST_DATA_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VBLANK 2:2 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VBLANK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VBLANK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VBLANK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VACTIVE_SPACE_VBLANK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_VACTIVE_SPACE_VBLANK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_STALL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_STALL_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_STALL_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_A_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_A_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_A_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_B_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_B_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_LINE_B_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SEC_POLICY_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SEC_POLICY_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_SEC_POLICY_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_INIT 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_HEAD_TIMING_RG_SEM_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN 0x00611DA4 /* RW-4R */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_8_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_8_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_8_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_9_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_9_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_9_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_10_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_10_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_10_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_11_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_11_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_11_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_12_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_12_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_12_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_13_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_13_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_13_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_14_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_14_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_14_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_15_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_15_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_15_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_16_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_16_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_16_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_17_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_17_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_17_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_18_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_18_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_18_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_19_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_19_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_19_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_20_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_20_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_20_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_21_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_21_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_21_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_22_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_22_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_22_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_23_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_23_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_23_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_24_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_24_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_24_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_25_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_25_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_25_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_26_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_26_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_26_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_27_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_27_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_27_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_28_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_28_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_28_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_29_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_29_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_29_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_30_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_30_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_30_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_31_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_31_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_31_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WIN_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM 0x00611DA8 /* RW-4R */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_8_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_8_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_8_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_9_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_9_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_9_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_10_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_10_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_10_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_11_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_11_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_11_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_12_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_12_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_12_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_13_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_13_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_13_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_14_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_14_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_14_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_15_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_15_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_15_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_16_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_16_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_16_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_17_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_17_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_17_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_18_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_18_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_18_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_19_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_19_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_19_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_20_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_20_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_20_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_21_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_21_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_21_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_22_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_22_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_22_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_23_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_23_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_23_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_24_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_24_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_24_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_25_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_25_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_25_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_26_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_26_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_26_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_27_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_27_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_27_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_28_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_28_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_28_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_29_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_29_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_29_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_30_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_30_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_30_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_31_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_31_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_31_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_WINIM_CH_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER 0x00611DAC /* RW-4R */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CORE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CORE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CORE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_INIT 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_WRBK_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_INIT 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_EXC_OTHER_CURS_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP 0x00611DB0 /* RW-4R */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SUPERVISOR_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_VBIOS_RELEASE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_VBIOS_RELEASE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_A_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_A_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_A_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_B_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_B_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_SW_GENERIC_B_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_MSF_PIN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_MSF_PIN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_MSF_PIN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_ERROR 7:7 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_ERROR_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_AWAKEN 8:8 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_AWAKEN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_AWAKEN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_AWAKEN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_WIN_SEM 9:9 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_WIN_SEM_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_WIN_SEM_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_WIN_SEM_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_WRBK_SEM 10:10 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_WRBK_SEM_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_WRBK_SEM_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_CTRL_DISP_WRBK_SEM_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR 0x00611DB4 /* RW-4R */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_4_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_4_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_5_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_5_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_6_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_6_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_7_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_7_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_OR_SOR_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_2_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_2_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_3_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_3_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_INIT 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_EN_OR_DSI_OP_DONE_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING(i) (0x00611DC0+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_LOADV 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_LOADV_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_LOADV_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_LOADV_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_LAST_DATA_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_LAST_DATA_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_VBLANK 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_VBLANK_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_VBLANK_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_VBLANK_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_VACTIVE_SPACE_VBLANK_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_VACTIVE_SPACE_VBLANK_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_STALL_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_STALL_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_STALL_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_LINE_A_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_LINE_A_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_LINE_A_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_LINE_B_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_LINE_B_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_LINE_B_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_SEC_POLICY_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_SEC_POLICY_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_SEC_POLICY_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_HEAD_TIMING_RG_SEM_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN 0x00611DE4 /* RW-4R */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_8_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_8_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_8_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_9_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_9_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_9_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_10_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_10_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_10_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_11_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_11_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_11_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_12_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_12_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_12_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_13_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_13_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_13_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_14_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_14_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_14_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_15_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_15_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_15_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_16_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_16_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_16_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_17_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_17_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_17_FORWARD 0x00000001 /* -W--V */
|
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_18_INIT 0x00000000 /* R-I-V */
|
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_18_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_18_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_19_INIT 0x00000000 /* R-I-V */
|
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_19_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_19_FORWARD 0x00000001 /* -W--V */
|
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_20_INIT 0x00000000 /* R-I-V */
|
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_20_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_20_FORWARD 0x00000001 /* -W--V */
|
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_21 21:21 /* RWIVF */
|
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_21_INIT 0x00000000 /* R-I-V */
|
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_21_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_21_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_22_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_22_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_22_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_23_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_23_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_23_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_24_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_24_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_24_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_25_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_25_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_25_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_26_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_26_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_26_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_27_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_27_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_27_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_28_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_28_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_28_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_29_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_29_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_29_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_30_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_30_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_30_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_31_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_31_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_31_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WIN_CH_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM 0x00611DE8 /* RW-4R */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_8_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_8_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_8_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_9_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_9_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_9_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_10_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_10_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_10_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_11_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_11_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_11_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_12_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_12_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_12_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_13_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_13_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_13_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_14_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_14_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_14_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_15_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_15_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_15_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_16_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_16_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_16_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_17_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_17_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_17_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_18_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_18_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_18_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_19_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_19_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_19_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_20_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_20_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_20_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_21_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_21_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_21_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_22_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_22_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_22_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_23_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_23_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_23_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_24_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_24_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_24_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_25_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_25_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_25_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_26_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_26_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_26_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_27_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_27_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_27_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_28_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_28_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_28_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_29_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_29_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_29_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_30_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_30_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_30_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_31_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_31_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_31_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_WINIM_CH_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER 0x00611DEC /* RW-4R */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CORE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CORE_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CORE_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_WRBK_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_EXC_OTHER_CURS_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP 0x00611DF0 /* RW-4R */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SUPERVISOR_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_VBIOS_RELEASE_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_VBIOS_RELEASE_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SW_GENERIC_A_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SW_GENERIC_A_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SW_GENERIC_A_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SW_GENERIC_B_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SW_GENERIC_B_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_SW_GENERIC_B_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_MSF_PIN_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_MSF_PIN_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_MSF_PIN_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_ERROR 7:7 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_ERROR_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_ERROR_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_AWAKEN 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_AWAKEN_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_AWAKEN_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_AWAKEN_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_WIN_SEM 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_WIN_SEM_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_WIN_SEM_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_WIN_SEM_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_WRBK_SEM 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_WRBK_SEM_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_WRBK_SEM_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_CTRL_DISP_WRBK_SEM_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR 0x00611DF4 /* RW-4R */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_SOR_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2RM_OR_DSI_OP_DONE_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING(i) (0x00611E00+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_LOADV 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_LOADV_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_LOADV_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_LOADV_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_LAST_DATA_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_LAST_DATA_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_VBLANK 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_VBLANK_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_VBLANK_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_VBLANK_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_VACTIVE_SPACE_VBLANK_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_VACTIVE_SPACE_VBLANK_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_STALL_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_STALL_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_STALL_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_LINE_A_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_LINE_A_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_LINE_A_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_LINE_B_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_LINE_B_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_LINE_B_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_SEC_POLICY_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_SEC_POLICY_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_SEC_POLICY_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_HEAD_TIMING_RG_SEM_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN 0x00611E24 /* RW-4R */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_8_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_8_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_8_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_9_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_9_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_9_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_10_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_10_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_10_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_11_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_11_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_11_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_12_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_12_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_12_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_13_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_13_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_13_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_14_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_14_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_14_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_15_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_15_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_15_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_16_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_16_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_16_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_17_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_17_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_17_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_18_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_18_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_18_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_19_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_19_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_19_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_20_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_20_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_20_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_21_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_21_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_21_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_22_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_22_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_22_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_23_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_23_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_23_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_24_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_24_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_24_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_25_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_25_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_25_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_26_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_26_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_26_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_27_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_27_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_27_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_28_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_28_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_28_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_29_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_29_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_29_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_30_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_30_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_30_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_31_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_31_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_31_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WIN_CH_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM 0x00611E28 /* RW-4R */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_8_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_8_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_8_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_9_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_9_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_9_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_10_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_10_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_10_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_11_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_11_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_11_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_12_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_12_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_12_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_13_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_13_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_13_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_14_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_14_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_14_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_15_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_15_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_15_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_16_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_16_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_16_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_17_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_17_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_17_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_18_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_18_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_18_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_19_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_19_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_19_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_20_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_20_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_20_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_21_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_21_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_21_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_22_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_22_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_22_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_23_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_23_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_23_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_24_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_24_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_24_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_25_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_25_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_25_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_26_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_26_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_26_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_27_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_27_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_27_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_28_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_28_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_28_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_29_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_29_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_29_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_30_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_30_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_30_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_31_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_31_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_31_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_WINIM_CH_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER 0x00611E2C /* RW-4R */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CORE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CORE_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CORE_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_WRBK_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_EXC_OTHER_CURS_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP 0x00611E30 /* RW-4R */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SUPERVISOR_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_VBIOS_RELEASE_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_VBIOS_RELEASE_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SW_GENERIC_A_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SW_GENERIC_A_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SW_GENERIC_A_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SW_GENERIC_B_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SW_GENERIC_B_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_SW_GENERIC_B_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_MSF_PIN_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_MSF_PIN_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_MSF_PIN_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_ERROR 7:7 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_ERROR_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_ERROR_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_AWAKEN 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_AWAKEN_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_AWAKEN_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_AWAKEN_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_WIN_SEM 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_WIN_SEM_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_WIN_SEM_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_WIN_SEM_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_WRBK_SEM 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_WRBK_SEM_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_WRBK_SEM_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_CTRL_DISP_WRBK_SEM_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR 0x00611E34 /* RW-4R */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_SOR_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_INIT 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_NOP 0x00000000 /* */
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#define NV_PDISP_FE_PMU_FWD2GSP_OR_DSI_OP_DONE_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING(i) (0x00611E40+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_LOADV 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_LOADV_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_LOADV_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_LOADV_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_LAST_DATA_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_LAST_DATA_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_VBLANK 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_VBLANK_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_VBLANK_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_VBLANK_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_VACTIVE_SPACE_VBLANK_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_VACTIVE_SPACE_VBLANK_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_STALL_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_STALL_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_STALL_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_LINE_A_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_LINE_A_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_LINE_A_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_LINE_B_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_LINE_B_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_LINE_B_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_SEC_POLICY_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_SEC_POLICY_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_SEC_POLICY_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_HEAD_TIMING_RG_SEM_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN 0x00611E64 /* RW-4R */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_8_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_8_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_8_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_9_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_9_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_9_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_10_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_10_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_10_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_11_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_11_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_11_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_12_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_12_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_12_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_13_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_13_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_13_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_14_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_14_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_14_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_15_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_15_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_15_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_16_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_16_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_16_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_17_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_17_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_17_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_18_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_18_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_18_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_19_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_19_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_19_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_20_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_20_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_20_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_21_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_21_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_21_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_22_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_22_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_22_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_23_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_23_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_23_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_24_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_24_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_24_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_25_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_25_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_25_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_26_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_26_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_26_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_27_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_27_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_27_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_28_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_28_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_28_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_29_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_29_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_29_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_30_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_30_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_30_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_31_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_31_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_31_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WIN_CH_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM 0x00611E68 /* RW-4R */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_8_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_8_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_8_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_9_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_9_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_9_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_10_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_10_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_10_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_11_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_11_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_11_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_12_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_12_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_12_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_13_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_13_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_13_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_14_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_14_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_14_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_15_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_15_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_15_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_16_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_16_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_16_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_17_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_17_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_17_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_18_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_18_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_18_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_19_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_19_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_19_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_20_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_20_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_20_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_21_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_21_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_21_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_22_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_22_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_22_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_23_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_23_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_23_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_24_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_24_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_24_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_25_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_25_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_25_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_26_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_26_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_26_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_27_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_27_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_27_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_28_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_28_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_28_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_29_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_29_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_29_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_30_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_30_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_30_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_31_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_31_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_31_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_WINIM_CH_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER 0x00611E6C /* RW-4R */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CORE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CORE_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CORE_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_WRBK_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_EXC_OTHER_CURS_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP 0x00611E70 /* RW-4R */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SUPERVISOR_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_VBIOS_RELEASE_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_VBIOS_RELEASE_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SW_GENERIC_A_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SW_GENERIC_A_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SW_GENERIC_A_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SW_GENERIC_B_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SW_GENERIC_B_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_SW_GENERIC_B_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_MSF_PIN_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_MSF_PIN_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_MSF_PIN_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_ERROR 7:7 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_ERROR_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_ERROR_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_AWAKEN 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_AWAKEN_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_AWAKEN_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_AWAKEN_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_WIN_SEM 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_WIN_SEM_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_WIN_SEM_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_WIN_SEM_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_WRBK_SEM 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_WRBK_SEM_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_WRBK_SEM_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_CTRL_DISP_WRBK_SEM_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR 0x00611E74 /* RW-4R */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_SOR_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2RM_OR_DSI_OP_DONE_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING(i) (0x00611E80+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_LOADV 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_LOADV_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_LOADV_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_LOADV_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_LAST_DATA 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_LAST_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_LAST_DATA_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_LAST_DATA_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_VBLANK 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_VBLANK_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_VBLANK_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_VBLANK_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_VACTIVE_SPACE_VBLANK 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_VACTIVE_SPACE_VBLANK_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_VACTIVE_SPACE_VBLANK_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_VACTIVE_SPACE_VBLANK_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_STALL 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_STALL_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_STALL_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_STALL_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_LINE_A 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_LINE_A_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_LINE_A_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_LINE_A_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_LINE_B 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_LINE_B_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_LINE_B_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_LINE_B_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_SEC_POLICY 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_SEC_POLICY_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_SEC_POLICY_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_SEC_POLICY_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM__SIZE_1 6 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_HEAD_TIMING_RG_SEM_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN 0x00611EA4 /* RW-4R */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_8_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_8_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_8_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_9_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_9_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_9_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_10_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_10_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_10_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_11_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_11_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_11_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_12_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_12_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_12_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_13_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_13_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_13_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_14_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_14_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_14_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_15_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_15_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_15_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_16_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_16_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_16_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_17_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_17_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_17_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_18_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_18_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_18_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_19_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_19_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_19_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_20_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_20_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_20_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_21_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_21_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_21_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_22_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_22_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_22_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_23_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_23_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_23_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_24_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_24_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_24_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_25_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_25_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_25_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_26_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_26_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_26_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_27_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_27_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_27_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_28_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_28_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_28_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_29_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_29_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_29_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_30_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_30_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_30_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_31_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_31_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_31_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WIN_CH_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM 0x00611EA8 /* RW-4R */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_8 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_8_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_8_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_8_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_9 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_9_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_9_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_9_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_10 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_10_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_10_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_10_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_11 11:11 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_11_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_11_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_11_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_12 12:12 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_12_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_12_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_12_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_13 13:13 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_13_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_13_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_13_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_14 14:14 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_14_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_14_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_14_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_15 15:15 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_15_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_15_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_15_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_16 16:16 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_16_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_16_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_16_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_17 17:17 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_17_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_17_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_17_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_18 18:18 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_18_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_18_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_18_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_19 19:19 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_19_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_19_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_19_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_20 20:20 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_20_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_20_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_20_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_21 21:21 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_21_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_21_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_21_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_22 22:22 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_22_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_22_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_22_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_23 23:23 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_23_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_23_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_23_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_24 24:24 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_24_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_24_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_24_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_25 25:25 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_25_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_25_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_25_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_26 26:26 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_26_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_26_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_26_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_27 27:27 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_27_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_27_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_27_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_28 28:28 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_28_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_28_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_28_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_29 29:29 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_29_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_29_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_29_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_30 30:30 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_30_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_30_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_30_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_31 31:31 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_31_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_31_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_31_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH__SIZE_1 32 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_WINIM_CH_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER 0x00611EAC /* RW-4R */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CORE 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CORE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CORE_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CORE_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_4 12:12 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_5 13:13 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_6 14:14 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_7 15:15 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_WRBK_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_0 16:16 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_1 17:17 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_2 18:18 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_3 19:19 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_4 20:20 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_5 21:21 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_6 22:22 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_7 23:23 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS(i) (16+(i)):(16+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_EXC_OTHER_CURS_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP 0x00611EB0 /* RW-4R */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR1 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR2 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR3 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR__SIZE_1 3 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SUPERVISOR_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_VBIOS_RELEASE 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_VBIOS_RELEASE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_VBIOS_RELEASE_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_VBIOS_RELEASE_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SW_GENERIC_A 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SW_GENERIC_A_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SW_GENERIC_A_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SW_GENERIC_A_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SW_GENERIC_B 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SW_GENERIC_B_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SW_GENERIC_B_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_SW_GENERIC_B_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_MSF_PIN 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_MSF_PIN_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_MSF_PIN_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_MSF_PIN_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_ERROR 7:7 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_ERROR_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_ERROR_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_AWAKEN 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_AWAKEN_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_AWAKEN_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_AWAKEN_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_WIN_SEM 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_WIN_SEM_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_WIN_SEM_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_WIN_SEM_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_WRBK_SEM 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_WRBK_SEM_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_WRBK_SEM_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_CTRL_DISP_WRBK_SEM_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR 0x00611EB4 /* RW-4R */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_0 0:0 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_1 1:1 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_2 2:2 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_3 3:3 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_4 4:4 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_4_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_4_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_4_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_5 5:5 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_5_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_5_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_5_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_6 6:6 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_6_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_6_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_6_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_7 7:7 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_7_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_7_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_7_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_SOR_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_0 8:8 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_0_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_0_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_1 9:9 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_1_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_1_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_2 10:10 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_2_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_2_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_2_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_3 11:11 /* RWIVF */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_3_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_3_NOP 0x00000000 /* RW--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_3_FORWARD 0x00000001 /* -W--V */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE(i) (8+(i)):(8+(i)) /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE__SIZE_1 4 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_INIT 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_NOP 0x00000000 /* */
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#define NV_PDISP_FE_GSP_FWD2PMU_OR_DSI_OP_DONE_FORWARD 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_DISPATCH 0x00611EC0 /* R--4R */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_0 0:0 /* R--VF */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_1 1:1 /* R--VF */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_2 2:2 /* R--VF */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_3 3:3 /* R--VF */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_4 4:4 /* R--VF */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_5 5:5 /* R--VF */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_6 6:6 /* R--VF */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_7 7:7 /* R--VF */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_HEAD_TIMING_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WIN 9:9 /* R--VF */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WIN_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WIN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WINIM 10:10 /* R--VF */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WINIM_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_WINIM_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_OTHER 11:11 /* R--VF */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_OTHER_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_EXC_OTHER_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_CTRL_DISP 12:12 /* R--VF */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_CTRL_DISP_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_CTRL_DISP_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_OR 13:13 /* R--VF */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_OR_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_RM_INTR_DISPATCH_OR_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH 0x00611EC4 /* R--4R */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_0 0:0 /* R--VF */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_1 1:1 /* R--VF */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_2 2:2 /* R--VF */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_3 3:3 /* R--VF */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_4 4:4 /* R--VF */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_5 5:5 /* R--VF */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_6 6:6 /* R--VF */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_7 7:7 /* R--VF */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_HEAD_TIMING_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_EXC_WIN 9:9 /* R--VF */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_EXC_WIN_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_EXC_WIN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_EXC_WINIM 10:10 /* R--VF */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_EXC_WINIM_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_EXC_WINIM_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_EXC_OTHER 11:11 /* R--VF */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_EXC_OTHER_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_EXC_OTHER_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_CTRL_DISP 12:12 /* R--VF */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_CTRL_DISP_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_CTRL_DISP_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_OR 13:13 /* R--VF */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_OR_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_PMU_INTR_DISPATCH_OR_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH 0x00611EC8 /* R--4R */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_0 0:0 /* R--VF */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_0_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_1 1:1 /* R--VF */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_1_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_2 2:2 /* R--VF */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_2_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_3 3:3 /* R--VF */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_3_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_4 4:4 /* R--VF */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_4_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_5 5:5 /* R--VF */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_5_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_6 6:6 /* R--VF */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_6_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_7 7:7 /* R--VF */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_7_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING(i) (0+(i)):(0+(i)) /* */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING__SIZE_1 8 /* */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_NOT_PENDING 0x00000000 /* */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_HEAD_TIMING_PENDING 0x00000001 /* */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_EXC_WIN 9:9 /* R--VF */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_EXC_WIN_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_EXC_WIN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_EXC_WINIM 10:10 /* R--VF */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_EXC_WINIM_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_EXC_WINIM_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_EXC_OTHER 11:11 /* R--VF */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_EXC_OTHER_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_EXC_OTHER_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_CTRL_DISP 12:12 /* R--VF */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_CTRL_DISP_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_CTRL_DISP_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_OR 13:13 /* R--VF */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_OR_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PDISP_FE_GSP_INTR_DISPATCH_OR_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK 0x00612204 /* RW-4R */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_RG(i) (0x00612200+(i)*2048) /* RW-4A */
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#define NV_PDISP_FE_CMGR_CLK_RG__SIZE_1 8 /* */
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#define NV_PDISP_FE_CMGR_CLK_RG__PRIV_LEVEL_MASK 0x00612204 /* */
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#define NV_PDISP_FE_CMGR_CLK_RG_MODE 7:6 /* R--VF */
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#define NV_PDISP_FE_CMGR_CLK_RG_MODE_NORMAL 0x00000001 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_RG_MODE_SAFE 0x00000002 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_RG_FORCE_SAFE 11:11 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_RG_FORCE_SAFE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_RG_FORCE_SAFE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_RG_FORCE_SAFE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_RG_STATE 23:23 /* R--VF */
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#define NV_PDISP_FE_CMGR_CLK_RG_STATE_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_RG_STATE_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR(i) (0x00612300+(i)*2048) /* RW-4A */
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#define NV_PDISP_FE_CMGR_CLK_SOR__SIZE_1 8 /* */
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#define NV_PDISP_FE_CMGR_CLK_SOR__PRIV_LEVEL_MASK 0x00612204 /* */
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#define NV_PDISP_FE_CMGR_CLK_SOR_MODE 7:6 /* R--VF */
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#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_NORMAL 0x00000001 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_SAFE 0x00000002 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD 15:12 /* R--VF */
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#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_NONE 0x0000000F /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_0 0x00000000 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_1 0x00000001 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_2 0x00000002 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_3 0x00000003 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_4 0x00000004 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_5 0x00000005 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_6 0x00000006 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_HEAD_7 0x00000007 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS 17:16 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_INIT 0x00000002 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_DP_NORMAL 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_DP_SAFE 0x00000002 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_FEEDBACK 0x00000003 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_FRL_NORMAL 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_MODE_BYPASS_FRL_SAFE 0x00000002 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED 22:18 /* RWIUF */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_DP_1_62GHZ 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_DP_2_70GHZ 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_DP_5_40GHZ 0x00000002 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_DP_8_10GHZ 0x00000003 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_2_16GHZ 0x00000004 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_2_43GHZ 0x00000005 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_3_24GHZ 0x00000006 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_4_32GHZ 0x00000007 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_TMDS_0_25_TO_0_85GHZ 0x00000008 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_TMDS_0_50_TO_1_70GHZ 0x00000009 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_TMDS_1_00_TO_3_40GHZ 0x0000000a /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_TMDS_3_40_TO_6_00GHZ 0x0000000b /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_HDMI_FRL_3G 0x0000000c /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_HDMI_FRL_6G 0x0000000d /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_HDMI_FRL_8G 0x0000000e /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_HDMI_FRL_10G 0x0000000f /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_HDMI_FRL_12G 0x00000010 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_6_75GHZ 0x00000011 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_6_48GHZ 0x00000012 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_LINK_SPEED_EDP_5_94GHZ 0x00000013 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_STATE 23:23 /* R--VF */
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#define NV_PDISP_FE_CMGR_CLK_SOR_STATE_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_STATE_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE 25:24 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_SINGLE_PCLK 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_DIFF_PCLK 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_SINGLE_DPCLK 0x00000002 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CLK_SOURCE_DIFF_DPCLK 0x00000003 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL(i) (0x00612304+(i)*2048) /* RW-4A */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL__SIZE_1 8 /* */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL__PRIV_LEVEL_MASK 0x00612204 /* */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR 2:2 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE 5:3 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPA 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPB 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPC 0x00000002 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPD 0x00000003 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPE 0x00000004 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPF 0x00000005 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SOR_CTRL_FDBKCLK_OVR_MODE_IFPG 0x00000006 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL(i) (0x00612308+(i)*128) /* RW-4A */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL__SIZE_1 6 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL__PRIV_LEVEL_MASK 0x00612204 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND 3:0 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR0 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR1 0x00000002 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR2 0x00000003 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR3 0x00000004 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR4 0x00000005 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR5 0x00000006 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR6 0x00000007 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR7 0x00000008 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR 4:4 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR_PRIMARY 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_FRONTEND_SOR_SECONDARY 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_CAL_SEL 5:5 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_CAL_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_CAL_SEL_PRIMARY 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_CAL_SEL_SECONDARY 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_CAL_EN 6:6 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_CAL_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_CAL_EN_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_CAL_EN_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_COMPOUT 7:7 /* R--VF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_COMPOUT_LOW 0x00000000 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_COMPOUT_HIGH 0x00000001 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TMDS_TERMADJ 11:8 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TMDS_TERMADJ_INIT 0x00000008 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TMDS_TERMADJ_500OHM 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_EN 12:12 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_EN_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TERM_EN_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_MODE 16:16 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_DIV 17:17 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_DIV_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_SEL 20:18 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_PRBS_SEL 22:21 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_PRBS_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_CLK_EN_DIFF_DET 23:23 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_CLK_EN_DIFF_DET_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_PHY_TYPE 24:24 /* R--VF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_PHY_TYPE_DP 0x00000000 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_PHY_TYPE_USB 0x00000001 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_BITS_CHECKER 25:25 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_CTRL_TX_PATT_GEN_BITS_CHECKER_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK 0x00612310 /* RW-4R */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_PMU_ENABLED 0x00000046 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL(i) (0x0061230C+(i)*128) /* RW-4A */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL__SIZE_1 6 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL__PRIV_LEVEL_MASK 0x00612310 /* */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD10_LEVEL 3:0 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD10_LEVEL_INIT 0x00000004 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD10_LEVEL_0_80V 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD10_LEVEL_0_85V 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD10_LEVEL_0_90V 0x00000002 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD10_LEVEL_0_95V 0x00000003 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD10_LEVEL_1_00V 0x00000004 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD10_LEVEL_1_05V 0x00000005 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD10_LEVEL_1_10V 0x00000006 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD10_LEVEL_1_15V 0x00000007 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_BG_TEMP_COEFF 7:4 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_BG_TEMP_COEFF_INIT 0x00000003 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD09_LEVEL 11:8 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD09_LEVEL_INIT 0x00000004 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD09_LEVEL_0_72V 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD09_LEVEL_0_765V 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD09_LEVEL_0_81V 0x00000002 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD09_LEVEL_0_855V 0x00000003 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD09_LEVEL_0_90V 0x00000004 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD09_LEVEL_0_945V 0x00000005 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_LINK_SEC_CTRL_AVDD09_LEVEL_0_99V 0x00000006 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SF(i) (0x00612420+(i)*2048) /* RW-4A */
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#define NV_PDISP_FE_CMGR_CLK_SF__SIZE_1 8 /* */
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#define NV_PDISP_FE_CMGR_CLK_SF__PRIV_LEVEL_MASK 0x00612204 /* */
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#define NV_PDISP_FE_CMGR_CLK_SF_MODE 7:6 /* R--VF */
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#define NV_PDISP_FE_CMGR_CLK_SF_MODE_NORMAL 0x00000001 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SF_MODE_SAFE 0x00000002 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SOR 15:12 /* R--VF */
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#define NV_PDISP_FE_CMGR_CLK_SF_SOR_NONE 0x0000000F /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SOR_0 0x00000000 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SOR_1 0x00000001 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SOR_2 0x00000002 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SOR_3 0x00000003 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SOR_4 0x00000004 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SOR_5 0x00000005 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SOR_6 0x00000006 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SOR_7 0x00000007 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SAFE_CTRL 17:16 /* RWIVF */
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#define NV_PDISP_FE_CMGR_CLK_SF_SAFE_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SAFE_CTRL_CMGR 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SAFE_CTRL_BYPASS 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SAFE_CTRL_SOR 0x00000002 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SF_SAFE_CTRL_SAFE 0x00000003 /* RW--V */
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#define NV_PDISP_FE_CMGR_CLK_SF_STATE 23:23 /* R--VF */
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#define NV_PDISP_FE_CMGR_CLK_SF_STATE_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_FE_CMGR_CLK_SF_STATE_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY(i) (0x0061204C+(i)*2048) /* RW-4A */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY__SIZE_1 8 /* */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_VALUE 15:0 /* RWIVF */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_WRITE_MODE 28:28 /* RWIVF */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_WRITE_MODE_ACTIVE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_WRITE_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_WRITE_MODE_ASSEMBLY 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_UPDATE 29:29 /* RWIVF */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_UPDATE_IMMEDIATE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_UPDATE_CORE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_STATUS 31:30 /* R-IVF */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_STATUS_ACTIVE 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_STATUS_ARMED 0x00000001 /* R---V */
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#define NV_PDISP_FE_CONTINUOUS_START_DELAY_STATUS_ASSEMBLY 0x00000002 /* R---V */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY(i) (0x00612054+(i)*2048) /* RW-4A */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY__SIZE_1 8 /* */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_VALUE 15:0 /* RWIVF */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_WRITE_MODE 28:28 /* RWIVF */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_WRITE_MODE_ACTIVE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_WRITE_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_WRITE_MODE_ASSEMBLY 0x00000001 /* RW--V */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_UPDATE 29:29 /* RWIVF */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_UPDATE_IMMEDIATE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_UPDATE_CORE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_STATUS 31:30 /* R--VF */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_STATUS_ACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_STATUS_ARMED 0x00000001 /* R---V */
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#define NV_PDISP_FE_ONE_SHOT_START_DELAY_STATUS_ASSEMBLY 0x00000002 /* R---V */
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#define NV_PDISP_FE_ELV_BLOCK(i) (0x00612068+(i)*2048) /* RW-4A */
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#define NV_PDISP_FE_ELV_BLOCK__SIZE_1 8 /* */
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#define NV_PDISP_FE_ELV_BLOCK_CTRL 0:0 /* RWIVF */
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#define NV_PDISP_FE_ELV_BLOCK_CTRL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_ELV_BLOCK_CTRL_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_ELV_BLOCK_CTRL_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV 1:1 /* RWIVF */
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#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV_DONE 0x00000000 /* R---V */
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#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_ELV_BLOCK_ALLOW_ONE_ELV_TRIGGER 0x00000001 /* -W--V */
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#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV 2:2 /* RWIVF */
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#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV_DONE 0x00000000 /* R---V */
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#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_FE_ELV_BLOCK_RELEASE_ONE_SHOT_ELV_TRIGGER 0x00000001 /* -W--V */
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#define NV_PDISP_FE_FLIPLOCK 0x0061206C /* RW-4R */
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#define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME 23:0 /* RWIVF */
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#define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME_INIT 0x00000080 /* RWI-V */
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#define NV_PDISP_FE_FLIPLOCK_LSR_MIN_TIME_32NS 0x00000020 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP 0x00640000 /* RW-4R */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD0_EXISTS 0:0 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD0_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD0_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD0_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD1_EXISTS 1:1 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD1_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD1_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD1_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD2_EXISTS 2:2 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD2_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD2_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD2_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD3_EXISTS 3:3 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD3_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD3_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD3_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD4_EXISTS 4:4 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD4_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD4_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD4_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD5_EXISTS 5:5 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD5_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD5_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD5_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD6_EXISTS 6:6 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD6_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD6_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD6_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD7_EXISTS 7:7 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD7_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD7_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD7_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS__SIZE_1 8 /* */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_HEAD_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR0_EXISTS 8:8 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR0_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR0_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR0_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR1_EXISTS 9:9 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR1_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR1_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR1_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR2_EXISTS 10:10 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR2_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR2_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR2_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR3_EXISTS 11:11 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR3_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR3_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR3_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR4_EXISTS 12:12 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR4_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR4_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR4_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR5_EXISTS 13:13 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR5_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR5_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR5_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR6_EXISTS 14:14 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR6_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR6_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR6_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR7_EXISTS 15:15 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR7_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR7_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR7_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS(i) (8+(i)):(8+(i)) /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS__SIZE_1 8 /* */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAP_SOR_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB 0x00640004 /* RW-4R */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW0_EXISTS 0:0 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW0_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW0_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW0_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW1_EXISTS 1:1 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW1_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW1_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW1_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW2_EXISTS 2:2 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW2_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW2_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW2_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW3_EXISTS 3:3 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW3_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW3_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW3_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW4_EXISTS 4:4 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW4_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW4_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW4_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW5_EXISTS 5:5 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW5_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW5_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW5_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW6_EXISTS 6:6 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW6_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW6_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW6_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW7_EXISTS 7:7 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW7_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW7_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW7_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW8_EXISTS 8:8 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW8_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW8_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW8_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW9_EXISTS 9:9 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW9_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW9_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW9_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW10_EXISTS 10:10 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW10_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW10_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW10_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW11_EXISTS 11:11 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW11_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW11_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW11_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW12_EXISTS 12:12 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW12_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW12_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW12_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW13_EXISTS 13:13 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW13_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW13_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW13_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW14_EXISTS 14:14 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW14_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW14_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW14_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW15_EXISTS 15:15 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW15_EXISTS_INIT 0x00000000 /* RWI-V */
|
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW15_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW15_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW16_EXISTS 16:16 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW16_EXISTS_INIT 0x00000000 /* RWI-V */
|
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW16_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW16_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW17_EXISTS 17:17 /* RWIVF */
|
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW17_EXISTS_INIT 0x00000000 /* RWI-V */
|
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW17_EXISTS_NO 0x00000000 /* RW--V */
|
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW17_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW18_EXISTS 18:18 /* RWIVF */
|
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW18_EXISTS_INIT 0x00000000 /* RWI-V */
|
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW18_EXISTS_NO 0x00000000 /* RW--V */
|
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW18_EXISTS_YES 0x00000001 /* RW--V */
|
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW19_EXISTS 19:19 /* RWIVF */
|
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW19_EXISTS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW19_EXISTS_NO 0x00000000 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW19_EXISTS_YES 0x00000001 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW20_EXISTS 20:20 /* RWIVF */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW20_EXISTS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW20_EXISTS_NO 0x00000000 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW20_EXISTS_YES 0x00000001 /* RW--V */
|
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW21_EXISTS 21:21 /* RWIVF */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW21_EXISTS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW21_EXISTS_NO 0x00000000 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW21_EXISTS_YES 0x00000001 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW22_EXISTS 22:22 /* RWIVF */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW22_EXISTS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW22_EXISTS_NO 0x00000000 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW22_EXISTS_YES 0x00000001 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW23_EXISTS 23:23 /* RWIVF */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW23_EXISTS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW23_EXISTS_NO 0x00000000 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW23_EXISTS_YES 0x00000001 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW24_EXISTS 24:24 /* RWIVF */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW24_EXISTS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW24_EXISTS_NO 0x00000000 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW24_EXISTS_YES 0x00000001 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW25_EXISTS 25:25 /* RWIVF */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW25_EXISTS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW25_EXISTS_NO 0x00000000 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW25_EXISTS_YES 0x00000001 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW26_EXISTS 26:26 /* RWIVF */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW26_EXISTS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW26_EXISTS_NO 0x00000000 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW26_EXISTS_YES 0x00000001 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW27_EXISTS 27:27 /* RWIVF */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW27_EXISTS_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW27_EXISTS_NO 0x00000000 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW27_EXISTS_YES 0x00000001 /* RW--V */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW28_EXISTS 28:28 /* RWIVF */
|
|
#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW28_EXISTS_INIT 0x00000000 /* RWI-V */
|
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW28_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW28_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW29_EXISTS 29:29 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW29_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW29_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW29_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW30_EXISTS 30:30 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW30_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW30_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW30_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW31_EXISTS 31:31 /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW31_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW31_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW31_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS(i) (0+(i)):(0+(i)) /* RWIVF */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS__SIZE_1 32 /* */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS_NO 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SYS_CAPB_WINDOW_EXISTS_YES 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_LOCK_PIN_CAP 0x00640008 /* RW-4R */
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#define NV_PDISP_FE_SW_LOCK_PIN_CAP_FLIP_LOCK_PINS 3:0 /* RWIVF */
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#define NV_PDISP_FE_SW_LOCK_PIN_CAP_FLIP_LOCK_PINS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_LOCK_PIN_CAP_SCAN_LOCK_PINS 7:4 /* RWIVF */
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#define NV_PDISP_FE_SW_LOCK_PIN_CAP_SCAN_LOCK_PINS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_LOCK_PIN_CAP_STEREO_PINS 11:8 /* RWIVF */
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#define NV_PDISP_FE_SW_LOCK_PIN_CAP_STEREO_PINS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA 0x00640010 /* RW-4R */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* RWIUF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ROTATION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_PLANAR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_VGA_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MSCG_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ASR 24:24 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ASR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ASR_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_ASR_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_CDE 25:25 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_CDE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_CDE_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_CDE_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT 26:26 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_SUPPORT_LATENCY_EVENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPB 0x00640014 /* RW-4R */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC 0x00640018 /* RW-4R */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE 10:8 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_ONE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_TWO 0x00000002 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_THREE 0x00000003 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_CLEAR_RECTANGLES_PER_SURFACE_FOUR 0x00000004 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* RWIVF */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA(i) (0x00640680+(i)*32) /* RW-4A */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA__SIZE_1 8 /* */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT 16:16 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT 17:17 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT 18:18 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT 19:19 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT 20:20 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT 21:21 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT 22:22 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT 23:23 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT 24:24 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB(i) (0x00640684+(i)*32) /* RW-4A */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB__SIZE_1 8 /* */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_VGA 0:0 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_VGA_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_VGA_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_VGA_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ 9:6 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR 12:10 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD 14:14 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_INIT 0x00000000 /* RWI-V */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT 15:15 /* RWIVF */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* RW--V */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* RW--V */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC(i) (0x00640688+(i)*32) /* RW-4A */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC__SIZE_1 8 /* */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION 4:0 /* RWIVF */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION_INIT 0x00000000 /* RWI-V */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* RWIVF */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE_INIT 0x00000000 /* RWI-V */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION 12:8 /* RWIVF */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION_INIT 0x00000000 /* RWI-V */
|
|
#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* RWIVF */
|
|
#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE_INIT 0x00000000 /* RWI-V */
|
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPD(i) (0x0064068C+(i)*32) /* RW-4A */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPD__SIZE_1 8 /* */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE(i) (0x00640690+(i)*32) /* RW-4A */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE__SIZE_1 8 /* */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE 3:0 /* RWIUF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE 13:8 /* RWIUF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422 16:16 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420 17:17 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPF(i) (0x00640694+(i)*32) /* RW-4A */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPF__SIZE_1 8 /* */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* RWIVF */
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#define NV_PDISP_FE_SW_POSTCOMP_HEAD_HDR_CAPF_VFILTER_MAX_PIXELS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_HEAD_RG_CAPA(i) (0x00640048+(i)*16) /* RW-4A */
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#define NV_PDISP_FE_SW_HEAD_RG_CAPA__SIZE_1 8 /* */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA(i) (0x006400C0+(i)*16) /* RW-4A */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA__SIZE_1 8 /* */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI(i) (i):(i) /* RWIUF */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI__SIZE_1 4 /* */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI0 0:0 /* RWIUF */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI0_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI0_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI1 1:1 /* RWIUF */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI1_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI1_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI2 2:2 /* RWIUF */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI2_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI2_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI3 3:3 /* RWIUF */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI3_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_HEAD_SF_CAPA_SUPPORT_DSI3_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP(i) (0x00640144+(i)*8) /* RW-4A */
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#define NV_PDISP_FE_SW_SOR_CAP__SIZE_1 8 /* */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_18 0:0 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_18_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_24 1:1 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_24_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_18 2:2 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_18_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_24 3:3 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_24_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_A 8:8 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_A_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_B 9:9 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_B_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DUAL_TMDS 11:11 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_DUAL_TMDS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_DISPLAY_OVER_PCIE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_OVER_USB 14:14 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_OVER_USB_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_OVER_USB_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_OVER_USB_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_SDI 16:16 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_SDI_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_SDI_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_SDI_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_A 24:24 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_A_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_A_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_A_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_B 25:25 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_B_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_B_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_B_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_INTERLACE 26:26 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_INTERLACE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_8_LANES 27:27 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_8_LANES_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_HDMI_FRL 28:28 /* RWIVF */
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#define NV_PDISP_FE_SW_SOR_CAP_HDMI_FRL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x00640780+(i)*32) /* RW-4A */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x00640784+(i)*32) /* RW-4A */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x00640788+(i)*32) /* RW-4A */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ 9:6 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR 12:10 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD 14:14 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x0064078C+(i)*32) /* RW-4A */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x00640790+(i)*32) /* RW-4A */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ 9:6 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR 12:10 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD 14:14 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x00640794+(i)*32) /* RW-4A */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* RWIVF */
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#define NV_PDISP_FE_SW_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CLK_CAP(i) (0x00640608+(i)*4) /* RW-4A */
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#define NV_PDISP_FE_SW_SOR_CLK_CAP__SIZE_1 8 /* */
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#define NV_PDISP_FE_SW_SOR_CLK_CAP_DP_MAX 7:0 /* RWIUF */
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#define NV_PDISP_FE_SW_SOR_CLK_CAP_DP_MAX_INIT 0x00000051 /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CLK_CAP_TMDS_MAX 23:16 /* RWIUF */
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#define NV_PDISP_FE_SW_SOR_CLK_CAP_TMDS_MAX_INIT 0x0000003C /* RWI-V */
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#define NV_PDISP_FE_SW_SOR_CLK_CAP_LVDS_MAX 31:24 /* RWIUF */
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#define NV_PDISP_FE_SW_SOR_CLK_CAP_LVDS_MAX_INIT 0x00000000 /* RWI-V */
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#define NV_UDISP_HASH 0x00001FFF:0x00000000 /* RW--M */
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#define NV_UDISP_HASH_BASE 0x00000000 /* */
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#define NV_UDISP_HASH_LIMIT 0x00001FFF /* */
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#define NV_UDISP_OBJ_MEM 0x0000FFFF:0x00002000 /* RW--M */
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#define NV_UDISP_OBJ_MEM_BASE 0x00002000 /* */
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#define NV_UDISP_OBJ_MEM_LIMIT 0x0000FFFF /* */
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#define NV_UDISP_HASH_TBL /* ----G */
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#define NV_UDISP_HASH_TBL_HANDLE (0*32+31):(0*32+0) /* RWXVF */
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#define NV_UDISP_HASH_TBL_CLIENT_ID (1*32+13):(1*32+0) /* RWXVF */
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#define NV_UDISP_HASH_TBL_INSTANCE (1*32+24):(1*32+14) /* RWXUF */
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#define NV_UDISP_HASH_TBL_INSTANCE_INVALID 0x00000000 /* RW--V */
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#define NV_UDISP_HASH_TBL_CHN (1*32+31):(1*32+25) /* RWXUF */
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#define NV_DMA /* ----G */
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#define NV_DMA_TARGET_NODE (0*32+1):(0*32+0) /* RWXVF */
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#define NV_DMA_TARGET_NODE_PHYSICAL_NVM 0x00000001 /* RW--V */
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#define NV_DMA_TARGET_NODE_PHYSICAL_PCI 0x00000002 /* RW--V */
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#define NV_DMA_TARGET_NODE_PHYSICAL_PCI_COHERENT 0x00000003 /* RW--V */
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#define NV_DMA_ACCESS (0*32+2):(0*32+2) /* RWXVF */
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#define NV_DMA_ACCESS_READ_ONLY 0x00000000 /* RW--V */
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#define NV_DMA_ACCESS_READ_AND_WRITE 0x00000001 /* RW--V */
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#define NV_DMA_PAGE_SIZE (0*32+6):(0*32+6) /* RWXUF */
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#define NV_DMA_PAGE_SIZE_BIG 0x00000000 /* RW--V */
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#define NV_DMA_PAGE_SIZE_SMALL 0x00000001 /* RW--V */
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#define NV_DMA_KIND (0*32+20):(0*32+20) /* RWXVF */
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#define NV_DMA_KIND_PITCH 0x00000000 /* RW--V */
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#define NV_DMA_KIND_BLOCKLINEAR 0x00000001 /* RW--V */
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#define NV_DMA_ADDRESS_BASE_LO (1*32+31):(1*32+0) /* RWXUF */
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#define NV_DMA_ADDRESS_BASE_HI (2*32+6):(2*32+0) /* RWXUF */
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#define NV_DMA_ADDRESS_LIMIT_LO (3*32+31):(3*32+0) /* RWXUF */
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#define NV_DMA_ADDRESS_LIMIT_HI (4*32+6):(4*32+0) /* RWXUF */
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#define NV_DMA_SIZE 20 /* */
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#define NV_DMA_ALIGN 32 /* */
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#define NV_DMA_ADDRESS_BASE_SHIFT 8 /* */
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#define NV_PDISP_IHUB_COMMON_CAPA 0x0062E000 /* R--4R */
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#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRIES 15:0 /* R--UF */
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#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH 17:16 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_32B 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_64B 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_128B 0x00000002 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_MEMPOOL_ENTRY_WIDTH_256B 0x00000003 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_ROTATION 18:18 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_ROTATION_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_ROTATION_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_PLANAR 19:19 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_PLANAR_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_PLANAR_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_VGA 20:20 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_VGA_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_VGA_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION 21:21 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_MEMPOOL_COMPRESSION_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_MSCG 22:22 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_MSCG_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_MSCG_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH 23:23 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_SUPPORT_MCLK_SWITCH_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_ROTATION 29:28 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_ROTATION_16B 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_ROTATION_32B 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_ROTATION_64B 0x00000002 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_ROTATION_128B 0x00000003 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION 31:30 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_32B 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_64B 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_128B 0x00000002 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPA_REQUEST_SIZE_PER_LINE_NON_ROTATION_256B 0x00000003 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPB 0x0062E004 /* R--4R */
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#define NV_PDISP_IHUB_COMMON_CAPB_MAX_PLANAR_ROTATION_THREAD_GROUPS 5:0 /* R--UF */
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#define NV_PDISP_IHUB_COMMON_CAPB_MAX_SEMI_PLANAR_ROTATION_THREAD_GROUPS 11:6 /* R--UF */
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#define NV_PDISP_IHUB_COMMON_CAPB_MAX_PACKED_2BPP_ROTATION_THREAD_GROUPS 17:12 /* R--UF */
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#define NV_PDISP_IHUB_COMMON_CAPB_MAX_PACKED_1BPP_ROTATION_THREAD_GROUPS 23:18 /* R--UF */
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#define NV_PDISP_IHUB_COMMON_CAPB_MAX_PACKED_422_ROTATION_THREAD_GROUPS 29:24 /* R--UF */
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#define NV_PDISP_IHUB_COMMON_CAPC 0x0062E008 /* R--4R */
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#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE 1:0 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_32B 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_64B 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_128B 0x00000002 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPC_PITCH_REQUEST_SIZE_256B 0x00000003 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED 6:4 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_NONE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_TWO 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_FOUR 0x00000002 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_EIGHT 0x00000003 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPC_MAX_LINES_BUFFERED_SIXTEEN 0x00000004 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR 11:11 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPC_SUPPORT_SEMI_PLANAR_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP 12:12 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CAPC_SUPPORT_HOR_VER_FLIP_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_PM_GROUP 0x0062E118 /* RW-4R */
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#define NV_PDISP_IHUB_COMMON_PM_GROUP_SELECT 1:0 /* RWIUF */
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#define NV_PDISP_IHUB_COMMON_PM_GROUP_SELECT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_PM_GROUP_SELECT_UNDERFLOW 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_PM_GROUP_SELECT_MSCG 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_PM_GROUP_SELECT_MCLK_ASR 0x00000002 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_PM_CLIENT_SELECT 0x0062E120 /* RW-4R */
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#define NV_PDISP_IHUB_COMMON_PM_CLIENT_SELECT_WIN_MASK 7:0 /* RWIUF */
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#define NV_PDISP_IHUB_COMMON_PM_CLIENT_SELECT_WIN_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_PM_CLIENT_SELECT_HEAD_MASK 19:16 /* RWIUF */
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#define NV_PDISP_IHUB_COMMON_PM_CLIENT_SELECT_HEAD_MASK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL 0x0062E018 /* RW-4R */
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#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_HEAD_INSTANCE 7:5 /* RWIUF */
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#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_HEAD_INSTANCE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE 10:9 /* RWIVF */
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#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE_IMMEDIATE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE_STRICT 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_MODE_SEMI_STRICT 0x00000002 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE 31:31 /* RWIVF */
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#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE_DONE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_CONFIG_CONTROL_UPDATE_TRIGGER 0x00000001 /* -W--T */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL 0x0062E024 /* RW-4R */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_SWITCH 1:1 /* RWIVF */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_SWITCH_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_SWITCH_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_SWITCH_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_MSCG 2:2 /* RWIVF */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_MSCG_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_MSCG_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_MSCG_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_CRITICAL 5:5 /* RWIVF */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_CRITICAL_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_CRITICAL_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_CRITICAL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_CURSOR_COMPRESS 14:14 /* RWIVF */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_CURSOR_COMPRESS_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_CURSOR_COMPRESS_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_CURSOR_COMPRESS_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_COMPRESS_OPTIMIZE_LATENCY 15:15 /* RWIVF */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_COMPRESS_OPTIMIZE_LATENCY_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_COMPRESS_OPTIMIZE_LATENCY_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_COMPRESS_OPTIMIZE_LATENCY_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_NO_COMPRESS 16:16 /* RWIVF */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_NO_COMPRESS_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_NO_COMPRESS_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_NO_COMPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_DRAIN_METER 17:17 /* RWIVF */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_DRAIN_METER_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_DRAIN_METER_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_DRAIN_METER_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER_WAIT_FOR_TIMER_EXPIRY 29:29 /* RWIVF */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER_WAIT_FOR_TIMER_EXPIRY_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER_WAIT_FOR_TIMER_EXPIRY_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER_WAIT_FOR_TIMER_EXPIRY_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_REQ_LIMIT 30:30 /* RWIVF */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_REQ_LIMIT_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_REQ_LIMIT_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_REQ_LIMIT_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER 31:31 /* RWIVF */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MISC_CTL_FETCH_METER_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_MSCG_MIN_CYCLE_TIME 0x0062E100 /* RW-4R */
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#define NV_PDISP_IHUB_COMMON_MSCG_MIN_CYCLE_TIME_USEC 22:0 /* RWIUF */
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#define NV_PDISP_IHUB_COMMON_MSCG_MIN_CYCLE_TIME_USEC_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_MSCG_MIN_CYCLE_TIME_EXIT_USEC 31:23 /* RWIUF */
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#define NV_PDISP_IHUB_COMMON_MSCG_MIN_CYCLE_TIME_EXIT_USEC_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_MCLK_SWITCH_TIME 0x0062E104 /* RW-4R */
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#define NV_PDISP_IHUB_COMMON_MCLK_SWITCH_TIME_USEC 15:0 /* RWIUF */
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#define NV_PDISP_IHUB_COMMON_MCLK_SWITCH_TIME_USEC_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_ASR_MIN_CYCLE_TIME 0x0062E108 /* RW-4R */
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#define NV_PDISP_IHUB_COMMON_ASR_MIN_CYCLE_TIME_USEC 15:0 /* RWIUF */
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#define NV_PDISP_IHUB_COMMON_ASR_MIN_CYCLE_TIME_USEC_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_ASR_MIN_CYCLE_TIME_EXIT_USEC 31:24 /* RWIUF */
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#define NV_PDISP_IHUB_COMMON_ASR_MIN_CYCLE_TIME_EXIT_USEC_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_FETCH_METER_CYCLE_TIME 0x0062E110 /* RW-4R */
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#define NV_PDISP_IHUB_COMMON_FETCH_METER_CYCLE_TIME_108MHZ_CLK_COUNT 15:0 /* RWIUF */
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#define NV_PDISP_IHUB_COMMON_FETCH_METER_CYCLE_TIME_108MHZ_CLK_COUNT_INIT 0x00000008 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_FETCH_METER_CYCLE_TIME_UPDATE 16:16 /* RWIVF */
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#define NV_PDISP_IHUB_COMMON_FETCH_METER_CYCLE_TIME_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_COMMON_FETCH_METER_CYCLE_TIME_UPDATE_GLOBAL 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_COMMON_FETCH_METER_CYCLE_TIME_STATUS 31:31 /* R--VF */
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#define NV_PDISP_IHUB_COMMON_FETCH_METER_CYCLE_TIME_STATUS_DONE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_COMMON_FETCH_METER_CYCLE_TIME_STATUS_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_COMMON_QUEUEING_THRESHOLD 0x0062E114 /* RW-4R */
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#define NV_PDISP_IHUB_COMMON_QUEUEING_THRESHOLD_REQUEST_COUNT 15:0 /* RWIUF */
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#define NV_PDISP_IHUB_COMMON_QUEUEING_THRESHOLD_REQUEST_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG(i) (0x00628000+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_ENTRIES 15:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_ENTRIES_INIT 0x00000544 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_UPDATE 16:16 /* RWIVF */
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#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_UPDATE_GLOBAL 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_UPDATE_IDLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_STATUS 31:31 /* R--VF */
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#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_STATUS_DONE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_POOL_CONFIG_STATUS_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_FETCH_METER(i) (0x00628004+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_FETCH_METER__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_FETCH_METER_SLOTS 7:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_FETCH_METER_SLOTS_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_FETCH_METER_SLOTS_ONE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_FETCH_METER_SLOTS_MAX 0x0000000F /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_FETCH_METER_UPDATE 16:16 /* RWIVF */
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#define NV_PDISP_IHUB_WINDOW_FETCH_METER_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_FETCH_METER_UPDATE_GLOBAL 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_FETCH_METER_UPDATE_IDLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_FETCH_METER_STATUS 31:31 /* R--VF */
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#define NV_PDISP_IHUB_WINDOW_FETCH_METER_STATUS_DONE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_FETCH_METER_STATUS_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT(i) (0x0062800C+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_LIMIT 11:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_LIMIT_INIT 0x00000FFF /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_LIMIT_MAX 0x00000FFF /* */
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#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_UPDATE 16:16 /* RWIVF */
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#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_UPDATE_GLOBAL 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_UPDATE_IDLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_STATUS 31:31 /* R--VF */
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#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_STATUS_DONE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_REQ_LIMIT_STATUS_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLA(i) (0x00628030+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLA__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLA_MODE 29:29 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLA_MODE_IGNORE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLA_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLA_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLA_OSM_VBLANK_SWITCH 30:30 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLA_OSM_VBLANK_SWITCH_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLA_OSM_VBLANK_SWITCH_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLA_OSM_VBLANK_SWITCH_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLB(i) (0x00628034+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLB__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLB_MID_WATERMARK 28:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLB_MID_WATERMARK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLB_STATUS 31:31 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLB_STATUS_NOT_IN_WINDOW 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_CTLB_STATUS_IN_WINDOW 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_OK_FETCH(i) (0x00628130+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_OK_FETCH__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_OK_FETCH_COUNT 31:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_OK_FETCH_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_OK_DWCF(i) (0x00628134+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_OK_DWCF__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_OK_DWCF_COUNT 31:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_SWITCH_OK_DWCF_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA(i) (0x00628040+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA_MSCG_LOW_WATERMARK 28:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA_MSCG_LOW_WATERMARK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA_MODE 29:29 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA_MODE_IGNORE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA_OSM_VBLANK_MSCG 30:30 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA_OSM_VBLANK_MSCG_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA_OSM_VBLANK_MSCG_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA_OSM_VBLANK_MSCG_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA_STATUS 31:31 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA_STATUS_NOT_BELOW_LOW 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLA_STATUS_BELOW_LOW 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLB(i) (0x00628044+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLB__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLB_MSCG_POWERUP_WATERMARK 28:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLB_MSCG_POWERUP_WATERMARK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLB_STATUS 31:31 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLB_STATUS_NOT_BELOW_POWERUP 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLB_STATUS_BELOW_POWERUP 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLC(i) (0x00628048+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLC__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLC_MSCG_HIGH_WATERMARK 28:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLC_MSCG_HIGH_WATERMARK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLC_STATUS 31:31 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLC_STATUS_NOT_ABOVE_HIGH 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_CTLC_STATUS_ABOVE_HIGH 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_OK_FETCH(i) (0x00628110+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_MSCG_OK_FETCH__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_MSCG_OK_FETCH_COUNT 31:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_MSCG_OK_FETCH_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_WAKE_FETCH(i) (0x00628114+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_MSCG_WAKE_FETCH__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_MSCG_WAKE_FETCH_COUNT 31:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_MSCG_WAKE_FETCH_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_OK_DWCF(i) (0x00628118+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_MSCG_OK_DWCF__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_MSCG_OK_DWCF_COUNT 31:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_MSCG_OK_DWCF_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_MSCG_WAKE_DWCF(i) (0x0062811C+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_MSCG_WAKE_DWCF__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_MSCG_WAKE_DWCF_COUNT 31:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_MSCG_WAKE_DWCF_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_CTL(i) (0x0062804C+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_CTL__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_CTL_CRITICAL_WATERMARK 14:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_CTL_CRITICAL_WATERMARK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_CTL_MODE 29:29 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_CTL_MODE_IGNORE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_CTL_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_CTL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP(i) (0x00628074+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP_NUM 5:1 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP_NUM_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP_UPDATE 16:16 /* RWIVF */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP_UPDATE_GLOBAL 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP_UPDATE_IDLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP_STATUS 31:31 /* R--VF */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP_STATUS_DONE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_THREAD_GROUP_STATUS_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_REQ(i) (0x00628078+(i)*512) /* R--4A */
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#define NV_PDISP_IHUB_WINDOW_REQ__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_REQ_LINE 15:0 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_DRAIN_METER(i) (0x006280A0+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_DRAIN_METER__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_DRAIN_METER_SLOTS 7:0 /* RWIUF */
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#define NV_PDISP_IHUB_WINDOW_DRAIN_METER_SLOTS_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_DRAIN_METER_SLOTS_ONE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_DRAIN_METER_SLOTS_MAX 0x00000020 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_DRAIN_METER_UPDATE 16:16 /* RWIVF */
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#define NV_PDISP_IHUB_WINDOW_DRAIN_METER_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_WINDOW_DRAIN_METER_UPDATE_GLOBAL 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_DRAIN_METER_UPDATE_IDLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_WINDOW_DRAIN_METER_STATUS 31:31 /* R--VF */
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#define NV_PDISP_IHUB_WINDOW_DRAIN_METER_STATUS_DONE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_DRAIN_METER_STATUS_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA(i) (0x006280A4+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_LINE_NUMBER 15:0 /* RWIVF */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_LINE_NUMBER_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_SEL 29:27 /* RWIVF */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_SEL_NO_QUEUEING_NO_SPLUP 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_SEL_NO_QUEUEING_SPLUP 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_SEL_QUEUEING_NO_SPLUP 0x00000002 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_SEL_QUEUEING_SPLUP 0x00000003 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_SEL_LINE_NUMBER 0x00000004 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_TAG_SEL 30:30 /* RWIVF */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_TAG_SEL_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_TAG_SEL_IHUB_TIMER 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_TAG_SEL_CRITICAL_REQ 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_ENABLE 31:31 /* RWIVF */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_ENABLE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_ENABLE_CLEAR 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLA_ENABLE_SET 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLB(i) (0x006280A8+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLB__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLB_THRESHOLD_PIXELS 27:0 /* RWIVF */
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#define NV_PDISP_IHUB_WINDOW_CRITICAL_LATENCY_CTLB_THRESHOLD_PIXELS_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_STATUS(i) (0x006280B0+(i)*512) /* R--4A */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_STATUS__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_STATUS_FORMATTER_LUMA_ENTRIES 4:0 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_STATUS_FORMATTER_CR_U_ENTRIES 9:5 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_STATUS_FORMATTER_CR_L_ENTRIES 14:10 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_STATUS_HOLD_ENTRIES 19:16 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_STATUS_RDOUT_LUMA_THREADID 22:20 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_STATUS_RDOUT_CR_U_THREADID 25:23 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_STATUS_RDOUT_CR_L_THREADID 28:26 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_DECOMP_STATUS(i) (0x006280B4+(i)*512) /* R--4A */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_DECOMP_STATUS__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_DECOMP_STATUS_THREAD_0_ENTRIES 3:0 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_DECOMP_STATUS_THREAD_1_ENTRIES 7:4 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_DECOMP_STATUS_THREAD_2_ENTRIES 11:8 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_DECOMP_STATUS_THREAD_3_ENTRIES 15:12 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_DECOMP_STATUS_THREAD_4_ENTRIES 19:16 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_DECOMP_STATUS_THREAD_5_ENTRIES 23:20 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_DECOMP_STATUS_THREAD_6_ENTRIES 27:24 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_UFLOW_DECOMP_STATUS_THREAD_7_ENTRIES 31:28 /* R--UF */
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#define NV_PDISP_IHUB_WINDOW_COMPRESS(i) (0x00628100+(i)*512) /* R--4A */
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#define NV_PDISP_IHUB_WINDOW_COMPRESS__SIZE_1 32 /* */
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#define NV_PDISP_IHUB_WINDOW_COMPRESS_SUBOPT_CODE_COUNT 15:0 /* R-IUF */
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#define NV_PDISP_IHUB_WINDOW_COMPRESS_SUBOPT_CODE_COUNT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_IHUB_CURS_POOL_CONFIG(i) (0x0062C000+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_CURS_POOL_CONFIG__SIZE_1 8 /* */
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#define NV_PDISP_IHUB_CURS_POOL_CONFIG_ENTRIES 15:0 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_POOL_CONFIG_ENTRIES_INIT 0x00000040 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_POOL_CONFIG_UPDATE 16:16 /* RWIVF */
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#define NV_PDISP_IHUB_CURS_POOL_CONFIG_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_POOL_CONFIG_UPDATE_GLOBAL 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_CURS_POOL_CONFIG_UPDATE_IDLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_CURS_POOL_CONFIG_STATUS 31:31 /* R--VF */
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#define NV_PDISP_IHUB_CURS_POOL_CONFIG_STATUS_DONE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_CURS_POOL_CONFIG_STATUS_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_CURS_FETCH_METER(i) (0x0062C004+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_CURS_FETCH_METER__SIZE_1 8 /* */
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#define NV_PDISP_IHUB_CURS_FETCH_METER_SLOTS 7:0 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_FETCH_METER_SLOTS_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_FETCH_METER_SLOTS_ONE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_CURS_FETCH_METER_SLOTS_MAX 0x0000000F /* RW--V */
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#define NV_PDISP_IHUB_CURS_FETCH_METER_UPDATE 16:16 /* RWIVF */
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#define NV_PDISP_IHUB_CURS_FETCH_METER_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_FETCH_METER_UPDATE_GLOBAL 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_CURS_FETCH_METER_UPDATE_IDLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_CURS_FETCH_METER_STATUS 31:31 /* R--VF */
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#define NV_PDISP_IHUB_CURS_FETCH_METER_STATUS_DONE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_CURS_FETCH_METER_STATUS_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_CURS_REQ_LIMIT(i) (0x0062C008+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_CURS_REQ_LIMIT__SIZE_1 8 /* */
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#define NV_PDISP_IHUB_CURS_REQ_LIMIT_LIMIT 11:0 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_REQ_LIMIT_LIMIT_INIT 0x00000FFF /* RWI-V */
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#define NV_PDISP_IHUB_CURS_REQ_LIMIT_LIMIT_MAX 0x00000FFF /* */
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#define NV_PDISP_IHUB_CURS_REQ_LIMIT_UPDATE 16:16 /* RWIVF */
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#define NV_PDISP_IHUB_CURS_REQ_LIMIT_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_REQ_LIMIT_UPDATE_GLOBAL 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_CURS_REQ_LIMIT_UPDATE_IDLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_CURS_REQ_LIMIT_STATUS 31:31 /* R--VF */
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#define NV_PDISP_IHUB_CURS_REQ_LIMIT_STATUS_DONE 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_CURS_REQ_LIMIT_STATUS_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_CURS_FRAME_TIME(i) (0x0062C024+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_CURS_FRAME_TIME__SIZE_1 8 /* */
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#define NV_PDISP_IHUB_CURS_FRAME_TIME_IN_USEC 23:0 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_FRAME_TIME_IN_USEC_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA(i) (0x0062C040+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA__SIZE_1 8 /* */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA_MSCG_LOW_WATERMARK 28:0 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA_MSCG_LOW_WATERMARK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA_MODE 29:29 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA_MODE_IGNORE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA_OSM_VBLANK_MSCG 30:30 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA_OSM_VBLANK_MSCG_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA_OSM_VBLANK_MSCG_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA_OSM_VBLANK_MSCG_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA_STATUS 31:31 /* R--UF */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA_STATUS_NOT_BELOW_LOW 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLA_STATUS_BELOW_LOW 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLB(i) (0x0062C044+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLB__SIZE_1 8 /* */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLB_MSCG_POWERUP_WATERMARK 28:0 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLB_MSCG_POWERUP_WATERMARK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLB_STATUS 31:31 /* R--UF */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLB_STATUS_NOT_BELOW_POWERUP 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLB_STATUS_BELOW_POWERUP 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLC(i) (0x0062C048+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLC__SIZE_1 8 /* */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLC_MSCG_HIGH_WATERMARK 28:0 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLC_MSCG_HIGH_WATERMARK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLC_STATUS 31:31 /* R--UF */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLC_STATUS_NOT_ABOVE_HIGH 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_CURS_MSCG_CTLC_STATUS_ABOVE_HIGH 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLA(i) (0x0062C030+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLA__SIZE_1 8 /* */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLA_MODE 29:29 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLA_MODE_IGNORE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLA_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLA_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLA_OSM_VBLANK_SWITCH 30:30 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLA_OSM_VBLANK_SWITCH_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLA_OSM_VBLANK_SWITCH_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLA_OSM_VBLANK_SWITCH_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLB(i) (0x0062C034+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLB__SIZE_1 8 /* */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLB_MID_WATERMARK 28:0 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLB_MID_WATERMARK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLB_STATUS 31:31 /* R--UF */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLB_STATUS_NOT_IN_WINDOW 0x00000000 /* R---V */
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#define NV_PDISP_IHUB_CURS_SWITCH_CTLB_STATUS_IN_WINDOW 0x00000001 /* R---V */
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#define NV_PDISP_IHUB_CURS_SWITCH_OK_FETCH(i) (0x0062C038+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_CURS_SWITCH_OK_FETCH__SIZE_1 8 /* */
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#define NV_PDISP_IHUB_CURS_SWITCH_OK_FETCH_COUNT 31:0 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_SWITCH_OK_FETCH_COUNT__INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_SWITCH_OK_DWCF(i) (0x0062C03C+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_CURS_SWITCH_OK_DWCF__SIZE_1 8 /* */
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#define NV_PDISP_IHUB_CURS_SWITCH_OK_DWCF_COUNT 31:0 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_SWITCH_OK_DWCF_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_COUNT(i) (0x0062C020+(i)*512) /* RW-4A */
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#define NV_PDISP_IHUB_CURS_COUNT__SIZE_1 8 /* */
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#define NV_PDISP_IHUB_CURS_COUNT_LOADV 15:0 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_COUNT_LOADV_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_COUNT_START_FETCH 31:16 /* RWIUF */
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#define NV_PDISP_IHUB_CURS_COUNT_START_FETCH_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_IHUB_CURS_REQ(i) (0x0062C078+(i)*512) /* R--4A */
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#define NV_PDISP_IHUB_CURS_REQ__SIZE_1 8 /* */
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#define NV_PDISP_IHUB_CURS_REQ_LINE 15:0 /* R--UF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER(i) (0x00630020+(i)*2048) /* RW-4A */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER__SIZE_1 32 /* */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_VAL 15:0 /* RWIUF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO 15:14 /* RWIUF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_DIVIDE_BY_1 0x00000000 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_DIVIDE_BY_2 0x00000001 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_DIVIDE_BY_4 0x00000002 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_RATIO_DIVIDE_BY_8 0x00000003 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_PXVAL 13:0 /* RWIUF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_PXVAL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_WRITE_MODE 28:28 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_WRITE_MODE_ACTIVE 0x00000000 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_WRITE_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_WRITE_MODE_ASSEMBLY 0x00000001 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_UPDATE 29:29 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_UPDATE_IMMEDIATE 0x00000000 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_UPDATE_CORE 0x00000001 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_STATUS 31:30 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_STATUS_ACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_STATUS_ARMED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_METER_STATUS_ASSEMBLY 0x00000002 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG(i) (0x0063004C+(i)*2048) /* RW-4A */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG__SIZE_1 32 /* */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_SIZE_OVERFLOW 0:0 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_SIZE_OVERFLOW_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_SIZE_OVERFLOW_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_SIZE_OVERFLOW_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_SIZE_OVERFLOW_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_MISSING_SAMPLES 1:1 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_MISSING_SAMPLES_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_MISSING_SAMPLES_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_MISSING_SAMPLES_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_MISSING_SAMPLES_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_EXCESS_SAMPLES 2:2 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_EXCESS_SAMPLES_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_EXCESS_SAMPLES_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_EXCESS_SAMPLES_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_ILUT_EXCESS_SAMPLES_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_SIZE_OVERFLOW 6:6 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_SIZE_OVERFLOW_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_SIZE_OVERFLOW_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_SIZE_OVERFLOW_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_SIZE_OVERFLOW_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_MISSING_SAMPLES 7:7 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_MISSING_SAMPLES_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_MISSING_SAMPLES_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_MISSING_SAMPLES_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_MISSING_SAMPLES_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_EXCESS_SAMPLES 8:8 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_EXCESS_SAMPLES_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_EXCESS_SAMPLES_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_EXCESS_SAMPLES_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_TMOLUT_EXCESS_SAMPLES_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_SIZE_OVERFLOW 12:12 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_SIZE_OVERFLOW_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_SIZE_OVERFLOW_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_SIZE_OVERFLOW_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_SIZE_OVERFLOW_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_BAD_SEGMENT_SETUP 13:13 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_BAD_SEGMENT_SETUP_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_BAD_SEGMENT_SETUP_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_BAD_SEGMENT_SETUP_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_BAD_SEGMENT_SETUP_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_WRITE_DURING_FRAME 14:14 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_WRITE_DURING_FRAME_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_WRITE_DURING_FRAME_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_WRITE_DURING_FRAME_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_WRITE_DURING_FRAME_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_BAD_SEGMENT_SIZE 15:15 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_BAD_SEGMENT_SIZE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_BAD_SEGMENT_SIZE_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_BAD_SEGMENT_SIZE_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC0LUT_BAD_SEGMENT_SIZE_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_SIZE_OVERFLOW 18:18 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_SIZE_OVERFLOW_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_SIZE_OVERFLOW_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_SIZE_OVERFLOW_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_SIZE_OVERFLOW_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_BAD_SEGMENT_SETUP 19:19 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_BAD_SEGMENT_SETUP_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_BAD_SEGMENT_SETUP_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_BAD_SEGMENT_SETUP_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_BAD_SEGMENT_SETUP_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_WRITE_DURING_FRAME 20:20 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_WRITE_DURING_FRAME_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_WRITE_DURING_FRAME_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_WRITE_DURING_FRAME_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_LUT_DEBUG_CSC1LUT_WRITE_DURING_FRAME_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX(i) (0x00630068+(i)*2048) /* RW-4A */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX__SIZE_1 32 /* */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT 3:0 /* RWIVF */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_PXGEN_PXCTL0 0x00000000 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_PXGEN_PXCTL1 0x00000001 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_PXGEN_PXCTL2 0x00000002 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_PXGEN_PXCTL3 0x00000003 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_FMT 0x00000004 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_PXGEN_CUP0 0x00000005 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_PXGEN_CUP1 0x00000006 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_DEGAMMA 0x00000007 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_PXGEN_CUP_CTL0 0x00000008 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_PXGEN_CUP_CTL1 0x00000009 /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_CGMT0 0x0000000A /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_CGMT1 0x0000000B /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_LUT0 0x0000000C /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_LUT1 0x0000000D /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_LUT2 0x0000000E /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DBGMUX_SELECT_LUT3 0x0000000F /* RW--V */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FXPT_COLOR_ALPHA_RED(i) (0x00630070+(i)*2048) /* RW-4A */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FXPT_COLOR_ALPHA_RED__SIZE_1 32 /* */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FXPT_COLOR_ALPHA_RED_A 7:0 /* RWIUF */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FXPT_COLOR_ALPHA_RED_A_INIT 0x000000FF /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FXPT_COLOR_ALPHA_RED_R 31:16 /* RWIUF */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FXPT_COLOR_ALPHA_RED_R_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FXPT_COLOR_GREEN_BLUE(i) (0x00630074+(i)*2048) /* RW-4A */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FXPT_COLOR_GREEN_BLUE__SIZE_1 32 /* */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FXPT_COLOR_GREEN_BLUE_G 15:0 /* RWIUF */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FXPT_COLOR_GREEN_BLUE_G_INIT 0x0000FFFF /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FXPT_COLOR_GREEN_BLUE_B 31:16 /* RWIUF */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FXPT_COLOR_GREEN_BLUE_B_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FP16_COLOR_ALPHA_RED(i) (0x00630078+(i)*2048) /* RW-4A */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FP16_COLOR_ALPHA_RED__SIZE_1 32 /* */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FP16_COLOR_ALPHA_RED_A 7:0 /* RWIUF */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FP16_COLOR_ALPHA_RED_A_INIT 0x000000FF /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FP16_COLOR_ALPHA_RED_R 31:16 /* RWIUF */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FP16_COLOR_ALPHA_RED_R_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FP16_COLOR_GREEN_BLUE(i) (0x0063007C+(i)*2048) /* RW-4A */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FP16_COLOR_GREEN_BLUE__SIZE_1 32 /* */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FP16_COLOR_GREEN_BLUE_G 15:0 /* RWIUF */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FP16_COLOR_GREEN_BLUE_G_INIT 0x00003C00 /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FP16_COLOR_GREEN_BLUE_B 31:16 /* RWIUF */
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#define NV_PDISP_PRECOMP_WIN_DFLT_FP16_COLOR_GREEN_BLUE_B_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA(i) (0x00630100+(i)*2048) /* R--4A */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA__SIZE_1 32 /* */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_FULL_WIDTH 4:0 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_UNIT_WIDTH 9:5 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_ALPHA_WIDTH 13:10 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT 16:16 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC00_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT 17:17 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC0LUT_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT 18:18 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC01_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT 19:19 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT 20:20 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_TMO_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT 21:21 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_TRUE 0x00000001 /* R---V */
|
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_GMA_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT 22:22 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_TRUE 0x00000001 /* R---V */
|
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC10_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT 23:23 /* R--VF */
|
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC1LUT_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT 24:24 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_TRUE 0x00000001 /* R---V */
|
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPA_CSC11_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPB(i) (0x00630104+(i)*2048) /* R--4A */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPB__SIZE_1 32 /* */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPB_FMT_PRECISION 4:0 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGSZ 9:6 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_LOGNR 12:10 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD 14:14 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_SFCLOAD_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT 15:15 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPB_ILUT_DIRECT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC(i) (0x00630108+(i)*2048) /* R--4A */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC__SIZE_1 32 /* */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_PRECISION 4:0 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP 5:5 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC00_UNITY_CLAMP_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGSZ 9:6 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_LOGNR 12:10 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD 14:14 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_SFCLOAD_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT 15:15 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC0LUT_DIRECT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_PRECISION 20:16 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP 21:21 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPC_CSC01_UNITY_CLAMP_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD(i) (0x0063010C+(i)*2048) /* R--4A */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD__SIZE_1 32 /* */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGSZ 3:0 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_LOGNR 6:4 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD 8:8 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_SFCLOAD_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT 9:9 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_TMO_DIRECT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_SF_PRECISION 16:12 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_CI_PRECISION 20:17 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB 21:21 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA 22:22 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_EXT_ALPHA_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPD_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE(i) (0x00630110+(i)*2048) /* R--4A */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE__SIZE_1 32 /* */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_PRECISION 4:0 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP 5:5 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC10_UNITY_CLAMP_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGSZ 9:6 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_LOGNR 12:10 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD 14:14 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_SFCLOAD_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT 15:15 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC1LUT_DIRECT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_PRECISION 20:16 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP 21:21 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPE_CSC11_UNITY_CLAMP_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPF(i) (0x00630114+(i)*2048) /* R--4A */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPF__SIZE_1 32 /* */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_2TAP 15:0 /* R--VF */
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#define NV_PDISP_PRECOMP_WIN_PIPE_HDR_CAPF_VSCLR_MAX_PIXELS_5TAP 31:16 /* R--VF */
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#define NV_PDISP_COMP_WIN_PIPE_CGCTL(i) (0x00630400+(i)*2048) /* RW-4A */
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#define NV_PDISP_COMP_WIN_PIPE_CGCTL__SIZE_1 32 /* */
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#define NV_PDISP_COMP_WIN_PIPE_CGCTL_VAL 31:0 /* RWIUF */
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#define NV_PDISP_COMP_WIN_PIPE_CGCTL_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER(i) (0x0061611C+(i)*2048) /* RW-4A */
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#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE 31:0 /* RWIUF */
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#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_HW 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_LOADV_COUNTER_VALUE_SW 0x00000000 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA(i) (0x00616140+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_FULL_WIDTH 4:0 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_UNIT_WIDTH 9:5 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT 16:16 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_OCSC0_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT 17:17 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_OCSC1_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT 18:18 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_SCLR_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT 19:19 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_HCLPF_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT 20:20 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_DTH_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT 21:21 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_OSCAN_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT 22:22 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_DSC_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT 23:23 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_VFILTER_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT 24:24 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPA_RCRC_PRESENT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPB(i) (0x00616144+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPB__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPB_VGA 0:0 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPB_VGA_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPB_VGA_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGSZ 9:6 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPB_OLUT_LOGNR 12:10 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD 14:14 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPB_OLUT_SFCLOAD_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT 15:15 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPB_OLUT_DIRECT_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC(i) (0x00616148+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_OCSC0_PRECISION 4:0 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP 5:5 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_OCSC0_UNITY_CLAMP_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_OCSC1_PRECISION 12:8 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP 13:13 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_OCSC1_UNITY_CLAMP_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_SCLR_SF_PRECISION 20:16 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_SCLR_CI_PRECISION 24:21 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB 25:25 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_EXT_RGB_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR 28:28 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_2X 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_SCLR_VS_MAX_SCALE_FACTOR_4X 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR 30:30 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_2X 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPC_SCLR_HS_MAX_SCALE_FACTOR_4X 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPD(i) (0x0061614C+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPD__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_2TAP 15:0 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPD_VSCLR_MAX_PIXELS_5TAP 31:16 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPE(i) (0x00616150+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPE__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE 3:0 /* R-IUF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPE_DSC_RATEBUFSIZE_INIT 0x00000006 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE 13:8 /* R-IUF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPE_DSC_LINEBUFSIZE_INIT 0x00000005 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422 16:16 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE422_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420 17:17 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPE_DSC_NATIVE420_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPF(i) (0x00616160+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPF__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_HDR_CAPF_VFILTER_MAX_PIXELS 15:0 /* R--VF */
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#define NV_PDISP_POSTCOMP_HEAD_DITHER(i) (0x00616154+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_DITHER__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_DITHER_PHASE 1:0 /* R-IVF */
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#define NV_PDISP_POSTCOMP_HEAD_DITHER_PHASE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG(i) (0x00616158+(i)*2048) /* RW-4A */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_SIZE_OVERFLOW 0:0 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_SIZE_OVERFLOW_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_SIZE_OVERFLOW_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_SIZE_OVERFLOW_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_SIZE_OVERFLOW_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_MISSING_SAMPLES 1:1 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_MISSING_SAMPLES_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_MISSING_SAMPLES_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_MISSING_SAMPLES_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_MISSING_SAMPLES_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_EXCESS_SAMPLES 2:2 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_EXCESS_SAMPLES_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_EXCESS_SAMPLES_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_EXCESS_SAMPLES_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_EXCESS_SAMPLES_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_BAD_SEGMENT_SIZE 3:3 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_BAD_SEGMENT_SIZE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_BAD_SEGMENT_SIZE_NOT_DETECTED 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_BAD_SEGMENT_SIZE_DETECTED 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_LUT_DEBUG_OLUT_BAD_SEGMENT_SIZE_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_FORCE_PIXEL(i) (0x0061615C+(i)*2048) /* RW-4A */
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#define NV_PDISP_POSTCOMP_HEAD_FORCE_PIXEL__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_FORCE_PIXEL_RED_CR 9:0 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_FORCE_PIXEL_RED_CR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_FORCE_PIXEL_GRE_Y 19:10 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_FORCE_PIXEL_GRE_Y_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_FORCE_PIXEL_BLU_CB 29:20 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_FORCE_PIXEL_BLU_CB_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_FORCE_PIXEL_ENABLE 31:31 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_FORCE_PIXEL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_FORCE_PIXEL_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_POSTCOMP_HEAD_FORCE_PIXEL_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE(i) (0x0061616C+(i)*2048) /* RW-4A */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION(i) (0+(i)):(0+(i)) /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION__SIZE_1 9 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION0 0:0 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION0_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION0_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION0_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION1 1:1 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION1_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION1_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION1_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION2 2:2 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION2_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION2_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION2_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION3 3:3 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION3_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION3_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION3_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION4 4:4 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION4_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION4_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION4_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION5 5:5 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION5_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION5_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION5_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION6 6:6 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION6_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION6_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION6_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION7 7:7 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION7_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION7_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION7_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION8 8:8 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION8_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION8_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION8_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_ERROR_REGION8_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION(i) ((i)+16):((i)+16) /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION__SIZE_1 9 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION0 16:16 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION0_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION0_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION0_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION1 17:17 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION1_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION1_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION1_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION2 18:18 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION2_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION2_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION2_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION3 19:19 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION3_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION3_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION3_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION4 20:20 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION4_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION4_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION4_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION5 21:21 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION5_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION5_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION5_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION6 22:22 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION6_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION6_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION6_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION7 23:23 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION7_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION7_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION7_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION8 24:24 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION8_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION8_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION8_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_PENDING_REGION8_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_VPR_COMP 31:31 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_VPR_COMP_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_VPR_COMP_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_VPR_COMP_YES 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_STATE_VPR_COMP_NO 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC(i,j) (0x00616170+(i)*2048+(j)*4) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC__SIZE_2 9 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_VALUE 31:0 /* R-IVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION_CRC_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION0_CRC(i) (0x00616170+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_REGION0_CRC__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION0_CRC_VALUE 31:0 /* R-IVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION0_CRC_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION1_CRC(i) (0x00616174+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_REGION1_CRC__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION1_CRC_VALUE 31:0 /* R-IVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION1_CRC_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION2_CRC(i) (0x00616178+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_REGION2_CRC__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION2_CRC_VALUE 31:0 /* R-IVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION2_CRC_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION3_CRC(i) (0x0061617C+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_REGION3_CRC__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION3_CRC_VALUE 31:0 /* R-IVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION3_CRC_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION4_CRC(i) (0x00616180+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_REGION4_CRC__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION4_CRC_VALUE 31:0 /* R-IVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION4_CRC_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION5_CRC(i) (0x00616184+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_REGION5_CRC__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION5_CRC_VALUE 31:0 /* R-IVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION5_CRC_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION6_CRC(i) (0x00616188+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_REGION6_CRC__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION6_CRC_VALUE 31:0 /* R-IVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION6_CRC_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION7_CRC(i) (0x0061618C+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_REGION7_CRC__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION7_CRC_VALUE 31:0 /* R-IVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION7_CRC_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_REGION8_CRC(i) (0x00616190+(i)*2048) /* R--4A */
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#define NV_PDISP_POSTCOMP_HEAD_REGION8_CRC__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_REGION8_CRC_VALUE 31:0 /* R-IVF */
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#define NV_PDISP_POSTCOMP_HEAD_REGION8_CRC_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_CTRL(i) (0x006161C0+(i)*2048) /* RW-4A */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_CTRL__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_CTRL_SOFT_RESET 0:0 /* RWIVF */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_CTRL_SOFT_RESET_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_CTRL_SOFT_RESET_DONE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_CTRL_SOFT_RESET_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_CTRL_SOFT_RESET_TRIGGER 0x00000001 /* -W--V */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE(i) (0x006161C4+(i)*2048) /* RW-4A */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE__SIZE_1 8 /* */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE_BYPASS_SLCG 0:0 /* RWIUF */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE_BYPASS_SLCG_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE_BYPASS_SLCG_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE_BYPASS_SLCG_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE_DISABLE_MMAP 1:1 /* RWIUF */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE_DISABLE_MMAP_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE_DISABLE_MMAP_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE_DISABLE_MMAP_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE_DISABLE_ICH 2:2 /* RWIUF */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE_DISABLE_ICH_INIT 0x00000000 /* RWI-V */
|
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE_DISABLE_ICH_TRUE 0x00000001 /* RW--V */
|
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#define NV_PDISP_POSTCOMP_HEAD_DSC_FORCE_DISABLE_ICH_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_STATUS(i) (0x006161C8+(i)*2048) /* R--4A */
|
|
#define NV_PDISP_POSTCOMP_HEAD_DSC_STATUS__SIZE_1 8 /* */
|
|
#define NV_PDISP_POSTCOMP_HEAD_DSC_STATUS_HINDEX 12:0 /* R--UF */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_STATUS_VINDEX 28:16 /* R--UF */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_STATUS_BUSY 31:31 /* R--UF */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_STATUS_BUSY_TRUE 0x00000001 /* R---V */
|
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#define NV_PDISP_POSTCOMP_HEAD_DSC_STATUS_BUSY_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_POSTCOMP_HEAD_DSC_SPARE(i) (0x006161CC+(i)*2048) /* RWI4A */
|
|
#define NV_PDISP_POSTCOMP_HEAD_DSC_SPARE__SIZE_1 8 /* */
|
|
#define NV_PDISP_POSTCOMP_HEAD_DSC_SPARE_ECO 31:0 /* RWIVF */
|
|
#define NV_PDISP_POSTCOMP_HEAD_DSC_SPARE_ECO_INIT 0x00000000 /* RWI-V */
|
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#define NV_PDISP_POSTCOMP_HEAD_DSC_DBG0(i) (0x006161D0+(i)*2048) /* R--4A */
|
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#define NV_PDISP_POSTCOMP_HEAD_DSC_DBG0__SIZE_1 8 /* */
|
|
#define NV_PDISP_POSTCOMP_HEAD_DSC_DBG0_VAL 31:0 /* R--UF */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK(i) (0x00616488+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK__SIZE_1 8 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWI-V */
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#define NV_PDISP_RG_CRC_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_RG_HEAD_CAPA(i) (0x00616300+(i)*2048) /* R--4A */
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#define NV_PDISP_RG_HEAD_CAPA__SIZE_1 8 /* */
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#define NV_PDISP_RG_HEAD_CAPA_REORDER_BANK_WIDTH_SIZE_MAX 13:0 /* R--UF */
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#define NV_PDISP_RG_SWAP_LOCKOUT(i) (0x00616304+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_SWAP_LOCKOUT__SIZE_1 8 /* */
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#define NV_PDISP_RG_SWAP_LOCKOUT_START 15:0 /* RWIUF */
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#define NV_PDISP_RG_SWAP_LOCKOUT_START_INIT 0x00000004 /* RWI-V */
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#define NV_PDISP_RG_ELV(i) (0x00616308+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_ELV__SIZE_1 8 /* */
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#define NV_PDISP_RG_ELV_START 14:0 /* RWIUF */
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#define NV_PDISP_RG_ELV_START_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_RG_UNDERFLOW(i) (0x0061630C+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_UNDERFLOW__SIZE_1 8 /* */
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#define NV_PDISP_RG_UNDERFLOW_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_RG_UNDERFLOW_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_UNDERFLOW_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_RG_UNDERFLOW_ENABLE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED 4:4 /* RWIVF */
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#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_YES 0x00000001 /* R---V */
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#define NV_PDISP_RG_UNDERFLOW_UNDERFLOWED_NO 0x00000000 /* R---V */
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#define NV_PDISP_RG_UNDERFLOW_LOADV_UNDERFLOWED 5:5 /* RWIVF */
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#define NV_PDISP_RG_UNDERFLOW_LOADV_UNDERFLOWED_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_UNDERFLOW_LOADV_UNDERFLOWED_CLR 0x00000001 /* -W--V */
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#define NV_PDISP_RG_UNDERFLOW_LOADV_UNDERFLOWED_YES 0x00000001 /* R---V */
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#define NV_PDISP_RG_UNDERFLOW_LOADV_UNDERFLOWED_NO 0x00000000 /* R---V */
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#define NV_PDISP_RG_UNDERFLOW_MODE 8:8 /* RWIVF */
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#define NV_PDISP_RG_UNDERFLOW_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_UNDERFLOW_MODE_REPEAT 0x00000000 /* RW--V */
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#define NV_PDISP_RG_UNDERFLOW_MODE_RED 0x00000001 /* RW--V */
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#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED 23:16 /* R-IVF */
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#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST 24:24 /* RWIVF */
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#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST_RST_DONE 0x00000000 /* R---V */
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#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST_RST_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_RG_UNDERFLOW_FRAMES_UFLOWED_RST_RST_TRIGGER 0x00000001 /* -W--V */
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#define NV_PDISP_RG_UNDERFLOW_PIXEL(i) (0x00616310+(i)*2048) /* R--4A */
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#define NV_PDISP_RG_UNDERFLOW_PIXEL__SIZE_1 8 /* */
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#define NV_PDISP_RG_UNDERFLOW_PIXEL_X_POSITION 15:0 /* R-IUF */
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#define NV_PDISP_RG_UNDERFLOW_PIXEL_X_POSITION_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_UNDERFLOW_PIXEL_Y_POSITION 31:16 /* R-IUF */
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#define NV_PDISP_RG_UNDERFLOW_PIXEL_Y_POSITION_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_STATUS(i) (0x00616314+(i)*2048) /* R--4A */
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#define NV_PDISP_RG_STATUS__SIZE_1 8 /* */
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#define NV_PDISP_RG_STATUS_STALLED 3:3 /* R--VF */
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#define NV_PDISP_RG_STATUS_STALLED_NO 0x00000000 /* R---V */
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#define NV_PDISP_RG_STATUS_STALLED_YES 0x00000001 /* R---V */
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#define NV_PDISP_RG_STATUS_EXTERNAL_UNSTALL_EVENT_CNT 8:5 /* R-IVF */
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#define NV_PDISP_RG_STATUS_EXTERNAL_UNSTALL_EVENT_CNT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_STATUS_RG_UNSTALL_CNT 12:9 /* R-IVF */
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#define NV_PDISP_RG_STATUS_RG_UNSTALL_CNT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_STATUS_ACT_HEAD_OPMODE 15:14 /* R--VF */
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#define NV_PDISP_RG_STATUS_ACT_HEAD_OPMODE_SLEEP 0x00000000 /* R---V */
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#define NV_PDISP_RG_STATUS_ACT_HEAD_OPMODE_SNOOZE 0x00000001 /* R---V */
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#define NV_PDISP_RG_STATUS_ACT_HEAD_OPMODE_AWAKE 0x00000002 /* R---V */
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#define NV_PDISP_RG_STATUS_HSYNC 16:16 /* R--VF */
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#define NV_PDISP_RG_STATUS_HSYNC_INACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_RG_STATUS_HSYNC_ACTIVE 0x00000001 /* R---V */
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#define NV_PDISP_RG_STATUS_HBLNK 17:17 /* R--VF */
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#define NV_PDISP_RG_STATUS_HBLNK_INACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_RG_STATUS_HBLNK_ACTIVE 0x00000001 /* R---V */
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#define NV_PDISP_RG_STATUS_VSYNC 20:20 /* R--VF */
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#define NV_PDISP_RG_STATUS_VSYNC_INACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_RG_STATUS_VSYNC_ACTIVE 0x00000001 /* R---V */
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#define NV_PDISP_RG_STATUS_VBLNK 21:21 /* R--VF */
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#define NV_PDISP_RG_STATUS_VBLNK_INACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_RG_STATUS_VBLNK_ACTIVE 0x00000001 /* R---V */
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#define NV_PDISP_RG_STATUS_FID 22:22 /* R--UF */
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#define NV_PDISP_RG_STATUS_FID_FLD0 0x00000000 /* R---V */
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#define NV_PDISP_RG_STATUS_FID_FLD1 0x00000001 /* R---V */
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#define NV_PDISP_RG_STATUS_BLNK 24:24 /* R--VF */
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#define NV_PDISP_RG_STATUS_BLNK_INACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_RG_STATUS_BLNK_ACTIVE 0x00000001 /* R---V */
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#define NV_PDISP_RG_STATUS_VACT_SPACE 25:25 /* R--VF */
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#define NV_PDISP_RG_STATUS_VACT_SPACE_INACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_RG_STATUS_VACT_SPACE_ACTIVE 0x00000001 /* R---V */
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#define NV_PDISP_RG_STATUS_STEREO 27:27 /* R--VF */
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#define NV_PDISP_RG_STATUS_STEREO_RIGHT 0x00000000 /* R---V */
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#define NV_PDISP_RG_STATUS_STEREO_LEFT 0x00000001 /* R---V */
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#define NV_PDISP_RG_STATUS_VIEWPORT 28:28 /* R--VF */
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#define NV_PDISP_RG_STATUS_VIEWPORT_INACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_RG_STATUS_VIEWPORT_ACTIVE 0x00000001 /* R---V */
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#define NV_PDISP_RG_STATUS_BORDER 29:29 /* R--VF */
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#define NV_PDISP_RG_STATUS_BORDER_INACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_RG_STATUS_BORDER_ACTIVE 0x00000001 /* R---V */
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#define NV_PDISP_RG_STATUS_LOCKED 30:30 /* R--VF */
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#define NV_PDISP_RG_STATUS_LOCKED_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_RG_STATUS_LOCKED_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP(i) (0x00616318+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP__SIZE_1 8 /* */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_VALUE 19:0 /* RWIUF */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_WRITE_MODE 28:28 /* RWIUF */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_WRITE_MODE_ACTIVE 0x00000000 /* RW--V */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_WRITE_MODE_ASSEMBLY 0x00000001 /* RW--V */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_WRITE_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_UPDATE 29:29 /* RWIUF */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_UPDATE_IMMEDIATE 0x00000000 /* RW--V */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_UPDATE_CORE 0x00000001 /* RW--V */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_STATUS 31:30 /* R--UF */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_STATUS_ACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_STATUS_ARMED 0x00000001 /* R---V */
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#define NV_PDISP_RG_UNSTALL_SPOOLUP_STATUS_ASSEMBLY 0x00000002 /* R---V */
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#define NV_PDISP_RG_IN_LOADV_COUNTER(i) (0x00616320+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_IN_LOADV_COUNTER__SIZE_1 8 /* */
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#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE 31:0 /* RWIUF */
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#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_IN_LOADV_COUNTER_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PDISP_RG_DPCA(i) (0x00616330+(i)*2048) /* R--4A */
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#define NV_PDISP_RG_DPCA__SIZE_1 8 /* */
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#define NV_PDISP_RG_DPCA_LINE_CNT 15:0 /* R--UF */
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#define NV_PDISP_RG_DPCA_FRM_CNT 31:16 /* R--UF */
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#define NV_PDISP_RG_DPCB(i) (0x00616334+(i)*2048) /* R--4A */
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#define NV_PDISP_RG_DPCB__SIZE_1 8 /* */
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#define NV_PDISP_RG_DPCB_PIXEL_CNT 15:0 /* R--UF */
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#define NV_PDISP_RG_LINE_A_INTR(i) (0x00616348+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_LINE_A_INTR__SIZE_1 8 /* */
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#define NV_PDISP_RG_LINE_A_INTR_LINE_CNT 15:0 /* RWIUF */
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#define NV_PDISP_RG_LINE_A_INTR_LINE_CNT_INIT 0x0000FFFF /* RWI-V */
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#define NV_PDISP_RG_LINE_A_INTR_ENABLE 31:31 /* RWIUF */
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#define NV_PDISP_RG_LINE_A_INTR_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_LINE_A_INTR_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_RG_LINE_A_INTR_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_RG_LINE_B_INTR(i) (0x0061634C+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_LINE_B_INTR__SIZE_1 8 /* */
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#define NV_PDISP_RG_LINE_B_INTR_LINE_CNT 15:0 /* RWIUF */
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#define NV_PDISP_RG_LINE_B_INTR_LINE_CNT_INIT 0x0000FFFF /* RWI-V */
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#define NV_PDISP_RG_LINE_B_INTR_ENABLE 31:31 /* RWIUF */
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#define NV_PDISP_RG_LINE_B_INTR_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_LINE_B_INTR_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_RG_LINE_B_INTR_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH(i) (0x00616360+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH__SIZE_1 8 /* */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_HEIGHT 13:0 /* R-IUF */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_HEIGHT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_ENABLE 14:14 /* R-IVF */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_ENABLE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_ENABLE_NO 0x00000000 /* R---V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_EXTEND_ENABLE_YES 0x00000001 /* R---V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_HEIGHT 29:16 /* RWIUF */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_HEIGHT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_ENABLE 30:30 /* RWIVF */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_SET_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_UPDATE 31:31 /* RWIVF */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_UPDATE_DONE 0x00000000 /* R---V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_UPDATE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_BACK_PORCH_UPDATE_TRIGGER 0x00000001 /* -W--V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH(i) (0x00616364+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH__SIZE_1 8 /* */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_HEIGHT 13:0 /* R-IUF */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_HEIGHT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_ENABLE 14:14 /* R-IVF */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_ENABLE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_ENABLE_NO 0x00000000 /* R---V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_EXTEND_ENABLE_YES 0x00000001 /* R---V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_HEIGHT 29:16 /* RWIUF */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_HEIGHT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_ENABLE 30:30 /* RWIVF */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_SET_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_UPDATE 31:31 /* RWIVF */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_UPDATE_DONE 0x00000000 /* R---V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_UPDATE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_FRONT_PORCH_UPDATE_TRIGGER 0x00000001 /* -W--V */
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#define NV_PDISP_RG_RASTER_EXTEND(i) (0x00616368+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_RASTER_EXTEND__SIZE_1 8 /* */
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#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_WIDTH 13:0 /* R-IUF */
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#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_WIDTH_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_ENABLE 14:14 /* R-IVF */
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#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_ENABLE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_ENABLE_NO 0x00000000 /* R---V */
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#define NV_PDISP_RG_RASTER_EXTEND_EXTEND_ENABLE_YES 0x00000001 /* R---V */
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#define NV_PDISP_RG_RASTER_EXTEND_SET_WIDTH 29:16 /* RWIUF */
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#define NV_PDISP_RG_RASTER_EXTEND_SET_WIDTH_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_RASTER_EXTEND_SET_ENABLE 30:30 /* RWIVF */
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#define NV_PDISP_RG_RASTER_EXTEND_SET_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_RASTER_EXTEND_SET_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_RG_RASTER_EXTEND_SET_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_RG_RASTER_EXTEND_UPDATE 31:31 /* RWIVF */
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#define NV_PDISP_RG_RASTER_EXTEND_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_RASTER_EXTEND_UPDATE_DONE 0x00000000 /* R---V */
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#define NV_PDISP_RG_RASTER_EXTEND_UPDATE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_RG_RASTER_EXTEND_UPDATE_TRIGGER 0x00000001 /* -W--V */
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#define NV_PDISP_RG_RASTER_EXTEND_TRIGGER_SELECT(i) (0x0061636C+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_RASTER_EXTEND_TRIGGER_SELECT__SIZE_1 8 /* */
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#define NV_PDISP_RG_RASTER_EXTEND_TRIGGER_SELECT_VFP 2:0 /* RWIUF */
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#define NV_PDISP_RG_RASTER_EXTEND_TRIGGER_SELECT_VFP_INIT 0x00000007 /* RWI-V */
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#define NV_PDISP_RG_RASTER_EXTEND_TRIGGER_SELECT_VFP_RG0 0x00000000 /* RW--V */
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#define NV_PDISP_RG_RASTER_EXTEND_TRIGGER_SELECT_VFP_RG1 0x00000001 /* RW--V */
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#define NV_PDISP_RG_RASTER_EXTEND_TRIGGER_SELECT_VFP_RG2 0x00000002 /* RW--V */
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#define NV_PDISP_RG_RASTER_EXTEND_TRIGGER_SELECT_VFP_RG3 0x00000003 /* RW--V */
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#define NV_PDISP_RG_RASTER_EXTEND_TRIGGER_SELECT_VFP_LOCAL 0x00000007 /* RW--V */
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#define NV_PDISP_RG_HEAD_CLK_CAP(i) (0x006163C0+(i)*2048) /* R--4A */
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#define NV_PDISP_RG_HEAD_CLK_CAP__SIZE_1 8 /* */
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#define NV_PDISP_RG_HEAD_CLK_CAP_PCLK_MAX 7:0 /* R--UF */
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#define NV_PDISP_RG_MISC_CTL(i) (0x006163C4+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_MISC_CTL__SIZE_1 8 /* */
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#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL 4:4 /* RWIVF */
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#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL_DONE 0x00000000 /* R---V */
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#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_RG_MISC_CTL_FORCE_UNSTALL_TRIGGER 0x00000001 /* -W--V */
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#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST 13:13 /* RWIVF */
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#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST_DONE 0x00000000 /* R---V */
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#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_RG_MISC_CTL_UNSTALL_CNT_RST_TRIGGER 0x00000001 /* -W--V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY(i) (0x006163C8+(i)*2048) /* RW-4A */
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#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY__SIZE_1 8 /* */
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#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_BACK_PORCH 3:0 /* RWIUF */
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#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_BACK_PORCH_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_BACK_PORCH_TWO 0x00000001 /* RW--V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_BACK_PORCH_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_FRONT_PORCH 7:4 /* RWIUF */
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#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_FRONT_PORCH_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_FRONT_PORCH_TWO 0x00000001 /* RW--V */
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#define NV_PDISP_RG_RASTER_V_EXTEND_MULTIPLY_FRONT_PORCH_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_CURSOR_PIPE_METER(i) (0x00616208+(i)*2048) /* RW-4A */
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#define NV_PDISP_CURSOR_PIPE_METER__SIZE_1 8 /* */
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#define NV_PDISP_CURSOR_PIPE_METER_VAL 15:0 /* RWIUF */
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#define NV_PDISP_CURSOR_PIPE_METER_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_CURSOR_PIPE_METER_RATIO 15:14 /* RWIUF */
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#define NV_PDISP_CURSOR_PIPE_METER_RATIO_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_CURSOR_PIPE_METER_RATIO_DIVIDE_BY_1 0x00000000 /* RW--V */
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#define NV_PDISP_CURSOR_PIPE_METER_RATIO_DIVIDE_BY_2 0x00000001 /* RW--V */
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#define NV_PDISP_CURSOR_PIPE_METER_RATIO_DIVIDE_BY_4 0x00000002 /* RW--V */
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#define NV_PDISP_CURSOR_PIPE_METER_RATIO_DIVIDE_BY_8 0x00000003 /* RW--V */
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#define NV_PDISP_CURSOR_PIPE_METER_PXVAL 13:0 /* RWIUF */
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#define NV_PDISP_CURSOR_PIPE_METER_PXVAL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_CURSOR_PIPE_METER_WRITE_MODE 28:28 /* RWIVF */
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#define NV_PDISP_CURSOR_PIPE_METER_WRITE_MODE_ACTIVE 0x00000000 /* RW--V */
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#define NV_PDISP_CURSOR_PIPE_METER_WRITE_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_CURSOR_PIPE_METER_WRITE_MODE_ASSEMBLY 0x00000001 /* RW--V */
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#define NV_PDISP_CURSOR_PIPE_METER_UPDATE 29:29 /* RWIVF */
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#define NV_PDISP_CURSOR_PIPE_METER_UPDATE_IMMEDIATE 0x00000000 /* RW--V */
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#define NV_PDISP_CURSOR_PIPE_METER_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_CURSOR_PIPE_METER_UPDATE_CORE 0x00000001 /* RW--V */
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#define NV_PDISP_CURSOR_PIPE_METER_STATUS 31:30 /* R--VF */
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#define NV_PDISP_CURSOR_PIPE_METER_STATUS_ACTIVE 0x00000000 /* R---V */
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#define NV_PDISP_CURSOR_PIPE_METER_STATUS_ARMED 0x00000001 /* R---V */
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#define NV_PDISP_CURSOR_PIPE_METER_STATUS_ASSEMBLY 0x00000002 /* R---V */
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#define NV_PDISP_SF_TEST(i) (0x0061650C+(i)*2048) /* R--4A */
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#define NV_PDISP_SF_TEST__SIZE_1 8 /* */
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#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE 9:8 /* R--UF */
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#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_SLEEP 0x00000000 /* R---V */
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#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_SNOOZE 0x00000001 /* R---V */
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#define NV_PDISP_SF_TEST_ACT_HEAD_OPMODE_AWAKE 0x00000002 /* R---V */
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#define NV_PDISP_SF_TEST_OWNER_MASK 13:10 /* R--UF */
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#define NV_PDISP_SF_TEST_OWNER_MASK_HEAD0 0x00000001 /* R---V */
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#define NV_PDISP_SF_TEST_OWNER_MASK_HEAD1 0x00000002 /* R---V */
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#define NV_PDISP_SF_TEST_OWNER_MASK_HEAD2 0x00000004 /* R---V */
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#define NV_PDISP_SF_TEST_OWNER_MASK_HEAD3 0x00000008 /* R---V */
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#define NV_PDISP_SF_TEST_OWNER_MASK_NONE 0x00000000 /* R---V */
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#define NV_PDISP_SF_TEST_INFIFO_WORK_STATE 18:18 /* R-IUF */
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#define NV_PDISP_SF_TEST_INFIFO_WORK_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_TEST_INFIFO_WORK_STATE_DROP 0x00000000 /* R---V */
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#define NV_PDISP_SF_TEST_INFIFO_WORK_STATE_NORMAL 0x00000001 /* R---V */
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#define NV_PDISP_SF_AUDIO_CNTRL0(i) (0x00616528+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_AUDIO_CNTRL0__SIZE_1 8 /* */
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#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY 6:4 /* RWIVF */
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#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_INIT 0x00000007 /* RWI-V */
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#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_NONE 0x00000007 /* RW--V */
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#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_ZERO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_ONE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_TWO 0x00000002 /* RW--V */
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#define NV_PDISP_SF_AUDIO_CNTRL0_DEVICE_ENTRY_THREE 0x00000003 /* RW--V */
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#define NV_PDISP_SF_AUDIO_CNTRL0_AFIFO_FLUSH 12:12 /* RWIVF */
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#define NV_PDISP_SF_AUDIO_CNTRL0_AFIFO_FLUSH_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_AUDIO_CNTRL0_AFIFO_FLUSH_ENABLED 0x00000001 /* RW--V */
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#define NV_PDISP_SF_AUDIO_CNTRL0_AFIFO_FLUSH_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_SF_SPARE0(i) (0x00616530+(i)*2048) /* RWI4A */
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#define NV_PDISP_SF_SPARE0__SIZE_1 8 /* */
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#define NV_PDISP_SF_SPARE0_DP_VERSION 0:0 /* RWIVF */
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#define NV_PDISP_SF_SPARE0_DP_VERSION_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_SPARE0_DP_VERSION_11 0x00000000 /* RW--V */
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#define NV_PDISP_SF_SPARE0_DP_VERSION_12 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK(i) (0x0061670C+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWI-V */
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#define NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK(i) (0x00616710+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWI-V */
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#define NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL(i) (0x00616540+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_DP_LINKCTL__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_LINKCTL__PRIV_LEVEL_MASK NV_PDISP_SF_DP_MST_LINKCTL_PRIV_LEVEL_MASK /* */
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#define NV_PDISP_SF_DP_LINKCTL_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_LINKCTL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_TUSIZE 8:2 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_TUSIZE_INIT 0x00000040 /* RWI-V */
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#define NV_PDISP_SF_DP_LINKCTL_SYNCMODE 10:10 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_SYNCMODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_LINKCTL_SYNCMODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_SYNCMODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT 11:11 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT_PRIMARY 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_SELECT_SECONDARY 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_RESERVED 13:12 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_RESERVED_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_LINKCTL_ENHANCEDFRAME 14:14 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_ENHANCEDFRAME_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_LINKCTL_ENHANCEDFRAME_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_ENHANCEDFRAME_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL 15:15 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_TRIGGER_ALL_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_ZERO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_ONE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_TWO 0x00000003 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_FOUR 0x0000000F /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_LANECOUNT_EIGHT 0x000000FF /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_ENABLE 24:24 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN 26:26 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_DONE 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_TRIGGER 0x00000001 /* -W--T */
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#define NV_PDISP_SF_DP_LINKCTL_SINGLE_HEAD_MST 27:27 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_SINGLE_HEAD_MST_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_LINKCTL_SINGLE_HEAD_MST_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_SINGLE_HEAD_MST_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_MODE 29:28 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_MODE_LOADV 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_MODE_IMMEDIATE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_FORCE_RATE_GOVERN_MODE_VACTIVE 0x00000003 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_FORMAT_MODE 30:30 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_FORMAT_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_LINKCTL_FORMAT_MODE_SINGLE_STREAM 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_FORMAT_MODE_MULTI_STREAM 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_AUDIO_OVER_RIGHT_PANEL_ENABLE 31:31 /* RWIVF */
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#define NV_PDISP_SF_DP_LINKCTL_AUDIO_OVER_RIGHT_PANEL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_LINKCTL_AUDIO_OVER_RIGHT_PANEL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_LINKCTL_AUDIO_OVER_RIGHT_PANEL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_MN(i) (0x0061654C+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_DP_MN__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_MN_N_VAL 23:0 /* RWIVF */
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#define NV_PDISP_SF_DP_MN_N_VAL_INIT 0x00008000 /* RWI-V */
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#define NV_PDISP_SF_DP_MN_M_DELTA 27:24 /* RWIVF */
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#define NV_PDISP_SF_DP_MN_M_DELTA_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_MN_SECONDARY_OVERRIDE 28:28 /* RWIVF */
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#define NV_PDISP_SF_DP_MN_SECONDARY_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_MN_SECONDARY_OVERRIDE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_MN_SECONDARY_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_MN_M_MOD 31:30 /* RWIVF */
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#define NV_PDISP_SF_DP_MN_M_MOD_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_MN_M_MOD_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_MN_M_MOD_INC 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_MN_M_MOD_DEC 0x00000002 /* RW--V */
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#define NV_PDISP_SF_DP_CONFIG(i) (0x00616550+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_DP_CONFIG__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_CONFIG_WATERMARK 5:0 /* RWIVF */
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#define NV_PDISP_SF_DP_CONFIG_WATERMARK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_COUNT 14:8 /* RWIVF */
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#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_FRAC 19:16 /* RWIVF */
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#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_FRAC_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_POLARITY 24:24 /* RWIVF */
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#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_POLARITY_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_POLARITY_NEGATIVE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_POLARITY_POSITIVE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE 27:26 /* RWIVF */
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#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE_INIT 0x00000002 /* RWI-V */
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#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE_LEGACY 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_CONFIG_ACTIVESYM_CNTL_MODE_AUTO 0x00000002 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL(i) (0x00616560+(i)*2048) /* RWI4A */
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#define NV_PDISP_SF_DP_AUDIO_CTRL__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_ENABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE 3:2 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_AUTO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_DISABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_ENABLE 0x00000002 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_PACKETID 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_PACKETID_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_STATUS 21:21 /* R-IVF */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_STATUS_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_STATUS_ENABLE 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_MUTE_STATUS_DISABLE 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS 31:31 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS_DONE 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_AUDIO_CTRL_NEW_SETTINGS_TRIGGER 0x00000001 /* -W--T */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS(i) (0x00616568+(i)*2048) /* RWI4A */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_VALUE 16:0 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_WRITE_MODE 28:28 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_WRITE_MODE_ACTIVE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_WRITE_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_WRITE_MODE_ASSEMBLY 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_UPDATE 29:29 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_UPDATE_IMMEDIATE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_UPDATE_CORE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_STATUS 31:30 /* R-IVF */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_STATUS_ACTIVE 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_STATUS_ARMED 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_AUDIO_HBLANK_SYMBOLS_STATUS_ASSEMBLY 0x00000002 /* R---V */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS(i) (0x0061656C+(i)*2048) /* RWI4A */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_VALUE 20:0 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_WRITE_MODE 28:28 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_WRITE_MODE_ACTIVE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_WRITE_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_WRITE_MODE_ASSEMBLY 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_UPDATE 29:29 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_UPDATE_IMMEDIATE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_UPDATE_CORE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_STATUS 31:30 /* R-IVF */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_STATUS_ACTIVE 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_STATUS_ARMED 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_AUDIO_VBLANK_SYMBOLS_STATUS_ASSEMBLY 0x00000002 /* R---V */
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#define NV_PDISP_SF_DP_STREAM_CTL(i) (0x00616578+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_DP_STREAM_CTL__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_STREAM_CTL__PRIV_LEVEL_MASK NV_PDISP_SF_DP_MST_STREAM_CTL_PRIV_LEVEL_MASK /* */
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#define NV_PDISP_SF_DP_STREAM_CTL_START 5:0 /* RWIVF */
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#define NV_PDISP_SF_DP_STREAM_CTL_START_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DP_STREAM_CTL_LENGTH 13:8 /* RWIVF */
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#define NV_PDISP_SF_DP_STREAM_CTL_LENGTH_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_STREAM_CTL_START_ACTIVE 21:16 /* R-IVF */
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#define NV_PDISP_SF_DP_STREAM_CTL_START_ACTIVE_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_SF_DP_STREAM_CTL_LENGTH_ACTIVE 29:24 /* R-IVF */
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#define NV_PDISP_SF_DP_STREAM_CTL_LENGTH_ACTIVE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_STREAM_BW(i) (0x0061657C+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_DP_STREAM_BW__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_STREAM_BW_ALLOCATED 15:0 /* RWIVF */
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#define NV_PDISP_SF_DP_STREAM_BW_ALLOCATED_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_STREAM_BW_TIMESLICE 31:16 /* RWIVF */
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#define NV_PDISP_SF_DP_STREAM_BW_TIMESLICE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_STREAM_CTL_RESERVED__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_STREAM_CTL_RESERVED__SIZE_2 6 /* */
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#define NV_PDISP_SF_DP_STREAM_CTL_RESERVED_VALUE 31:0 /* RWIVF */
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#define NV_PDISP_SF_DP_STREAM_CTL_RESERVED_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_STREAM_BW_RESERVED__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_STREAM_BW_RESERVED__SIZE_2 6 /* */
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#define NV_PDISP_SF_DP_STREAM_BW_RESERVED_VALUE 31:0 /* RWIVF */
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#define NV_PDISP_SF_DP_STREAM_BW_RESERVED_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_STREAM_CTL_ARRAY(i,j) (((j)==0)?(0x00616578+(i)*2048):(0x00616584+(i)*2048)+((j)-1)*8) /* */
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#define NV_PDISP_SF_DP_STREAM_CTL_ARRAY__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_STREAM_CTL_ARRAY__SIZE_2 2 /* */
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#define NV_PDISP_SF_DP_STREAM_BW_ARRAY(i,j) (((j)==0)?(0x0061657C+(i)*2048):(0x00616588+(i)*2048)+((j)-1)*8) /* */
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#define NV_PDISP_SF_DP_STREAM_BW_ARRAY__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_STREAM_BW_ARRAY__SIZE_2 2 /* */
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#define NV_PDISP_SF_HDMI_CTRL(i) (0x006165C0+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_HDMI_CTRL__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_CTRL_REKEY 6:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_CTRL_REKEY_INIT 0x00000038 /* RWI-V */
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#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT 8:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_2CH 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_8CH 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_SELECT 10:10 /* RWIVF */
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#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_SELECT_HW_BASED 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_CTRL_AUDIO_LAYOUT_SELECT_SW_BASED 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_CTRL_SAMPLE_FLAT 12:12 /* RWIVF */
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#define NV_PDISP_SF_HDMI_CTRL_SAMPLE_FLAT_CLR 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_CTRL_SAMPLE_FLAT_SET 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_CTRL_MAX_AC_PACKET 20:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_CTRL_MAX_AC_PACKET_INIT 0x00000002 /* RWI-V */
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#define NV_PDISP_SF_HDMI_CTRL_AUDIO 24:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_CTRL_AUDIO_DIS 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_CTRL_AUDIO_EN 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_HDMI_CTRL_ENABLE 30:30 /* RWIVF */
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#define NV_PDISP_SF_HDMI_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_CTRL_ENABLE_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSYNC_WINDOW(i) (0x006165C8+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_HDMI_VSYNC_WINDOW__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_END 9:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_END_INIT 0x00000210 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_START 25:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_START_INIT 0x00000200 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE 31:31 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE_YES 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE_DIS 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSYNC_WINDOW_ENABLE_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_FRL_FLUSH(i) (0x006165CC+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_HDMI_FRL_FLUSH__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_FRL_FLUSH_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_FRL_FLUSH_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_FRL_FLUSH_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_FRL_FLUSH_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_FRL_FLUSH_CNTL 1:1 /* RWIVF */
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#define NV_PDISP_SF_HDMI_FRL_FLUSH_CNTL_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_HDMI_FRL_FLUSH_CNTL_DONE 0x00000000 /* R---V */
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#define NV_PDISP_SF_HDMI_FRL_FLUSH_CNTL_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_SF_HDMI_FRL_FLUSH_CNTL_TRIGGER 0x00000001 /* -W--T */
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#define NV_PDISP_SF_DSC_STREAM_CRC_CTRL(i) (0x00616658+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_DSC_STREAM_CRC_CTRL__SIZE_1 8 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_CTRL_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_SF_DSC_STREAM_CRC_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_CTRL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK(i) (0x00616708+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK__SIZE_1 8 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWI-V */
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#define NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DSC_STREAM_CRCA(i) (0x0061665C+(i)*2048) /* R--4A */
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#define NV_PDISP_SF_DSC_STREAM_CRCA__SIZE_1 8 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRCA__PRIV_LEVEL_MASK NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK /* */
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#define NV_PDISP_SF_DSC_STREAM_CRCA_COUNT 3:0 /* R--UF */
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#define NV_PDISP_SF_DSC_STREAM_CRCA_CRC0 31:16 /* R--UF */
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#define NV_PDISP_SF_DSC_STREAM_CRCB(i) (0x00616660+(i)*2048) /* R--4A */
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#define NV_PDISP_SF_DSC_STREAM_CRCB__SIZE_1 8 /* */
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#define NV_PDISP_SF_DSC_STREAM_CRCB__PRIV_LEVEL_MASK NV_PDISP_SF_DSC_STREAM_CRC_PRIV_LEVEL_MASK /* */
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#define NV_PDISP_SF_DSC_STREAM_CRCB_CRC1 15:0 /* R--UF */
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#define NV_PDISP_SF_DSC_STREAM_CRCB_CRC2 31:16 /* R--UF */
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#define NV_PDISP_SF_DP_IRQ(i) (0x00616664+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_DP_IRQ__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_IRQ_LANE0_PIXPACK_OVERFLOW0 0:0 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE0_PIXPACK_OVERFLOW0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_PIXPACK_OVERFLOW0_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_PIXPACK_OVERFLOW0_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_PIXPACK_OVERFLOW0_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE1_PIXPACK_OVERFLOW0 1:1 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE1_PIXPACK_OVERFLOW0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_PIXPACK_OVERFLOW0_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_PIXPACK_OVERFLOW0_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_PIXPACK_OVERFLOW0_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE2_PIXPACK_OVERFLOW0 2:2 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE2_PIXPACK_OVERFLOW0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_PIXPACK_OVERFLOW0_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_PIXPACK_OVERFLOW0_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_PIXPACK_OVERFLOW0_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE3_PIXPACK_OVERFLOW0 3:3 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE3_PIXPACK_OVERFLOW0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_PIXPACK_OVERFLOW0_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_PIXPACK_OVERFLOW0_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_PIXPACK_OVERFLOW0_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE0_PIXPACK_OVERFLOW1 4:4 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE0_PIXPACK_OVERFLOW1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_PIXPACK_OVERFLOW1_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_PIXPACK_OVERFLOW1_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_PIXPACK_OVERFLOW1_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE1_PIXPACK_OVERFLOW1 5:5 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE1_PIXPACK_OVERFLOW1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_PIXPACK_OVERFLOW1_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_PIXPACK_OVERFLOW1_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_PIXPACK_OVERFLOW1_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE2_PIXPACK_OVERFLOW1 6:6 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE2_PIXPACK_OVERFLOW1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_PIXPACK_OVERFLOW1_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_PIXPACK_OVERFLOW1_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_PIXPACK_OVERFLOW1_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE3_PIXPACK_OVERFLOW1 7:7 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE3_PIXPACK_OVERFLOW1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_PIXPACK_OVERFLOW1_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_PIXPACK_OVERFLOW1_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_PIXPACK_OVERFLOW1_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE0_STEER_ERROR0 8:8 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE0_STEER_ERROR0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_STEER_ERROR0_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_STEER_ERROR0_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_STEER_ERROR0_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE1_STEER_ERROR0 9:9 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE1_STEER_ERROR0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_STEER_ERROR0_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_STEER_ERROR0_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_STEER_ERROR0_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE2_STEER_ERROR0 10:10 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE2_STEER_ERROR0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_STEER_ERROR0_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_STEER_ERROR0_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_STEER_ERROR0_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE3_STEER_ERROR0 11:11 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE3_STEER_ERROR0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_STEER_ERROR0_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_STEER_ERROR0_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_STEER_ERROR0_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE0_STEER_ERROR1 12:12 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE0_STEER_ERROR1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_STEER_ERROR1_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_STEER_ERROR1_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_STEER_ERROR1_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE1_STEER_ERROR1 13:13 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE1_STEER_ERROR1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_STEER_ERROR1_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_STEER_ERROR1_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_STEER_ERROR1_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE2_STEER_ERROR1 14:14 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE2_STEER_ERROR1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_STEER_ERROR1_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_STEER_ERROR1_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_STEER_ERROR1_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE3_STEER_ERROR1 15:15 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE3_STEER_ERROR1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_STEER_ERROR1_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_STEER_ERROR1_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_STEER_ERROR1_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE0_FIFO_OVERFLOW0 16:16 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE0_FIFO_OVERFLOW0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_FIFO_OVERFLOW0_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_FIFO_OVERFLOW0_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_FIFO_OVERFLOW0_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE1_FIFO_OVERFLOW0 17:17 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE1_FIFO_OVERFLOW0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_FIFO_OVERFLOW0_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_FIFO_OVERFLOW0_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_FIFO_OVERFLOW0_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE2_FIFO_OVERFLOW0 18:18 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE2_FIFO_OVERFLOW0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_FIFO_OVERFLOW0_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_FIFO_OVERFLOW0_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_FIFO_OVERFLOW0_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE3_FIFO_OVERFLOW0 19:19 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE3_FIFO_OVERFLOW0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_FIFO_OVERFLOW0_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_FIFO_OVERFLOW0_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_FIFO_OVERFLOW0_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE0_FIFO_OVERFLOW1 20:20 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE0_FIFO_OVERFLOW1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_FIFO_OVERFLOW1_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_FIFO_OVERFLOW1_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE0_FIFO_OVERFLOW1_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE1_FIFO_OVERFLOW1 21:21 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE1_FIFO_OVERFLOW1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_FIFO_OVERFLOW1_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_FIFO_OVERFLOW1_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE1_FIFO_OVERFLOW1_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE2_FIFO_OVERFLOW1 22:22 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE2_FIFO_OVERFLOW1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_FIFO_OVERFLOW1_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_FIFO_OVERFLOW1_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE2_FIFO_OVERFLOW1_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_LANE3_FIFO_OVERFLOW1 23:23 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_LANE3_FIFO_OVERFLOW1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_FIFO_OVERFLOW1_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_FIFO_OVERFLOW1_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_LANE3_FIFO_OVERFLOW1_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_SPKT_OVERRUN0 24:24 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_SPKT_OVERRUN0_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_SPKT_OVERRUN0_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_SPKT_OVERRUN0_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_SPKT_OVERRUN0_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_SPKT_OVERRUN1 25:25 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_SPKT_OVERRUN1_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_SPKT_OVERRUN1_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_SPKT_OVERRUN1_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_SPKT_OVERRUN1_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_8LANE_SKEW0_GT64 26:26 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_8LANE_SKEW0_GT64_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_8LANE_SKEW0_GT64_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_8LANE_SKEW0_GT64_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_8LANE_SKEW0_GT64_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_8LANE_SKEW1_GT64 27:27 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_8LANE_SKEW1_GT64_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_8LANE_SKEW1_GT64_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_8LANE_SKEW1_GT64_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_8LANE_SKEW1_GT64_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_IN_FIFO0_OVERFLOW 28:28 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_IN_FIFO0_OVERFLOW_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_IN_FIFO0_OVERFLOW_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_IN_FIFO0_OVERFLOW_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_IN_FIFO0_OVERFLOW_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_IN_FIFO1_OVERFLOW 29:29 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_IN_FIFO1_OVERFLOW_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_IN_FIFO1_OVERFLOW_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_IN_FIFO1_OVERFLOW_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_IN_FIFO1_OVERFLOW_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_DSC_BUF_OVERFLOW 30:30 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_DSC_BUF_OVERFLOW_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_DSC_BUF_OVERFLOW_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_DSC_BUF_OVERFLOW_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_DSC_BUF_OVERFLOW_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_DSC_DPB_DETECT 31:31 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_DSC_DPB_DETECT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_IRQ_DSC_DPB_DETECT_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_DSC_DPB_DETECT_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_IRQ_DSC_DPB_DETECT_RESET 0x00000001 /* -W--C */
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#define NV_PDISP_SF_DP_IRQ_MASK(i) (0x00616668+(i)*2048) /* RWI4A */
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#define NV_PDISP_SF_DP_IRQ_MASK__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_PIXPACK_OVERFLOW0 0:0 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_PIXPACK_OVERFLOW0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_PIXPACK_OVERFLOW0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_PIXPACK_OVERFLOW0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_PIXPACK_OVERFLOW0 1:1 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_PIXPACK_OVERFLOW0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_PIXPACK_OVERFLOW0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_PIXPACK_OVERFLOW0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_PIXPACK_OVERFLOW0 2:2 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_PIXPACK_OVERFLOW0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_PIXPACK_OVERFLOW0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_PIXPACK_OVERFLOW0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_PIXPACK_OVERFLOW0 3:3 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_PIXPACK_OVERFLOW0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_PIXPACK_OVERFLOW0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_PIXPACK_OVERFLOW0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_PIXPACK_OVERFLOW1 4:4 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_PIXPACK_OVERFLOW1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_PIXPACK_OVERFLOW1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_PIXPACK_OVERFLOW1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_PIXPACK_OVERFLOW1 5:5 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_PIXPACK_OVERFLOW1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_PIXPACK_OVERFLOW1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_PIXPACK_OVERFLOW1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_PIXPACK_OVERFLOW1 6:6 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_PIXPACK_OVERFLOW1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_PIXPACK_OVERFLOW1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_PIXPACK_OVERFLOW1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_PIXPACK_OVERFLOW1 7:7 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_PIXPACK_OVERFLOW1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_PIXPACK_OVERFLOW1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_PIXPACK_OVERFLOW1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_STEER_ERROR0 8:8 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_STEER_ERROR0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_STEER_ERROR0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_STEER_ERROR0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_STEER_ERROR0 9:9 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_STEER_ERROR0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_STEER_ERROR0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_STEER_ERROR0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_STEER_ERROR0 10:10 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_STEER_ERROR0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_STEER_ERROR0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_STEER_ERROR0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_STEER_ERROR0 11:11 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_STEER_ERROR0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_STEER_ERROR0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_STEER_ERROR0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_STEER_ERROR1 12:12 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_STEER_ERROR1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_STEER_ERROR1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_STEER_ERROR1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_STEER_ERROR1 13:13 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_STEER_ERROR1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_STEER_ERROR1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_STEER_ERROR1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_STEER_ERROR1 14:14 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_STEER_ERROR1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_STEER_ERROR1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_STEER_ERROR1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_STEER_ERROR1 15:15 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_STEER_ERROR1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_STEER_ERROR1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_STEER_ERROR1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_FIFO_OVERFLOW0 16:16 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_FIFO_OVERFLOW0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_FIFO_OVERFLOW0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_FIFO_OVERFLOW0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_FIFO_OVERFLOW0 17:17 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_FIFO_OVERFLOW0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_FIFO_OVERFLOW0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_FIFO_OVERFLOW0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_FIFO_OVERFLOW0 18:18 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_FIFO_OVERFLOW0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_FIFO_OVERFLOW0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_FIFO_OVERFLOW0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_FIFO_OVERFLOW0 19:19 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_FIFO_OVERFLOW0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_FIFO_OVERFLOW0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_FIFO_OVERFLOW0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_FIFO_OVERFLOW1 20:20 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_FIFO_OVERFLOW1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_FIFO_OVERFLOW1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE0_FIFO_OVERFLOW1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_FIFO_OVERFLOW1 21:21 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_FIFO_OVERFLOW1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_FIFO_OVERFLOW1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE1_FIFO_OVERFLOW1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_FIFO_OVERFLOW1 22:22 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_FIFO_OVERFLOW1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_FIFO_OVERFLOW1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE2_FIFO_OVERFLOW1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_FIFO_OVERFLOW1 23:23 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_FIFO_OVERFLOW1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_FIFO_OVERFLOW1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_LANE3_FIFO_OVERFLOW1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_SPKT_OVERRUN0 24:24 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_SPKT_OVERRUN0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_SPKT_OVERRUN0_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_SPKT_OVERRUN0_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_SPKT_OVERRUN1 25:25 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_SPKT_OVERRUN1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_SPKT_OVERRUN1_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_SPKT_OVERRUN1_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_8LANE_SKEW0_GT64 26:26 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_8LANE_SKEW0_GT64_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_8LANE_SKEW0_GT64_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_8LANE_SKEW0_GT64_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_8LANE_SKEW1_GT64 27:27 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_8LANE_SKEW1_GT64_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_8LANE_SKEW1_GT64_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_8LANE_SKEW1_GT64_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_IN_FIFO0_OVERFLOW 28:28 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_IN_FIFO0_OVERFLOW_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_IN_FIFO0_OVERFLOW_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_IN_FIFO0_OVERFLOW_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_IN_FIFO1_OVERFLOW 29:29 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_IN_FIFO1_OVERFLOW_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_IN_FIFO1_OVERFLOW_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_IN_FIFO1_OVERFLOW_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_DSC_BUF_OVERFLOW 30:30 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_DSC_BUF_OVERFLOW_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_DSC_BUF_OVERFLOW_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_DSC_BUF_OVERFLOW_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_DSC_DPB_DETECT 31:31 /* RWIVF */
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#define NV_PDISP_SF_DP_IRQ_MASK_DSC_DPB_DETECT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_IRQ_MASK_DSC_DPB_DETECT_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_IRQ_MASK_DSC_DPB_DETECT_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_MSA0_DEBUG_MAUD(i) (0x0061666C+(i)*2048) /* R--4A */
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#define NV_PDISP_SF_DP_MSA0_DEBUG_MAUD__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_MSA0_DEBUG_MAUD_VALUE 23:0 /* R--UF */
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#define NV_PDISP_SF_DP_MSA1_DEBUG_MAUD(i) (0x00616670+(i)*2048) /* R--4A */
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#define NV_PDISP_SF_DP_MSA1_DEBUG_MAUD__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_MSA1_DEBUG_MAUD_VALUE 23:0 /* R--UF */
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#define NV_PDISP_SF_DP_MSA0_DEBUG_NAUD(i) (0x00616674+(i)*2048) /* R--4A */
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#define NV_PDISP_SF_DP_MSA0_DEBUG_NAUD__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_MSA0_DEBUG_NAUD_VALUE 23:0 /* R--UF */
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#define NV_PDISP_SF_DP_MSA1_DEBUG_NAUD(i) (0x00616678+(i)*2048) /* R--4A */
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#define NV_PDISP_SF_DP_MSA1_DEBUG_NAUD__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_MSA1_DEBUG_NAUD_VALUE 23:0 /* R--UF */
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#define NV_PDISP_SF_HDMI_ACR_DEBUG_CTS(i) (0x0061667C+(i)*2048) /* R--4A */
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#define NV_PDISP_SF_HDMI_ACR_DEBUG_CTS__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_ACR_DEBUG_CTS_VALUE 19:0 /* R--UF */
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#define NV_PDISP_SF_DP_DEBUG2(i) (0x00616680+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_DP_DEBUG2__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_DEBUG2_BS_WATERMARK 0:0 /* RWIVF */
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#define NV_PDISP_SF_DP_DEBUG2_BS_WATERMARK_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DP_DEBUG2_BS_WATERMARK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_DEBUG2_BS_WATERMARK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_DEBUG2_LANE_FIFO_FLUSH_MODE 1:1 /* RWIVF */
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#define NV_PDISP_SF_DP_DEBUG2_LANE_FIFO_FLUSH_MODE_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_DP_DEBUG2_LANE_FIFO_FLUSH_MODE_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_DEBUG2_LANE_FIFO_FLUSH_MODE_ASAP 0x00000001 /* RW--V */
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#define NV_PDISP_SF_CLK_METER(i) (0x00616684+(i)*2048) /* RW-4A */
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#define NV_PDISP_SF_CLK_METER__SIZE_1 8 /* */
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#define NV_PDISP_SF_CLK_METER_COUNT 23:0 /* R--UF */
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#define NV_PDISP_SF_CLK_METER_DISABLE 30:30 /* RWIVF */
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#define NV_PDISP_SF_CLK_METER_DISABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_CLK_METER_DISABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_CLK_METER_DISABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_CLK_METER_BUSY 31:31 /* R--VF */
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#define NV_PDISP_SF_CLK_METER_BUSY_NO 0x00000000 /* R---V */
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#define NV_PDISP_SF_CLK_METER_BUSY_YES 0x00000001 /* R---V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL(i) (0x006F0000+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_ENABLE_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER 4:4 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_OTHER_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE 8:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_SINGLE_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW 9:9 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS(i) (0x006F0004+(i)*1024) /* R--4A */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS_SENT 0:0 /* R-IVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_DONE 0x00000001 /* R---V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_WAITING 0x00000000 /* R---V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_STATUS_SENT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER(i) (0x006F0008+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW(i) (0x006F000C+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH(i) (0x006F0010+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW(i) (0x006F0014+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH(i) (0x006F0018+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW(i) (0x006F001C+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_AVI_INFOFRAME_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL(i) (0x006F0040+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_ENABLE_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_OTHER 4:4 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_OTHER_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_SINGLE 8:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_SINGLE_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_HBLANK 12:12 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_HBLANK_DIS 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_CTRL_HBLANK_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_GENERIC_STATUS(i) (0x006F0044+(i)*1024) /* R--4A */
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#define NV_PDISP_SF_HDMI_GENERIC_STATUS__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GENERIC_STATUS_SENT 0:0 /* R-IVF */
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#define NV_PDISP_SF_HDMI_GENERIC_STATUS_SENT_DONE 0x00000001 /* R---V */
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#define NV_PDISP_SF_HDMI_GENERIC_STATUS_SENT_WAITING 0x00000000 /* R---V */
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#define NV_PDISP_SF_HDMI_GENERIC_STATUS_SENT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_HDMI_GENERIC_HEADER(i) (0x006F0048+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_GENERIC_HEADER__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB0 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB1 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB2 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_HEADER_HB2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW(i) (0x006F004C+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH(i) (0x006F0050+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW(i) (0x006F0054+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH(i) (0x006F0058+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW(i) (0x006F005C+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH(i) (0x006F0060+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW(i) (0x006F0064+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24 31:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH(i) (0x006F0068+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GENERIC_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL(i) (0x006F0080+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_ACR_CTRL__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE_NO 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE_DIS 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_PACKET_ENABLE_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE 16:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE_YES 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE_DIS 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_ENABLE_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_PRIORITY 20:20 /* RWIVF */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_PRIORITY_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_PRIORITY_HIGH 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_PRIORITY_LOW 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS 27:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_INIT 0x00000002 /* RWI-V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_32KHZ 0x00000003 /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_44_1KHZ 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_48KHZ 0x00000002 /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_88_2KHZ 0x00000008 /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_96KHZ 0x0000000A /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_176_4KHZ 0x0000000C /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_FREQS_192KHZ 0x0000000E /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_CTS_SOURCE 31:31 /* RWIVF */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_CTS_SOURCE_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_CTS_SOURCE_HW 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_ACR_CTRL_CTS_SOURCE_SW 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_GCP_CTRL(i) (0x006F00C0+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_GCP_CTRL__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_GCP_CTRL_ENABLE_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_GCP_CTRL_OTHER 4:4 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GCP_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GCP_CTRL_OTHER_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_GCP_CTRL_SINGLE 8:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GCP_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GCP_CTRL_SINGLE_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS(i) (0x006F00C4+(i)*1024) /* R--4A */
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#define NV_PDISP_SF_HDMI_GCP_STATUS__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_SENT 0:0 /* R-IVF */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_SENT_DONE 0x00000001 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_SENT_WAITING 0x00000000 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_SENT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP 6:4 /* R--VF */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_0 0x00000004 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_1 0x00000001 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_2 0x00000002 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_START_PP_3 0x00000003 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP 10:8 /* R--VF */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_0 0x00000004 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_1 0x00000001 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_2 0x00000002 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_ACTIVE_END_PP_3 0x00000003 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP 14:12 /* R--VF */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP_0 0x00000004 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP_1 0x00000001 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP_2 0x00000002 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_START_PP_3 0x00000003 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP 18:16 /* R--VF */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP_0 0x00000004 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP_1 0x00000001 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP_2 0x00000002 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_VSYNC_END_PP_3 0x00000003 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP 22:20 /* R--VF */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP_0 0x00000004 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP_1 0x00000001 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP_2 0x00000002 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_START_PP_3 0x00000003 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP 26:24 /* R--VF */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP_0 0x00000004 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP_1 0x00000001 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP_2 0x00000002 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_STATUS_HSYNC_END_PP_3 0x00000003 /* R---V */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK(i) (0x006F00CC+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB0 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB0_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB0_SET_AVMUTE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB0_CLR_AVMUTE 0x00000010 /* RW--V */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB1 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB2 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB1_CTRL 24:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB1_CTRL_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB1_CTRL_SW 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_GCP_SUBPACK_SB1_CTRL_HW 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL(i) (0x006F0100+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_VSI_CTRL__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE_NO 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE_DIS 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_ENABLE_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_OTHER 4:4 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_OTHER_DIS 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_OTHER_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_SINGLE 8:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_SINGLE_DIS 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_SINGLE_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW 9:9 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_EN 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_DIS 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_CHKSUM_HW_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_VIDEO_FMT 16:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_VIDEO_FMT_SW_CONTROLLED 0x00000000 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_VIDEO_FMT_HW_CONTROLLED 0x00000001 /* RW--V */
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#define NV_PDISP_SF_HDMI_VSI_CTRL_VIDEO_FMT_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_STATUS(i) (0x006F0104+(i)*1024) /* R--4A */
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#define NV_PDISP_SF_HDMI_VSI_STATUS__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_VSI_STATUS_SENT 0:0 /* R-IVF */
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#define NV_PDISP_SF_HDMI_VSI_STATUS_SENT_DONE 0x00000001 /* R---V */
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#define NV_PDISP_SF_HDMI_VSI_STATUS_SENT_WAITING 0x00000000 /* R---V */
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#define NV_PDISP_SF_HDMI_VSI_STATUS_SENT_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_HDMI_VSI_HEADER(i) (0x006F0108+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_VSI_HEADER__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_VSI_HEADER_HB0 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_HEADER_HB0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_HEADER_HB1 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_HEADER_HB1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_HEADER_HB2 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_HEADER_HB2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW(i) (0x006F010C+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB0 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB1 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB2 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB3 31:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_LOW_PB3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH(i) (0x006F0110+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB5 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB6 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK0_HIGH_PB6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW(i) (0x006F0114+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB7 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB8 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB8_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB9 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB9_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB10 31:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_LOW_PB10_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH(i) (0x006F0118+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB11 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB11_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB12 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB12_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB13 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK1_HIGH_PB13_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW(i) (0x006F011C+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB14 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB14_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB15 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB15_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB16 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB16_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB17 31:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_LOW_PB17_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH(i) (0x006F0120+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB18 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB18_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB19 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB19_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB20 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK2_HIGH_PB20_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW(i) (0x006F0124+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB21 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB21_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB22 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB22_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB23 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB23_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB24 31:24 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_LOW_PB24_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH(i) (0x006F0128+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH__SIZE_1 8 /* */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB25 7:0 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB25_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB26 15:8 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB26_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB27 23:16 /* RWIVF */
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#define NV_PDISP_SF_HDMI_VSI_SUBPACK3_HIGH_PB27_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL(i) (0x006F0300+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE 1:1 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE_DONE 0x00000000 /* R---V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_IMMEDIATE_TRIGGER 0x00000001 /* -W--T */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_MSA_STEREO_OVERRIDE 2:2 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_MSA_STEREO_OVERRIDE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_MSA_STEREO_OVERRIDE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_CTRL_MSA_STEREO_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER(i) (0x006F0304+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB3 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_HEADER_HB3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0(i) (0x006F0308+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB0 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB1 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB2 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB3 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK0_DB3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1(i) (0x006F030C+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB4 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB5 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB6 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB7 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK1_DB7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2(i) (0x006F0310+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB8 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB8_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB9 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB9_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB10 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB10_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB11 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK2_DB11_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3(i) (0x006F0314+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB12 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB12_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB13 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB13_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB14 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB14_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB15 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK3_DB15_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4(i) (0x006F0318+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB16 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB16_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB17 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB17_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB18 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB18_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB19 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK4_DB19_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5(i) (0x006F031C+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB20 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB20_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB21 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB21_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB22 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB22_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB23 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK5_DB23_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6(i) (0x006F0320+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB24 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB24_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB25 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB25_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB26 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB26_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB27 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK6_DB27_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7(i) (0x006F0324+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB28 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB28_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB29 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB29_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB30 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB30_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB31 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME_SUBPACK7_DB31_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL(i) (0x006F0330+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL_HEADER_OVERRIDE 4:4 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL_HEADER_OVERRIDE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL_HEADER_OVERRIDE_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_CTRL_HEADER_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER(i) (0x006F0334+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB0 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB1 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB2 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB3 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_AUDIO_INFOFRAME_HEADER_HB3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER(i) (0x006F0344+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB0 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB1 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB2 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB3 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_HEADER_HB3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0(i) (0x006F0348+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB0 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB0_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB1 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB1_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB2 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB2_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB3 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK0_DB3_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1(i) (0x006F034C+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB4 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB4_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB5 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB5_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB6 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB6_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB7 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK1_DB7_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2(i) (0x006F0350+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB8 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB8_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB9 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB9_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB10 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB10_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB11 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK2_DB11_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3(i) (0x006F0354+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB12 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB12_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB13 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB13_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB14 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB14_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB15 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK3_DB15_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4(i) (0x006F0358+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB16 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB16_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB17 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB17_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB18 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB18_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB19 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK4_DB19_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5(i) (0x006F035C+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB20 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB20_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB21 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB21_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB22 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB22_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB23 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK5_DB23_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6(i) (0x006F0360+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB24 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB24_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB25 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB25_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB26 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB26_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB27 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK6_DB27_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7(i) (0x006F0364+(i)*1024) /* RW-4A */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7__SIZE_1 8 /* */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB28 7:0 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB28_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB29 15:8 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB29_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB30 23:16 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB30_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB31 31:24 /* RWIVF */
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#define NV_PDISP_SF_DP_GENERIC_INFOFRAME1_SUBPACK7_DB31_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_CAP(i) (0x0061C000+(i)*2048) /* R--4A */
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#define NV_PDISP_SOR_CAP__SIZE_1 8 /* */
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#define NV_PDISP_SOR_CAP_SINGLE_LVDS_18 0:0 /* R--VF */
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#define NV_PDISP_SOR_CAP_SINGLE_LVDS_18_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_SINGLE_LVDS_18_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_SINGLE_LVDS_24 1:1 /* R--VF */
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#define NV_PDISP_SOR_CAP_SINGLE_LVDS_24_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_SINGLE_LVDS_24_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_DUAL_LVDS_18 2:2 /* R--VF */
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#define NV_PDISP_SOR_CAP_DUAL_LVDS_18_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_DUAL_LVDS_18_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_DUAL_LVDS_24 3:3 /* R--VF */
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#define NV_PDISP_SOR_CAP_DUAL_LVDS_24_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_DUAL_LVDS_24_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_SINGLE_TMDS_A 8:8 /* R--VF */
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#define NV_PDISP_SOR_CAP_SINGLE_TMDS_A_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_SINGLE_TMDS_A_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_SINGLE_TMDS_B 9:9 /* R--VF */
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#define NV_PDISP_SOR_CAP_SINGLE_TMDS_B_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_SINGLE_TMDS_B_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_DUAL_TMDS 11:11 /* R--VF */
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#define NV_PDISP_SOR_CAP_DUAL_TMDS_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_DUAL_TMDS_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_DISPLAY_OVER_PCIE 13:13 /* R--VF */
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#define NV_PDISP_SOR_CAP_DISPLAY_OVER_PCIE_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_DISPLAY_OVER_PCIE_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_DP_OVER_USB 14:14 /* R--VF */
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#define NV_PDISP_SOR_CAP_DP_OVER_USB_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_DP_OVER_USB_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_SDI 16:16 /* R--VF */
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#define NV_PDISP_SOR_CAP_SDI_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_SDI_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_DP_A 24:24 /* R--VF */
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#define NV_PDISP_SOR_CAP_DP_A_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_DP_A_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_DP_B 25:25 /* R--VF */
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#define NV_PDISP_SOR_CAP_DP_B_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_DP_B_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_DP_INTERLACE 26:26 /* R--VF */
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#define NV_PDISP_SOR_CAP_DP_INTERLACE_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_DP_INTERLACE_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_DP_8_LANES 27:27 /* R--VF */
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#define NV_PDISP_SOR_CAP_DP_8_LANES_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_DP_8_LANES_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_HDMI_FRL 28:28 /* R--VF */
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#define NV_PDISP_SOR_CAP_HDMI_FRL_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_HDMI_FRL_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_CAP_LVDS_ONLY 31:31 /* R--VF */
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#define NV_PDISP_SOR_CAP_LVDS_ONLY_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_CAP_LVDS_ONLY_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_PWR(i) (0x0061C004+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_PWR__SIZE_1 8 /* */
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#define NV_PDISP_SOR_PWR_NORMAL_STATE 0:0 /* RWIVF */
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#define NV_PDISP_SOR_PWR_NORMAL_STATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_PWR_NORMAL_STATE_PD 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_PWR_NORMAL_STATE_PU 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_PWR_NORMAL_START 1:1 /* RWIVF */
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#define NV_PDISP_SOR_PWR_NORMAL_START_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_PWR_NORMAL_START_NORMAL 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_PWR_NORMAL_START_ALT 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_PWR_SAFE_STATE 16:16 /* RWIVF */
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#define NV_PDISP_SOR_PWR_SAFE_STATE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_PWR_SAFE_STATE_PD 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_PWR_SAFE_STATE_PU 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_PWR_SAFE_START 17:17 /* RWIVF */
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#define NV_PDISP_SOR_PWR_SAFE_START_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_PWR_SAFE_START_NORMAL 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_PWR_SAFE_START_ALT 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_PWR_HALT_DELAY 24:24 /* R--VF */
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#define NV_PDISP_SOR_PWR_HALT_DELAY_DONE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_PWR_HALT_DELAY_ACTIVE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_PWR_MODE 28:28 /* R-IVF */
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#define NV_PDISP_SOR_PWR_MODE_INIT 0x00000001 /* R-I-V */
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#define NV_PDISP_SOR_PWR_MODE_NORMAL 0x00000000 /* R---V */
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#define NV_PDISP_SOR_PWR_MODE_SAFE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_PWR_SETTING_NEW 31:31 /* RWIVF */
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#define NV_PDISP_SOR_PWR_SETTING_NEW_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SOR_PWR_SETTING_NEW_DONE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_PWR_SETTING_NEW_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_SOR_PWR_SETTING_NEW_TRIGGER 0x00000001 /* -W--T */
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#define NV_PDISP_SOR_TEST(i) (0x0061C008+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_TEST__SIZE_1 8 /* */
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#define NV_PDISP_SOR_TEST_ACT_HEAD_OPMODE 9:8 /* R--UF */
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#define NV_PDISP_SOR_TEST_ACT_HEAD_OPMODE_SLEEP 0x00000000 /* R---V */
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#define NV_PDISP_SOR_TEST_ACT_HEAD_OPMODE_SNOOZE 0x00000001 /* R---V */
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#define NV_PDISP_SOR_TEST_ACT_HEAD_OPMODE_AWAKE 0x00000002 /* R---V */
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#define NV_PDISP_SOR_TEST_OWNER_MASK 13:10 /* R--UF */
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#define NV_PDISP_SOR_TEST_OWNER_MASK_HEAD0 0x00000001 /* R---V */
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#define NV_PDISP_SOR_TEST_OWNER_MASK_HEAD1 0x00000002 /* R---V */
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#define NV_PDISP_SOR_TEST_OWNER_MASK_HEAD2 0x00000004 /* R---V */
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#define NV_PDISP_SOR_TEST_OWNER_MASK_HEAD3 0x00000008 /* R---V */
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#define NV_PDISP_SOR_TEST_OWNER_MASK_NONE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_TEST_TGEN 14:14 /* RWIVF */
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#define NV_PDISP_SOR_TEST_TGEN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_TEST_TGEN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_TEST_TGEN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_TEST_TCHK 15:15 /* RWIVF */
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#define NV_PDISP_SOR_TEST_TCHK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_TEST_TCHK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_TEST_TCHK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_PWM_DIV(i) (0x0061C080+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_PWM_DIV__SIZE_1 8 /* */
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#define NV_PDISP_SOR_PWM_DIV_DIVIDE 23:0 /* RWIUF */
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#define NV_PDISP_SOR_PWM_DIV_DIVIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_PWM_CTL(i) (0x0061C084+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_PWM_CTL__SIZE_1 8 /* */
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#define NV_PDISP_SOR_PWM_CTL_DUTY_CYCLE 23:0 /* RWIUF */
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#define NV_PDISP_SOR_PWM_CTL_DUTY_CYCLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_PWM_CTL_CLKSEL 30:30 /* RWIUF */
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#define NV_PDISP_SOR_PWM_CTL_CLKSEL_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_PWM_CTL_CLKSEL_PCLK 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_PWM_CTL_CLKSEL_XTAL 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW 31:31 /* RWIVF */
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#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW_DONE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_SOR_PWM_CTL_SETTING_NEW_TRIGGER 0x00000001 /* -W--T */
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#define NV_PDISP_SOR_DP_LINKCTL(i,j) (0x0061C10C+(i)*2048+(j)*128) /* RW-4A */
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#define NV_PDISP_SOR_DP_LINKCTL__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_LINKCTL__SIZE_2 2 /* */
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#define NV_PDISP_SOR_DP_LINKCTL_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK 1:1 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_ASYNC_FIFO_BLOCK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_ENHANCEDFRAME 14:14 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL_ENHANCEDFRAME_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL_ENHANCEDFRAME_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_ENHANCEDFRAME_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT 23:16 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_ZERO 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_ONE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_TWO 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_FOUR 0x0000000F /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_LANECOUNT_EIGHT 0x000000FF /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN 27:26 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_D102 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_SBLERRRATE 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_LINKQUALPTTRN_PRBS7 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_FORMAT_MODE 30:30 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL_FORMAT_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL_FORMAT_MODE_SINGLE_STREAM 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_FORMAT_MODE_MULTI_STREAM 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_FORCE_IDLEPTTRN 31:31 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL_FORCE_IDLEPTTRN_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_LINKCTL0_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL0_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL0_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_ASYNC_FIFO_BLOCK 1:1 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL0_ASYNC_FIFO_BLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL0_ASYNC_FIFO_BLOCK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_ASYNC_FIFO_BLOCK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_ENHANCEDFRAME 14:14 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL0_ENHANCEDFRAME_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL0_ENHANCEDFRAME_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_ENHANCEDFRAME_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT 23:16 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_ZERO 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_ONE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_TWO 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_FOUR 0x0000000F /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_LANECOUNT_EIGHT 0x000000FF /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN 27:26 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_D102 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_SBLERRRATE 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_LINKQUALPTTRN_PRBS7 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_FORMAT_MODE 30:30 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL0_FORMAT_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL0_FORMAT_MODE_SINGLE_STREAM 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_FORMAT_MODE_MULTI_STREAM 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_FORCE_IDLEPTTRN 31:31 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL0_FORCE_IDLEPTTRN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL0_FORCE_IDLEPTTRN_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL0_FORCE_IDLEPTTRN_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_LINKCTL1_ENABLE 0:0 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL1_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL1_ENABLE_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_ENABLE_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_ASYNC_FIFO_BLOCK 1:1 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL1_ASYNC_FIFO_BLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL1_ASYNC_FIFO_BLOCK_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_ASYNC_FIFO_BLOCK_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_ENHANCEDFRAME 14:14 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL1_ENHANCEDFRAME_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL1_ENHANCEDFRAME_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_ENHANCEDFRAME_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT 23:16 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_ZERO 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_ONE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_TWO 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_FOUR 0x0000000F /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_LANECOUNT_EIGHT 0x000000FF /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN 27:26 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_D102 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_SBLERRRATE 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_LINKQUALPTTRN_PRBS7 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_FORMAT_MODE 30:30 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL1_FORMAT_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL1_FORMAT_MODE_SINGLE_STREAM 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_FORMAT_MODE_MULTI_STREAM 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_FORCE_IDLEPTTRN 31:31 /* RWIVF */
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#define NV_PDISP_SOR_DP_LINKCTL1_FORCE_IDLEPTTRN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LINKCTL1_FORCE_IDLEPTTRN_NO 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_LINKCTL1_FORCE_IDLEPTTRN_YES 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG(i,j) (0x0061C110+(i)*2048+(j)*28) /* RW-4A */
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#define NV_PDISP_SOR_DP_TPG__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_TPG__SIZE_2 2 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN 3:0 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_TRAINING1 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_TRAINING2 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_TRAINING3 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_D102 0x00000004 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_SBLERRRATE 0x00000005 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_PRBS7 0x00000006 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_CSTM 0x00000007 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_PATTERN_TRAINING4 0x0000000B /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_SCRAMBLEREN 4:4 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG_LANE0_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_CHANNELCODING 6:6 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG_LANE0_CHANNELCODING_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_CHANNELCODING_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE0_CHANNELCODING_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN 11:8 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_TRAINING1 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_TRAINING2 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_TRAINING3 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_D102 0x00000004 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_SBLERRRATE 0x00000005 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_PRBS7 0x00000006 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_CSTM 0x00000007 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_PATTERN_TRAINING4 0x0000000B /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_SCRAMBLEREN 12:12 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG_LANE1_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_CHANNELCODING 14:14 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG_LANE1_CHANNELCODING_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_CHANNELCODING_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE1_CHANNELCODING_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN 19:16 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_TRAINING1 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_TRAINING2 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_TRAINING3 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_D102 0x00000004 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_SBLERRRATE 0x00000005 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_PRBS7 0x00000006 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_CSTM 0x00000007 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_PATTERN_TRAINING4 0x0000000B /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_SCRAMBLEREN 20:20 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG_LANE2_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_CHANNELCODING 22:22 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG_LANE2_CHANNELCODING_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_CHANNELCODING_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE2_CHANNELCODING_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN 27:24 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_TRAINING1 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_TRAINING2 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_TRAINING3 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_D102 0x00000004 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_SBLERRRATE 0x00000005 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_PRBS7 0x00000006 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_CSTM 0x00000007 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_PATTERN_TRAINING4 0x0000000B /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_SCRAMBLEREN 28:28 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG_LANE3_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_CHANNELCODING 30:30 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG_LANE3_CHANNELCODING_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_CHANNELCODING_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE3_CHANNELCODING_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN(i) (3+(i)*8):((i)*8) /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN__SIZE_1 4 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_NOPATTERN 0x00000000 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_TRAINING1 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_TRAINING2 0x00000002 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_TRAINING3 0x00000003 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_D102 0x00000004 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_SBLERRRATE 0x00000005 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_PRBS7 0x00000006 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_CSTM 0x00000007 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_HBR2_COMPLIANCE 0x00000008 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_CP2520_PAT1 0x00000009 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_CP2520_PAT3 0x0000000A /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_PATTERN_TRAINING4 0x0000000B /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN(i) (4+(i)*8):(4+(i)*8) /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN__SIZE_1 4 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN_INIT 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_SCRAMBLEREN_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING(i) (6+(i)*8):(6+(i)*8) /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING__SIZE_1 4 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING_INIT 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG_LANE_CHANNELCODING_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_TPG0__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN 3:0 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_TRAINING1 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_TRAINING2 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_TRAINING3 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_D102 0x00000004 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_SBLERRRATE 0x00000005 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_PRBS7 0x00000006 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_CSTM 0x00000007 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_PATTERN_TRAINING4 0x0000000B /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_SCRAMBLEREN 4:4 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_CHANNELCODING 6:6 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_CHANNELCODING_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_CHANNELCODING_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE0_CHANNELCODING_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN 11:8 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_TRAINING1 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_TRAINING2 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_TRAINING3 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_D102 0x00000004 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_SBLERRRATE 0x00000005 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_PRBS7 0x00000006 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_CSTM 0x00000007 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_PATTERN_TRAINING4 0x0000000B /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_SCRAMBLEREN 12:12 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_CHANNELCODING 14:14 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_CHANNELCODING_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_CHANNELCODING_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE1_CHANNELCODING_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN 19:16 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_TRAINING1 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_TRAINING2 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_TRAINING3 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_D102 0x00000004 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_SBLERRRATE 0x00000005 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_PRBS7 0x00000006 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_CSTM 0x00000007 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_PATTERN_TRAINING4 0x0000000B /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_SCRAMBLEREN 20:20 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_CHANNELCODING 22:22 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_CHANNELCODING_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_CHANNELCODING_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE2_CHANNELCODING_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN 27:24 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_TRAINING1 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_TRAINING2 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_TRAINING3 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_D102 0x00000004 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_SBLERRRATE 0x00000005 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_PRBS7 0x00000006 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_CSTM 0x00000007 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_PATTERN_TRAINING4 0x0000000B /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_SCRAMBLEREN 28:28 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_CHANNELCODING 30:30 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_CHANNELCODING_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_CHANNELCODING_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE3_CHANNELCODING_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN(i) (3+(i)*8):((i)*8) /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN__SIZE_1 4 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_NOPATTERN 0x00000000 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_TRAINING1 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_TRAINING2 0x00000002 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_TRAINING3 0x00000003 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_D102 0x00000004 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_SBLERRRATE 0x00000005 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_PRBS7 0x00000006 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_CSTM 0x00000007 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_HBR2_COMPLIANCE 0x00000008 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_CP2520_PAT1 0x00000009 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_CP2520_PAT3 0x0000000A /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_PATTERN_TRAINING4 0x0000000B /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN(i) (4+(i)*8):(4+(i)*8) /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN__SIZE_1 4 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN_INIT 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_SCRAMBLEREN_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING(i) (6+(i)*8):(6+(i)*8) /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING__SIZE_1 4 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING_INIT 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG0_LANE_CHANNELCODING_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_TPG1__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN 3:0 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_TRAINING1 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_TRAINING2 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_TRAINING3 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_D102 0x00000004 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_SBLERRRATE 0x00000005 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_PRBS7 0x00000006 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_CSTM 0x00000007 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_PATTERN_TRAINING4 0x0000000B /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_SCRAMBLEREN 4:4 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_CHANNELCODING 6:6 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_CHANNELCODING_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_CHANNELCODING_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE0_CHANNELCODING_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN 11:8 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_TRAINING1 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_TRAINING2 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_TRAINING3 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_D102 0x00000004 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_SBLERRRATE 0x00000005 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_PRBS7 0x00000006 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_CSTM 0x00000007 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_PATTERN_TRAINING4 0x0000000B /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_SCRAMBLEREN 12:12 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_CHANNELCODING 14:14 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_CHANNELCODING_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_CHANNELCODING_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE1_CHANNELCODING_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN 19:16 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_TRAINING1 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_TRAINING2 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_TRAINING3 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_D102 0x00000004 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_SBLERRRATE 0x00000005 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_PRBS7 0x00000006 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_CSTM 0x00000007 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_PATTERN_TRAINING4 0x0000000B /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_SCRAMBLEREN 20:20 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_CHANNELCODING 22:22 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_CHANNELCODING_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_CHANNELCODING_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE2_CHANNELCODING_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN 27:24 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_NOPATTERN 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_TRAINING1 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_TRAINING2 0x00000002 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_TRAINING3 0x00000003 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_D102 0x00000004 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_SBLERRRATE 0x00000005 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_PRBS7 0x00000006 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_CSTM 0x00000007 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_HBR2_COMPLIANCE 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_CP2520_PAT1 0x00000009 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_CP2520_PAT3 0x0000000A /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_PATTERN_TRAINING4 0x0000000B /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_SCRAMBLEREN 28:28 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_SCRAMBLEREN_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_SCRAMBLEREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_SCRAMBLEREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_CHANNELCODING 30:30 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_CHANNELCODING_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_CHANNELCODING_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE3_CHANNELCODING_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN(i) (3+(i)*8):((i)*8) /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN__SIZE_1 4 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_NOPATTERN 0x00000000 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_TRAINING1 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_TRAINING2 0x00000002 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_TRAINING3 0x00000003 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_D102 0x00000004 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_SBLERRRATE 0x00000005 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_PRBS7 0x00000006 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_CSTM 0x00000007 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_HBR2_COMPLIANCE 0x00000008 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_CP2520_PAT1 0x00000009 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_CP2520_PAT3 0x0000000A /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_PATTERN_TRAINING4 0x0000000B /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN(i) (4+(i)*8):(4+(i)*8) /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN__SIZE_1 4 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN_INIT 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_SCRAMBLEREN_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING(i) (6+(i)*8):(6+(i)*8) /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING__SIZE_1 4 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING_INIT 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_TPG1_LANE_CHANNELCODING_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_TPG_CONFIG(i) (0x0061C114+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_DP_TPG_CONFIG__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_TPG_CONFIG_HBR2_COMPLIANCE_PERIOD 16:0 /* RWIVF */
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#define NV_PDISP_SOR_DP_TPG_CONFIG_HBR2_COMPLIANCE_PERIOD_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK(i) (0x0061C718+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK(i) (0x0061C71C+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWI-V */
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#define NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MS_CTL(i) (0x0061C150+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_DP_MS_CTL__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_MS_CTL__PRIV_LEVEL_MASK NV_PDISP_SOR_DP_MST_MS_CTL_PRIV_LEVEL_MASK /* */
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#define NV_PDISP_SOR_DP_MS_CTL_SEND_ACT 0:0 /* RWIVF */
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#define NV_PDISP_SOR_DP_MS_CTL_SEND_ACT_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_MS_CTL_SEND_ACT_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MS_CTL_SEND_ACT_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_MS_CTL_SF_MASK 11:8 /* RWIVF */
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#define NV_PDISP_SOR_DP_MS_CTL_SF_MASK_INIT 0x0000000F /* RWI-V */
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#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE 29:29 /* RWIVF */
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#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE_YES 0x00000001 /* R---V */
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#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE_NO 0x00000000 /* R---V */
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#define NV_PDISP_SOR_DP_MS_CTL_SIXTEEN_MTP_AFTER_TRIG_IMMEDIATE_DONE_RESET 0x00000000 /* -W--V */
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#define NV_PDISP_SOR_DP_MS_CTL_TRIG_ON_ATTACH 30:30 /* RWIVF */
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#define NV_PDISP_SOR_DP_MS_CTL_TRIG_ON_ATTACH_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_SOR_DP_MS_CTL_TRIG_ON_ATTACH_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_DP_MS_CTL_TRIG_ON_ATTACH_DISABLE 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE 31:31 /* RWIVF */
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#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE_DONE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_SOR_DP_MS_CTL_TRIG_IMMEDIATE_TRIGGER 0x00000001 /* -W--T */
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#define NV_PDISP_SOR_DP_LQ_CSTM(i,j) (0x0061C154+(i)*2048+(j)*4) /* RW-4A */
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#define NV_PDISP_SOR_DP_LQ_CSTM__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_LQ_CSTM__SIZE_2 3 /* */
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#define NV_PDISP_SOR_DP_LQ_CSTM_SYM 31:0 /* RWIUF */
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#define NV_PDISP_SOR_DP_LQ_CSTM_SYM_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LQ_CSTM0(i) (0x0061C154+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_DP_LQ_CSTM0__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_LQ_CSTM0_SYM 31:0 /* RWIUF */
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#define NV_PDISP_SOR_DP_LQ_CSTM0_SYM_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LQ_CSTM1(i) (0x0061C158+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_DP_LQ_CSTM1__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_LQ_CSTM1_SYM 31:0 /* RWIUF */
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#define NV_PDISP_SOR_DP_LQ_CSTM1_SYM_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_LQ_CSTM2(i) (0x0061C15C+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_DP_LQ_CSTM2__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_LQ_CSTM2_SYM 31:0 /* RWIUF */
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#define NV_PDISP_SOR_DP_LQ_CSTM2_SYM_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_ECF0(i) (0x0061C160+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_DP_ECF0__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_ECF0__PRIV_LEVEL_MASK NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK /* */
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#define NV_PDISP_SOR_DP_ECF0_VALUE 31:0 /* RWIVF */
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#define NV_PDISP_SOR_DP_ECF0_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_ECF0_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_ECF1(i) (0x0061C164+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_DP_ECF1__SIZE_1 8 /* */
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#define NV_PDISP_SOR_DP_ECF1__PRIV_LEVEL_MASK NV_PDISP_SOR_DP_MST_ECF_PRIV_LEVEL_MASK /* */
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#define NV_PDISP_SOR_DP_ECF1_VALUE 30:0 /* RWIVF */
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#define NV_PDISP_SOR_DP_ECF1_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_DP_ECF1_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS 31:31 /* RWIVF */
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#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS_DONE 0x00000000 /* R---V */
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#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS_PENDING 0x00000001 /* R---V */
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#define NV_PDISP_SOR_DP_ECF1_NEW_SETTINGS_TRIGGER 0x00000001 /* -W--T */
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#define NV_PDISP_SOR_HDMI2_CTRL(i) (0x0061C5BC+(i)*2048) /* RW-4A */
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#define NV_PDISP_SOR_HDMI2_CTRL__SIZE_1 8 /* */
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#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE 0:0 /* RWIVF */
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#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_HDMI2_CTRL_CLOCK_MODE 1:1 /* RWIVF */
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#define NV_PDISP_SOR_HDMI2_CTRL_CLOCK_MODE_NORMAL 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_AT_LOADV 2:2 /* RWIVF */
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#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_AT_LOADV_DISABLE 0x00000000 /* RWI-V */
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#define NV_PDISP_SOR_HDMI2_CTRL_SCRAMBLE_AT_LOADV_ENABLE 0x00000001 /* RW--V */
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#define NV_PDISP_SOR_HDMI2_CTRL_SSCP_LENGTH 7:4 /* RWIVF */
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#define NV_PDISP_SOR_HDMI2_CTRL_SSCP_LENGTH_INIT 0x00000008 /* RWI-V */
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#define NV_PDISP_SOR_HDMI2_CTRL_SSCP_START 31:16 /* RWIVF */
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#define NV_PDISP_SOR_HDMI2_CTRL_SSCP_START_INIT 0x00000214 /* RWI-V */
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#define NV_VERIF_DP_BFM_REG_VC_ALC(i) (0x00000008+(i)*1) /* */
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#define NV_VERIF_DP_BFM_REG_VC_ALC__SIZE_1 63 /* */
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#define NV_VERIF_DP_BFM_REG_VC_ALC_VALUE 6:0 /* */
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#define NV_VERIF_DP_BFM_REG_VC_ALC_PBN 31:16 /* */
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#define NV_VERIF_DP_BFM_REG_ALC_VLD 0x00000047 /* */
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#define NV_VERIF_DP_BFM_REG_ALC_VLD_VALUE 0:0 /* */
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#define NV_VERIF_DP_BFM_REG_ALC_VLD_VALUE_INIT 0x00000000 /* */
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#define NV_VERIF_DP_BFM_REG_ALC_VLD_VALUE_ENABLE 0x00000001 /* */
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#define NV_VERIF_DP_BFM_REG_ALC_VLD_VALUE_DISABLE 0x00000000 /* */
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#define NV_PDISP_WBOR_CAP(i) (0x00622000+(i)*512) /* R--4A */
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#define NV_PDISP_WBOR_CAP__SIZE_1 8 /* */
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#define NV_PDISP_WBOR_CAP_MAX_PIXELS_PER_LINE 15:0 /* R-IVF */
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#define NV_PDISP_WBOR_CAP_MAX_PIXELS_PER_LINE_INIT 0x00000F00 /* R-I-V */
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#define NV_PDISP_WBOR_MMUNACK(i) (0x00622004+(i)*512) /* RW-4A */
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#define NV_PDISP_WBOR_MMUNACK__SIZE_1 8 /* */
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#define NV_PDISP_WBOR_MMUNACK_COUNT 15:0 /* RWIVF */
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#define NV_PDISP_WBOR_MMUNACK_COUNT_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_WBOR_MMUNACK_COUNT_RESET 0x00000000 /* RW--V */
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#define NV_PDISP_WBOR_LOADV_COUNTER(i) (0x00622008+(i)*512) /* RW-4A */
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#define NV_PDISP_WBOR_LOADV_COUNTER__SIZE_1 8 /* */
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#define NV_PDISP_WBOR_LOADV_COUNTER_VALUE 31:0 /* RWIUF */
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#define NV_PDISP_WBOR_LOADV_COUNTER_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_WBOR_LOADV_COUNTER_VALUE_ZERO 0x00000000 /* RW--V */
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#define NV_PDISP_WBOR_GET_STATUS(i) (0x0062200C+(i)*512) /* R--4A */
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#define NV_PDISP_WBOR_GET_STATUS__SIZE_1 8 /* */
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#define NV_PDISP_WBOR_GET_STATUS_HEAD_OP_MODE 1:0 /* R-IUF */
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#define NV_PDISP_WBOR_GET_STATUS_HEAD_OP_MODE_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_WBOR_GET_STATUS_HEAD_OP_MODE_SLEEP 0x00000000 /* R---V */
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#define NV_PDISP_WBOR_GET_STATUS_HEAD_OP_MODE_SNOOZE 0x00000001 /* R---V */
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#define NV_PDISP_WBOR_GET_STATUS_HEAD_OP_MODE_AWAKE 0x00000002 /* R---V */
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#define NV_PDISP_WBOR_GET_STATUS_STALLED 12:12 /* R-IUF */
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#define NV_PDISP_WBOR_GET_STATUS_STALLED_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_WBOR_GET_STATUS_STALLED_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_WBOR_GET_STATUS_STALLED_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_WBOR_GET_STATUS_ATTACHED 31:31 /* R-IUF */
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#define NV_PDISP_WBOR_GET_STATUS_ATTACHED_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_WBOR_GET_STATUS_ATTACHED_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_WBOR_GET_STATUS_ATTACHED_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_WBOR_CRCA(i) (0x00622010+(i)*512) /* RW-4A */
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#define NV_PDISP_WBOR_CRCA__SIZE_1 8 /* */
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#define NV_PDISP_WBOR_CRCA_VALID 0:0 /* R-IVF */
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#define NV_PDISP_WBOR_CRCA_VALID_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_WBOR_CRCA_VALID_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_WBOR_CRCA_VALID_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_WBOR_CRCA_ERROR 1:1 /* R-IVF */
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#define NV_PDISP_WBOR_CRCA_ERROR_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_WBOR_CRCA_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_WBOR_CRCA_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_WBOR_CRCA_VPR_STATUS 2:2 /* R-IVF */
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#define NV_PDISP_WBOR_CRCA_VPR_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_WBOR_CRCA_VPR_STATUS_FALSE 0x00000000 /* R---V */
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#define NV_PDISP_WBOR_CRCA_VPR_STATUS_TRUE 0x00000001 /* R---V */
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#define NV_PDISP_WBOR_CRCA_FORCE_ENABLE 31:31 /* RWIVF */
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#define NV_PDISP_WBOR_CRCA_FORCE_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_WBOR_CRCA_FORCE_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PDISP_WBOR_CRCA_FORCE_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK(i) (0x00622014+(i)*512) /* RW-4A */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK__SIZE_1 8 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL 0x000FFFFF /* RWI-V */
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#define NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_PDISP_WBOR_CRCB(i) (0x00622018+(i)*512) /* R--4A */
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#define NV_PDISP_WBOR_CRCB__SIZE_1 8 /* */
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#define NV_PDISP_WBOR_CRCB__PRIV_LEVEL_MASK NV_PDISP_WBOR_CRC_PRIV_LEVEL_MASK /* */
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#define NV_PDISP_WBOR_CRCB_CRC 31:0 /* R-IVF */
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#define NV_PDISP_WBOR_CRCB_CRC_INIT 0x00000000 /* R-I-V */
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#define NV_PDISP_WBOR_ELV(i) (0x0062201C+(i)*512) /* RW-4A */
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#define NV_PDISP_WBOR_ELV__SIZE_1 8 /* */
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#define NV_PDISP_WBOR_ELV_START 14:0 /* RWIUF */
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#define NV_PDISP_WBOR_ELV_START_INIT 0x00000003 /* RWI-V */
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#define NV_PDISP_VGA_INDIRECT_SCRATCH(i) (0x00625E00+(i)*4) /* RW-4A */
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#define NV_PDISP_VGA_INDIRECT_SCRATCH__SIZE_1 16 /* */
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#define NV_PDISP_VGA_INDIRECT_SCRATCH_BYTE3 31:24 /* RWX-F */
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#define NV_PDISP_VGA_INDIRECT_SCRATCH_BYTE2 23:16 /* RWX-F */
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#define NV_PDISP_VGA_INDIRECT_SCRATCH_BYTE1 15:8 /* RWX-F */
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#define NV_PDISP_VGA_INDIRECT_SCRATCH_BYTE0 7:0 /* RWX-F */
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#define NV_PDISP_VGA_BASE 0x00625F00 /* RW-4R */
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#define NV_PDISP_VGA_BASE_TARGET 1:0 /* RWIVF */
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#define NV_PDISP_VGA_BASE_TARGET_PHYS_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_VGA_BASE_TARGET_PHYS_NVM 0x00000001 /* RW--V */
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#define NV_PDISP_VGA_BASE_TARGET_PHYS_PCI 0x00000002 /* RW--V */
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#define NV_PDISP_VGA_BASE_TARGET_PHYS_PCI_COHERENT 0x00000003 /* RW--V */
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#define NV_PDISP_VGA_BASE_STATUS 3:3 /* RWIVF */
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#define NV_PDISP_VGA_BASE_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_VGA_BASE_STATUS_INVALID 0x00000000 /* RW--V */
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#define NV_PDISP_VGA_BASE_STATUS_VALID 0x00000001 /* RW--V */
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#define NV_PDISP_VGA_BASE_ADDR 31:10 /* RWIVF */
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#define NV_PDISP_VGA_BASE_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_VGA_WORKSPACE_BASE 0x00625F04 /* RW-4R */
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#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET 1:0 /* RWIVF */
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#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET_PHYS_INIT 0x00000001 /* RWI-V */
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#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET_PHYS_NVM 0x00000001 /* RW--V */
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#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET_PHYS_PCI 0x00000002 /* RW--V */
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#define NV_PDISP_VGA_WORKSPACE_BASE_TARGET_PHYS_PCI_COHERENT 0x00000003 /* RW--V */
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#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS 3:3 /* RWIVF */
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#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_INIT 0x00000000 /* RWI-V */
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#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_INVALID 0x00000000 /* RW--V */
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#define NV_PDISP_VGA_WORKSPACE_BASE_STATUS_VALID 0x00000001 /* RW--V */
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#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR 31:8 /* RWIVF */
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#define NV_PDISP_VGA_WORKSPACE_BASE_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_UDISP 0x006FFFFF:0x00670000 /* RW--D */
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#define NV_UDISP_PVT 0x0067FFFF:0x00670000 /* RW--D */
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#define NV_UDISP_CORE 0x0068FFFF:0x00680000 /* RW--D */
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#define NV_UDISP_REMAP 0x006FFFFF:0x00690000 /* RW--D */
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#define NV_UDISP_REMAP_PAGE0 0x0069FFFF:0x00690000 /* RW--D */
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#define NV_UDISP_REMAP_PAGE1 0x006AFFFF:0x006A0000 /* RW--D */
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#define NV_UDISP_REMAP_PAGE2 0x006BFFFF:0x006B0000 /* RW--D */
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#define NV_UDISP_REMAP_PAGE3 0x006CFFFF:0x006C0000 /* RW--D */
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#define NV_UDISP_REMAP_PAGE4 0x006DFFFF:0x006D0000 /* RW--D */
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#define NV_UDISP_REMAP_PAGE5 0x006EFFFF:0x006E0000 /* RW--D */
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#define NV_UDISP_REMAP_PAGE6 0x006FFFFF:0x006F0000 /* RW--D */
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#define NV_UDISP_FE_CORE_PUT 0x00680000 /* RW-4R */
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#define NV_UDISP_FE_CORE_PUT_POINTER 11:2 /* RWIUF */
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#define NV_UDISP_FE_CORE_PUT_POINTER_INIT 0x00000000 /* RWI-V */
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#define NV_UDISP_FE_CORE_PUT_POINTER_STATUS 31:31 /* R-IVF */
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#define NV_UDISP_FE_CORE_PUT_POINTER_STATUS_INIT 0x00000001 /* R-I-V */
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#define NV_UDISP_FE_CORE_PUT_POINTER_STATUS_WRITABLE 0x00000000 /* R---V */
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#define NV_UDISP_FE_CORE_PUT_POINTER_STATUS_LOCKED 0x00000001 /* R---V */
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#define NV_UDISP_FE_CORE_GET 0x00680004 /* R--4R */
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#define NV_UDISP_FE_CORE_GET_POINTER 11:2 /* R--UF */
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#define NV_UDISP_FE_SAT_PUT(i) (0x00690000+(i)*4096) /* RW-4A */
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#define NV_UDISP_FE_SAT_PUT__SIZE_1 72 /* */
|
|
#define NV_UDISP_FE_SAT_PUT_POINTER 11:2 /* RWIUF */
|
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#define NV_UDISP_FE_SAT_PUT_POINTER_INIT 0x00000000 /* RWI-V */
|
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#define NV_UDISP_FE_SAT_PUT_POINTER_STATUS 31:31 /* R-IVF */
|
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#define NV_UDISP_FE_SAT_PUT_POINTER_STATUS_INIT 0x00000001 /* R-I-V */
|
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#define NV_UDISP_FE_SAT_PUT_POINTER_STATUS_WRITABLE 0x00000000 /* R---V */
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#define NV_UDISP_FE_SAT_PUT_POINTER_STATUS_LOCKED 0x00000001 /* R---V */
|
|
#define NV_UDISP_FE_SAT_GET(i) (0x00690004+(i)*4096) /* R--4A */
|
|
#define NV_UDISP_FE_SAT_GET__SIZE_1 72 /* */
|
|
#define NV_UDISP_FE_SAT_GET_POINTER 11:2 /* R--UF */
|
|
#define NV_UDISP_FE_PUT(i) ((i)>0?((0x00690000+(((i)-1))*4096)):0x00680000) /* */
|
|
#define NV_UDISP_FE_PUT__SIZE_1 73 /* */
|
|
#define NV_UDISP_FE_PUT_POINTER 11:2 /* */
|
|
#define NV_UDISP_FE_PUT_POINTER_INIT 0x00000000 /* */
|
|
#define NV_UDISP_FE_PUT_POINTER_STATUS 31:31 /* */
|
|
#define NV_UDISP_FE_PUT_POINTER_STATUS_INIT 0x00000001 /* */
|
|
#define NV_UDISP_FE_PUT_POINTER_STATUS_WRITABLE 0x00000000 /* */
|
|
#define NV_UDISP_FE_PUT_POINTER_STATUS_LOCKED 0x00000001 /* */
|
|
#define NV_UDISP_FE_GET(i) ((i)>0?((0x00690004+(((i)-1))*4096)):0x00680004) /* */
|
|
#define NV_UDISP_FE_GET__SIZE_1 73 /* */
|
|
#define NV_UDISP_FE_GET_POINTER 11:2 /* */
|
|
#define NV_UDISP_FE_CHN_ARMED_PCALC 0x00670000 /* R--4R */
|
|
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN_PVT(i) (0x00674000+(i)*1024) /* R--4A */
|
|
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN_PVT__SIZE_1 32 /* */
|
|
#define NV_UDISP_FE_CHN_ARMED_BASEADR_WIN_PVT(i) (0x00674200+(i)*1024) /* R--4A */
|
|
#define NV_UDISP_FE_CHN_ARMED_BASEADR_WIN_PVT__SIZE_1 32 /* */
|
|
#define NV_UDISP_FE_CHN_ASSY_CORE_PVT 0x0067E000 /* R--4R */
|
|
#define NV_UDISP_FE_CHN_ARMED_CORE_PVT 0x0067F000 /* R--4R */
|
|
#define NV_UDISP_FE_CHN_ASSY_BASEADR_CORE 0x00680000 /* */
|
|
#define NV_UDISP_FE_CHN_ARMED_BASEADR_CORE (0x00680000+32768) /* */
|
|
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN(i) ((0x00690000+(i)*4096)) /* */
|
|
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WIN__SIZE_1 32 /* */
|
|
#define NV_UDISP_FE_CHN_ARMED_BASEADR_WIN(i) ((0x00690000+(i)*4096)+2048) /* */
|
|
#define NV_UDISP_FE_CHN_ARMED_BASEADR_WIN__SIZE_1 32 /* */
|
|
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM(i) ((0x00690000+(((i)+32))*4096)) /* */
|
|
#define NV_UDISP_FE_CHN_ASSY_BASEADR_WINIM__SIZE_1 32 /* */
|
|
#define NV_UDISP_FE_CHN_ARMED_BASEADR_WINIM(i) ((0x00690000+(((i)+32))*4096)+2048) /* */
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#define NV_UDISP_FE_CHN_ARMED_BASEADR_WINIM__SIZE_1 32 /* */
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#define NV_UDISP_FE_CHN_ASSY_BASEADR_CURS(i) (0x006D8000+(i)*4096) /* RW-4A */
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#define NV_UDISP_FE_CHN_ASSY_BASEADR_CURS__SIZE_1 8 /* */
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#define NV_UDISP_FE_CHN_ARMED_BASEADR_CURS(i) (0x006D8800+(i)*4096) /* R--4A */
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#define NV_UDISP_FE_CHN_ARMED_BASEADR_CURS__SIZE_1 8 /* */
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#define NV_UDISP_FE_CHN_ASSY_BASEADR(i) ((i)>0?(((0x00690000+((i)-1)*4096))):0x00680000) /* */
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#define NV_UDISP_FE_CHN_ASSY_BASEADR__SIZE_1 81 /* */
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#define NV_UDISP_FE_CHN_ARMED_BASEADR(i) ((i)>0?(((0x00690000+((i)-1)*4096)+2048)):(0x00680000+32768)) /* */
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#define NV_UDISP_FE_CHN_ARMED_BASEADR__SIZE_1 81 /* */
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#define NV_UDISP_FE_CHN_PCALC 0x00670000 /* R--4R */
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#define NV_UDISP_FE_CHN_CORE_PVT 0x0067E000 /* R--4R */
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#define NV_UDISP_FE_CHN_WIN_PVT(i) (0x00674000+(i)*1024) /* R--4A */
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#define NV_UDISP_FE_CHN_WIN_PVT__SIZE_1 32 /* */
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#define NV_UDISP_FE_CHN_CORE_VARIABLES 0x0067E400 /* R--4R */
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#define NV_UDISP_FE_CHN_LOCAL 0x0067E800 /* R--4R */
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#define NV_UDISP_FE_CHN_CORE 0x00680000 /* */
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#define NV_UDISP_FE_CHN_WIN(i) (((0x00690000+(i)*4096))) /* */
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#define NV_UDISP_FE_CHN_WIN__SIZE_1 32 /* */
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#define NV_UDISP_FE_CHN_WINIM(i) (((0x00690000+(((i)+32))*4096))) /* */
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#define NV_UDISP_FE_CHN_WINIM__SIZE_1 32 /* */
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#define NV_UDISP_FE_CHN_CURS(i) ((0x006D8000+(i)*4096)) /* */
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#define NV_UDISP_FE_CHN_CURS__SIZE_1 8 /* */
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#define NV_UDISP_FE_CHN_CORE_BASEADR 0x00680000 /* */
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#define NV_UDISP_FE_CHN_WIN_BASEADR(i) (((0x00690000+(i)*4096))) /* */
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#define NV_UDISP_FE_CHN_WIN_BASEADR__SIZE_1 32 /* */
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#define NV_UDISP_FE_CHN_WINIM_BASEADR(i) (((0x00690000+(((i)+32))*4096))) /* */
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#define NV_UDISP_FE_CHN_WINIM_BASEADR__SIZE_1 32 /* */
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#define NV_UDISP_FE_CHN_CURS_BASEADR(i) ((0x006D8000+(i)*4096)) /* */
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#define NV_UDISP_FE_CHN_CURS_BASEADR__SIZE_1 8 /* */
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#define NV_UDISP_DMA /* ----G */
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#define NV_UDISP_DMA_OPCODE 31:29 /* RWXVF */
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#define NV_UDISP_DMA_OPCODE_METHOD 0x00000000 /* RW--V */
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#define NV_UDISP_DMA_OPCODE_JUMP 0x00000001 /* RW--V */
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#define NV_UDISP_DMA_OPCODE_NONINC_METHOD 0x00000002 /* RW--V */
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#define NV_UDISP_DMA_OPCODE_SET_SUBDEVICE_MASK 0x00000003 /* RW--V */
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#define NV_UDISP_DMA_METHOD_COUNT 27:18 /* RWXUF */
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#define NV_UDISP_DMA_METHOD_OFFSET 13:2 /* RWXUF */
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#define NV_UDISP_DMA_DATA 31:0 /* RWXUF */
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#define NV_UDISP_DMA_DATA_NOP 0x00000000 /* RW--V */
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#define NV_UDISP_DMA_JUMP_OFFSET 11:2 /* RWXUF */
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#define NV_UDISP_DMA_SET_SUBDEVICE_MASK_VALUE 11:0 /* RWXUF */
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