1503 lines
132 KiB
C
1503 lines
132 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_ce_h__
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#define __ga102_dev_ce_h__
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/* This file is autogenerated. Do not edit */
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#define NV_CE 0x105fff:0x104000 /* RW--D */
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#define NV_CE_ENGCAP 0x00104020 /* C--4R */
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#define NV_CE_ENGCAP_RESERVED 0:0 /* C--UF */
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#define NV_CE_ENGCAP_RESERVED_NOT_SUPPORTED 0x00000000 /* C---V */
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#define NV_CE_CLASS 0x00104024 /* C--4R */
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#define NV_CE_CLASS_CODE 15:0 /* C--UF */
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#define NV_CE_CLASS_CODE_VALUE 51125 /* C---V */
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#define NV_CE_PCE_MAP 0x00104028 /* R--4R */
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#define NV_CE_PCE_MAP_VALUE 23:0 /* R-XVF */
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#define NV_CE_HSH_PCE_MASK 0x0010404c /* C--4R */
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#define NV_CE_HSH_PCE_MASK_VALUE 23:0 /* C--VF */
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#define NV_CE_HSH_PCE_MASK_VALUE_INIT 15 /* C---V */
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#define NV_CE_HSH_PCE_UTLB_STRIDE 0x00104050 /* C--4R */
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#define NV_CE_HSH_PCE_UTLB_STRIDE_VALUE 3:0 /* C--VF */
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#define NV_CE_HSH_PCE_UTLB_STRIDE_VALUE_INIT 2 /* C---V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK 0x00104048 /* RW-4R */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWI-V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000C /* RWI-V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_CE_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_CE_OPT 0x00104040 /* RW-4R */
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#define NV_CE_OPT__PRIV_LEVEL_MASK 0x00104048 /* */
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#define NV_CE_OPT_FAULT_BUF_MAGIC_NUM_CHK 0:0 /* RWIVF */
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#define NV_CE_OPT_FAULT_BUF_MAGIC_NUM_CHK_TRUE 0x00000001 /* RWI-V */
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#define NV_CE_OPT_FAULT_BUF_MAGIC_NUM_CHK_FALSE 0x00000000 /* RW--V */
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#define NV_CE_OPT_FAULT_BUF_CRC_EN 1:1 /* RWIVF */
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#define NV_CE_OPT_FAULT_BUF_CRC_EN_TRUE 0x00000001 /* RWI-V */
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#define NV_CE_OPT_FAULT_BUF_CRC_EN_FALSE 0x00000000 /* RW--V */
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#define NV_CE_OPT_PCE_PRI_CONFIG_DLY_CNT 10:2 /* RWIVF */
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#define NV_CE_OPT_PCE_PRI_CONFIG_DLY_CNT__INIT 0x0 /* RWI-V */
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#define NV_CE_OPT_PCE_RST_CONFIG_DLY_CNT 19:11 /* RWIVF */
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#define NV_CE_OPT_PCE_RST_CONFIG_DLY_CNT__INIT 0x0 /* RWI-V */
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#define NV_CE_OPT_STALLREQ_LEGACY 20:20 /* RWIVF */
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#define NV_CE_OPT_STALLREQ_LEGACY_TRUE 0x00000001 /* RW--V */
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#define NV_CE_OPT_STALLREQ_LEGACY_FALSE 0x00000000 /* RWI-V */
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#define NV_CE_OPT_CONFIG_UPDATE_CTX_LD 21:21 /* RWIVF */
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#define NV_CE_OPT_CONFIG_UPDATE_CTX_LD_TRUE 0x00000001 /* RWI-V */
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#define NV_CE_OPT_CONFIG_UPDATE_CTX_LD_FALSE 0x00000000 /* RW--V */
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#define NV_CE_OPT_IGNORE_NVLINK_DISABLE 22:22 /* RWIVF */
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#define NV_CE_OPT_IGNORE_NVLINK_DISABLE_TRUE 0x00000001 /* RW--V */
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#define NV_CE_OPT_IGNORE_NVLINK_DISABLE_FALSE 0x00000000 /* RWI-V */
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#define NV_CE_OPT_RESERVED_CYA0 28:28 /* RWIVF */
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#define NV_CE_OPT_RESERVED_CYA0_TRUE 0x00000001 /* RW--V */
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#define NV_CE_OPT_RESERVED_CYA0_FALSE 0x00000000 /* RWI-V */
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#define NV_CE_OPT_RESERVED_CYA1 29:29 /* RWIVF */
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#define NV_CE_OPT_RESERVED_CYA1_TRUE 0x00000001 /* RW--V */
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#define NV_CE_OPT_RESERVED_CYA1_FALSE 0x00000000 /* RWI-V */
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#define NV_CE_OPT_RESERVED_CYA2 30:30 /* RWIVF */
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#define NV_CE_OPT_RESERVED_CYA2_TRUE 0x00000001 /* RW--V */
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#define NV_CE_OPT_RESERVED_CYA2_FALSE 0x00000000 /* RWI-V */
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#define NV_CE_OPT_RESERVED_CYA3 31:31 /* RWIVF */
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#define NV_CE_OPT_RESERVED_CYA3_TRUE 0x00000001 /* RW--V */
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#define NV_CE_OPT_RESERVED_CYA3_FALSE 0x00000000 /* RWI-V */
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#define NV_CE_ELCG 0x00104044 /* RW-4R */
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#define NV_CE_ELCG_UNUSED_PCE 0:0 /* RWIVF */
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#define NV_CE_ELCG_UNUSED_PCE_ENABLE 0x00000001 /* RW--V */
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#define NV_CE_ELCG_UNUSED_PCE_DISABLE 0x00000000 /* RWI-V */
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#define NV_CE_ELCG_UNUSED_PCE__PROD 0x00000001 /* RW--V */
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#define NV_CE_METHOD_BUFFER 0x0010402c /* R--4R */
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#define NV_CE_METHOD_BUFFER_DEPTH 15:0 /* R--VF */
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#define NV_CE_PCE2LCE_CONFIG(i) (0x00104100+(i)*0x4) /* RW-4A */
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#define NV_CE_PCE2LCE_CONFIG__SIZE_1 6 /* */
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#define NV_CE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE 3:0 /* RWIVF */
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#define NV_CE_PCE2LCE_CONFIG_PCE_ASSIGNED_LCE_NONE 0x0000000f /* RW--V */
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#define NV_CE_PCE2LCE_CONFIG_0_PCE_ASSIGNED_LCE_INIT 0x0000000f /* RWI-V */
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#define NV_CE_PCE2LCE_CONFIG_1_PCE_ASSIGNED_LCE_INIT 0x0000000f /* RWI-V */
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#define NV_CE_PCE2LCE_CONFIG_2_PCE_ASSIGNED_LCE_INIT 0x0000000f /* RWI-V */
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#define NV_CE_PCE2LCE_CONFIG_3_PCE_ASSIGNED_LCE_INIT 0x0000000f /* RWI-V */
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#define NV_CE_PCE2LCE_CONFIG_4_PCE_ASSIGNED_LCE_INIT 0x00000002 /* RWI-V */
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#define NV_CE_PCE2LCE_CONFIG_5_PCE_ASSIGNED_LCE_INIT 0x00000003 /* RWI-V */
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#define NV_CE_GRCE_CONFIG(i) (0x001041c0+(i)*0x4) /* RW-4A */
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#define NV_CE_GRCE_CONFIG__SIZE_1 2 /* */
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#define NV_CE_GRCE_CONFIG_SHARED_LCE 3:0 /* RWIVF */
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#define NV_CE_GRCE_CONFIG_SHARED_LCE_NONE 0xf /* RW--V */
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#define NV_CE_GRCE_CONFIG_0_SHARED_LCE_INIT 0x00000003 /* RWI-V */
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#define NV_CE_GRCE_CONFIG_1_SHARED_LCE_INIT 0x00000002 /* RWI-V */
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#define NV_CE_GRCE_CONFIG_SHARED 30:30 /* RWIVF */
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#define NV_CE_GRCE_CONFIG_0_SHARED_INIT 0x00000001 /* RWI-V */
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#define NV_CE_GRCE_CONFIG_1_SHARED_INIT 0x00000001 /* RWI-V */
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#define NV_CE_GRCE_CONFIG_TIMESLICE 31:31 /* RWIVF */
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#define NV_CE_GRCE_CONFIG_TIMESLICE_SHORT 0x00000000 /* RWI-V */
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#define NV_CE_GRCE_CONFIG_TIMESLICE_LONG 0x00000001 /* RW--V */
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#define NV_CE_PRI_CE_FE_CG 0x00104200 /* RWI4R */
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#define NV_CE_PRI_CE_FE_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
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#define NV_CE_PRI_CE_FE_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
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#define NV_CE_PRI_CE_FE_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */
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#define NV_CE_PRI_CE_FE_CG_IDLE_CG_EN 6:6 /* RWIVF */
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#define NV_CE_PRI_CE_FE_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_CE_PRI_CE_FE_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_CE_PRI_CE_FE_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
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#define NV_CE_PRI_CE_FE_CG_STATE_CG_EN 7:7 /* */
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#define NV_CE_PRI_CE_FE_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
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#define NV_CE_PRI_CE_FE_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_STATE_CG_EN__PROD 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_CE_PRI_CE_FE_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */
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#define NV_CE_PRI_CE_FE_CG_STALL_CG_EN 14:14 /* RWIVF */
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#define NV_CE_PRI_CE_FE_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_CE_PRI_CE_FE_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_CE_PRI_CE_FE_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */
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#define NV_CE_PRI_CE_FE_CG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_CE_PRI_CE_FE_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
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#define NV_CE_PRI_CE_FE_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */
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#define NV_CE_PRI_CE_FE_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
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#define NV_CE_PRI_CE_FE_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
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#define NV_CE_PRI_CE_FE_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
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#define NV_CE_PRI_CE_FE_CG_THROT_CLK_CNT 23:20 /* */
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#define NV_CE_PRI_CE_FE_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
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#define NV_CE_PRI_CE_FE_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_CE_PRI_CE_FE_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_THROT_CLK_EN 28:28 /* */
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#define NV_CE_PRI_CE_FE_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
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#define NV_CE_PRI_CE_FE_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_THROT_CLK_EN__PROD 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_CE_PRI_CE_FE_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
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#define NV_CE_PRI_CE_FE_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_PAUSE_CG_EN 30:30 /* */
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#define NV_CE_PRI_CE_FE_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
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#define NV_CE_PRI_CE_FE_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_HALT_CG_EN 31:31 /* */
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#define NV_CE_PRI_CE_FE_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
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#define NV_CE_PRI_CE_FE_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG_HALT_CG_EN__PROD 0x00000000 /* */
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#define NV_CE_PRI_CE_FE_CG1 0x00104204 /* RWI4R */
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#define NV_CE_PRI_CE_FE_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_CE_PRI_CE_FE_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_CE_PRI_CE_FE_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_CE_PRI_CE_FE_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
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#define NV_CE_PRI_CE_FE_CG1_SLCG 10:1 /* RWIVF */
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#define NV_CE_PRI_CE_FE_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_CE_PRI_CE_FE_CG1_SLCG_DISABLED 0x000003FF /* RWI-V */
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#define NV_CE_PRI_CE_FE_CG1_SLCG__PROD 0x00000000 /* RW--V */
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#define NV_CE_SHIM_PMM 0x00104030 /* RW-4R */
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#define NV_CE_SHIM_PMM_SEL0 5:0 /* RWEUF */
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#define NV_CE_SHIM_PMM_SEL0_LCE_IDLE 0x00000000 /* RWE-V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_PCES_IDLE 0x00000001 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_HOST2CE_MTHD 0x00000002 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_HOST2CE_MTHD_CREDIT 0x00000003 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_HOST2CE_MTHD_LDMA 0x00000004 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_HOST2CE_MTHD_SOC 0x00000005 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_FAULT_MSG 0x00000006 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_FAULT2SAVE_REQ 0x00000007 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_FAULT2SAVE_START 0x00000008 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_SAVE_BUSY 0x00000009 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_SAVE_2XMTHDS 0x0000000A /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_SAVE_MTHD_IS_LDMA 0x0000000B /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_SAVE_REQ 0x0000000C /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_SAVE_ACK_PREEMPTED 0x0000000D /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_SAVE_ACK_NONPREEMPTED 0x0000000E /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_LOAD_BUSY 0x0000000F /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_LOAD_2XMTHDS 0x00000010 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_LOAD_MTHD_IS_LDMA 0x00000011 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_CHANNEL_RESTART_CYCLES 0x00000012 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_LOAD_PREEMPTED_REQ 0x00000013 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_LOAD_NONPREEMPTED_REQ 0x00000014 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_LOAD_CTX_PTR_MISMATCH 0x00000015 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_LOAD_RD_LATENCY 0x00000016 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_METHOD_BUFFER_ALMOST_FULL 0x00000017 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_COMMIT_QUEUE_FULL 0x00000018 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_AFIFO_FULL 0x00000019 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_FLUSH_SYS_REQ 0x0000001A /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_FLUSH_GL_REQ 0x0000001B /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_SHIM2FB_PVLD 0x0000001C /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_SHIM2FB_PRDY 0x0000001D /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_OLDEST_COPY_COMPLETED 0x0000001E /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_MTHD_BUFFER_RD_COMMIT 0x0000001F /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_WAIT4SHIM2FB_ARB_GNT 0x00000020 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_WAIT4GRCE_ARB_GNT 0x00000021 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_BIND_ACK_LATENCY 0x00000022 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_LATENCY_FLUSH_ACK 0x00000023 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_LCE_SENT_A_COPY 0x00000024 /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_STATIC_PATTERN_0_1_GROUP 0x0000003E /* RW--V */
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#define NV_CE_SHIM_PMM_SEL0_STATIC_PATTERN_1_1_GROUP 0x0000003F /* RW--V */
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#define NV_CE_SHIM_PMM_SEL1 11:6 /* RWEUF */
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#define NV_CE_SHIM_PMM_SEL1_LCE_IDLE 0x00000000 /* RWE-V */
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#define NV_CE_SHIM_PMM_SEL2 17:12 /* RWEUF */
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#define NV_CE_SHIM_PMM_SEL2_LCE_IDLE 0x00000000 /* RWE-V */
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#define NV_CE_SHIM_PMM_SEL3 23:18 /* RWEUF */
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#define NV_CE_SHIM_PMM_SEL3_LCE_IDLE 0x00000000 /* RWE-V */
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#define NV_CE_SHIM_PMM_LCE_SEL 27:24 /* RWEUF */
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#define NV_CE_SHIM_PMM_LCE_SEL_INIT 0x00000000 /* RWE-V */
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#define NV_CE_SHIM_PMM_PERFMON_ENABLE 31:31 /* RWEVF */
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#define NV_CE_SHIM_PMM_PERFMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_CE_SHIM_PMM_PERFMON_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_CE_LCE_STATUS(i) (0x00104400+(i)*0x80) /* R--4A */
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#define NV_CE_LCE_STATUS__SIZE_1 5 /* */
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#define NV_CE_LCE_STATUS_TOP 0:0 /* R-IVF */
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#define NV_CE_LCE_STATUS_TOP_IDLE 0x00000000 /* R-I-V */
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#define NV_CE_LCE_STATUS_TOP_NONIDLE 0x00000001 /* R---V */
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#define NV_CE_LCE_BIND_STATUS(i) (0x00104404+(i)*0x80) /* R--4A */
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#define NV_CE_LCE_BIND_STATUS__SIZE_1 5 /* */
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#define NV_CE_LCE_BIND_STATUS_BOUND 0:0 /* R-IVF */
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#define NV_CE_LCE_BIND_STATUS_BOUND_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_LCE_BIND_STATUS_BOUND_TRUE 0x00000001 /* R---V */
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#define NV_CE_LCE_BIND_STATUS_CTX_PTR 28:1 /* R-IVF */
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#define NV_CE_LCE_BIND_STATUS_CTX_PTR_INIT 0x01234567 /* R-I-V */
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#define NV_CE_LCE_BIND_STATUS_CTX_TARGET 30:29 /* R-IVF */
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#define NV_CE_LCE_BIND_STATUS_CTX_TARGET_INIT 0x00000000 /* R-I-V */
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#define NV_CE_LCE_CHANNEL_INFO(i) (0x00104408+(i)*0x80) /* R--4A */
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#define NV_CE_LCE_CHANNEL_INFO__SIZE_1 5 /* */
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#define NV_CE_LCE_CHANNEL_INFO_VAL 31:0 /* R-IVF */
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#define NV_CE_LCE_CHANNEL_INFO_VAL_NONE 0x00000000 /* R-I-V */
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#define NV_CE_LCE_DEBUG(i) (0x00104450+(i)*0x80) /* R--4A */
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#define NV_CE_LCE_DEBUG__SIZE_1 5 /* */
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#define NV_CE_LCE_DEBUG_METHOD_BUF_EMPTY 0:0 /* R--VF */
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#define NV_CE_LCE_DEBUG_AFIFO_EMPTY 1:1 /* R--VF */
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#define NV_CE_LCE_DEBUG_COMMIT_Q_EMPTY 2:2 /* R--VF */
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#define NV_CE_LCE_DEBUG_ALL_PCES_IDLE 3:3 /* R--VF */
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#define NV_CE_LCE_DEBUG_STALL_INTR_PENDING 4:4 /* R--VF */
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#define NV_CE_LCE_DEBUG_NONSTALL_INTR_PENDING 5:5 /* R--VF */
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#define NV_CE_LCE_DEBUG_RECEIVED_PAGE_FAULT 6:6 /* R--VF */
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#define NV_CE_LCE_DEBUG_RECEIVED_POISON 7:7 /* R--VF */
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#define NV_CE_LCE_DEBUG_AFIFO_STATE 10:8 /* R--VF */
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#define NV_CE_LCE_DEBUG_MAIN_FSM_STATE 15:11 /* R--VF */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK(i) (0x0010443c+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK__SIZE_1 5 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_CE_LCE_INTR_EN(i) (0x0010440c+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_INTR_EN__SIZE_1 5 /* */
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#define NV_CE_LCE_INTR_EN__PRIV_LEVEL_MASK NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK /* */
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#define NV_CE_LCE_INTR_EN_BLOCKPIPE 0:0 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_BLOCKPIPE_DISABLE 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_EN_BLOCKPIPE_ENABLE 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_EN_NONBLOCKPIPE 1:1 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_NONBLOCKPIPE_DISABLE 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_EN_NONBLOCKPIPE_ENABLE 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_EN_LAUNCHERR 2:2 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_LAUNCHERR_DISABLE 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_EN_LAUNCHERR_ENABLE 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_EN_INVALID_CONFIG 3:3 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_INVALID_CONFIG_DISABLE 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_EN_INVALID_CONFIG_ENABLE 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_EN_MTHD_BUFFER_FAULT 4:4 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_MTHD_BUFFER_FAULT_DISABLE 0x00000000 /* RWE-V */
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#define NV_CE_LCE_INTR_EN_MTHD_BUFFER_FAULT_ENABLE 0x00000001 /* RW--V */
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#define NV_CE_LCE_INTR_EN_FBUF_CRC_FAIL 5:5 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_FBUF_CRC_FAIL_DISABLE 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_EN_FBUF_CRC_FAIL_ENABLE 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_EN_FBUF_MAGIC_CHK_FAIL 6:6 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_FBUF_MAGIC_CHK_FAIL_DISABLE 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_EN_FBUF_MAGIC_CHK_FAIL_ENABLE 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_EN_POISON_ERROR 7:7 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_POISON_ERROR_DISABLE 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_EN_POISON_ERROR_ENABLE 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_EN_NONSTALLING_DEBUG 30:30 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_NONSTALLING_DEBUG_DISABLE 0x00000000 /* R-E-V */
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#define NV_CE_LCE_INTR_EN_NONSTALLING_DEBUG_ENABLE 0x00000001 /* R---V */
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#define NV_CE_LCE_INTR_EN_STALLING_DEBUG 31:31 /* RWEVF */
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#define NV_CE_LCE_INTR_EN_STALLING_DEBUG_DISABLE 0x00000000 /* R-E-V */
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#define NV_CE_LCE_INTR_EN_STALLING_DEBUG_ENABLE 0x00000001 /* R---V */
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#define NV_CE_LCE_INTR_STATUS(i) (0x00104410+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_INTR_STATUS__SIZE_1 5 /* */
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#define NV_CE_LCE_INTR_STATUS__PRIV_LEVEL_MASK NV_CE_LCE_INTR_EN_AND_STATUS_PRIV_LEVEL_MASK /* */
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#define NV_CE_LCE_INTR_STATUS_BLOCKPIPE 0:0 /* RWIVF */
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#define NV_CE_LCE_INTR_STATUS_BLOCKPIPE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_CE_LCE_INTR_STATUS_BLOCKPIPE_PENDING 0x00000001 /* R---V */
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#define NV_CE_LCE_INTR_STATUS_BLOCKPIPE_RESET 0x00000001 /* -W--C */
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#define NV_CE_LCE_INTR_STATUS_NONBLOCKPIPE 1:1 /* */
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#define NV_CE_LCE_INTR_STATUS_NONBLOCKPIPE_NOT_PENDING 0x00000000 /* */
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#define NV_CE_LCE_INTR_STATUS_NONBLOCKPIPE_PENDING 0x00000001 /* */
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#define NV_CE_LCE_INTR_STATUS_NONBLOCKPIPE_RESET 0x00000001 /* */
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#define NV_CE_LCE_INTR_STATUS_LAUNCHERR 2:2 /* RWIVF */
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#define NV_CE_LCE_INTR_STATUS_LAUNCHERR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_CE_LCE_INTR_STATUS_LAUNCHERR_PENDING 0x00000001 /* R---V */
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#define NV_CE_LCE_INTR_STATUS_LAUNCHERR_RESET 0x00000001 /* -W--C */
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#define NV_CE_LCE_INTR_STATUS_INVALID_CONFIG 3:3 /* RWIVF */
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#define NV_CE_LCE_INTR_STATUS_INVALID_CONFIG_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_CE_LCE_INTR_STATUS_INVALID_CONFIG_PENDING 0x00000001 /* R---V */
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#define NV_CE_LCE_INTR_STATUS_INVALID_CONFIG_RESET 0x00000001 /* -W--C */
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#define NV_CE_LCE_INTR_STATUS_MTHD_BUFFER_FAULT 4:4 /* RWIVF */
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#define NV_CE_LCE_INTR_STATUS_MTHD_BUFFER_FAULT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_CE_LCE_INTR_STATUS_MTHD_BUFFER_FAULT_PENDING 0x00000001 /* R---V */
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#define NV_CE_LCE_INTR_STATUS_MTHD_BUFFER_FAULT_RESET 0x00000001 /* -W--C */
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#define NV_CE_LCE_INTR_STATUS_FBUF_CRC_FAIL 5:5 /* RWIVF */
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#define NV_CE_LCE_INTR_STATUS_FBUF_CRC_FAIL_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_CE_LCE_INTR_STATUS_FBUF_CRC_FAIL_PENDING 0x00000001 /* R---V */
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#define NV_CE_LCE_INTR_STATUS_FBUF_CRC_FAIL_RESET 0x00000001 /* -W--C */
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#define NV_CE_LCE_INTR_STATUS_FBUF_MAGIC_CHK_FAIL 6:6 /* RWIVF */
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#define NV_CE_LCE_INTR_STATUS_FBUF_MAGIC_CHK_FAIL_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_CE_LCE_INTR_STATUS_FBUF_MAGIC_CHK_FAIL_PENDING 0x00000001 /* R---V */
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#define NV_CE_LCE_INTR_STATUS_FBUF_MAGIC_CHK_FAIL_RESET 0x00000001 /* -W--C */
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#define NV_CE_LCE_INTR_STATUS_POISON_ERROR 7:7 /* RWIVF */
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#define NV_CE_LCE_INTR_STATUS_POISON_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_CE_LCE_INTR_STATUS_POISON_ERROR_PENDING 0x00000001 /* R---V */
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#define NV_CE_LCE_INTR_STATUS_POISON_ERROR_RESET 0x00000001 /* -W--C */
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#define NV_CE_LCE_INTR_STATUS_STALLING_DEBUG 31:31 /* RWIVF */
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#define NV_CE_LCE_INTR_STATUS_STALLING_DEBUG_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_CE_LCE_INTR_STATUS_STALLING_DEBUG_PENDING 0x00000001 /* R---V */
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#define NV_CE_LCE_INTR_STATUS_STALLING_DEBUG_RESET 0x00000001 /* -W--C */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK(i) (0x00104438+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK__SIZE_1 5 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL(i) (0x00104424+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL__SIZE_1 5 /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL__PRIV_LEVEL_MASK NV_CE_LCE_INTR_NOTIFY_CTRL_PRIV_LEVEL_MASK /* */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_VECTOR 11:0 /* RWEUF */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_0_VECTOR__INIT 0 /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_1_VECTOR__INIT 0 /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_2_VECTOR__INIT 7 /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_3_VECTOR__INIT 8 /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_4_VECTOR__INIT 10 /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_GFID 6+20-1:20 /* RWEUF */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_GFID__INIT 0 /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_GSP 30:30 /* RWEUF */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_GSP_ENABLE 1 /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_GSP_DISABLE 0 /* RW--V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_CPU 31:31 /* RWEUF */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_CPU_ENABLE 1 /* RWE-V */
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#define NV_CE_LCE_INTR_NOTIFY_CTRL_CPU_DISABLE 0 /* RW--V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK(i) (0x00104428+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK__SIZE_1 5 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL(i) (0x0010442c+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_INTR_CTRL__SIZE_1 5 /* */
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#define NV_CE_LCE_INTR_CTRL__PRIV_LEVEL_MASK NV_CE_LCE_INTR_CTRL_PRIV_LEVEL_MASK /* */
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#define NV_CE_LCE_INTR_CTRL_VECTOR 11:0 /* RWEUF */
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#define NV_CE_LCE_INTR_CTRL_0_VECTOR__INIT 197 /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_1_VECTOR__INIT 198 /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_2_VECTOR__INIT 199 /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_3_VECTOR__INIT 200 /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_4_VECTOR__INIT 202 /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_GFID 6+20-1:20 /* RWEUF */
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#define NV_CE_LCE_INTR_CTRL_GFID__INIT 0 /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_GSP 30:30 /* RWEUF */
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#define NV_CE_LCE_INTR_CTRL_GSP_ENABLE 1 /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_GSP_DISABLE 0 /* RW--V */
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#define NV_CE_LCE_INTR_CTRL_CPU 31:31 /* RWEUF */
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#define NV_CE_LCE_INTR_CTRL_CPU_ENABLE 1 /* RWE-V */
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#define NV_CE_LCE_INTR_CTRL_CPU_DISABLE 0 /* RW--V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK(i) (0x00104430+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK__SIZE_1 5 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_CE_LCE_INTR_RETRIGGER(i) (0x00104434+(i)*0x80) /* -W-4A */
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#define NV_CE_LCE_INTR_RETRIGGER__SIZE_1 5 /* */
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#define NV_CE_LCE_INTR_RETRIGGER__PRIV_LEVEL_MASK NV_CE_LCE_INTR_RETRIGGER_PRIV_LEVEL_MASK /* */
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#define NV_CE_LCE_INTR_RETRIGGER_TRIGGER 0:0 /* -WEUF */
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#define NV_CE_LCE_INTR_RETRIGGER_TRIGGER_TRUE 1 /* -W--V */
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#define NV_CE_LCE_INTR_RETRIGGER_TRIGGER_FALSE 0 /* -WE-V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK(i) (0x00104440+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK__SIZE_1 5 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000F /* RWE-V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_CE_LCE_CYA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWE-V */
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#define NV_CE_LCE_OPT(i) (0x00104414+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_OPT__SIZE_1 5 /* */
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#define NV_CE_LCE_OPT__PRIV_LEVEL_MASK NV_CE_LCE_CYA_PRIV_LEVEL_MASK /* */
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#define NV_CE_LCE_OPT_IRQ_FORCE_REPORT_STALL 0:0 /* RWEVF */
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#define NV_CE_LCE_OPT_IRQ_FORCE_REPORT_STALL_FALSE 0x00000000 /* RWE-V */
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#define NV_CE_LCE_OPT_IRQ_FORCE_REPORT_STALL_TRUE 0x00000001 /* RW--V */
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#define NV_CE_LCE_OPT_RMW_OPT_ENABLE 1:1 /* RWEVF */
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#define NV_CE_LCE_OPT_RMW_OPT_ENABLE_TRUE 0x00000001 /* RWE-V */
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#define NV_CE_LCE_OPT_RMW_OPT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_CE_LCE_OPT_FORCE_FLUSH_SYS 2:2 /* RWEVF */
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#define NV_CE_LCE_OPT_FORCE_FLUSH_SYS_FALSE 0x00000000 /* RWE-V */
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#define NV_CE_LCE_OPT_FORCE_FLUSH_SYS_TRUE 0x00000001 /* RW--V */
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#define NV_CE_LCE_OPT_FORCE_BARRIERS_NPL 3:3 /* RWEVF */
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#define NV_CE_LCE_OPT_FORCE_BARRIERS_NPL_FALSE 0x00000000 /* RW--V */
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#define NV_CE_LCE_OPT_FORCE_BARRIERS_NPL_TRUE 0x00000001 /* RWE-V */
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#define NV_CE_LCE_OPT_FORCE_BARRIERS_NPL__PROD 0x00000001 /* RW--V */
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#define NV_CE_LCE_OPT_PIPELINED_FLUSH 4:4 /* RWEVF */
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#define NV_CE_LCE_OPT_PIPELINED_FLUSH_FALSE 0x00000000 /* RWE-V */
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#define NV_CE_LCE_OPT_PIPELINED_FLUSH_TRUE 0x00000001 /* RW--V */
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#define NV_CE_LCE_OPT_FORCE_MFB_FAULT 5:5 /* RWEVF */
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#define NV_CE_LCE_OPT_FORCE_MFB_FAULT_FALSE 0x00000000 /* RWE-V */
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#define NV_CE_LCE_OPT_FORCE_MFB_FAULT_TRUE 0x00000001 /* RW--V */
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#define NV_CE_LCE_OPT_L2_CLASS 6:6 /* RWEVF */
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#define NV_CE_LCE_OPT_L2_CLASS_EVICT_FIRST 0x00000000 /* RWE-V */
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#define NV_CE_LCE_OPT_L2_CLASS_EVICT_NORMAL 0x00000001 /* RW--V */
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#define NV_CE_LCE_OPT_EXT(i) (0x00104444+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_OPT_EXT__SIZE_1 5 /* */
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#define NV_CE_LCE_OPT_EXT__PRIV_LEVEL_MASK NV_CE_LCE_CYA_PRIV_LEVEL_MASK /* */
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#define NV_CE_LCE_OPT_EXT_LCE_PCE_STALLREQ_LEVEL 0:0 /* RWEVF */
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#define NV_CE_LCE_OPT_EXT_LCE_PCE_STALLREQ_LEVEL_FALSE 0x00000000 /* RWE-V */
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#define NV_CE_LCE_OPT_EXT_LCE_PCE_STALLREQ_LEVEL_TRUE 0x00000001 /* RW--V */
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#define NV_CE_LCE_OPT_EXT_FORCE_SEMA_NPL 1:1 /* RWEVF */
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#define NV_CE_LCE_OPT_EXT_FORCE_SEMA_NPL_FALSE 0x00000000 /* RW--V */
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#define NV_CE_LCE_OPT_EXT_FORCE_SEMA_NPL_TRUE 0x00000001 /* RWE-V */
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#define NV_CE_LCE_OPT_EXT_FORCE_CONST_FILL_NPL 2:2 /* RWEVF */
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#define NV_CE_LCE_OPT_EXT_FORCE_CONST_FILL_NPL_FALSE 0x00000000 /* RW--V */
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#define NV_CE_LCE_OPT_EXT_FORCE_CONST_FILL_NPL_TRUE 0x00000001 /* RWE-V */
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#define NV_CE_LCE_OPT_EXT_DEBUG_TRIGGER_NONSTALLING 30:30 /* -WEUF */
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#define NV_CE_LCE_OPT_EXT_DEBUG_TRIGGER_NONSTALLING_TRUE 1 /* -W--V */
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#define NV_CE_LCE_OPT_EXT_DEBUG_TRIGGER_NONSTALLING_FALSE 0 /* -WE-V */
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#define NV_CE_LCE_OPT_EXT_DEBUG_TRIGGER_STALLING 31:31 /* -WEUF */
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#define NV_CE_LCE_OPT_EXT_DEBUG_TRIGGER_STALLING_TRUE 1 /* -W--V */
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#define NV_CE_LCE_OPT_EXT_DEBUG_TRIGGER_STALLING_FALSE 0 /* -WE-V */
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#define NV_CE_LCE_OPT_OVERRIDE(i) (0x0010444c+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_OPT_OVERRIDE__SIZE_1 5 /* */
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#define NV_CE_LCE_OPT_OVERRIDE__PRIV_LEVEL_MASK NV_CE_LCE_CYA_PRIV_LEVEL_MASK /* */
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#define NV_CE_LCE_OPT_OVERRIDE_METHOD_CREDIT_CNT 15:0 /* RWEVF */
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#define NV_CE_LCE_OPT_OVERRIDE_METHOD_CREDIT_CNT__INIT 0x00000000 /* RWE-V */
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#define NV_CE_LCE_OPT_OVERRIDE_METHOD_BUFFER_SIZE 31:16 /* RWEVF */
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#define NV_CE_LCE_OPT_OVERRIDE_METHOD_BUFFER_SIZE_OVERRIDE__INIT 0x00000000 /* RWE-V */
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#define NV_CE_LCE_OPT_RESET(i) (0x00104448+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_OPT_RESET__SIZE_1 5 /* */
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#define NV_CE_LCE_OPT_RESET__PRIV_LEVEL_MASK NV_CE_LCE_CYA_PRIV_LEVEL_MASK /* */
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#define NV_CE_LCE_OPT_RESET_EXTEND 7:0 /* RWEVF */
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#define NV_CE_LCE_OPT_RESET_EXTEND__INIT 0x0 /* RWE-V */
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#define NV_CE_GRCE_OPT_RESET(i) (0x001041d0+(i)*0x4) /* RW-4A */
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#define NV_CE_GRCE_OPT_RESET__SIZE_1 2 /* */
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#define NV_CE_GRCE_OPT_RESET__PRIV_LEVEL_MASK 0x00104048 /* */
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#define NV_CE_GRCE_OPT_RESET_EXTEND 7:0 /* RWEVF */
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#define NV_CE_GRCE_OPT_RESET_EXTEND__INIT 0x0 /* RWE-V */
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#define NV_CE_LCE_LAUNCHERR(i) (0x00104418+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_LAUNCHERR__SIZE_1 5 /* */
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#define NV_CE_LCE_LAUNCHERR_REPORT 3:0 /* RWIVF */
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#define NV_CE_LCE_LAUNCHERR_REPORT_NO_ERR 0x00000000 /* RWI-V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_2D_LAYER_EXCEEDS_DEPTH 0x00000001 /* R---V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_INVALID_ALIGNMENT 0x00000002 /* R---V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_MEM2MEM_RECT_OUT_OF_BOUNDS 0x00000003 /* R---V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_SRC_LINE_ECXEEDS_PITCH 0x00000004 /* R---V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_SRC_LINE_EXCEEDS_NEG_PITCH 0x00000005 /* R---V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_DST_LINE_ECXEEDS_PITCH 0x00000006 /* R---V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_DST_LINE_EXCEEDS_NEG_PITCH 0x00000007 /* R---V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_BAD_SRC_PIXEL_COMP_REF 0x00000008 /* R---V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_INVALID_VALUE 0x00000009 /* R---V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_INVALID_UNUSED_FIELD 0x0000000a /* R---V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_INVALID_OPERATION 0x0000000b /* R---V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_NO_RESOURCES 0x0000000c /* R---V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_INVALID_CONFIG 0x0000000d /* R---V */
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#define NV_CE_LCE_LAUNCHERR_REPORT_METHOD_BUFFER_ACCESS_FAULT 0x0000000e /* R---V */
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#define NV_CE_LCE_ENGCTL(i) (0x0010441c+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_ENGCTL__SIZE_1 5 /* */
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#define NV_CE_LCE_ENGCTL_STALLREQ 8:8 /* RWIVF */
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#define NV_CE_LCE_ENGCTL_STALLREQ_FALSE 0x00000000 /* RWI-V */
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#define NV_CE_LCE_ENGCTL_STALLREQ_TRUE 0x00000001 /* RW--V */
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#define NV_CE_LCE_ENGCTL_STALLACK 9:9 /* R-IVF */
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#define NV_CE_LCE_ENGCTL_STALLACK_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_LCE_ENGCTL_STALLACK_TRUE 0x00000001 /* R---V */
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#define NV_CE_LCE_THROTTLE(i) (0x00104420+(i)*0x80) /* RW-4A */
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#define NV_CE_LCE_THROTTLE__SIZE_1 5 /* */
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#define NV_CE_LCE_THROTTLE_BUCKET_SIZE 11:0 /* RWIVF */
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#define NV_CE_LCE_THROTTLE_BUCKET_SIZE_INIT 0x00000064 /* RWI-V */
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#define NV_CE_LCE_THROTTLE_LEAK_COUNT 27:16 /* RWIVF */
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#define NV_CE_LCE_THROTTLE_LEAK_COUNT_DISABLE 0x00000000 /* RWI-V */
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#define NV_CE_LCE_THROTTLE_LEAK_SIZE 31:30 /* RWIVF */
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#define NV_CE_LCE_THROTTLE_LEAK_SIZE_16B 0x00000000 /* RW--V */
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#define NV_CE_LCE_THROTTLE_LEAK_SIZE_32B 0x00000001 /* RW--V */
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#define NV_CE_LCE_THROTTLE_LEAK_SIZE_64B 0x00000002 /* RWI-V */
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#define NV_CE_LCE_THROTTLE_LEAK_SIZE_128B 0x00000003 /* RW--V */
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#define NV_CE_PCE_CMD0(i) (0x00105000+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_CMD0__SIZE_1 6 /* */
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#define NV_CE_PCE_CMD0_SURFACE_COPY 0:0 /* R-IVF */
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#define NV_CE_PCE_CMD0_SURFACE_COPY_IDLE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_SURFACE_COPY_TRIGGER 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_MONITORED_FENCE_TYPE 1:1 /* R-IVF */
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#define NV_CE_PCE_CMD0_MONITORED_FENCE_TYPE_LEGACY 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_MONITORED_FENCE_TYPE_EXT 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_MONITORED_FENCE_PAYLOAD_SZ 2:2 /* R-IVF */
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#define NV_CE_PCE_CMD0_MONITORED_FENCE_PAYLOAD_SZ_ONE_WORD 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_MONITORED_FENCE_PAYLOAD_SZ_TWO_WORD 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_COPY_TYPE_MULTI 6:6 /* R-IVF */
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#define NV_CE_PCE_CMD0_COPY_TYPE_MULTI_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_COPY_TYPE_MULTI_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_COPY_TYPE_SRC 7:7 /* R-IVF */
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#define NV_CE_PCE_CMD0_COPY_TYPE_SRC_BL 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_COPY_TYPE_SRC_PITCH 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_COPY_TYPE_DST 8:8 /* R-IVF */
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#define NV_CE_PCE_CMD0_COPY_TYPE_DST_BL 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_COPY_TYPE_DST_PITCH 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_COPY_TYPE_SWIZ 9:9 /* R-IVF */
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#define NV_CE_PCE_CMD0_COPY_TYPE_SWIZ_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_COPY_TYPE_SWIZ_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_COPY_TYPE_BIGMEM 10:10 /* R-IVF */
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#define NV_CE_PCE_CMD0_COPY_TYPE_BIGMEM_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_COPY_TYPE_BIGMEM_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_BURSTSIZE_SRC 13:11 /* R-IVF */
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#define NV_CE_PCE_CMD0_BURSTSIZE_SRC_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_BURSTSIZE_DST 16:14 /* R-IVF */
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#define NV_CE_PCE_CMD0_BURSTSIZE_DST_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_PIPELINED_READS 19:19 /* R-IVF */
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#define NV_CE_PCE_CMD0_PIPELINED_READS_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_PIPELINED_READS_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_NO_RMW_HINT_DISABLE 20:20 /* R-IVF */
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#define NV_CE_PCE_CMD0_NO_RMW_HINT_DISABLE_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_NO_RMW_HINT_DISABLE_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_COPY_COMPLETION_MSG 21:21 /* R-IVF */
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#define NV_CE_PCE_CMD0_COPY_COMPLETION_MSG_ENABLE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_COPY_COMPLETION_MSG_DISABLE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_SRC_PHYS_MODE 22:22 /* R-IVF */
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#define NV_CE_PCE_CMD0_SRC_PHYS_MODE_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_SRC_PHYS_MODE_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_DST_PHYS_MODE 23:23 /* R-IVF */
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#define NV_CE_PCE_CMD0_DST_PHYS_MODE_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_DST_PHYS_MODE_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_BARRIER_COPY 25:24 /* R-IVF */
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#define NV_CE_PCE_CMD0_BARRIER_COPY_NONE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_BARRIER_COPY_BLOCKING 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_BARRIER_COPY_NONBLOCKING 0x00000002 /* R---V */
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#define NV_CE_PCE_CMD0_VPR_MODE 27:26 /* R-IVF */
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#define NV_CE_PCE_CMD0_VPR_MODE_NONE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_VPR_MODE_VID2VID 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_VPR_MODE_VID2SYS 0x00000002 /* R---V */
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#define NV_CE_PCE_CMD0_VPR_MODE_SYS2VID 0x00000003 /* R---V */
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#define NV_CE_PCE_CMD0_START_OF_PAGING 28:28 /* R-IVF */
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#define NV_CE_PCE_CMD0_START_OF_PAGING_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_START_OF_PAGING_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_CONDITIONAL_INTERRUPT 29:29 /* R-IVF */
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#define NV_CE_PCE_CMD0_CONDITIONAL_INTERRUPT_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_CONDITIONAL_INTERRUPT_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD0_DISABLE_PLC 30:30 /* R-IVF */
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#define NV_CE_PCE_CMD0_DISABLE_PLC_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD0_DISABLE_PLC_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_LINES_TO_COPY(i) (0x00105004+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_LINES_TO_COPY__SIZE_1 6 /* */
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#define NV_CE_PCE_LINES_TO_COPY_COUNT 31:0 /* R-IVF */
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#define NV_CE_PCE_LINES_TO_COPY_COUNT_INIT 0x00000001 /* R-I-V */
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#define NV_CE_PCE_SRC_PARAM0(i) (0x00105008+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_SRC_PARAM0__SIZE_1 6 /* */
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#define NV_CE_PCE_SRC_PARAM0_LOWER_OFFSET 31:0 /* R-IVF */
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#define NV_CE_PCE_SRC_PARAM0_LOWER_OFFSET_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_DST_PARAM0(i) (0x0010500c+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_DST_PARAM0__SIZE_1 6 /* */
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#define NV_CE_PCE_DST_PARAM0_LOWER_OFFSET 31:0 /* R-IVF */
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#define NV_CE_PCE_DST_PARAM0_LOWER_OFFSET_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_SRC_PARAM1(i) (0x00105010+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_SRC_PARAM1__SIZE_1 6 /* */
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#define NV_CE_PCE_SRC_PARAM1_LINE_LENGTH 31:0 /* R-IVF */
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#define NV_CE_PCE_SRC_PARAM1_LINE_LENGTH_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_DST_PARAM1(i) (0x00105014+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_DST_PARAM1__SIZE_1 6 /* */
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#define NV_CE_PCE_DST_PARAM1_LINE_LENGTH 31:0 /* R-IVF */
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#define NV_CE_PCE_DST_PARAM1_LINE_LENGTH_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_SRC_PARAM2(i) (0x00105018+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_SRC_PARAM2__SIZE_1 6 /* */
|
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#define NV_CE_PCE_SRC_PARAM2_UPPER_OFFSET 16:0 /* R-IVF */
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#define NV_CE_PCE_SRC_PARAM2_UPPER_OFFSET_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_DST_PARAM2(i) (0x0010501c+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_DST_PARAM2__SIZE_1 6 /* */
|
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#define NV_CE_PCE_DST_PARAM2_UPPER_OFFSET 16:0 /* R-IVF */
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#define NV_CE_PCE_DST_PARAM2_UPPER_OFFSET_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_SRC_PARAM3(i) (0x00105020+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_SRC_PARAM3__SIZE_1 6 /* */
|
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#define NV_CE_PCE_SRC_PARAM3_SRC_LINES_PER_1ST_BLK 11:0 /* R-IVF */
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#define NV_CE_PCE_SRC_PARAM3_SRC_LINES_PER_1ST_BLK_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_SRC_PARAM3_SRC_LINES_PER_BLK 23:12 /* R-IVF */
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#define NV_CE_PCE_SRC_PARAM3_SRC_LINES_PER_BLK_INIT 0x00000004 /* R-I-V */
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#define NV_CE_PCE_DST_PARAM3(i) (0x00105024+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_DST_PARAM3__SIZE_1 6 /* */
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#define NV_CE_PCE_DST_PARAM3_DST_LINES_PER_1ST_BLK 11:0 /* R-IVF */
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#define NV_CE_PCE_DST_PARAM3_DST_LINES_PER_1ST_BLK_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_DST_PARAM3_DST_LINES_PER_BLK 23:12 /* R-IVF */
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#define NV_CE_PCE_DST_PARAM3_DST_LINES_PER_BLK_INIT 0x00000004 /* R-I-V */
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#define NV_CE_PCE_SRC_PARAM4(i) (0x00105028+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_SRC_PARAM4__SIZE_1 6 /* */
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#define NV_CE_PCE_SRC_PARAM4_BLKROW_SKIP 31:0 /* R-IVF */
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#define NV_CE_PCE_SRC_PARAM4_BLKROW_SKIP_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_DST_PARAM4(i) (0x0010502c+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_DST_PARAM4__SIZE_1 6 /* */
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#define NV_CE_PCE_DST_PARAM4_BLKROW_SKIP 31:0 /* R-IVF */
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#define NV_CE_PCE_DST_PARAM4_BLKROW_SKIP_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_SRC_PARAM6(i) (0x0010503c+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_SRC_PARAM6__SIZE_1 6 /* */
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#define NV_CE_PCE_SRC_PARAM6_BLKROW_SKIP_UPPER 3:0 /* R-IVF */
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#define NV_CE_PCE_SRC_PARAM6_BLKROW_SKIP_UPPER_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_DST_PARAM6(i) (0x0010504c+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_DST_PARAM6__SIZE_1 6 /* */
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#define NV_CE_PCE_DST_PARAM6_BLKROW_SKIP_UPPER 3:0 /* R-IVF */
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#define NV_CE_PCE_DST_PARAM6_BLKROW_SKIP_UPPER_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_SRC_PARAM5(i) (0x00105030+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_SRC_PARAM5__SIZE_1 6 /* */
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#define NV_CE_PCE_SRC_PARAM5_BURST_SKIP 15:0 /* R-IVF */
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#define NV_CE_PCE_SRC_PARAM5_BURST_SKIP_INIT 0x00000001 /* R-I-V */
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#define NV_CE_PCE_DST_PARAM5(i) (0x00105034+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_DST_PARAM5__SIZE_1 6 /* */
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#define NV_CE_PCE_DST_PARAM5_BURST_SKIP 15:0 /* R-IVF */
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#define NV_CE_PCE_DST_PARAM5_BURST_SKIP_INIT 0x00000001 /* R-I-V */
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#define NV_CE_PCE_SWIZZLE_CFG(i) (0x00105038+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_SWIZZLE_CFG__SIZE_1 6 /* */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_X 2:0 /* R-IVF */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_X_SRC_X 0x00000000 /* R-I-V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_X_SRC_Y 0x00000001 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_X_SRC_Z 0x00000002 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_X_SRC_W 0x00000003 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_X_SRC_CONST0 0x00000004 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_X_SRC_CONST1 0x00000005 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_X_NOWRITE 0x00000006 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_X_SRC_ZERO 0x00000007 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Y 6:4 /* R-IVF */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Y_SRC_X 0x00000000 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Y_SRC_Y 0x00000001 /* R-I-V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Y_SRC_Z 0x00000002 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Y_SRC_W 0x00000003 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Y_SRC_CONST0 0x00000004 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Y_SRC_CONST1 0x00000005 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Y_NOWRITE 0x00000006 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Y_SRC_ZERO 0x00000007 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Z 10:8 /* R-IVF */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Z_SRC_X 0x00000000 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Z_SRC_Y 0x00000001 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Z_SRC_Z 0x00000002 /* R-I-V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Z_SRC_W 0x00000003 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Z_SRC_CONST0 0x00000004 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Z_SRC_CONST1 0x00000005 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Z_NOWRITE 0x00000006 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_Z_SRC_ZERO 0x00000007 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_W 14:12 /* R-IVF */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_W_SRC_X 0x00000000 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_W_SRC_Y 0x00000001 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_W_SRC_Z 0x00000002 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_W_SRC_W 0x00000003 /* R-I-V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_W_SRC_CONST0 0x00000004 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_W_SRC_CONST1 0x00000005 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_W_NOWRITE 0x00000006 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_DST_W_SRC_ZERO 0x00000007 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CFG_BYTES_PER_CMP_LESS1 17:16 /* R-IVF */
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#define NV_CE_PCE_SWIZZLE_CFG_BYTES_PER_CMP_LESS1_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_SWIZZLE_CFG_CMP_PER_PIXEL_SRC_LESS1 21:20 /* R-IVF */
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#define NV_CE_PCE_SWIZZLE_CFG_CMP_PER_PIXEL_SRC_LESS1_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_SWIZZLE_CFG_CMP_PER_PIXEL_DST_LESS1 25:24 /* R-IVF */
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#define NV_CE_PCE_SWIZZLE_CFG_CMP_PER_PIXEL_DST_LESS1_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_SWIZZLE_CFG_CONST_SRC 31:31 /* R-IVF */
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#define NV_CE_PCE_SWIZZLE_CFG_CONST_SRC_CONST 0x00000000 /* R-I-V */
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#define NV_CE_PCE_SWIZZLE_CFG_CONST_SRC_TIMER 0x00000001 /* R---V */
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#define NV_CE_PCE_SWIZZLE_CONSTANT0(i) (0x00105040+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_SWIZZLE_CONSTANT0__SIZE_1 6 /* */
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#define NV_CE_PCE_SWIZZLE_CONSTANT0_FILL 31:0 /* R-IVF */
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#define NV_CE_PCE_SWIZZLE_CONSTANT0_FILL_INIT 0x01234567 /* R-I-V */
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#define NV_CE_PCE_SWIZZLE_CONSTANT1(i) (0x00105044+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_SWIZZLE_CONSTANT1__SIZE_1 6 /* */
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#define NV_CE_PCE_SWIZZLE_CONSTANT1_FILL 31:0 /* R-IVF */
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#define NV_CE_PCE_SWIZZLE_CONSTANT1_FILL_INIT 0x89abcdef /* R-I-V */
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#define NV_CE_PCE_CMD1(i) (0x00105048+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_CMD1__SIZE_1 6 /* */
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#define NV_CE_PCE_CMD1_FORCE_RMW_DISABLE 13:13 /* R-IVF */
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#define NV_CE_PCE_CMD1_FORCE_RMW_DISABLE_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD1_FORCE_RMW_DISABLE_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION 17:14 /* R-IVF */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_IMIN 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_IMAX 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_IAND 0x00000002 /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_IOR 0x00000003 /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_IXOR 0x00000004 /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_IADD 0x00000005 /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_INC 0x00000006 /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_DEC 0x00000007 /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_FADD 0x0000000a /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_FMIN 0x0000000b /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_FMAX 0x0000000c /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_FMUL 0x0000000d /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_IMUL 0x0000000e /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_SIGN 18:18 /* R-IVF */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_SIGN_SIGNED 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_SIGN_UNSIGNED 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_ENABLE 19:19 /* R-IVF */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_ENABLE_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_ENABLE_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_SZ 20:20 /* R-IVF */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_SZ_ONE_WORD 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD1_SEMAPHORE_REDUCTION_SZ_TWO_WORD 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD1_SEMA_ONLY 22:22 /* R-IVF */
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#define NV_CE_PCE_CMD1_SEMA_ONLY_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD1_SEMA_ONLY_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD1_CONST_WR 23:23 /* R-IVF */
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#define NV_CE_PCE_CMD1_CONST_WR_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD1_CONST_WR_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD1_SRC_BL_ACCESS 25:25 /* R-IVF */
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#define NV_CE_PCE_CMD1_SRC_BL_ACCESS_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD1_SRC_BL_ACCESS_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD1_DST_BL_ACCESS 26:26 /* R-IVF */
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#define NV_CE_PCE_CMD1_DST_BL_ACCESS_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD1_DST_BL_ACCESS_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD1_SEMA 27:27 /* R-IVF */
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#define NV_CE_PCE_CMD1_SEMA_TRUE 0x00000001 /* R---V */
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#define NV_CE_PCE_CMD1_SEMA_FALSE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_CMD1_RMW_OPT_ENABLE 30:30 /* R-IVF */
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#define NV_CE_PCE_CMD1_RMW_OPT_ENABLE_TRUE 0x00000001 /* R-I-V */
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#define NV_CE_PCE_CMD1_RMW_OPT_ENABLE_FALSE 0x00000000 /* R---V */
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#define NV_CE_PCE_SRC_PHYS_MODE(i) (0x00105050+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_SRC_PHYS_MODE__SIZE_1 6 /* */
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#define NV_CE_PCE_SRC_PHYS_MODE_TARGET 1:0 /* R-IVF */
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#define NV_CE_PCE_SRC_PHYS_MODE_TARGET_LOCAL_FB 0x00000000 /* R-I-V */
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#define NV_CE_PCE_SRC_PHYS_MODE_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
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#define NV_CE_PCE_SRC_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */
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#define NV_CE_PCE_SRC_PHYS_MODE_TARGET_PEERMEM 0x00000003 /* R---V */
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#define NV_CE_PCE_SRC_PHYS_MODE_PEER_ID 8:6 /* R-IVF */
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#define NV_CE_PCE_SRC_PHYS_MODE_PEER_ID_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_SRC_PHYS_MODE_FLA 9:9 /* R-IVF */
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#define NV_CE_PCE_SRC_PHYS_MODE_FLA_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_DST_PHYS_MODE(i) (0x00105054+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_DST_PHYS_MODE__SIZE_1 6 /* */
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#define NV_CE_PCE_DST_PHYS_MODE_TARGET 1:0 /* R-IVF */
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#define NV_CE_PCE_DST_PHYS_MODE_TARGET_LOCAL_FB 0x00000000 /* R-I-V */
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#define NV_CE_PCE_DST_PHYS_MODE_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
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#define NV_CE_PCE_DST_PHYS_MODE_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */
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#define NV_CE_PCE_DST_PHYS_MODE_TARGET_PEERMEM 0x00000003 /* R---V */
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#define NV_CE_PCE_DST_PHYS_MODE_PEER_ID 8:6 /* R-IVF */
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#define NV_CE_PCE_DST_PHYS_MODE_PEER_ID_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_DST_PHYS_MODE_FLA 9:9 /* R-IVF */
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#define NV_CE_PCE_DST_PHYS_MODE_FLA_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PIPESTATUS(i) (0x00105058+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_PIPESTATUS__SIZE_1 6 /* */
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#define NV_CE_PCE_PIPESTATUS_CTL 0:0 /* R-IVF */
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#define NV_CE_PCE_PIPESTATUS_CTL_IDLE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PIPESTATUS_CTL_NONIDLE 0x00000001 /* R---V */
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#define NV_CE_PCE_PIPESTATUS_GSTRIP 1:1 /* R-IVF */
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#define NV_CE_PCE_PIPESTATUS_GSTRIP_IDLE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PIPESTATUS_GSTRIP_NONIDLE 0x00000001 /* R---V */
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#define NV_CE_PCE_PIPESTATUS_RALIGN 2:2 /* R-IVF */
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#define NV_CE_PCE_PIPESTATUS_RALIGN_IDLE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PIPESTATUS_RALIGN_NONIDLE 0x00000001 /* R---V */
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#define NV_CE_PCE_PIPESTATUS_SWIZ 3:3 /* R-IVF */
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#define NV_CE_PCE_PIPESTATUS_SWIZ_IDLE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PIPESTATUS_SWIZ_NONIDLE 0x00000001 /* R---V */
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#define NV_CE_PCE_PIPESTATUS_WALIGN 4:4 /* R-IVF */
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#define NV_CE_PCE_PIPESTATUS_WALIGN_IDLE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PIPESTATUS_WALIGN_NONIDLE 0x00000001 /* R---V */
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#define NV_CE_PCE_PIPESTATUS_GPAD 5:5 /* R-IVF */
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#define NV_CE_PCE_PIPESTATUS_GPAD_IDLE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PIPESTATUS_GPAD_NONIDLE 0x00000001 /* R---V */
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#define NV_CE_PCE_PIPESTATUS_RDAT 6:6 /* R-IVF */
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#define NV_CE_PCE_PIPESTATUS_RDAT_IDLE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PIPESTATUS_RDAT_NONIDLE 0x00000001 /* R---V */
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#define NV_CE_PCE_PIPESTATUS_RDACK 7:7 /* R-IVF */
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#define NV_CE_PCE_PIPESTATUS_RDACK_IDLE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PIPESTATUS_RDACK_NONIDLE 0x00000001 /* R---V */
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#define NV_CE_PCE_PIPESTATUS_WRACK 8:8 /* R-IVF */
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#define NV_CE_PCE_PIPESTATUS_WRACK_IDLE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PIPESTATUS_WRACK_NONIDLE 0x00000001 /* R---V */
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#define NV_CE_PCE_PIPESTATUS_RCMD_STALL 10:10 /* R-IVF */
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#define NV_CE_PCE_PIPESTATUS_RCMD_STALL_NONACTIVE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PIPESTATUS_RCMD_STALL_ACTIVE 0x00000001 /* R---V */
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#define NV_CE_PCE_PIPESTATUS_WCMD_STALL 11:11 /* R-IVF */
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#define NV_CE_PCE_PIPESTATUS_WCMD_STALL_NONACTIVE 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PIPESTATUS_WCMD_STALL_ACTIVE 0x00000001 /* R---V */
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#define NV_CE_PCE_GLOBAL_COUNTER_LOWER(i) (0x00105070+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_GLOBAL_COUNTER_LOWER__SIZE_1 6 /* */
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#define NV_CE_PCE_GLOBAL_COUNTER_LOWER_VAL 31:0 /* R-IVF */
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#define NV_CE_PCE_GLOBAL_COUNTER_LOWER_VAL_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_GLOBAL_COUNTER_UPPER(i) (0x00105074+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_GLOBAL_COUNTER_UPPER__SIZE_1 6 /* */
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#define NV_CE_PCE_GLOBAL_COUNTER_UPPER_VAL 31:0 /* R-IVF */
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#define NV_CE_PCE_GLOBAL_COUNTER_UPPER_VAL_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PAGEOUT_START_PALOWER(i) (0x00105078+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_PAGEOUT_START_PALOWER__SIZE_1 6 /* */
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#define NV_CE_PCE_PAGEOUT_START_PALOWER_VAL 31:0 /* R-IVF */
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#define NV_CE_PCE_PAGEOUT_START_PALOWER_VAL_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PAGEOUT_START_PAUPPER(i) (0x0010507c+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_PAGEOUT_START_PAUPPER__SIZE_1 6 /* */
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#define NV_CE_PCE_PAGEOUT_START_PAUPPER_VAL 4:0 /* R-IVF */
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#define NV_CE_PCE_PAGEOUT_START_PAUPPER_VAL_INIT 0x00000000 /* R-I-V */
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#define NV_CE_PCE_PMM(i) (0x00105068+(i)*0xc0) /* RW-4A */
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#define NV_CE_PCE_PMM__SIZE_1 6 /* */
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#define NV_CE_PCE_PMM_SEL0 5:0 /* RWEUF */
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#define NV_CE_PCE_PMM_SEL0_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE_PMM_SEL0_COP_SUBID_EXHAUSTED 0x00000001 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_RDAT_BUF_FULL 0x00000002 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_RDAT_BUF_EMPTY 0x00000003 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_RDAT_DATA_OUT_OF_ORDER 0x00000004 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_OUT_RD_REQ 0x00000005 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_OUT_SMALL_RD 0x00000006 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_OUT_WR_REQ 0x00000007 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_OUT_SMALL_WR 0x00000008 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_OUT_WR_DATA_WE 0x00000009 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_OUT_PACKED_REQ 0x0000000A /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_OUT_IFC_PRDY 0x0000000B /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_OUT_IFC_PVLD 0x0000000C /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_CMD_SRC_STARVED 0x0000000D /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_CMD_DST_STARVED 0x0000000E /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_RDAT_BUF_STARVED 0x0000000F /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_CMD_SRC_BUSY 0x00000010 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_CMD_DST_BUSY 0x00000011 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_IN_RD_DATA 0x00000012 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_OUT_WR_DATA 0x00000013 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_CMD_BUSY 0x00000014 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_TLB_ACK 0x00000015 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_FE_LATENCY_TLB_ACK_CYCLES 0x00000016 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_WCMD_FIFO_FULL 0x00000017 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_RCMD_FIFO_FULL 0x00000018 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_WCTL_FIFO_FULL 0x00000019 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_RMW_FIFO_FULL 0x0000001A /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_RCTL_FIFO_FULL 0x0000001B /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_FE_ORQ_FIFO_FULL 0x0000001C /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_RCTL_PIPEADV 0x0000001D /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_WCTL_PIPEADV 0x0000001E /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_CTL2GPAD_PVLD 0x0000001F /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_CTL2GPAD_PRDY 0x00000020 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_CE2FB_PRDY 0x00000021 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_CE2FB_PVLD 0x00000022 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_FE_BUSY 0x00000023 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_FE_STALLED_ON_COP 0x00000024 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_FE_WAITING_FOR_PARAM_PACKET 0x00000025 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_FE_LATENCY_NUM_RD_REQUESTS 0x00000026 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_FE_LATENCY_TOTAL_CYCLES 0x00000027 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_FE_STALL_BUSY 0x00000028 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_SOP_REQ 0x00000029 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_SOP_ACK 0x0000002A /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_VPRMODE_NONE 0x0000002B /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_VPRMODE_VID2VID 0x0000002C /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_VPRMODE_VID2SYS 0x0000002D /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_VPRMODE_SYS2VID 0x0000002E /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_FE_COPY_STARTED 0x0000002F /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_PCE_COPY_COMPLETED 0x00000030 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_PCE_NACK_RECEIVED 0x00000031 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_PCE_FAULTED_AND_STALLED 0x00000032 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_PCE_HALTED 0x00000033 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_STATIC_PATTERN_0_1_GROUP 0x00000034 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_STATIC_PATTERN_1_1_GROUP 0x00000035 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_PCE_POISON_RECEIVED 0x00000036 /* RW--V */
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#define NV_CE_PCE_PMM_SEL0_COP_RD_WR_COMBINED_DATA 0x00000037 /* RW--V */
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#define NV_CE_PCE_PMM_SEL1 13:8 /* RWEUF */
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#define NV_CE_PCE_PMM_SEL1_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE_PMM_SEL2 21:16 /* RWEUF */
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#define NV_CE_PCE_PMM_SEL2_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE_PMM_SEL3 29:24 /* RWEUF */
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#define NV_CE_PCE_PMM_SEL3_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE_PMM_PERFMON_ENABLE 31:31 /* RWEVF */
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#define NV_CE_PCE_PMM_PERFMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_CE_PCE_PMM_PERFMON_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_CE_PCE0_PMM 0x00105068 /* RW-4P */
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#define NV_CE_PCE0_PMM_SEL0 5:0 /* RWEUF */
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#define NV_CE_PCE0_PMM_SEL0_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE0_PMM_SEL0_COP_SUBID_EXHAUSTED 0x00000001 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_RDAT_BUF_FULL 0x00000002 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_RDAT_BUF_EMPTY 0x00000003 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_RDAT_DATA_OUT_OF_ORDER 0x00000004 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_OUT_RD_REQ 0x00000005 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_OUT_SMALL_RD 0x00000006 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_OUT_WR_REQ 0x00000007 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_OUT_SMALL_WR 0x00000008 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_OUT_WR_DATA_WE 0x00000009 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_OUT_PACKED_REQ 0x0000000A /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_OUT_IFC_PRDY 0x0000000B /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_OUT_IFC_PVLD 0x0000000C /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_CMD_SRC_STARVED 0x0000000D /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_CMD_DST_STARVED 0x0000000E /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_RDAT_BUF_STARVED 0x0000000F /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_CMD_SRC_BUSY 0x00000010 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_CMD_DST_BUSY 0x00000011 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_IN_RD_DATA 0x00000012 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_OUT_WR_DATA 0x00000013 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_CMD_BUSY 0x00000014 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_TLB_ACK 0x00000015 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_FE_LATENCY_TLB_ACK_CYCLES 0x00000016 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_WCMD_FIFO_FULL 0x00000017 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_RCMD_FIFO_FULL 0x00000018 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_WCTL_FIFO_FULL 0x00000019 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_RMW_FIFO_FULL 0x0000001A /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_RCTL_FIFO_FULL 0x0000001B /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_FE_ORQ_FIFO_FULL 0x0000001C /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_RCTL_PIPEADV 0x0000001D /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_WCTL_PIPEADV 0x0000001E /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_CTL2GPAD_PVLD 0x0000001F /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_CTL2GPAD_PRDY 0x00000020 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_CE2FB_PRDY 0x00000021 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_CE2FB_PVLD 0x00000022 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_FE_BUSY 0x00000023 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_FE_STALLED_ON_COP 0x00000024 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_FE_WAITING_FOR_PARAM_PACKET 0x00000025 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_FE_LATENCY_NUM_RD_REQUESTS 0x00000026 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_FE_LATENCY_TOTAL_CYCLES 0x00000027 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_FE_STALL_BUSY 0x00000028 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_SOP_REQ 0x00000029 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_SOP_ACK 0x0000002A /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_VPRMODE_NONE 0x0000002B /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_VPRMODE_VID2VID 0x0000002C /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_VPRMODE_VID2SYS 0x0000002D /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_VPRMODE_SYS2VID 0x0000002E /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_FE_COPY_STARTED 0x0000002F /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_PCE_COPY_COMPLETED 0x00000030 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_PCE_NACK_RECEIVED 0x00000031 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_PCE_FAULTED_AND_STALLED 0x00000032 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_PCE_HALTED 0x00000033 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_STATIC_PATTERN_0_1_GROUP 0x00000034 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_STATIC_PATTERN_1_1_GROUP 0x00000035 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_PCE_POISON_RECEIVED 0x00000036 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL0_COP_RD_WR_COMBINED_DATA 0x00000037 /* RW--V */
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#define NV_CE_PCE0_PMM_SEL1 13:8 /* RWEUF */
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#define NV_CE_PCE0_PMM_SEL1_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE0_PMM_SEL2 21:16 /* RWEUF */
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#define NV_CE_PCE0_PMM_SEL2_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE0_PMM_SEL3 29:24 /* RWEUF */
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#define NV_CE_PCE0_PMM_SEL3_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE0_PMM_PERFMON_ENABLE 31:31 /* RWEVF */
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#define NV_CE_PCE0_PMM_PERFMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_CE_PCE0_PMM_PERFMON_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_CE_PCE1_PMM 0x00105128 /* RW-4P */
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#define NV_CE_PCE1_PMM_SEL0 5:0 /* RWEUF */
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#define NV_CE_PCE1_PMM_SEL0_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE1_PMM_SEL0_COP_SUBID_EXHAUSTED 0x00000001 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_RDAT_BUF_FULL 0x00000002 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_RDAT_BUF_EMPTY 0x00000003 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_RDAT_DATA_OUT_OF_ORDER 0x00000004 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_OUT_RD_REQ 0x00000005 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_OUT_SMALL_RD 0x00000006 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_OUT_WR_REQ 0x00000007 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_OUT_SMALL_WR 0x00000008 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_OUT_WR_DATA_WE 0x00000009 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_OUT_PACKED_REQ 0x0000000A /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_OUT_IFC_PRDY 0x0000000B /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_OUT_IFC_PVLD 0x0000000C /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_CMD_SRC_STARVED 0x0000000D /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_CMD_DST_STARVED 0x0000000E /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_RDAT_BUF_STARVED 0x0000000F /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_CMD_SRC_BUSY 0x00000010 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_CMD_DST_BUSY 0x00000011 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_IN_RD_DATA 0x00000012 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_OUT_WR_DATA 0x00000013 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_CMD_BUSY 0x00000014 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_TLB_ACK 0x00000015 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_FE_LATENCY_TLB_ACK_CYCLES 0x00000016 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_WCMD_FIFO_FULL 0x00000017 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_RCMD_FIFO_FULL 0x00000018 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_WCTL_FIFO_FULL 0x00000019 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_RMW_FIFO_FULL 0x0000001A /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_RCTL_FIFO_FULL 0x0000001B /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_FE_ORQ_FIFO_FULL 0x0000001C /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_RCTL_PIPEADV 0x0000001D /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_WCTL_PIPEADV 0x0000001E /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_CTL2GPAD_PVLD 0x0000001F /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_CTL2GPAD_PRDY 0x00000020 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_CE2FB_PRDY 0x00000021 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_CE2FB_PVLD 0x00000022 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_FE_BUSY 0x00000023 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_FE_STALLED_ON_COP 0x00000024 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_FE_WAITING_FOR_PARAM_PACKET 0x00000025 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_FE_LATENCY_NUM_RD_REQUESTS 0x00000026 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_FE_LATENCY_TOTAL_CYCLES 0x00000027 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_FE_STALL_BUSY 0x00000028 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_SOP_REQ 0x00000029 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_SOP_ACK 0x0000002A /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_VPRMODE_NONE 0x0000002B /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_VPRMODE_VID2VID 0x0000002C /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_VPRMODE_VID2SYS 0x0000002D /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_VPRMODE_SYS2VID 0x0000002E /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_FE_COPY_STARTED 0x0000002F /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_PCE_COPY_COMPLETED 0x00000030 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_PCE_NACK_RECEIVED 0x00000031 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_PCE_FAULTED_AND_STALLED 0x00000032 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_PCE_HALTED 0x00000033 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_STATIC_PATTERN_0_1_GROUP 0x00000034 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_STATIC_PATTERN_1_1_GROUP 0x00000035 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_PCE_POISON_RECEIVED 0x00000036 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL0_COP_RD_WR_COMBINED_DATA 0x00000037 /* RW--V */
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#define NV_CE_PCE1_PMM_SEL1 13:8 /* RWEUF */
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#define NV_CE_PCE1_PMM_SEL1_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE1_PMM_SEL2 21:16 /* RWEUF */
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#define NV_CE_PCE1_PMM_SEL2_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE1_PMM_SEL3 29:24 /* RWEUF */
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#define NV_CE_PCE1_PMM_SEL3_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE1_PMM_PERFMON_ENABLE 31:31 /* RWEVF */
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#define NV_CE_PCE1_PMM_PERFMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_CE_PCE1_PMM_PERFMON_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_CE_PCE2_PMM 0x001051e8 /* RW-4P */
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#define NV_CE_PCE2_PMM_SEL0 5:0 /* RWEUF */
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#define NV_CE_PCE2_PMM_SEL0_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE2_PMM_SEL0_COP_SUBID_EXHAUSTED 0x00000001 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_RDAT_BUF_FULL 0x00000002 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_RDAT_BUF_EMPTY 0x00000003 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_RDAT_DATA_OUT_OF_ORDER 0x00000004 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_OUT_RD_REQ 0x00000005 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_OUT_SMALL_RD 0x00000006 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_OUT_WR_REQ 0x00000007 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_OUT_SMALL_WR 0x00000008 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_OUT_WR_DATA_WE 0x00000009 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_OUT_PACKED_REQ 0x0000000A /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_OUT_IFC_PRDY 0x0000000B /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_OUT_IFC_PVLD 0x0000000C /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_CMD_SRC_STARVED 0x0000000D /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_CMD_DST_STARVED 0x0000000E /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_RDAT_BUF_STARVED 0x0000000F /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_CMD_SRC_BUSY 0x00000010 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_CMD_DST_BUSY 0x00000011 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_IN_RD_DATA 0x00000012 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_OUT_WR_DATA 0x00000013 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_CMD_BUSY 0x00000014 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_TLB_ACK 0x00000015 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_FE_LATENCY_TLB_ACK_CYCLES 0x00000016 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_WCMD_FIFO_FULL 0x00000017 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_RCMD_FIFO_FULL 0x00000018 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_WCTL_FIFO_FULL 0x00000019 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_RMW_FIFO_FULL 0x0000001A /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_RCTL_FIFO_FULL 0x0000001B /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_FE_ORQ_FIFO_FULL 0x0000001C /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_RCTL_PIPEADV 0x0000001D /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_WCTL_PIPEADV 0x0000001E /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_CTL2GPAD_PVLD 0x0000001F /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_CTL2GPAD_PRDY 0x00000020 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_CE2FB_PRDY 0x00000021 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_CE2FB_PVLD 0x00000022 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_FE_BUSY 0x00000023 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_FE_STALLED_ON_COP 0x00000024 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_FE_WAITING_FOR_PARAM_PACKET 0x00000025 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_FE_LATENCY_NUM_RD_REQUESTS 0x00000026 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_FE_LATENCY_TOTAL_CYCLES 0x00000027 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_FE_STALL_BUSY 0x00000028 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_SOP_REQ 0x00000029 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_SOP_ACK 0x0000002A /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_VPRMODE_NONE 0x0000002B /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_VPRMODE_VID2VID 0x0000002C /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_VPRMODE_VID2SYS 0x0000002D /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_VPRMODE_SYS2VID 0x0000002E /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_FE_COPY_STARTED 0x0000002F /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_PCE_COPY_COMPLETED 0x00000030 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_PCE_NACK_RECEIVED 0x00000031 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_PCE_FAULTED_AND_STALLED 0x00000032 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_PCE_HALTED 0x00000033 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_STATIC_PATTERN_0_1_GROUP 0x00000034 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_STATIC_PATTERN_1_1_GROUP 0x00000035 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_PCE_POISON_RECEIVED 0x00000036 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL0_COP_RD_WR_COMBINED_DATA 0x00000037 /* RW--V */
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#define NV_CE_PCE2_PMM_SEL1 13:8 /* RWEUF */
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#define NV_CE_PCE2_PMM_SEL1_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE2_PMM_SEL2 21:16 /* RWEUF */
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#define NV_CE_PCE2_PMM_SEL2_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE2_PMM_SEL3 29:24 /* RWEUF */
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#define NV_CE_PCE2_PMM_SEL3_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE2_PMM_PERFMON_ENABLE 31:31 /* RWEVF */
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#define NV_CE_PCE2_PMM_PERFMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_CE_PCE2_PMM_PERFMON_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_CE_PCE3_PMM 0x001052a8 /* RW-4P */
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#define NV_CE_PCE3_PMM_SEL0 5:0 /* RWEUF */
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#define NV_CE_PCE3_PMM_SEL0_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE3_PMM_SEL0_COP_SUBID_EXHAUSTED 0x00000001 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_RDAT_BUF_FULL 0x00000002 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_RDAT_BUF_EMPTY 0x00000003 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_RDAT_DATA_OUT_OF_ORDER 0x00000004 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_OUT_RD_REQ 0x00000005 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_OUT_SMALL_RD 0x00000006 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_OUT_WR_REQ 0x00000007 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_OUT_SMALL_WR 0x00000008 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_OUT_WR_DATA_WE 0x00000009 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_OUT_PACKED_REQ 0x0000000A /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_OUT_IFC_PRDY 0x0000000B /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_OUT_IFC_PVLD 0x0000000C /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_CMD_SRC_STARVED 0x0000000D /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_CMD_DST_STARVED 0x0000000E /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_RDAT_BUF_STARVED 0x0000000F /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_CMD_SRC_BUSY 0x00000010 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_CMD_DST_BUSY 0x00000011 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_IN_RD_DATA 0x00000012 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_OUT_WR_DATA 0x00000013 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_CMD_BUSY 0x00000014 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_TLB_ACK 0x00000015 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_FE_LATENCY_TLB_ACK_CYCLES 0x00000016 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_WCMD_FIFO_FULL 0x00000017 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_RCMD_FIFO_FULL 0x00000018 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_WCTL_FIFO_FULL 0x00000019 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_RMW_FIFO_FULL 0x0000001A /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_RCTL_FIFO_FULL 0x0000001B /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_FE_ORQ_FIFO_FULL 0x0000001C /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_RCTL_PIPEADV 0x0000001D /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_WCTL_PIPEADV 0x0000001E /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_CTL2GPAD_PVLD 0x0000001F /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_CTL2GPAD_PRDY 0x00000020 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_CE2FB_PRDY 0x00000021 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_CE2FB_PVLD 0x00000022 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_FE_BUSY 0x00000023 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_FE_STALLED_ON_COP 0x00000024 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_FE_WAITING_FOR_PARAM_PACKET 0x00000025 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_FE_LATENCY_NUM_RD_REQUESTS 0x00000026 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_FE_LATENCY_TOTAL_CYCLES 0x00000027 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_FE_STALL_BUSY 0x00000028 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_SOP_REQ 0x00000029 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_SOP_ACK 0x0000002A /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_VPRMODE_NONE 0x0000002B /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_VPRMODE_VID2VID 0x0000002C /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_VPRMODE_VID2SYS 0x0000002D /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_VPRMODE_SYS2VID 0x0000002E /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_FE_COPY_STARTED 0x0000002F /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_PCE_COPY_COMPLETED 0x00000030 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_PCE_NACK_RECEIVED 0x00000031 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_PCE_FAULTED_AND_STALLED 0x00000032 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_PCE_HALTED 0x00000033 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_STATIC_PATTERN_0_1_GROUP 0x00000034 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_STATIC_PATTERN_1_1_GROUP 0x00000035 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_PCE_POISON_RECEIVED 0x00000036 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL0_COP_RD_WR_COMBINED_DATA 0x00000037 /* RW--V */
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#define NV_CE_PCE3_PMM_SEL1 13:8 /* RWEUF */
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#define NV_CE_PCE3_PMM_SEL1_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE3_PMM_SEL2 21:16 /* RWEUF */
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#define NV_CE_PCE3_PMM_SEL2_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE3_PMM_SEL3 29:24 /* RWEUF */
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#define NV_CE_PCE3_PMM_SEL3_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE3_PMM_PERFMON_ENABLE 31:31 /* RWEVF */
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#define NV_CE_PCE3_PMM_PERFMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_CE_PCE3_PMM_PERFMON_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_CE_PCE4_PMM 0x00105368 /* RW-4P */
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#define NV_CE_PCE4_PMM_SEL0 5:0 /* RWEUF */
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#define NV_CE_PCE4_PMM_SEL0_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE4_PMM_SEL0_COP_SUBID_EXHAUSTED 0x00000001 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_RDAT_BUF_FULL 0x00000002 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_RDAT_BUF_EMPTY 0x00000003 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_RDAT_DATA_OUT_OF_ORDER 0x00000004 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_OUT_RD_REQ 0x00000005 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_OUT_SMALL_RD 0x00000006 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_OUT_WR_REQ 0x00000007 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_OUT_SMALL_WR 0x00000008 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_OUT_WR_DATA_WE 0x00000009 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_OUT_PACKED_REQ 0x0000000A /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_OUT_IFC_PRDY 0x0000000B /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_OUT_IFC_PVLD 0x0000000C /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_CMD_SRC_STARVED 0x0000000D /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_CMD_DST_STARVED 0x0000000E /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_RDAT_BUF_STARVED 0x0000000F /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_CMD_SRC_BUSY 0x00000010 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_CMD_DST_BUSY 0x00000011 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_IN_RD_DATA 0x00000012 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_OUT_WR_DATA 0x00000013 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_CMD_BUSY 0x00000014 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_TLB_ACK 0x00000015 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_FE_LATENCY_TLB_ACK_CYCLES 0x00000016 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_WCMD_FIFO_FULL 0x00000017 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_RCMD_FIFO_FULL 0x00000018 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_WCTL_FIFO_FULL 0x00000019 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_RMW_FIFO_FULL 0x0000001A /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_RCTL_FIFO_FULL 0x0000001B /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_FE_ORQ_FIFO_FULL 0x0000001C /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_RCTL_PIPEADV 0x0000001D /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_WCTL_PIPEADV 0x0000001E /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_CTL2GPAD_PVLD 0x0000001F /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_CTL2GPAD_PRDY 0x00000020 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_CE2FB_PRDY 0x00000021 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_CE2FB_PVLD 0x00000022 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_FE_BUSY 0x00000023 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_FE_STALLED_ON_COP 0x00000024 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_FE_WAITING_FOR_PARAM_PACKET 0x00000025 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_FE_LATENCY_NUM_RD_REQUESTS 0x00000026 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_FE_LATENCY_TOTAL_CYCLES 0x00000027 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_FE_STALL_BUSY 0x00000028 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_SOP_REQ 0x00000029 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_SOP_ACK 0x0000002A /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_VPRMODE_NONE 0x0000002B /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_VPRMODE_VID2VID 0x0000002C /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_VPRMODE_VID2SYS 0x0000002D /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_VPRMODE_SYS2VID 0x0000002E /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_FE_COPY_STARTED 0x0000002F /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_PCE_COPY_COMPLETED 0x00000030 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_PCE_NACK_RECEIVED 0x00000031 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_PCE_FAULTED_AND_STALLED 0x00000032 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_PCE_HALTED 0x00000033 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_STATIC_PATTERN_0_1_GROUP 0x00000034 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_STATIC_PATTERN_1_1_GROUP 0x00000035 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_PCE_POISON_RECEIVED 0x00000036 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL0_COP_RD_WR_COMBINED_DATA 0x00000037 /* RW--V */
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#define NV_CE_PCE4_PMM_SEL1 13:8 /* RWEUF */
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#define NV_CE_PCE4_PMM_SEL1_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE4_PMM_SEL2 21:16 /* RWEUF */
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#define NV_CE_PCE4_PMM_SEL2_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE4_PMM_SEL3 29:24 /* RWEUF */
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#define NV_CE_PCE4_PMM_SEL3_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE4_PMM_PERFMON_ENABLE 31:31 /* RWEVF */
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#define NV_CE_PCE4_PMM_PERFMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_CE_PCE4_PMM_PERFMON_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_CE_PCE5_PMM 0x00105428 /* RW-4P */
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#define NV_CE_PCE5_PMM_SEL0 5:0 /* RWEUF */
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#define NV_CE_PCE5_PMM_SEL0_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE5_PMM_SEL0_COP_SUBID_EXHAUSTED 0x00000001 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_RDAT_BUF_FULL 0x00000002 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_RDAT_BUF_EMPTY 0x00000003 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_RDAT_DATA_OUT_OF_ORDER 0x00000004 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_OUT_RD_REQ 0x00000005 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_OUT_SMALL_RD 0x00000006 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_OUT_WR_REQ 0x00000007 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_OUT_SMALL_WR 0x00000008 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_OUT_WR_DATA_WE 0x00000009 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_OUT_PACKED_REQ 0x0000000A /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_OUT_IFC_PRDY 0x0000000B /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_OUT_IFC_PVLD 0x0000000C /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_CMD_SRC_STARVED 0x0000000D /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_CMD_DST_STARVED 0x0000000E /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_RDAT_BUF_STARVED 0x0000000F /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_CMD_SRC_BUSY 0x00000010 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_CMD_DST_BUSY 0x00000011 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_IN_RD_DATA 0x00000012 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_OUT_WR_DATA 0x00000013 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_CMD_BUSY 0x00000014 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_TLB_ACK 0x00000015 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_FE_LATENCY_TLB_ACK_CYCLES 0x00000016 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_WCMD_FIFO_FULL 0x00000017 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_RCMD_FIFO_FULL 0x00000018 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_WCTL_FIFO_FULL 0x00000019 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_RMW_FIFO_FULL 0x0000001A /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_RCTL_FIFO_FULL 0x0000001B /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_FE_ORQ_FIFO_FULL 0x0000001C /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_RCTL_PIPEADV 0x0000001D /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_WCTL_PIPEADV 0x0000001E /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_CTL2GPAD_PVLD 0x0000001F /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_CTL2GPAD_PRDY 0x00000020 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_CE2FB_PRDY 0x00000021 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_CE2FB_PVLD 0x00000022 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_FE_BUSY 0x00000023 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_FE_STALLED_ON_COP 0x00000024 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_FE_WAITING_FOR_PARAM_PACKET 0x00000025 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_FE_LATENCY_NUM_RD_REQUESTS 0x00000026 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_FE_LATENCY_TOTAL_CYCLES 0x00000027 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_FE_STALL_BUSY 0x00000028 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_SOP_REQ 0x00000029 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_SOP_ACK 0x0000002A /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_VPRMODE_NONE 0x0000002B /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_VPRMODE_VID2VID 0x0000002C /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_VPRMODE_VID2SYS 0x0000002D /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_VPRMODE_SYS2VID 0x0000002E /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_FE_COPY_STARTED 0x0000002F /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_PCE_COPY_COMPLETED 0x00000030 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_PCE_NACK_RECEIVED 0x00000031 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_PCE_FAULTED_AND_STALLED 0x00000032 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_PCE_HALTED 0x00000033 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_STATIC_PATTERN_0_1_GROUP 0x00000034 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_STATIC_PATTERN_1_1_GROUP 0x00000035 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_PCE_POISON_RECEIVED 0x00000036 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL0_COP_RD_WR_COMBINED_DATA 0x00000037 /* RW--V */
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#define NV_CE_PCE5_PMM_SEL1 13:8 /* RWEUF */
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#define NV_CE_PCE5_PMM_SEL1_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE5_PMM_SEL2 21:16 /* RWEUF */
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#define NV_CE_PCE5_PMM_SEL2_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE5_PMM_SEL3 29:24 /* RWEUF */
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#define NV_CE_PCE5_PMM_SEL3_COP_READS_IN_FLIGHT 0x00000000 /* RWE-V */
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#define NV_CE_PCE5_PMM_PERFMON_ENABLE 31:31 /* RWEVF */
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#define NV_CE_PCE5_PMM_PERFMON_ENABLE_ENABLE 0x00000001 /* RW--V */
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#define NV_CE_PCE5_PMM_PERFMON_ENABLE_DISABLE 0x00000000 /* RWE-V */
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#define NV_CE_PCE_CAP(i) (0x00105060+(i)*0xc0) /* R--4A */
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#define NV_CE_PCE_CAP__SIZE_1 6 /* */
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#define NV_CE_PCE_CAP_VPR_PAGING 0:0 /* R--VF */
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#define NV_CE_PCE_CAP_VPR_PAGING_DISABLED 0x00000000 /* R---V */
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#define NV_CE_PCE_CAP_VPR_PAGING_ENABLED 0x00000001 /* R---V */
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#endif // __ga102_dev_ce_h__
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