271 lines
28 KiB
C
271 lines
28 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_timer_h__
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#define __ga102_dev_timer_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PTIMER 0x00009fff:0x00009000 /* RW--D */
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#define NV_PTIMER_PRI_TIMEOUT 0x00009080 /* */
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#define NV_PTIMER_PRI_TIMEOUT_PERIOD 23:0 /* */
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#define NV_PTIMER_PRI_TIMEOUT_PERIOD_MIN 0x00000003 /* */
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#define NV_PTIMER_PRI_TIMEOUT_PERIOD_MAX 0x00ffffff /* */
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#define NV_PTIMER_PRI_TIMEOUT_PERIOD_RTL 0x00000015 /* */
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#define NV_PTIMER_PRI_TIMEOUT_PERIOD_SHORT 0x00000006 /* */
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#define NV_PTIMER_PRI_TIMEOUT_PERIOD_INIT 0x00000100 /* */
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#define NV_PTIMER_PRI_TIMEOUT_EN 31:31 /* */
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#define NV_PTIMER_PRI_TIMEOUT_EN_DISABLED 0x00000000 /* */
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#define NV_PTIMER_PRI_TIMEOUT_EN_ENABLED 0x00000001 /* */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x00009084 /* RW-4R */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_TO 0:0 /* RWXVF */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_TO_ERROR 0x1 /* RW--V */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_TO_CLEAR 0x0 /* -W--V */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_TO_NONE 0x0 /* RW--V */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_WRITE 1:1 /* RWXVF */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_WRITE_TRUE 0x1 /* RW--V */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_WRITE_FALSE 0x0 /* RW--V */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_ADDR 24:2 /* RWXVF */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_FECS_TGT 31:31 /* RWXVF */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_FECS_TGT_TRUE 0x1 /* RW--V */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_FECS_TGT_FALSE 0x0 /* RW--V */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x00009088 /* RW-4R */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_1_DATA 31:0 /* RWXVF */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_1_DATA_WAS_READ 0x0 /* RW--V */
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#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x0000908C /* RW-4R */
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#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE_DATA 31:0 /* RWXVF */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3 0x00009090 /* R--4R */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_SUBID 3:0 /* R-XVF */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_SUBID_NONXVE_PMU 0 /* */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_SUBID_NONXVE_I2C 1 /* */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_SUBID_NONXVE_JTAG 2 /* */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_SUBID_NONXVE_IFF 3 /* */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_SUBID_NONXVE_SEC2 4 /* */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_SUBID_NONXVE_GSP 5 /* */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_SUBID_NONXVE_NVDEC0 6 /* */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_SUBID_NONXVE_NVDEC1 7 /* */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_SUBID_NONXVE_NVDEC2 12 /* */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_SUBID_NONXVE_NVDEC3 14 /* */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_SUBID_NONXVE_NVDEC4 15 /* */
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#define NV_PTIMER_PRI_TIMEOUT_SAVE_3_GFID 15:8 /* R-XVF */
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#define NV_PTIMER_ALARM_INTR 0x00009140 /* RW-4R */
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#define NV_PTIMER_ALARM_INTR_MASK 0:0 /* RWIVF */
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#define NV_PTIMER_ALARM_INTR_MASK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PTIMER_ALARM_INTR_MASK_ENABLED 0x00000001 /* RW--V */
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#define NV_PTIMER_INTR_EN_0 0x00009140 /* */
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#define NV_PTIMER_INTR_EN_0_ALARM 0:0 /* */
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#define NV_PTIMER_INTR_EN_0_ALARM_DISABLED 0x00000000 /* */
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#define NV_PTIMER_INTR_EN_0_ALARM_ENABLED 0x00000001 /* */
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#define NV_PTIMER_INTR_EN_0_TIMER 1:1 /* */
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#define NV_PTIMER_INTR_EN_0_TIMER_DISABLED 0x00000000 /* */
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#define NV_PTIMER_INTR_EN_0_TIMER_ENABLED 0x00000001 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK 0x00009308 /* RW-4R */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 8 /* RWI-V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTIMER_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTIMER_TIMER_CFG0 0x00009300 /* RW-4R */
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#define NV_PTIMER_TIMER_CFG0__PRIV_LEVEL_MASK 0x00009308 /* */
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#define NV_PTIMER_TIMER_CFG0_DEN 4:0 /* RWIUF */
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#define NV_PTIMER_TIMER_CFG0_DEN_27MHZ_REF 0x1b /* RW--V */
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#define NV_PTIMER_TIMER_CFG0_DEN_25MHZ_REF 0x0 /* RW--V */
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#define NV_PTIMER_TIMER_CFG0_DEN_108MHZ_REF 0x1b /* RWI-V */
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#define NV_PTIMER_TIMER_CFG0_DEN_100MHZ_REF 0x0 /* RW--V */
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#define NV_PTIMER_TIMER_CFG0_DEN_EMULATION 0x0 /* RW--V */
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#define NV_PTIMER_TIMER_CFG0_NUM 18:16 /* RWIUF */
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#define NV_PTIMER_TIMER_CFG0_NUM_27MHZ_REF 0x1 /* RW--V */
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#define NV_PTIMER_TIMER_CFG0_NUM_25MHZ_REF 0x0 /* RW--V */
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#define NV_PTIMER_TIMER_CFG0_NUM_108MHZ_REF 0x7 /* RWI-V */
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#define NV_PTIMER_TIMER_CFG0_NUM_100MHZ_REF 0x0 /* RW--V */
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#define NV_PTIMER_TIMER_CFG0_NUM_EMULATION 0x0 /* RW--V */
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#define NV_PTIMER_TIMER_CFG1 0x00009304 /* RW-4R */
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#define NV_PTIMER_TIMER_CFG1__PRIV_LEVEL_MASK 0x00009308 /* */
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#define NV_PTIMER_TIMER_CFG1_INTEGER 5:0 /* RWIUF */
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#define NV_PTIMER_TIMER_CFG1_INTEGER_27MHZ_REF 0x000025 /* RW--V */
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#define NV_PTIMER_TIMER_CFG1_INTEGER_25MHZ_REF 0x000028 /* RW--V */
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#define NV_PTIMER_TIMER_CFG1_INTEGER_108MHZ_REF 0x000009 /* RWI-V */
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#define NV_PTIMER_TIMER_CFG1_INTEGER_100MHZ_REF 0x00000a /* RW--V */
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#define NV_PTIMER_TIMER_CFG1_INTEGER_EMULATION 0x000002 /* RW--V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK 0x0000948c /* RW-4R */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTIMER_TICK_FREQ_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTIMER_GR_TICK_FREQ 0x00009480 /* RW-4R */
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#define NV_PTIMER_GR_TICK_FREQ__PRIV_LEVEL_MASK 0x0000948c /* */
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#define NV_PTIMER_GR_TICK_FREQ_SELECT 2:0 /* RWIUF */
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#define NV_PTIMER_GR_TICK_FREQ_SELECT_MAX 0x00000000 /* RW--V */
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#define NV_PTIMER_GR_TICK_FREQ_SELECT_DEFAULT 0x00000005 /* RWI-V */
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#define NV_PTIMER_GR_TICK_FREQ_SELECT_MIN 0x00000007 /* RW--V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK 0x00009430 /* RW-4R */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 15 /* RWI-V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0F /* RW--V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x08 /* RW--V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PTIMER_TIME_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWI-V */
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#define NV_PTIMER_TIME_0 0x00009400 /* RW-4R */
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#define NV_PTIMER_TIME_0__PRIV_LEVEL_MASK 0x00009430 /* */
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#define NV_PTIMER_TIME_0_NSEC 31:5 /* RWXUF */
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#define NV_PTIMER_TIME_1 0x00009410 /* RW-4R */
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#define NV_PTIMER_TIME_1__PRIV_LEVEL_MASK 0x00009430 /* */
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#define NV_PTIMER_TIME_1_NSEC 28:0 /* RWXUF */
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#define NV_PTIMER_RO_TIME_0 0x00009404 /* R--4R */
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#define NV_PTIMER_RO_TIME_0_NSEC 31:5 /* R-XUF */
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#define NV_PTIMER_RO_TIME_1 0x00009414 /* R--4R */
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#define NV_PTIMER_RO_TIME_1_NSEC 28:0 /* R-XUF */
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#define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */
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#define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWIUF */
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#define NV_PTIMER_ALARM_0_NSEC_INIT 0x0 /* RWI-V */
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#define NV_PTIMER_TIMER_0 0x00009428 /* RW-4R */
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#define NV_PTIMER_TIMER_0_NSEC 31:0 /* */
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#define NV_PTIMER_TIMER_0_USEC 31:10 /* RWIUF */
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#define NV_PTIMER_TIMER_0_USEC_INIT 0x0 /* RWI-V */
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#define NV_PTIMER_VF_TIMER(i) (0x00009800+(i)*4) /* RW-4A */
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#define NV_PTIMER_VF_TIMER__SIZE_1 64 /* */
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#define NV_PTIMER_VF_TIMER_NSEC 31:0 /* */
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#define NV_PTIMER_VF_TIMER_USEC 31:10 /* RWIUF */
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#define NV_PTIMER_VF_TIMER_USEC_INIT 0x0 /* RWI-V */
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#define NV_PTIMER_VF_TIMER_INTR_VECTOR 0x00009440 /* C--4R */
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#define NV_PTIMER_VF_TIMER_INTR_VECTOR_ID 7:0 /* C--VF */
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#define NV_PTIMER_VF_TIMER_INTR_VECTOR_ID_VALUE 148 /* C---V */
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#define NV_PTIMER_PRI_TMR_CG1 0x00009600 /* RW-4R */
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#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
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#define NV_PTIMER_PRI_TMR_CG1_SLCG 1:1 /* RWIVF */
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#define NV_PTIMER_PRI_TMR_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_PTIMER_PRI_TMR_CG1_SLCG_DISABLED 0x00000001 /* RWI-V */
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#define NV_PTIMER_PRI_TMR_CG1_SLCG__PROD 0x00000000 /* RW--V */
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#endif // __ga102_dev_timer_h__
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