15346 lines
1.9 MiB
15346 lines
1.9 MiB
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_pwr_pri_h__
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#define __ga102_dev_pwr_pri_h__
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/* This file is autogenerated. Do not edit */
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#define NV_PPWR 0x10bfff:0x10a000 /* RW--D */
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#define NV_PPWR_DEVICE_MAP_GROUP_MMODE 0x00000000 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_RISCV_CTL 0x00000001 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_PIC 0x00000002 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_TIMER 0x00000003 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_HOSTIF 0x00000004 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_DMA 0x00000005 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_PMB 0x00000006 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_DIO 0x00000007 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_KEY 0x00000008 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_DEBUG 0x00000009 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_SHA 0x0000000a /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_KMEM 0x0000000b /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_BROM 0x0000000c /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_ROM_PATCH 0x0000000d /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_IOPMP 0x0000000e /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_NOACCESS 0x0000000f /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_SCP 0x00000010 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_FBIF 0x00000011 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_FALCON_ONLY 0x00000012 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_PRGN_CTL 0x00000013 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_SCRATCH_GROUP0 0x00000014 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_SCRATCH_GROUP1 0x00000015 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_SCRATCH_GROUP2 0x00000016 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_SCRATCH_GROUP3 0x00000017 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_PLM 0x00000018 /* */
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#define NV_PPWR_DEVICE_MAP_GROUP_HUB_DIO 0x00000019 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK 0x0010a280 /* RWI4R */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK 0x0010a284 /* RWI4R */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK 0x0010a288 /* RWI4R */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK 0x0010a28c /* RWI4R */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK 0x0010a290 /* RWI4R */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_IRQTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK 0x0010a294 /* RWI4R */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_MTHDCTX_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK 0x0010a0e8 /* RWI4R */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse1" /* */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PPWR_FALCON_HSCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK 0x0010a0ec /* RWI4R */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse2" /* */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PPWR_FALCON_DIODT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK 0x0010a298 /* RWI4R */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_INIT 0x00000008 /* RWI-V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_INIT 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_SCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK 0x0010a29c /* RWI4R */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_WDTMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK 0x0010a3d0 /* RWI4R */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK 0x0010a3c4 /* RWI4R */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000013 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_RESET_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK 0x0010a3f0 /* RWI4R */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000014 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK 0x0010a3f4 /* RWI4R */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000015 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK 0x0010a3f8 /* RWI4R */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000016 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK 0x0010a3fc /* RWI4R */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000017 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK(i) (0x0010a18c+(i)*16) /* RW-4A */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__SIZE_1 1 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000006 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK(i) (0x0010a2b0+(i)*4) /* RW-4A */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__SIZE_1 4 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000006 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK 0x0010a190 /* RW-4R */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_DMA_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK 0x0010a194 /* RW-4R */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK 0x0010a198 /* RW-4R */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_AMAP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK 0x0010a19c /* RW-4R */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK 0x0010a1a0 /* RW-4R */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_TMR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK 0x0010a1a4 /* RW-4R */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK 0x0010a1a8 /* RW-4R */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse3" /* */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK 0x0010a1ac /* RW-4R */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_CARVEOUT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK 0x0010a1b0 /* RW-4R */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_SAFETY_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK 0x0010a1b8 /* RWI4R */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_DEFAULT_PRIV_LEVEL 0x00000008 /* RWI-V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_NO_ACCESS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK 0x0010a1bc /* RW-4R */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_PTIMER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK 0x0010a1e0 /* RW-4R */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_IDLESTATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK 0x0010a1e4 /* RW-4R */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_ENG_STATE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK 0x0010a1e8 /* RW-4R */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK 0x0010a1ec /* RW-4R */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_PM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK 0x0010a1f0 /* RW-4R */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_SP_MIN_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK 0x0010a1f4 /* RW-4R */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_EXCI_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK 0x0010a1f8 /* RW-4R */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_SVEC_SPR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK 0x0010a1fc /* RW-4R */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse0" /* */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PPWR_FALCON_BRKPT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK 0x0010a220 /* RW-4R */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse4" /* */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK 0x0010a224 /* RW-4R */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_RSTAT0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK 0x0010a228 /* RW-4R */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_EXTERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK 0x0010a22c /* RW-4R */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_CSBERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_IRQSSET 0x0010a000 /* -W-4R */
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#define NV_PPWR_FALCON_IRQSSET__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_FALCON_IRQSSET_GPTMR 0:0 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSSET_WDTMR 1:1 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSSET_MTHD 2:2 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSSET_CTXSW 3:3 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSSET_HALT 4:4 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_HALT_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSSET_EXTERR 5:5 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSSET_SWGEN0 6:6 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSSET_SWGEN1 7:7 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSSET_EXT 15:8 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_EXT_CTXE 8:8 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_CTXE_SET 1 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_LIMITV 9:9 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_LIMITV_SET 1 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_ECC 10:10 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_ECC_SET 1 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_SECOND 11:11 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_SECOND_SET 1 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_THERM 12:12 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_THERM_SET 1 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_MISCIO 13:13 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_MISCIO_SET 1 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_RTTIMER 14:14 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_RTTIMER_SET 1 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_RSVD8 15:15 /* */
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#define NV_PPWR_FALCON_IRQSSET_EXT_RSVD8_SET 1 /* */
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#define NV_PPWR_FALCON_IRQSSET_DMA 16:16 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_DMA_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSSET_SHA 17:17 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_SHA_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSSET_MEMERR 18:18 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_MEMERR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSSET_ICD 22:22 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_ICD_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSSET_IOPMP 23:23 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_IOPMP_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSSET_CORE_MISMATCH 24:24 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSSET_CORE_MISMATCH_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR 0x0010a004 /* -W-4R */
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#define NV_PPWR_FALCON_IRQSCLR__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_FALCON_IRQSCLR_GPTMR 0:0 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_WDTMR 1:1 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_MTHD 2:2 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_CTXSW 3:3 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_HALT 4:4 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_HALT_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_EXTERR 5:5 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_SWGEN0 6:6 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_SWGEN1 7:7 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_EXT 15:8 /* */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_CTXE 8:8 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_CTXE_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_LIMITV 9:9 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_LIMITV_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_ECC 10:10 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_ECC_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_SECOND 11:11 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_SECOND_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_THERM 12:12 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_THERM_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_MISCIO 13:13 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_MISCIO_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_RTTIMER 14:14 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_RTTIMER_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_RSVD8 15:15 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_EXT_RSVD8_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_DMA 16:16 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_DMA_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_SHA 17:17 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_SHA_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_MEMERR 18:18 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_MEMERR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_ICD 22:22 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_ICD_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_IOPMP 23:23 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_IOPMP_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSCLR_CORE_MISMATCH 24:24 /* -WXVF */
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#define NV_PPWR_FALCON_IRQSCLR_CORE_MISMATCH_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQSTAT 0x0010a008 /* R--4R */
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#define NV_PPWR_FALCON_IRQSTAT__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_FALCON_IRQSTAT_GPTMR 0:0 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_GPTMR_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_GPTMR_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_WDTMR 1:1 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_WDTMR_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_WDTMR_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_MTHD 2:2 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_MTHD_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_MTHD_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_CTXSW 3:3 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_CTXSW_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_CTXSW_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_HALT 4:4 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_HALT_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_HALT_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_EXTERR 5:5 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_EXTERR_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_EXTERR_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_SWGEN0 6:6 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_SWGEN0_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_SWGEN0_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_SWGEN1 7:7 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_SWGEN1_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_SWGEN1_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT 15:8 /* */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_CTXE 8:8 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_CTXE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_CTXE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_LIMITV 9:9 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_LIMITV_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_LIMITV_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_ECC 10:10 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_ECC_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_ECC_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_SECOND 11:11 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_SECOND_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_SECOND_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_THERM 12:12 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_THERM_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_THERM_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_MISCIO 13:13 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_MISCIO_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_MISCIO_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_RTTIMER 14:14 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_RTTIMER_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_RTTIMER_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_RSVD8 15:15 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_RSVD8_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_EXT_RSVD8_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_DMA 16:16 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_DMA_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_DMA_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_SHA 17:17 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_SHA_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_SHA_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_MEMERR 18:18 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSTAT_MEMERR_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_MEMERR_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQSTAT_ICD 22:22 /* R-XVF */
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#define NV_PPWR_FALCON_IRQSTAT_ICD_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_ICD_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_IOPMP 23:23 /* R-XVF */
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#define NV_PPWR_FALCON_IRQSTAT_IOPMP_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_IOPMP_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_CORE_MISMATCH 24:24 /* R-XVF */
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#define NV_PPWR_FALCON_IRQSTAT_CORE_MISMATCH_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSTAT_CORE_MISMATCH_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_IRQMODE 0x0010a00c /* RW-4R */
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#define NV_PPWR_FALCON_IRQMODE__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_FALCON_IRQMODE__PRIV_LEVEL_MASK 0x0010a290 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_GPTMR 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_GPTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_GPTMR_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_GPTMR_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_WDTMR 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_WDTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_WDTMR_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_WDTMR_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_MTHD 2:2 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_MTHD_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_MTHD_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_MTHD_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_CTXSW 3:3 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_CTXSW_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_CTXSW_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_CTXSW_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_HALT 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_HALT_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_HALT_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_HALT_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXTERR 5:5 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXTERR_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXTERR_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXTERR_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_SWGEN0 6:6 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_SWGEN0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_SWGEN0_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_SWGEN0_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_SWGEN1 7:7 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_SWGEN1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_SWGEN1_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_SWGEN1_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT 15:8 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_INIT 0x000000fc /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_CTXE 8:8 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_CTXE_TRUE 1 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_CTXE_FALSE 0 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_LIMITV 9:9 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_LIMITV_TRUE 1 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_LIMITV_FALSE 0 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_ECC 10:10 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_ECC_TRUE 1 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_ECC_FALSE 0 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_SECOND 11:11 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_SECOND_TRUE 1 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_SECOND_FALSE 0 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_THERM 12:12 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_THERM_TRUE 1 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_THERM_FALSE 0 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_MISCIO 13:13 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_MISCIO_TRUE 1 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_MISCIO_FALSE 0 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_RTTIMER 14:14 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_RTTIMER_TRUE 1 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_RTTIMER_FALSE 0 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_RSVD8 15:15 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_RSVD8_TRUE 1 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_EXT_RSVD8_FALSE 0 /* */
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#define NV_PPWR_FALCON_IRQMODE_LVL_DMA 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_DMA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_DMA_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_DMA_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_SHA 17:17 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_SHA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_SHA_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_SHA_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_MEMERR 18:18 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_MEMERR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_MEMERR_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_MEMERR_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_ICD 22:22 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_ICD_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_ICD_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_ICD_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_IOPMP 23:23 /* RWIVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_IOPMP_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_IOPMP_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_IOPMP_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_CORE_MISMATCH 24:24 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMODE_LVL_CORE_MISMATCH_INIT 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_CORE_MISMATCH_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMODE_LVL_CORE_MISMATCH_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_IRQSCMASK 0x0010a0e0 /* RW-4R */
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#define NV_PPWR_FALCON_IRQSCMASK__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_FALCON_IRQSCMASK__PRIV_LEVEL_MASK 0x0010a1a4 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_GPTMR 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_GPTMR_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_GPTMR_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_WDTMR 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_WDTMR_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_WDTMR_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_MTHD 2:2 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_MTHD_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_MTHD_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_CTXSW 3:3 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_CTXSW_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_CTXSW_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_HALT 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_HALT_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_HALT_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_EXTERR 5:5 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_EXTERR_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_EXTERR_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_SWGEN0 6:6 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_SWGEN0_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_SWGEN0_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_SWGEN1 7:7 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_SWGEN1_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_SWGEN1_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT 15:8 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_ENABLE 0x000000ff /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_CTXE 8:8 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_CTXE_ENABLE 1 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_CTXE_DISABLE 0 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_LIMITV 9:9 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_LIMITV_ENABLE 1 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_LIMITV_DISABLE 0 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_ECC 10:10 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_ECC_ENABLE 1 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_ECC_DISABLE 0 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_SECOND 11:11 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_SECOND_ENABLE 1 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_SECOND_DISABLE 0 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_THERM 12:12 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_THERM_ENABLE 1 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_THERM_DISABLE 0 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_MISCIO 13:13 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_MISCIO_ENABLE 1 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_MISCIO_DISABLE 0 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_RTTIMER 14:14 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_RTTIMER_ENABLE 1 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_RTTIMER_DISABLE 0 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_RSVD8 15:15 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_RSVD8_ENABLE 1 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_EXT_RSVD8_DISABLE 0 /* */
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#define NV_PPWR_FALCON_IRQSCMASK_DMA 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_DMA_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_DMA_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_SHA 17:17 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_SHA_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_SHA_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_MEMERR 18:18 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_MEMERR_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_MEMERR_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_ICD 22:22 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_ICD_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_ICD_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_IOPMP 23:23 /* RWIVF */
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#define NV_PPWR_FALCON_IRQSCMASK_IOPMP_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_IRQSCMASK_IOPMP_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQSCMASK_CORE_MISMATCH 24:24 /* R-IVF */
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#define NV_PPWR_FALCON_IRQSCMASK_CORE_MISMATCH_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQSCMASK_CORE_MISMATCH_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMSET 0x0010a010 /* -W-4R */
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#define NV_PPWR_FALCON_IRQMSET__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IRQMSET__PRIV_LEVEL_MASK 0x0010a290 /* */
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#define NV_PPWR_FALCON_IRQMSET_GPTMR 0:0 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_WDTMR 1:1 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_MTHD 2:2 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_CTXSW 3:3 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_HALT 4:4 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_HALT_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_EXTERR 5:5 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_SWGEN0 6:6 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_SWGEN1 7:7 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_EXT 15:8 /* */
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#define NV_PPWR_FALCON_IRQMSET_EXT_CTXE 8:8 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_EXT_CTXE_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_EXT_LIMITV 9:9 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_EXT_LIMITV_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_EXT_ECC 10:10 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_EXT_ECC_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_EXT_SECOND 11:11 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_EXT_SECOND_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_EXT_THERM 12:12 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_EXT_THERM_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_EXT_MISCIO 13:13 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_EXT_MISCIO_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_EXT_RTTIMER 14:14 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_EXT_RTTIMER_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_EXT_RSVD8 15:15 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_EXT_RSVD8_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_DMA 16:16 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_DMA_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_SHA 17:17 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_SHA_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_MEMERR 18:18 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_MEMERR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_ICD 22:22 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_ICD_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_IOPMP 23:23 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_IOPMP_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMSET_CORE_MISMATCH 24:24 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMSET_CORE_MISMATCH_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR 0x0010a014 /* -W-4R */
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#define NV_PPWR_FALCON_IRQMCLR__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IRQMCLR__PRIV_LEVEL_MASK 0x0010a290 /* */
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#define NV_PPWR_FALCON_IRQMCLR_GPTMR 0:0 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_WDTMR 1:1 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_MTHD 2:2 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_CTXSW 3:3 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_HALT 4:4 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_HALT_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_EXTERR 5:5 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_SWGEN0 6:6 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_SWGEN1 7:7 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_EXT 15:8 /* */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_CTXE 8:8 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_CTXE_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_LIMITV 9:9 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_LIMITV_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_ECC 10:10 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_ECC_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_SECOND 11:11 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_SECOND_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_THERM 12:12 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_THERM_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_MISCIO 13:13 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_MISCIO_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_RTTIMER 14:14 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_RTTIMER_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_RSVD8 15:15 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_EXT_RSVD8_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_DMA 16:16 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_DMA_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_SHA 17:17 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_SHA_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_MEMERR 18:18 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_MEMERR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_ICD 22:22 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_ICD_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_IOPMP 23:23 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMCLR_IOPMP_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_IRQMCLR_CORE_MISMATCH 24:24 /* -WXVF */
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#define NV_PPWR_FALCON_IRQMASK 0x0010a018 /* R--4R */
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#define NV_PPWR_FALCON_IRQMASK__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IRQMASK_GPTMR 0:0 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_GPTMR_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_GPTMR_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_WDTMR 1:1 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_WDTMR_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_WDTMR_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_MTHD 2:2 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_MTHD_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_MTHD_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_CTXSW 3:3 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_CTXSW_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_CTXSW_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_HALT 4:4 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_HALT_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_HALT_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_EXTERR 5:5 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_EXTERR_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_EXTERR_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_SWGEN0 6:6 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_SWGEN0_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_SWGEN0_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_SWGEN1 7:7 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_SWGEN1_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_SWGEN1_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_EXT 15:8 /* */
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#define NV_PPWR_FALCON_IRQMASK_EXT_CTXE 8:8 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_EXT_CTXE_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_CTXE_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_LIMITV 9:9 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_EXT_LIMITV_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_LIMITV_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_ECC 10:10 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_EXT_ECC_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_ECC_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_SECOND 11:11 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_EXT_SECOND_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_SECOND_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_THERM 12:12 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_EXT_THERM_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_THERM_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_MISCIO 13:13 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_EXT_MISCIO_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_MISCIO_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_RTTIMER 14:14 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_EXT_RTTIMER_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_RTTIMER_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_RSVD8 15:15 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_EXT_RSVD8_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_EXT_RSVD8_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_DMA 16:16 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_DMA_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_DMA_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_SHA 17:17 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_SHA_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_SHA_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_MEMERR 18:18 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_MEMERR_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_MEMERR_DISABLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_ICD 22:22 /* R-XVF */
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#define NV_PPWR_FALCON_IRQMASK_ICD_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_ICD_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_IOPMP 23:23 /* R-XVF */
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#define NV_PPWR_FALCON_IRQMASK_IOPMP_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_IOPMP_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_IRQMASK_CORE_MISMATCH 24:24 /* R-IVF */
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#define NV_PPWR_FALCON_IRQMASK_CORE_MISMATCH_ENABLE 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_IRQMASK_CORE_MISMATCH_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_IRQDEST 0x0010a01c /* RW-4R */
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#define NV_PPWR_FALCON_IRQDEST__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IRQDEST__PRIV_LEVEL_MASK 0x0010a290 /* */
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#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR_FALCON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_GPTMR_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR_FALCON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_WDTMR_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD 2:2 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD_FALCON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_MTHD_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW 3:3 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW_FALCON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_CTXSW_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_HALT 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_HALT_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_HALT_FALCON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_HALT_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR 5:5 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR_FALCON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXTERR_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0 6:6 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0_FALCON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN0_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1 7:7 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1_FALCON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_SWGEN1_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT 15:8 /* */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_CTXE 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_CTXE_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_CTXE_FALCON 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_LIMITV 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_LIMITV_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_LIMITV_FALCON 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_ECC 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_ECC_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_ECC_FALCON 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_SECOND 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_SECOND_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_SECOND_FALCON 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_THERM 12:12 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_THERM_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_THERM_FALCON 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_MISCIO 13:13 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_MISCIO_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_MISCIO_FALCON 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_RTTIMER 14:14 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_RTTIMER_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_RTTIMER_FALCON 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_RSVD8 15:15 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_RSVD8_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_HOST_EXT_RSVD8_FALCON 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR 17:17 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD 18:18 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW 19:19 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT 20:20 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_HALT_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR 21:21 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0 22:22 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1 23:23 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT 31:24 /* */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_CTXE 24:24 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_CTXE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_CTXE_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_CTXE_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_CTXE_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_CTXE_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_LIMITV 25:25 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_LIMITV_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_LIMITV_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_LIMITV_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_LIMITV_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_LIMITV_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_ECC 26:26 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_ECC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_ECC_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_ECC_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_ECC_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_ECC_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_SECOND 27:27 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_SECOND_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_SECOND_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_SECOND_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_SECOND_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_SECOND_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_THERM 28:28 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_THERM_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_THERM_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_THERM_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_THERM_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_THERM_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_MISCIO 29:29 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_MISCIO_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_MISCIO_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_MISCIO_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_MISCIO_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_MISCIO_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_RTTIMER 30:30 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_RTTIMER_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_RTTIMER_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_RTTIMER_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_RTTIMER_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_RTTIMER_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_RSVD8 31:31 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_RSVD8_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_RSVD8_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_RSVD8_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_RSVD8_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST_TARGET_EXT_RSVD8_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2 0x0010a03c /* RW-4R */
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#define NV_PPWR_FALCON_IRQDEST2__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IRQDEST2__PRIV_LEVEL_MASK 0x0010a290 /* */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_DMA 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_DMA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_DMA_FALCON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_DMA_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_SHA 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_SHA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_SHA_FALCON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_SHA_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_MEMERR 2:2 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_MEMERR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_MEMERR_FALCON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_MEMERR_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_ICD 6:6 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_ICD_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_ICD_FALCON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_ICD_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_IOPMP 7:7 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_IOPMP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_IOPMP_FALCON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_IOPMP_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_CORE_MISMATCH 8:8 /* R-IVF */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_CORE_MISMATCH_INIT 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_CORE_MISMATCH_FALCON 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_IRQDEST2_HOST_CORE_MISMATCH_HOST 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_DMA 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_DMA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_DMA_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_DMA_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_DMA_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_SHA 17:17 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_SHA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_SHA_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_SHA_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_SHA_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_SHA_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_MEMERR 18:18 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_MEMERR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_MEMERR_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_MEMERR_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_MEMERR_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_MEMERR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_ICD 22:22 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_ICD_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_ICD_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_ICD_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_ICD_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_ICD_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_IOPMP 23:23 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_IOPMP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_IOPMP_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_IOPMP_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_IOPMP_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_IOPMP_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_CORE_MISMATCH 24:24 /* RWIVF */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_FALCON_IRQ0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_FALCON_IRQ1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_HOST_NORMAL 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IRQDEST2_TARGET_CORE_MISMATCH_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_GPTMRINT 0x0010a020 /* RW-4R */
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#define NV_PPWR_FALCON_GPTMRINT__DEVICE_MAP 0x00000003 /* */
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#define NV_PPWR_FALCON_GPTMRINT__PRIV_LEVEL_MASK 0x0010a1a0 /* */
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#define NV_PPWR_FALCON_GPTMRINT_VAL 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_GPTMRINT_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_GPTMRVAL 0x0010a024 /* RW-4R */
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#define NV_PPWR_FALCON_GPTMRVAL__DEVICE_MAP 0x00000003 /* */
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#define NV_PPWR_FALCON_GPTMRVAL__PRIV_LEVEL_MASK 0x0010a1a0 /* */
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#define NV_PPWR_FALCON_GPTMRVAL_VAL 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_GPTMRVAL_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_GPTMRCTL 0x0010a028 /* RW-4R */
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#define NV_PPWR_FALCON_GPTMRCTL__DEVICE_MAP 0x00000003 /* */
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#define NV_PPWR_FALCON_GPTMRCTL__PRIV_LEVEL_MASK 0x0010a1a0 /* */
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#define NV_PPWR_FALCON_GPTMRCTL_GPTMREN 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_GPTMRCTL_GPTMREN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_GPTMRCTL_GPTMREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_GPTMRCTL_GPTMREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_GPTMRCTL_GPTMR_SRC_MODE 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_GPTMRCTL_GPTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_GPTMRCTL_GPTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_GPTMRCTL_GPTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_PTIMER0 0x0010a02c /* R--4R */
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#define NV_PPWR_FALCON_PTIMER0__DEVICE_MAP 0x00000003 /* */
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#define NV_PPWR_FALCON_PTIMER0__PRIV_LEVEL_MASK 0x0010a1bc /* */
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#define NV_PPWR_FALCON_PTIMER0_VAL 31:0 /* R--VF */
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#define NV_PPWR_FALCON_PTIMER1 0x0010a030 /* R--4R */
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#define NV_PPWR_FALCON_PTIMER1__DEVICE_MAP 0x00000003 /* */
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#define NV_PPWR_FALCON_PTIMER1__PRIV_LEVEL_MASK 0x0010a1bc /* */
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#define NV_PPWR_FALCON_PTIMER1_VAL 31:0 /* R--VF */
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#define NV_PPWR_FALCON_WDTMRVAL 0x0010a034 /* RW-4R */
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#define NV_PPWR_FALCON_WDTMRVAL__DEVICE_MAP 0x00000003 /* */
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#define NV_PPWR_FALCON_WDTMRVAL__PRIV_LEVEL_MASK 0x0010a29c /* */
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#define NV_PPWR_FALCON_WDTMRVAL_VAL 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_WDTMRVAL_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_WDTMRCTL 0x0010a038 /* RW-4R */
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#define NV_PPWR_FALCON_WDTMRCTL__DEVICE_MAP 0x00000003 /* */
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#define NV_PPWR_FALCON_WDTMRCTL__PRIV_LEVEL_MASK 0x0010a29c /* */
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#define NV_PPWR_FALCON_WDTMRCTL_WDTMREN 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_WDTMRCTL_WDTMREN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_WDTMRCTL_WDTMREN_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_WDTMRCTL_WDTMREN_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_WDTMRCTL_WDTMR_SRC_MODE 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_WDTMRCTL_WDTMR_SRC_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_WDTMRCTL_WDTMR_SRC_MODE_ENGCLK 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_WDTMRCTL_WDTMR_SRC_MODE_PTIMER 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_MTHDDATA 0x0010a064 /* R--4R */
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#define NV_PPWR_FALCON_MTHDDATA__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_MTHDDATA__PRIV_LEVEL_MASK 0x0010a294 /* */
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#define NV_PPWR_FALCON_MTHDDATA_DATA 31:0 /* R-XVF */
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#define NV_PPWR_FALCON_MTHDID 0x0010a068 /* RW-4R */
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#define NV_PPWR_FALCON_MTHDID__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_MTHDID__PRIV_LEVEL_MASK 0x0010a294 /* */
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#define NV_PPWR_FALCON_MTHDID_ID 11:0 /* RWXVF */
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#define NV_PPWR_FALCON_MTHDID_SUBCH 14:12 /* RWXVF */
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#define NV_PPWR_FALCON_MTHDID_PRIV 15:15 /* RWXVF */
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#define NV_PPWR_FALCON_MTHDID_PRIV_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_MTHDID_PRIV_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_MTHDID_WPEND 16:16 /* R-XVF */
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#define NV_PPWR_FALCON_MTHDID_WPEND_DONE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_MTHDID_WPEND_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_MTHDWDAT 0x0010a06c /* RW-4R */
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#define NV_PPWR_FALCON_MTHDWDAT__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_MTHDWDAT__PRIV_LEVEL_MASK 0x0010a294 /* */
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#define NV_PPWR_FALCON_MTHDWDAT_DATA 31:0 /* RWXVF */
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#define NV_PPWR_FALCON_MTHDCOUNT 0x0010a070 /* R--4R */
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#define NV_PPWR_FALCON_MTHDCOUNT__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_MTHDCOUNT__PRIV_LEVEL_MASK 0x0010a294 /* */
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#define NV_PPWR_FALCON_MTHDCOUNT_COUNT 15:0 /* R-IVF */
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#define NV_PPWR_FALCON_MTHDCOUNT_COUNT_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_MTHDPOP 0x0010a074 /* -W-4R */
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#define NV_PPWR_FALCON_MTHDPOP__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_MTHDPOP__PRIV_LEVEL_MASK 0x0010a294 /* */
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#define NV_PPWR_FALCON_MTHDPOP_POP 0:0 /* -WXVF */
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#define NV_PPWR_FALCON_MTHDPOP_POP_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_MTHDPOP_POP_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_FALCON_MTHDRAMSZ 0x0010a078 /* RW-4R */
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#define NV_PPWR_FALCON_MTHDRAMSZ__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_MTHDRAMSZ__PRIV_LEVEL_MASK 0x0010a294 /* */
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#define NV_PPWR_FALCON_MTHDRAMSZ_RAMSZ 15:0 /* RWIVF */
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#define NV_PPWR_FALCON_MTHDRAMSZ_RAMSZ_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_CURCTX 0x0010a050 /* RW-4R */
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#define NV_PPWR_FALCON_CURCTX__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_CURCTX__PRIV_LEVEL_MASK 0x0010a294 /* */
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#define NV_PPWR_FALCON_CURCTX_CTXVLD 30:30 /* RWIVF */
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#define NV_PPWR_FALCON_CURCTX_CTXVLD_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_CURCTX_CTXVLD_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CURCTX_CTXVLD_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_CURCTX_CTXTGT 29:28 /* RWIVF */
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#define NV_PPWR_FALCON_CURCTX_CTXTGT_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_CURCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CURCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_CURCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_CURCTX_CTXPTR 27:0 /* RWIVF */
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#define NV_PPWR_FALCON_CURCTX_CTXPTR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_NXTCTX 0x0010a054 /* RW-4R */
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#define NV_PPWR_FALCON_NXTCTX__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_NXTCTX__PRIV_LEVEL_MASK 0x0010a294 /* */
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#define NV_PPWR_FALCON_NXTCTX_CTXVLD 30:30 /* RWIVF */
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#define NV_PPWR_FALCON_NXTCTX_CTXVLD_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_NXTCTX_CTXVLD_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_NXTCTX_CTXVLD_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_NXTCTX_CTXTGT 29:28 /* RWIVF */
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#define NV_PPWR_FALCON_NXTCTX_CTXTGT_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_NXTCTX_CTXTGT_LOCAL_FB 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_NXTCTX_CTXTGT_COHERENT_SYSMEM 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_NXTCTX_CTXTGT_NONCOHERENT_SYSMEM 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_NXTCTX_CTXPTR 27:0 /* RWIVF */
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#define NV_PPWR_FALCON_NXTCTX_CTXPTR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_CTXACK 0x0010a058 /* -W-4R */
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#define NV_PPWR_FALCON_CTXACK__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_CTXACK__PRIV_LEVEL_MASK 0x0010a294 /* */
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#define NV_PPWR_FALCON_CTXACK_SAVE_ACK 0:0 /* -WXVF */
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#define NV_PPWR_FALCON_CTXACK_SAVE_ACK_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_CTXACK_SAVE_ACK_CLEAR 0x00000000 /* -W--V */
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#define NV_PPWR_FALCON_CTXACK_REST_ACK 1:1 /* -WXVF */
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#define NV_PPWR_FALCON_CTXACK_REST_ACK_SET 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_CTXACK_REST_ACK_CLEAR 0x00000000 /* -W--V */
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#define NV_PPWR_FALCON_MAILBOX0 0x0010a040 /* RW-4R */
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#define NV_PPWR_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_MAILBOX1 0x0010a044 /* RW-4R */
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#define NV_PPWR_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_ITFEN 0x0010a048 /* RW-4R */
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#define NV_PPWR_FALCON_ITFEN__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_ITFEN__PRIV_LEVEL_MASK 0x0010a294 /* */
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#define NV_PPWR_FALCON_ITFEN_CTXEN 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_ITFEN_CTXEN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_ITFEN_CTXEN_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ITFEN_CTXEN_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ITFEN_MTHDEN 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_ITFEN_MTHDEN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_ITFEN_MTHDEN_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ITFEN_MTHDEN_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ITFEN_PRIV_POSTWR 2:2 /* RWIVF */
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#define NV_PPWR_FALCON_ITFEN_PRIV_POSTWR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_ITFEN_PRIV_POSTWR_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ITFEN_PRIV_POSTWR_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ITFEN_PRIV_SECWL_CPUCTL_ALIAS_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ITFEN_CTXSW_NACK 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_ITFEN_CTXSW_NACK_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ITFEN_CTXSW_NACK_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_ITFEN_HIRQ_NONSTALL_EDGE 12:12 /* R-IVF */
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#define NV_PPWR_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_ITFEN_HIRQ_NONSTALL_EDGE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IDLESTATE 0x0010a04c /* RW-4R */
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#define NV_PPWR_FALCON_IDLESTATE__DEVICE_MAP 0x00000013 /* */
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#define NV_PPWR_FALCON_IDLESTATE__PRIV_LEVEL_MASK 0x0010a1e0 /* */
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#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY 0:0 /* R--VF */
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#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_IDLESTATE_FALCON_BUSY_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY 15:1 /* R--VF */
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#define NV_PPWR_FALCON_IDLESTATE_ENGINE_BUSY_CYA 17:16 /* RWIVF */
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#define NV_PPWR_FALCON_IDLESTATE_ENGINE_BUSY_CYA_HW 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IDLESTATE_ENGINE_BUSY_CYA_RESERVED 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_BUSY 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_IDLESTATE_ENGINE_BUSY_CYA_SW_IDLE 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_IDLESTATE_RISCV_BUSY 20:20 /* R--VF */
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#define NV_PPWR_FALCON_IDLESTATE_RISCV_BUSY_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_IDLESTATE_RISCV_BUSY_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IDLESTATE_INT_BUSY_SHA 24:24 /* R-IVF */
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#define NV_PPWR_FALCON_IDLESTATE_INT_BUSY_SHA_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IDLESTATE_INT_BUSY_SHA_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_FHSTATE 0x0010a05c /* R--4R */
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#define NV_PPWR_FALCON_FHSTATE__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_FHSTATE__PRIV_LEVEL_MASK 0x0010a1e4 /* */
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#define NV_PPWR_FALCON_FHSTATE_FALCON_HALTED 0:0 /* R--VF */
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#define NV_PPWR_FALCON_FHSTATE_FALCON_HALTED_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_FHSTATE_FALCON_HALTED_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_FHSTATE_EXT_HALTED 15:1 /* R--VF */
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#define NV_PPWR_FALCON_FHSTATE_ENGINE_FAULTED 16:16 /* R--VF */
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#define NV_PPWR_FALCON_FHSTATE_ENGINE_FAULTED_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_FHSTATE_ENGINE_FAULTED_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_FHSTATE_STALL_REQ 17:17 /* R--VF */
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#define NV_PPWR_FALCON_FHSTATE_STALL_REQ_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_FHSTATE_STALL_REQ_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_FHSTATE_RISCV_HALTED 20:20 /* R--VF */
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#define NV_PPWR_FALCON_FHSTATE_RISCV_HALTED_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_FHSTATE_RISCV_HALTED_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_PRIVSTATE 0x0010a060 /* RW-4R */
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#define NV_PPWR_FALCON_PRIVSTATE__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_FALCON_PRIVSTATE__PRIV_LEVEL_MASK 0x0010a3d0 /* */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PRIVSTATE_PRIV_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SFTRESET 0x0010a07c /* RW-4R */
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#define NV_PPWR_FALCON_SFTRESET__DEVICE_MAP 0x00000013 /* */
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#define NV_PPWR_FALCON_SFTRESET__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_SFTRESET_EXT 0:0 /* RWXVF */
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#define NV_PPWR_FALCON_SFTRESET_EXT_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SFTRESET_EXT_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ENGCTL 0x0010a0a4 /* RW-4R */
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#define NV_PPWR_FALCON_ENGCTL__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_ENGCTL_INV_CONTEXT 0:0 /* RWXVF */
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#define NV_PPWR_FALCON_ENGCTL_INV_CONTEXT_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ENGCTL_INV_CONTEXT_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ENGCTL_SET_STALLREQ 1:1 /* RWXVF */
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#define NV_PPWR_FALCON_ENGCTL_SET_STALLREQ_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ENGCTL_SET_STALLREQ_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ENGCTL_CLR_STALLREQ 2:2 /* RWXVF */
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#define NV_PPWR_FALCON_ENGCTL_CLR_STALLREQ_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ENGCTL_CLR_STALLREQ_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ENGCTL_SWITCH_CONTEXT 3:3 /* RWXVF */
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#define NV_PPWR_FALCON_ENGCTL_SWITCH_CONTEXT_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ENGCTL_SWITCH_CONTEXT_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ENGCTL_STALLREQ 8:8 /* R-XVF */
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#define NV_PPWR_FALCON_ENGCTL_STALLREQ_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_ENGCTL_STALLREQ_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_ENGCTL_STALLACK 9:9 /* R-XVF */
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#define NV_PPWR_FALCON_ENGCTL_STALLACK_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_ENGCTL_STALLACK_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_ADDR 0x0010a0ac /* RW-4R */
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#define NV_PPWR_FALCON_ADDR__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_ADDR__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_ADDR_LSB 5:0 /* R-IVF */
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#define NV_PPWR_FALCON_ADDR_LSB_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_ADDR_MSB 11:6 /* RWIVF */
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#define NV_PPWR_FALCON_ADDR_MSB_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_ADDR_EXT 11:0 /* */
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#define NV_PPWR_FALCON_PRICFG 0x0010a0f8 /* R--4R */
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#define NV_PPWR_FALCON_PRICFG__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_PRICFG_ALL 31:0 /* R--VF */
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#define NV_PPWR_FALCON_DMACTL 0x0010a10c /* RW-4R */
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#define NV_PPWR_FALCON_DMACTL__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMACTL__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_DMACTL_REQUIRE_CTX 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMACTL_REQUIRE_CTX_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMACTL_REQUIRE_CTX_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMACTL_REQUIRE_CTX_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING 1:1 /* R--VF */
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#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMACTL_DMEM_SCRUBBING_DONE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING 2:2 /* R--VF */
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#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMACTL_IMEM_SCRUBBING_DONE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_DMACTL_SECURE_STAT 7:7 /* R--VF */
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#define NV_PPWR_FALCON_DMACTL_DCACHE_INVALIDATING 8:8 /* R--VF */
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#define NV_PPWR_FALCON_DMACTL_DCACHE_INVALIDATING_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMACTL_DCACHE_INVALIDATING_DONE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_DMACTL_ICACHE_INVALIDATING 9:9 /* R--VF */
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#define NV_PPWR_FALCON_DMACTL_ICACHE_INVALIDATING_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMACTL_ICACHE_INVALIDATING_DONE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_DMACTL_DMAQ_NUM 20:16 /* R--VF */
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#define NV_PPWR_FALCON_DMATRFBASE 0x0010a110 /* RW-4R */
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#define NV_PPWR_FALCON_DMATRFBASE__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMATRFBASE__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMATRFBASE_BASE 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMATRFBASE_BASE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMATRFMOFFS 0x0010a114 /* RW-4R */
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#define NV_PPWR_FALCON_DMATRFMOFFS__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMATRFMOFFS__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMATRFMOFFS_OFFS 23:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMATRFCMD 0x0010a118 /* RW-4R */
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#define NV_PPWR_FALCON_DMATRFCMD__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMATRFCMD__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMATRFCMD_FULL 0:0 /* R-XVF */
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#define NV_PPWR_FALCON_DMATRFCMD_FULL_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMATRFCMD_FULL_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_DMATRFCMD_IDLE 1:1 /* R-XVF */
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#define NV_PPWR_FALCON_DMATRFCMD_IDLE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMATRFCMD_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_DMATRFCMD_SEC 3:2 /* RWXVF */
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#define NV_PPWR_FALCON_DMATRFCMD_IMEM 4:4 /* RWXVF */
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#define NV_PPWR_FALCON_DMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_IMEM_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_WRITE 5:5 /* RWXVF */
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#define NV_PPWR_FALCON_DMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_WRITE_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_NOTIFY 6:6 /* RWXVF */
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#define NV_PPWR_FALCON_DMATRFCMD_NOTIFY_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_NOTIFY_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_SIZE 10:8 /* RWXVF */
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#define NV_PPWR_FALCON_DMATRFCMD_SIZE_4B 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_SIZE_8B 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_SIZE_16B 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_SIZE_32B 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_SIZE_64B 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_SIZE_128B 0x00000005 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_SIZE_256B 0x00000006 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_CTXDMA 14:12 /* RWXVF */
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#define NV_PPWR_FALCON_DMATRFCMD_SET_DMTAG 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_DMATRFCMD_SET_DMTAG_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMATRFCMD_SET_DMTAG_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_SET_DMTAG_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_ERROR 20:20 /* R-IVF */
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#define NV_PPWR_FALCON_DMATRFCMD_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMATRFCMD_ERROR_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_DMATRFCMD_LVL 26:24 /* RWXVF */
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#define NV_PPWR_FALCON_DMATRFCMD_SET_DMLVL 27:27 /* RWIVF */
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#define NV_PPWR_FALCON_DMATRFCMD_SET_DMLVL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMATRFCMD_SET_DMLVL_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFCMD_SET_DMLVL_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMATRFFBOFFS 0x0010a11c /* RW-4R */
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#define NV_PPWR_FALCON_DMATRFFBOFFS__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMATRFFBOFFS__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMATRFFBOFFS_OFFS 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMATRFFBOFFS_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMAPOLL_FB 0x0010a120 /* RW-4R */
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#define NV_PPWR_FALCON_DMAPOLL_FB__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMAPOLL_FB__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMAPOLL_FB_RCOUNT 31:24 /* R--VF */
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#define NV_PPWR_FALCON_DMAPOLL_FB_WCOUNT 23:16 /* R--VF */
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#define NV_PPWR_FALCON_DMAPOLL_FB_CFG_W_FENCE 5:5 /* RWIVF */
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#define NV_PPWR_FALCON_DMAPOLL_FB_CFG_W_FENCE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMAPOLL_FB_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMAPOLL_FB_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMAPOLL_FB_CFG_R_FENCE 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_DMAPOLL_FB_CFG_R_FENCE_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMAPOLL_FB_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMAPOLL_FB_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMAPOLL_FB_DMA_ACTIVE 1:1 /* R--VF */
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#define NV_PPWR_FALCON_DMAPOLL_FB_DMA_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMAPOLL_FB_DMA_ACTIVE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_DMAPOLL_FB_FENCE_ACTIVE 0:0 /* R--VF */
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#define NV_PPWR_FALCON_DMAPOLL_FB_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMAPOLL_FB_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_DMAPOLL_CP 0x0010a124 /* RW-4R */
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#define NV_PPWR_FALCON_DMAPOLL_CP__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMAPOLL_CP__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMAPOLL_CP_RCOUNT 31:24 /* R--VF */
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#define NV_PPWR_FALCON_DMAPOLL_CP_WCOUNT 23:16 /* R--VF */
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#define NV_PPWR_FALCON_DMAPOLL_CP_CFG_W_FENCE 5:5 /* RWIVF */
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#define NV_PPWR_FALCON_DMAPOLL_CP_CFG_W_FENCE_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMAPOLL_CP_CFG_W_FENCE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMAPOLL_CP_CFG_W_FENCE_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMAPOLL_CP_CFG_R_FENCE 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_DMAPOLL_CP_CFG_R_FENCE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMAPOLL_CP_CFG_R_FENCE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMAPOLL_CP_CFG_R_FENCE_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMAPOLL_CP_DMA_ACTIVE 1:1 /* R--VF */
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#define NV_PPWR_FALCON_DMAPOLL_CP_DMA_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMAPOLL_CP_DMA_ACTIVE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_DMAPOLL_CP_FENCE_ACTIVE 0:0 /* R--VF */
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#define NV_PPWR_FALCON_DMAPOLL_CP_FENCE_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMAPOLL_CP_FENCE_ACTIVE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_DMATRFBASE1 0x0010a128 /* RW-4R */
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#define NV_PPWR_FALCON_DMATRFBASE1__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMATRFBASE1__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMATRFBASE1_BASE 8:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMATRFBASE1_BASE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBRD_LOW 0x0010a2c0 /* R--4R */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBRD_LOW__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBRD_LOW__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBRD_LOW_VAL 31:0 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBRD_HIGH 0x0010a2c4 /* R--4R */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBRD_HIGH__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBRD_HIGH__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBRD_HIGH_VAL 30:0 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBRD_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBWR_LOW 0x0010a2c8 /* R--4R */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBWR_LOW__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBWR_LOW__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBWR_LOW_VAL 31:0 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBWR_HIGH 0x0010a2cc /* R--4R */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBWR_HIGH__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBWR_HIGH__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBWR_HIGH_VAL 30:0 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_FINISHED_FBWR_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBRD_LOW 0x0010a2d0 /* R--4R */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBRD_LOW__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBRD_LOW__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBRD_LOW_VAL 31:0 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBRD_HIGH 0x0010a2d4 /* R--4R */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBRD_HIGH__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBRD_HIGH__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBRD_HIGH_VAL 30:0 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBRD_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBWR_LOW 0x0010a2d8 /* R--4R */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBWR_LOW__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBWR_LOW__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBWR_LOW_VAL 31:0 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBWR_HIGH 0x0010a2dc /* R--4R */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBWR_HIGH__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBWR_HIGH__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBWR_HIGH_VAL 30:0 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_CURRENT_FBWR_HIGH_OBIT 31:31 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_CTL 0x0010a2e0 /* RW-4R */
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#define NV_PPWR_FALCON_DMAINFO_CTL__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMAINFO_CTL__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_DMAINFO_CTL_CLR_FBRD 0:0 /* -WXVF */
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#define NV_PPWR_FALCON_DMAINFO_CTL_CLR_FBRD_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_DMAINFO_CTL_CLR_FBRD_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_FALCON_DMAINFO_CTL_CLR_FBWR 1:1 /* -WXVF */
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#define NV_PPWR_FALCON_DMAINFO_CTL_CLR_FBWR_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_DMAINFO_CTL_CLR_FBWR_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION 2:2 /* RWXVF */
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#define NV_PPWR_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMAINFO_CTL_INTR_ERR_COMPLETION_CLR 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE 3:3 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_NORMAL 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_DMAINFO_CTL_INTR_ERR_DMATYPE_TAGGED 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD 4:4 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_DMAINFO_CTL_INTR_ERR_DMAREAD_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMAINFO_ERR_TAG_HIGH 0x0010a2e4 /* R--4R */
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#define NV_PPWR_FALCON_DMAINFO_ERR_TAG_HIGH__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMAINFO_ERR_TAG_HIGH__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMAINFO_ERR_TAG_HIGH_VAL 30:0 /* R--VF */
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#define NV_PPWR_FALCON_DMAINFO_ERR_TAG_LOW 0x0010a2e8 /* R--4R */
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#define NV_PPWR_FALCON_DMAINFO_ERR_TAG_LOW__DEVICE_MAP 0x00000005 /* */
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#define NV_PPWR_FALCON_DMAINFO_ERR_TAG_LOW__PRIV_LEVEL_MASK 0x0010a190 /* */
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#define NV_PPWR_FALCON_DMAINFO_ERR_TAG_LOW_VAL 31:0 /* R--VF */
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#define NV_PPWR_FALCON_IMEMC(i) (0x0010a180+(i)*16) /* RW-4A */
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#define NV_PPWR_FALCON_IMEMC__SIZE_1 1 /* */
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#define NV_PPWR_FALCON_IMEMC__DEVICE_MAP 0x00000006 /* */
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#define NV_PPWR_FALCON_IMEMC__PRIV_LEVEL_MASK NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */
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#define NV_PPWR_FALCON_IMEMC_OFFS 7:2 /* RWIVF */
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#define NV_PPWR_FALCON_IMEMC_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IMEMC_BLK 23:8 /* RWIVF */
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#define NV_PPWR_FALCON_IMEMC_BLK_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IMEMC_AINCW 24:24 /* RWIVF */
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#define NV_PPWR_FALCON_IMEMC_AINCW_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IMEMC_AINCW_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IMEMC_AINCW_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IMEMC_AINCR 25:25 /* RWIVF */
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#define NV_PPWR_FALCON_IMEMC_AINCR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IMEMC_AINCR_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IMEMC_AINCR_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IMEMC_SECURE 28:28 /* RWIVF */
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#define NV_PPWR_FALCON_IMEMC_SECURE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IMEMC_SEC_ATOMIC 29:29 /* R-IVF */
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#define NV_PPWR_FALCON_IMEMC_SEC_ATOMIC_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IMEMC_SEC_ATOMIC_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IMEMC_SEC_WR_VIO 30:30 /* R-IVF */
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#define NV_PPWR_FALCON_IMEMC_SEC_WR_VIO_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IMEMC_SEC_WR_VIO_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IMEMC_SEC_LOCK 31:31 /* R-IVF */
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#define NV_PPWR_FALCON_IMEMC_SEC_LOCK_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_IMEMC_SEC_LOCK_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IMEMD(i) (0x0010a184+(i)*16) /* RW-4A */
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#define NV_PPWR_FALCON_IMEMD__SIZE_1 1 /* */
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#define NV_PPWR_FALCON_IMEMD__DEVICE_MAP 0x00000006 /* */
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#define NV_PPWR_FALCON_IMEMD__PRIV_LEVEL_MASK NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */
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#define NV_PPWR_FALCON_IMEMD_DATA 31:0 /* RWXVF */
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#define NV_PPWR_FALCON_IMEMT(i) (0x0010a188+(i)*16) /* RW-4A */
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#define NV_PPWR_FALCON_IMEMT__SIZE_1 1 /* */
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#define NV_PPWR_FALCON_IMEMT__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IMEMT__PRIV_LEVEL_MASK NV_PPWR_FALCON_PMB_IMEM_PRIV_LEVEL_MASK /* */
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#define NV_PPWR_FALCON_IMEMT_TAG 15:0 /* RWXVF */
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#define NV_PPWR_FALCON_DMEMC(i) (0x0010a1c0+(i)*8) /* RW-4A */
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#define NV_PPWR_FALCON_DMEMC__SIZE_1 4 /* */
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#define NV_PPWR_FALCON_DMEMC__DEVICE_MAP 0x00000006 /* */
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#define NV_PPWR_FALCON_DMEMC__PRIV_LEVEL_MASK NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
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#define NV_PPWR_FALCON_DMEMC_ADDRESS 23:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMEMC_ADDRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMEMC_OFFS 7:2 /* */
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#define NV_PPWR_FALCON_DMEMC_OFFS_INIT 0 /* */
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#define NV_PPWR_FALCON_DMEMC_BLK 23:8 /* */
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#define NV_PPWR_FALCON_DMEMC_BLK_INIT 0 /* */
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#define NV_PPWR_FALCON_DMEMC_AINCW 24:24 /* RWIVF */
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#define NV_PPWR_FALCON_DMEMC_AINCW_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMEMC_AINCW_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMEMC_AINCW_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEMC_AINCR 25:25 /* RWIVF */
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#define NV_PPWR_FALCON_DMEMC_AINCR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMEMC_AINCR_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMEMC_AINCR_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEMC_SETTAG 26:26 /* RWIVF */
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#define NV_PPWR_FALCON_DMEMC_SETTAG_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMEMC_SETTAG_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMEMC_SETTAG_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEMC_SETLVL 27:27 /* RWIVF */
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#define NV_PPWR_FALCON_DMEMC_SETLVL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMEMC_SETLVL_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMEMC_SETLVL_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEMC_VA 28:28 /* RWIVF */
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#define NV_PPWR_FALCON_DMEMC_VA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMEMC_VA_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMEMC_VA_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEMC_MISS 29:29 /* R-IVF */
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#define NV_PPWR_FALCON_DMEMC_MISS_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMEMC_MISS_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_DMEMC_MULTIHIT 30:30 /* R-IVF */
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#define NV_PPWR_FALCON_DMEMC_MULTIHIT_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMEMC_MULTIHIT_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_DMEMC_LVLERR 31:31 /* R-IVF */
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#define NV_PPWR_FALCON_DMEMC_LVLERR_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_DMEMC_LVLERR_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_DMEMD(i) (0x0010a1c4+(i)*8) /* RW-4A */
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#define NV_PPWR_FALCON_DMEMD__SIZE_1 4 /* */
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#define NV_PPWR_FALCON_DMEMD__DEVICE_MAP 0x00000006 /* */
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#define NV_PPWR_FALCON_DMEMD__PRIV_LEVEL_MASK NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
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#define NV_PPWR_FALCON_DMEMD_DATA 31:0 /* RWXVF */
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#define NV_PPWR_FALCON_DMEMT(i) (0x0010a210+(i)*4) /* -W-4A */
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#define NV_PPWR_FALCON_DMEMT__SIZE_1 4 /* */
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#define NV_PPWR_FALCON_DMEMT__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_DMEMT__PRIV_LEVEL_MASK NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
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#define NV_PPWR_FALCON_DMEMT_TAG 15:0 /* -WXVF */
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#define NV_PPWR_FALCON_DMEML(i) (0x0010a2a0+(i)*4) /* -W-4A */
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#define NV_PPWR_FALCON_DMEML__SIZE_1 4 /* */
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#define NV_PPWR_FALCON_DMEML__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_DMEML__PRIV_LEVEL_MASK NV_PPWR_FALCON_PMB_DMEM_PRIV_LEVEL_MASK /* */
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#define NV_PPWR_FALCON_DMEML_LVL 2:0 /* -WXVF */
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#define NV_PPWR_FALCON_LOCKPMB 0x0010a170 /* RW-4R */
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#define NV_PPWR_FALCON_LOCKPMB__DEVICE_MAP 0x00000006 /* */
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#define NV_PPWR_FALCON_LOCKPMB_IMEM 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_LOCKPMB_IMEM_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_LOCKPMB_IMEM_LOCK 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_LOCKPMB_IMEM_UNLOCK 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_LOCKPMB_DMEM 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_LOCKPMB_DMEM_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_LOCKPMB_DMEM_LOCK 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_LOCKPMB_DMEM_UNLOCK 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_LOCKPMB_EXT2MEM 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_LOCKPMB_EXT2MEM_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_LOCKPMB_EXT2MEM_LOCK 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_LOCKPMB_EXT2MEM_UNLOCK 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE0 0x0010a174 /* RW-4R */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE0__DEVICE_MAP 0x00000006 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE0__PRIV_LEVEL_MASK 0x0010a1ac /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE0_START_BLOCK 15:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE0_START_BLOCK_INIT 0x0000ffff /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE0_END_BLOCK 31:16 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE0_END_BLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE1 0x0010a178 /* RW-4R */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE1__DEVICE_MAP 0x00000006 /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE1__PRIV_LEVEL_MASK 0x0010a1ac /* */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE1_START_BLOCK 15:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE1_START_BLOCK_INIT 0x0000ffff /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE1_END_BLOCK 31:16 /* RWIVF */
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#define NV_PPWR_FALCON_DMEM_PRIV_RANGE1_END_BLOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMEM_DUMMY 0x0010a258 /* R--4R */
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#define NV_PPWR_FALCON_DMEM_DUMMY__DEVICE_MAP 0x00000006 /* */
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#define NV_PPWR_FALCON_DMEM_DUMMY_DATA 31:0 /* R-IVF */
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#define NV_PPWR_FALCON_DMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_DMEM_DUMMY__PRIV_LEVEL_MASK 0x0010a284 /* */
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#define NV_PPWR_FALCON_IMEM_DUMMY 0x0010a1b4 /* R--4R */
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#define NV_PPWR_FALCON_IMEM_DUMMY__DEVICE_MAP 0x00000006 /* */
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#define NV_PPWR_FALCON_IMEM_DUMMY_DATA 31:0 /* R-IVF */
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#define NV_PPWR_FALCON_IMEM_DUMMY_DATA_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_IMEM_DUMMY__PRIV_LEVEL_MASK 0x0010a280 /* */
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#define NV_PPWR_FALCON_DIO_RESET_DELAY 0x0010a274 /* RW-4R */
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#define NV_PPWR_FALCON_DIO_RESET_DELAY__DEVICE_MAP 0x00000007 /* */
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#define NV_PPWR_FALCON_DIO_RESET_DELAY__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_DIO_RESET_DELAY_VALUE 15:0 /* RWIVF */
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#define NV_PPWR_FALCON_DIO_RESET_DELAY_VALUE_INIT 0x00000100 /* RWI-V */
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#define NV_PPWR_FALCON_DOC_CTRL 0x0010a340 /* RW-4R */
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#define NV_PPWR_FALCON_DOC_CTRL__DEVICE_MAP 0x00000007 /* */
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#define NV_PPWR_FALCON_DOC_CTRL__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_DOC_CTRL_COUNT 7:0 /* R--VF */
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#define NV_PPWR_FALCON_DOC_CTRL_RESET 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_DOC_CTRL_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DOC_CTRL_STOP 17:17 /* RWIVF */
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#define NV_PPWR_FALCON_DOC_CTRL_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DOC_CTRL_EMPTY 18:18 /* R-IVF */
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#define NV_PPWR_FALCON_DOC_CTRL_EMPTY_INIT 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_DOC_CTRL_WR_FINISHED 19:19 /* R-IVF */
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#define NV_PPWR_FALCON_DOC_CTRL_WR_FINISHED_INIT 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_DOC_CTRL_RD_FINISHED 20:20 /* R-IVF */
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#define NV_PPWR_FALCON_DOC_CTRL_RD_FINISHED_INIT 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_DOC_CTRL_WR_ERROR 21:21 /* RWIVF */
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#define NV_PPWR_FALCON_DOC_CTRL_WR_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DOC_CTRL_RD_ERROR 22:22 /* RWIVF */
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#define NV_PPWR_FALCON_DOC_CTRL_RD_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DOC_CTRL_PROTOCOL_ERROR 23:23 /* RWIVF */
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#define NV_PPWR_FALCON_DOC_CTRL_PROTOCOL_ERROR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DOC_D0 0x0010a344 /* RW-4R */
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#define NV_PPWR_FALCON_DOC_D0__DEVICE_MAP 0x00000007 /* */
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#define NV_PPWR_FALCON_DOC_D0__PRIV_LEVEL_MASK 0x0010a0ec /* */
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#define NV_PPWR_FALCON_DOC_D0_DATA 31:0 /* RW-VF */
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#define NV_PPWR_FALCON_DOC_D1 0x0010a348 /* RW-4R */
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#define NV_PPWR_FALCON_DOC_D1__DEVICE_MAP 0x00000007 /* */
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#define NV_PPWR_FALCON_DOC_D1__PRIV_LEVEL_MASK 0x0010a0ec /* */
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#define NV_PPWR_FALCON_DOC_D1_DATA 31:0 /* RW-VF */
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#define NV_PPWR_FALCON_DOC_D2 0x0010a34c /* RW-4R */
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#define NV_PPWR_FALCON_DOC_D2__DEVICE_MAP 0x00000007 /* */
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#define NV_PPWR_FALCON_DOC_D2__PRIV_LEVEL_MASK 0x0010a0ec /* */
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#define NV_PPWR_FALCON_DOC_D2_DATA 15:0 /* RW-VF */
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#define NV_PPWR_FALCON_DIC_CTRL 0x0010a350 /* RW-4R */
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#define NV_PPWR_FALCON_DIC_CTRL__DEVICE_MAP 0x00000007 /* */
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#define NV_PPWR_FALCON_DIC_CTRL__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_DIC_CTRL_COUNT 7:0 /* R--VF */
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#define NV_PPWR_FALCON_DIC_CTRL_RESET 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_DIC_CTRL_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DIC_CTRL_VALID 19:19 /* R-IVF */
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#define NV_PPWR_FALCON_DIC_CTRL_VALID_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_DIC_CTRL_POP 20:20 /* -W-VF */
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#define NV_PPWR_FALCON_DIC_D0 0x0010a354 /* RW-4R */
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#define NV_PPWR_FALCON_DIC_D0__DEVICE_MAP 0x00000007 /* */
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#define NV_PPWR_FALCON_DIC_D0__PRIV_LEVEL_MASK 0x0010a0ec /* */
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#define NV_PPWR_FALCON_DIC_D0_DATA 31:0 /* RW-VF */
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#define NV_PPWR_FALCON_DIC_D1 0x0010a358 /* RW-4R */
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#define NV_PPWR_FALCON_DIC_D1__DEVICE_MAP 0x00000007 /* */
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#define NV_PPWR_FALCON_DIC_D1__PRIV_LEVEL_MASK 0x0010a0ec /* */
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#define NV_PPWR_FALCON_DIC_D1_DATA 31:0 /* RW-VF */
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#define NV_PPWR_FALCON_DIC_D2 0x0010a35c /* RW-4R */
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#define NV_PPWR_FALCON_DIC_D2__DEVICE_MAP 0x00000007 /* */
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#define NV_PPWR_FALCON_DIC_D2__PRIV_LEVEL_MASK 0x0010a0ec /* */
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#define NV_PPWR_FALCON_DIC_D2_DATA 15:0 /* RW-VF */
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#define NV_PPWR_FALCON_DIO_ERR 0x0010a360 /* R--4R */
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#define NV_PPWR_FALCON_DIO_ERR__DEVICE_MAP 0x00000007 /* */
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#define NV_PPWR_FALCON_DIO_ERR__PRIV_LEVEL_MASK 0x0010a0ec /* */
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#define NV_PPWR_FALCON_DIO_ERR_INFO 31:0 /* R--VF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0(i) (0x0010a300+(i)*4) /* RW-4A */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0__SIZE_1 4 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0__DEVICE_MAP 0x00000014 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0__PRIV_LEVEL_MASK 0x0010a3f0 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_VAL 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_0_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1(i) (0x0010a310+(i)*4) /* RW-4A */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1__SIZE_1 4 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1__DEVICE_MAP 0x00000015 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1__PRIV_LEVEL_MASK 0x0010a3f4 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_VAL 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2(i) (0x0010a320+(i)*4) /* RW-4A */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2__SIZE_1 4 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2__DEVICE_MAP 0x00000016 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2__PRIV_LEVEL_MASK 0x0010a3f8 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_VAL 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3(i) (0x0010a330+(i)*4) /* RW-4A */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3__SIZE_1 4 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3__DEVICE_MAP 0x00000017 /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3__PRIV_LEVEL_MASK 0x0010a3fc /* */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_VAL 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_COMMON_SCRATCH_GROUP_3_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_PRGNVER 0x0010a3d4 /* R-I4R */
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#define NV_PPWR_FALCON_PRGNVER_MAJOR 3:0 /* R-IVF */
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#define NV_PPWR_FALCON_PRGNVER_MAJOR_DEFT 0x00000002 /* R-I-V */
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#define NV_PPWR_FALCON_PRGNVER_MINOR 17:4 /* R-IVF */
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#define NV_PPWR_FALCON_PRGNVER_MINOR_DEFT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_PRGNVER_BUGFIX 31:18 /* R-IVF */
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#define NV_PPWR_FALCON_PRGNVER_BUGFIX_DEFT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_HWCFG 0x0010a108 /* R--4R */
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#define NV_PPWR_FALCON_HWCFG_IMEM_SIZE 8:0 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG_FALCON_VIEWABLE_IMEM_SIZE 8:0 /* */
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#define NV_PPWR_FALCON_HWCFG_DMEM_SIZE 17:9 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG_FALCON_VIEWABLE_DMEM_SIZE 17:9 /* */
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#define NV_PPWR_FALCON_HWCFG_METHODFIFO_DEPTH 26:18 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG_DMAQUEUE_DEPTH 31:27 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG1 0x0010a12c /* R--4R */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV 3:0 /* R-IVF */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_INIT 0x00000006 /* R-I-V */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_1_0 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_2_0 0x00000002 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_3_0 0x00000003 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_4_0 0x00000004 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_5_0 0x00000005 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_6_0 0x00000006 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_7_0 0x00000007 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_SECURITY_MODEL 5:4 /* R-IVF */
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#define NV_PPWR_FALCON_HWCFG1_SECURITY_MODEL_INIT 0x00000003 /* R-I-V */
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#define NV_PPWR_FALCON_HWCFG1_SECURITY_MODEL_NONE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_SECURITY_MODEL_LIGHT 0x00000002 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_SECURITY_MODEL_HEAVY 0x00000003 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_SUBVERSION 7:6 /* R-IVF */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_SUBVERSION_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_SUBVERSION_0 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_SUBVERSION_1 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_SUBVERSION_2 0x00000002 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_CORE_REV_SUBVERSION_3 0x00000003 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_IMEM_PORTS 11:8 /* R-IVF */
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#define NV_PPWR_FALCON_HWCFG1_IMEM_PORTS_INIT 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_HWCFG1_DMEM_PORTS 15:12 /* R-IVF */
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#define NV_PPWR_FALCON_HWCFG1_DMEM_PORTS_INIT 0x00000004 /* R-I-V */
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#define NV_PPWR_FALCON_HWCFG1_TAG_WIDTH 20:16 /* R-IVF */
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#define NV_PPWR_FALCON_HWCFG1_TAG_WIDTH_INIT 0x00000010 /* R-I-V */
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#define NV_PPWR_FALCON_HWCFG1_DMEM_TAG_WIDTH 25:21 /* R-IVF */
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#define NV_PPWR_FALCON_HWCFG1_DMEM_TAG_WIDTH_INIT 0x00000010 /* R-I-V */
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#define NV_PPWR_FALCON_HWCFG1_DBG_PRIV_BUS 27:27 /* R-IVF */
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#define NV_PPWR_FALCON_HWCFG1_DBG_PRIV_BUS_INIT 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_HWCFG1_DBG_PRIV_BUS_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_DBG_PRIV_BUS_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_CSB_SIZE_16M 28:28 /* R-IVF */
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#define NV_PPWR_FALCON_HWCFG1_CSB_SIZE_16M_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_HWCFG1_CSB_SIZE_16M_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_CSB_SIZE_16M_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_PRIV_DIRECT 29:29 /* R-IVF */
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#define NV_PPWR_FALCON_HWCFG1_PRIV_DIRECT_INIT 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_HWCFG1_PRIV_DIRECT_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_PRIV_DIRECT_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_DMEM_APERTURES 30:30 /* R-IVF */
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#define NV_PPWR_FALCON_HWCFG1_DMEM_APERTURES_INIT 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_HWCFG1_DMEM_APERTURES_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_DMEM_APERTURES_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_IMEM_AUTOFILL 31:31 /* R-IVF */
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#define NV_PPWR_FALCON_HWCFG1_IMEM_AUTOFILL_INIT 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_HWCFG1_IMEM_AUTOFILL_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG1_IMEM_AUTOFILL_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2 0x0010a0f4 /* R--4R */
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#define NV_PPWR_FALCON_HWCFG2_SHA 0:0 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_SHA_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_SHA_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_BMEM 1:1 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_BMEM_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_BMEM_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_PKCBOOT 2:2 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_PKCBOOT_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_PKCBOOT_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_DBGMODE 3:3 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_DBGMODE_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_DBGMODE_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_KMEM 4:4 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_KMEM_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_KMEM_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_HSCODE_REVOCATION 5:5 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_HSCODE_REVOCATION_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_HSCODE_REVOCATION_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_STRAP_FUN 6:6 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_STRAP_FUN_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_STRAP_FUN_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_VHR 7:7 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_VHR_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_VHR_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_HS 8:8 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_HS_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_HS_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_SECUREBUS 9:9 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_SECUREBUS_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_SECUREBUS_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_RISCV 10:10 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_RISCV_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_RISCV_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_RISCV_PL3_DISABLE 11:11 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_RISCV_PL3_DISABLE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_RISCV_PL3_DISABLE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_MEM_SCRUBBING 12:12 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_MEM_SCRUBBING_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_MEM_SCRUBBING_DONE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_BOOT_FROM_HS 14:14 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG2_BOOT_FROM_HS_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_HWCFG2_BOOT_FROM_HS_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_HWCFG3 0x0010a278 /* R--4R */
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#define NV_PPWR_FALCON_HWCFG3_IMEM_TOTAL_SIZE 11:0 /* R--VF */
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#define NV_PPWR_FALCON_HWCFG3_DMEM_TOTAL_SIZE 27:16 /* R--VF */
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#define NV_PPWR_FALCON_CGCTL 0x0010a0a0 /* RW-4R */
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#define NV_PPWR_FALCON_CGCTL__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_FALCON_CGCTL_CG_OVERRIDE 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_CGCTL_CG_OVERRIDE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_CG2 0x0010a134 /* RWI4R */
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#define NV_PPWR_FALCON_CG2__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_FALCON_CG2__PRIV_LEVEL_MASK 0x0010a1e8 /* */
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#define NV_PPWR_FALCON_CG2_SLCG 17:1 /* */
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#define NV_PPWR_FALCON_CG2_SLCG_ENABLED 0 /* */
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#define NV_PPWR_FALCON_CG2_SLCG_DISABLED 0x1FFFF /* */
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#define NV_PPWR_FALCON_CG2_SLCG__PROD 0x000A0 /* */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_DMA 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_DMA_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_DMA_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM 2:2 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_GC6_SR_FSM_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_PIPE 3:3 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_PIPE_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_PIPE_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_DIV 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_DIV_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_DIV_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_ICD 5:5 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_ICD_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_ICD_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_CFG 6:6 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_CFG_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_CFG_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_CTXSW 7:7 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_CTXSW_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_CTXSW_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_PMB 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_PMB_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_PMB_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_RF 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_RF_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_RF_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_MUL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_MUL_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_MUL_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_LDST 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_LDST_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_LDST_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_TSYNC 12:12 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_TSYNC_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_TSYNC_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_GPTMR 13:13 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_GPTMR_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_GPTMR_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_WDTMR 14:14 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_WDTMR_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_WDTMR_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_IRQSTAT 15:15 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_IRQSTAT_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_IRQSTAT_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_TOP 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_TOP_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_TOP_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FBIF 17:17 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FBIF_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FBIF_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_SHA 18:18 /* RWIVF */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_SHA__PROD 1 /* */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_SHA_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CG2_SLCG_FALCON_SHA_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_ENGID 0x0010a13c /* R--4R */
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#define NV_PPWR_FALCON_ENGID_INSTID 7:0 /* R-IVF */
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#define NV_PPWR_FALCON_ENGID_INSTID_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID 15:8 /* R--VF */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_SEC 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_DPU 0x00000002 /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_NVDEC 0x00000003 /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_PWR_PMU 0x00000004 /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_FBFACLON 0x00000005 /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_NVENC 0x00000006 /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_GPCCS 0x00000007 /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_FECS 0x00000008 /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_MINION 0x00000009 /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_XUSB 0x0000000a /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_GSP 0x0000000b /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_NVJPG 0x0000000c /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_OFA 0x0000000d /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_PSC 0x0000000e /* R---V */
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#define NV_PPWR_FALCON_ENGID_FAMILYID_SOE 0x0000000f /* R---V */
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#define NV_PPWR_FALCON_ENGINE 0x0010a3c0 /* RW-4R */
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#define NV_PPWR_FALCON_ENGINE__PRIV_LEVEL_MASK 0x0010a3c4 /* */
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#define NV_PPWR_FALCON_ENGINE_RESET 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_ENGINE_RESET_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ENGINE_RESET_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SCTL 0x0010a240 /* RW-4R */
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#define NV_PPWR_FALCON_SCTL__DEVICE_MAP 0x00000013 /* */
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#define NV_PPWR_FALCON_SCTL__PRIV_LEVEL_MASK 0x0010a298 /* */
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#define NV_PPWR_FALCON_SCTL_LSMODE 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL_LSMODE_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SCTL_LSMODE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SCTL_HSMODE 1:1 /* R--VF */
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#define NV_PPWR_FALCON_SCTL_HSMODE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_SCTL_HSMODE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_SCTL_LSMODE_LEVEL 5:4 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL_LSMODE_LEVEL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SCTL_UCODE_LEVEL 5:4 /* */
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#define NV_PPWR_FALCON_SCTL_UCODE_LEVEL_INIT 0 /* */
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#define NV_PPWR_FALCON_SCTL_DEBUG_PRIV_LEVEL 9:8 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL_DEBUG_PRIV_LEVEL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SCTL_RESET_LVLM_EN 12:12 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL_RESET_LVLM_EN_TRUE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SCTL_RESET_LVLM_EN_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SCTL_STALLREQ_CLR_EN 13:13 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL_STALLREQ_CLR_EN_TRUE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SCTL_STALLREQ_CLR_EN_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SCTL_AUTH_EN 14:14 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL_AUTH_EN_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SCTL_AUTH_EN_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SCTL1 0x0010a250 /* RW-4R */
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#define NV_PPWR_FALCON_SCTL1__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_SCTL1__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_SCTL1_CSBLVL_MASK 1:0 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL1_CSBLVL_MASK_INIT 0x00000003 /* RWI-V */
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#define NV_PPWR_FALCON_SCTL1_EXTLVL_MASK 3:2 /* RWIVF */
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#define NV_PPWR_FALCON_SCTL1_EXTLVL_MASK_INIT 0x00000003 /* RWI-V */
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#define NV_PPWR_FALCON_HSCTL 0x0010a0e4 /* RW-4R */
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#define NV_PPWR_FALCON_HSCTL__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_HSCTL__PRIV_LEVEL_MASK 0x0010a0e8 /* */
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#define NV_PPWR_FALCON_HSCTL_TRACEPC 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_HSCTL_TRACEPC_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_HSCTL_TRACEPC_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_HSCTL_SP_MIN 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_HSCTL_SP_MIN_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_HSCTL_SP_MIN_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SAFETY_CTRL 0x0010a2f4 /* RW-4R */
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#define NV_PPWR_FALCON_SAFETY_CTRL__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL__PRIV_LEVEL_MASK 0x0010a1b0 /* */
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#define NV_PPWR_FALCON_SAFETY_CTRL_FUSE_OPT_RISCV_DCLS_EN 17:17 /* R-IVF */
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#define NV_PPWR_FALCON_SAFETY_CTRL_FUSE_OPT_RISCV_DCLS_EN_INIT 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_CLK_EN 11:10 /* RWIVF */
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#define NV_PPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_CLK_EN_TRUE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_CLK_EN_FALSE 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_DIS 7:6 /* RWIVF */
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#define NV_PPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_DIS_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_DIS_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SAFETY_CTRL_RISCV_DCLS_DIS_FALSE 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY 0x0010a3b8 /* RW-4R */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY__PRIV_LEVEL_MASK 0x0010a1b0 /* */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY_CORE_MISMATCH 31:24 /* RWIVF */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY_CORE_MISMATCH_TRUE 0x000000a5 /* RW--V */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY_CORE_MISMATCH_FALSE 0x0000005a /* RWI-V */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_HALT 23:16 /* RW-VF */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_HALT_ENABLED 0x000000a5 /* RW--V */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_HALT_DISABLED 0x0000005a /* RW--V */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_TRIGGER_RESET 15:8 /* RW-VF */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_TRIGGER_RESET_ENABLED 0x000000a5 /* RW--V */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_TRIGGER_RESET_DISABLED 0x0000005a /* RW--V */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_INTERRUPT 7:0 /* RW-VF */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_INTERRUPT_ENABLED 0x000000a5 /* RW--V */
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#define NV_PPWR_FALCON_RISCV_DCLS_SECURITY_RISCV_INTERRUPT_DISABLED 0x0000005a /* RW--V */
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#define NV_PPWR_FALCON_OS 0x0010a080 /* RW-4R */
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#define NV_PPWR_FALCON_OS__DEVICE_MAP 0x00000013 /* */
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#define NV_PPWR_FALCON_OS_VERSION 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_OS_VERSION_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_RM 0x0010a084 /* RW-4R */
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#define NV_PPWR_FALCON_RM__DEVICE_MAP 0x00000013 /* */
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#define NV_PPWR_FALCON_RM_CONFIG 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_RM_CONFIG_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SOFT_PM 0x0010a088 /* RW-4R */
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#define NV_PPWR_FALCON_SOFT_PM__DEVICE_MAP 0x00000013 /* */
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#define NV_PPWR_FALCON_SOFT_PM__PRIV_LEVEL_MASK 0x0010a1ec /* */
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#define NV_PPWR_FALCON_SOFT_PM_TRIGGER_START 17:17 /* RWIVF */
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#define NV_PPWR_FALCON_SOFT_PM_TRIGGER_START_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SOFT_PM_TRIGGER_END 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_SOFT_PM_TRIGGER_END_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SOFT_PM_PROBE 5:0 /* RWIVF */
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#define NV_PPWR_FALCON_SOFT_PM_PROBE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SOFT_MODE 0x0010a08c /* RW-4R */
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#define NV_PPWR_FALCON_SOFT_MODE__DEVICE_MAP 0x00000013 /* */
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#define NV_PPWR_FALCON_SOFT_MODE__PRIV_LEVEL_MASK 0x0010a1ec /* */
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#define NV_PPWR_FALCON_SOFT_MODE_PROBE 5:0 /* RWIVF */
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#define NV_PPWR_FALCON_SOFT_MODE_PROBE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_PMM 0x0010a0a8 /* RW-4R */
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#define NV_PPWR_FALCON_PMM__DEVICE_MAP 0x00000013 /* */
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#define NV_PPWR_FALCON_PMM__PRIV_LEVEL_MASK 0x0010a1ec /* */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL 4:0 /* RWIVF */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_ANY 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_CODE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_DMAQ 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_DMFENCE 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_DMWAIT 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_IMWAIT 0x00000005 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_IPND 0x00000006 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_LDSTQ 0x00000007 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_SB 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_ANY_SC 0x00000009 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_CODE_SC 0x0000000a /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_DMAQ_SC 0x0000000b /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_DMFENCE_SC 0x0000000c /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_DMWAIT_SC 0x0000000d /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_IMWAIT_SC 0x0000000e /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_IPND_SC 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_LDSTQ_SC 0x00000010 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_STALL_SEL_SB_SC 0x00000011 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_IDLE_SEL 7:5 /* RWIVF */
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#define NV_PPWR_FALCON_PMM_FALCON_IDLE_SEL_WAITING 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_IDLE_SEL_WAITING_SC 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_IDLE_SEL_ENG_IDLE_SC 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_IDLE_SEL_MTHD_FULL_SC 0x00000005 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM0_SEL 11:8 /* RWIVF */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_0 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_2 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_3 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_4 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_5 0x00000005 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_0_SC 0x00000006 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_1_SC 0x00000007 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_2_SC 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_3_SC 0x00000009 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_4_SC 0x0000000a /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM0_SEL_5_SC 0x0000000b /* RW--V */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM1_SEL 15:12 /* RWIVF */
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#define NV_PPWR_FALCON_PMM_FALCON_SOFTPM1_SEL_0 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_PMM_FBIF_DSTAT_SEL 19:17 /* RWIVF */
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#define NV_PPWR_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_PMM_FBIF_DSTAT_SEL_RREQ 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_DSTAT_SEL_WREQ 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_DSTAT_SEL_1KTRANSFER_SC 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_DSTAT_SEL_RREQ_SC 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_DSTAT_SEL_WREQ_SC 0x00000005 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL 23:20 /* RWIVF */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC 0x00000005 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY 0x00000006 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_ORQ 0x00000007 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_RDAT_WAIT_SC 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_RDM_CLIENT_SC 0x00000009 /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_WDF_FULL_SC 0x0000000a /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_RQQ_FULL_SC 0x0000000b /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_RDM_PORTQ_SC 0x0000000c /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_RDM_ALLOC_SC 0x0000000d /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_FB_BSY_SC 0x0000000e /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL0_SEL_ORQ_SC 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL1_SEL 27:24 /* RWIVF */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL1_SEL_RDAT_WAIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL2_SEL 31:28 /* RWIVF */
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#define NV_PPWR_FALCON_PMM_FBIF_STALL2_SEL_RDAT_WAIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DEBUG1 0x0010a090 /* RW-4R */
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#define NV_PPWR_FALCON_DEBUG1__DEVICE_MAP 0x00000004 /* */
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#define NV_PPWR_FALCON_DEBUG1__PRIV_LEVEL_MASK 0x0010a294 /* */
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#define NV_PPWR_FALCON_DEBUG1_MTHD_DRAIN_TIME 15:0 /* RWIVF */
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#define NV_PPWR_FALCON_DEBUG1_MTHD_DRAIN_TIME_INIT 0x00000040 /* RWI-V */
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#define NV_PPWR_FALCON_DEBUG1_CTXSW_MODE 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_DEBUG1_CTXSW_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DEBUG1_TRACE_FORMAT 17:17 /* RWIVF */
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#define NV_PPWR_FALCON_DEBUG1_TRACE_FORMAT_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DEBUG1_TRACE_FORMAT_UNCOMPRESSED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DEBUG1_TRACE_FORMAT_COMPRESSED 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DEBUG1_CTXSW_MODE1 18:18 /* RWIVF */
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#define NV_PPWR_FALCON_DEBUG1_CTXSW_MODE1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DEBUG1_CTXSW_MODE1_BYPASS_IDLE_CHECKS 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DEBUG1_CTXSW_MODE1_DEFAULT 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DEBUGINFO 0x0010a094 /* RW-4R */
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#define NV_PPWR_FALCON_DEBUGINFO__DEVICE_MAP 0x00000013 /* */
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#define NV_PPWR_FALCON_DEBUGINFO_DATA 31:0 /* RWXVF */
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#define NV_PPWR_FALCON_SP_MIN 0x0010a270 /* RW-4R */
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#define NV_PPWR_FALCON_SP_MIN__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_SP_MIN__PRIV_LEVEL_MASK 0x0010a1f0 /* */
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#define NV_PPWR_FALCON_SP_MIN_VALUE 23:0 /* RWIVF */
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#define NV_PPWR_FALCON_SP_MIN_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_EXCI 0x0010a0d0 /* R--4R */
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#define NV_PPWR_FALCON_EXCI__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_EXCI__PRIV_LEVEL_MASK 0x0010a1f4 /* */
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#define NV_PPWR_FALCON_EXCI_EXPC 19:0 /* R-XVF */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE 24:20 /* R-XVF */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_TRAP0 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_TRAP1 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_TRAP2 0x00000002 /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_TRAP3 0x00000003 /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_ILL_INS 0x00000008 /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_INV_INS 0x00000009 /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_MISS_INS 0x0000000a /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_DHIT_INS 0x0000000b /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_SP_OVERFLOW 0x0000000d /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_BRKPT_INS 0x0000000f /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_DMEM_MISS_INS 0x00000010 /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_DMEM_DHIT_INS 0x00000011 /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_DMEM_PAFAULT_INS 0x00000012 /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_DMEM_PERMISSION_INS 0x00000013 /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_BROM_CALL_INS 0x00000015 /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_KMEM_VIOLATION_INS 0x00000016 /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXCAUSE_BMEM_PERMISSION_INS 0x00000017 /* R---V */
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#define NV_PPWR_FALCON_EXCI_EXPC_HIGH 31:28 /* R-XVF */
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#define NV_PPWR_FALCON_EXCI2 0x0010a0bc /* R--4R */
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#define NV_PPWR_FALCON_EXCI2__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_EXCI2__PRIV_LEVEL_MASK 0x0010a1f4 /* */
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#define NV_PPWR_FALCON_EXCI2_ADDRESS 31:0 /* R-IVF */
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#define NV_PPWR_FALCON_EXCI2_ADDRESS_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SVEC_SPR 0x0010a0d4 /* R--4R */
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#define NV_PPWR_FALCON_SVEC_SPR__DEVICE_MAP 0x00000010 /* */
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#define NV_PPWR_FALCON_SVEC_SPR__PRIV_LEVEL_MASK 0x0010a1f8 /* */
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#define NV_PPWR_FALCON_SVEC_SPR_SIGPASS 18:18 /* R-XVF */
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#define NV_PPWR_FALCON_SVEC_SPR_SIGPASS_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_SVEC_SPR_SIGPASS_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_CPUCTL 0x0010a100 /* RW-4R */
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#define NV_PPWR_FALCON_CPUCTL__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_CPUCTL__PRIV_LEVEL_MASK 0x0010a288 /* */
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#define NV_PPWR_FALCON_CPUCTL_IINVAL 0:0 /* -WXVF */
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#define NV_PPWR_FALCON_CPUCTL_IINVAL_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_CPUCTL_IINVAL_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_FALCON_CPUCTL_STARTCPU 1:1 /* -WXVF */
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#define NV_PPWR_FALCON_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_CPUCTL_STARTCPU_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_FALCON_CPUCTL_SRESET 2:2 /* -WXVF */
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#define NV_PPWR_FALCON_CPUCTL_SRESET_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_CPUCTL_SRESET_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_FALCON_CPUCTL_HRESET 3:3 /* -WXVF */
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#define NV_PPWR_FALCON_CPUCTL_HRESET_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_CPUCTL_HRESET_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_FALCON_CPUCTL_HALTED 4:4 /* R-XVF */
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#define NV_PPWR_FALCON_CPUCTL_HALTED_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_CPUCTL_HALTED_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_CPUCTL_STOPPED 5:5 /* R-XVF */
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#define NV_PPWR_FALCON_CPUCTL_STOPPED_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_CPUCTL_STOPPED_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_CPUCTL_ALIAS_EN 6:6 /* RWIVF */
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#define NV_PPWR_FALCON_CPUCTL_ALIAS_EN_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_CPUCTL_ALIAS_EN_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CPUCTL_ALIAS_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_CPUCTL_ALIAS 0x0010a130 /* -W-4R */
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#define NV_PPWR_FALCON_CPUCTL_ALIAS__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_CPUCTL_ALIAS_STARTCPU 1:1 /* -WXVF */
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#define NV_PPWR_FALCON_CPUCTL_ALIAS_STARTCPU_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_FALCON_CPUCTL_ALIAS_STARTCPU_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_FALCON_STACKCFG 0x0010a138 /* RW-4R */
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#define NV_PPWR_FALCON_STACKCFG__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_STACKCFG__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_STACKCFG_BOTTOM 23:0 /* RWXVF */
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#define NV_PPWR_FALCON_STACKCFG_BOTTOM_INIT 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_STACKCFG_SPEXC 31:31 /* RWIVF */
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#define NV_PPWR_FALCON_STACKCFG_SPEXC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_STACKCFG_SPEXC_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_STACKCFG_SPEXC_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_BOOTVEC 0x0010a104 /* RW-4R */
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#define NV_PPWR_FALCON_BOOTVEC__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_BOOTVEC__PRIV_LEVEL_MASK 0x0010a194 /* */
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#define NV_PPWR_FALCON_BOOTVEC_VEC 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_BOOTVEC_VEC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL 0x0010a254 /* RW-4R */
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#define NV_PPWR_FALCON_DBGCTL__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_FALCON_DBGCTL__PRIV_LEVEL_MASK 0x0010a1a8 /* */
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#define NV_PPWR_FALCON_DBGCTL_VAL 9:0 /* */
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#define NV_PPWR_FALCON_DBGCTL_VAL_INIT 0 /* */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_STOP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RUN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RUNB 2:2 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RUNB_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RUNB_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RUNB_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_STEP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_EMASK 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_EMASK_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR 5:5 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_SPR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RSTAT 6:6 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RSTAT_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIVWL_IBRKPT 7:7 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_PRIVWL_IBRKPT_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_PRIVWL_IBRKPT_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_PRIVWL_IBRKPT_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RREG_GPR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RDM 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RDM_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_TRACE_MODE 13:12 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_TRACE_MODE_FULL 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_TRACE_MODE_REDUCED 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_TRACE_MODE_STACK 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_DBGCTL_CYA 31:16 /* RWIVF */
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#define NV_PPWR_FALCON_DBGCTL_CYA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DBGCTL_CYA_ENABLE 0x00008afe /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT1 0x0010a098 /* RW-4R */
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#define NV_PPWR_FALCON_IBRKPT1__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IBRKPT1__PRIV_LEVEL_MASK 0x0010a1fc /* */
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#define NV_PPWR_FALCON_IBRKPT1_PC 23:0 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT1_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT1_SUPPRESS 29:29 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT1_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT1_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT1_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT1_SKIP 30:30 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT1_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT1_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT1_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT1_EN 31:31 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT1_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT1_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT1_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT2 0x0010a09c /* RW-4R */
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#define NV_PPWR_FALCON_IBRKPT2__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IBRKPT2__PRIV_LEVEL_MASK 0x0010a1fc /* */
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#define NV_PPWR_FALCON_IBRKPT2_PC 23:0 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT2_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT2_SUPPRESS 29:29 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT2_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT2_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT2_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT2_SKIP 30:30 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT2_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT2_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT2_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT2_EN 31:31 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT2_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT2_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT2_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT3 0x0010a0b0 /* RW-4R */
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#define NV_PPWR_FALCON_IBRKPT3__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IBRKPT3__PRIV_LEVEL_MASK 0x0010a1fc /* */
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#define NV_PPWR_FALCON_IBRKPT3_PC 23:0 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT3_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT3_SUPPRESS 29:29 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT3_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT3_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT3_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT3_SKIP 30:30 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT3_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT3_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT3_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT3_EN 31:31 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT3_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT3_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT3_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT4 0x0010a0b4 /* RW-4R */
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#define NV_PPWR_FALCON_IBRKPT4__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IBRKPT4__PRIV_LEVEL_MASK 0x0010a1fc /* */
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#define NV_PPWR_FALCON_IBRKPT4_PC 23:0 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT4_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT4_SUPPRESS 29:29 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT4_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT4_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT4_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT4_SKIP 30:30 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT4_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT4_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT4_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT4_EN 31:31 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT4_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT4_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT4_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT5 0x0010a0b8 /* RW-4R */
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#define NV_PPWR_FALCON_IBRKPT5__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IBRKPT5__PRIV_LEVEL_MASK 0x0010a1fc /* */
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#define NV_PPWR_FALCON_IBRKPT5_PC 23:0 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT5_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT5_SUPPRESS 29:29 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT5_SUPPRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT5_SUPPRESS_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT5_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT5_SKIP 30:30 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT5_SKIP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT5_SKIP_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT5_SKIP_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT5_EN 31:31 /* RWIVF */
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#define NV_PPWR_FALCON_IBRKPT5_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IBRKPT5_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IBRKPT5_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD 0x0010a200 /* RW-4R */
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#define NV_PPWR_FALCON_ICD_CMD__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_ICD_CMD__PRIV_LEVEL_MASK 0x0010a220 /* */
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#define NV_PPWR_FALCON_ICD_CMD_OPC 3:0 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_STOP 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_RUN 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_JRUN 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_RUNB 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_JRUNB 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_STEP 0x00000005 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_JSTEP 0x00000006 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_EMASK 0x00000007 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_WREG 0x00000009 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_WDM 0x0000000b /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_RCM 0x0000000c /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_WCM 0x0000000d /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_OPC_SBU 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_SZ 7:6 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_SZ_B 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_SZ_HW 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_SZ_W 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX 12:8 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG2 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG3 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG4 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG5 0x00000005 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG6 0x00000006 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG7 0x00000007 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG8 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG9 0x00000009 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG10 0x0000000a /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG11 0x0000000b /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG12 0x0000000c /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG13 0x0000000d /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG14 0x0000000e /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_REG15 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_IV0 0x00000010 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_IV1 0x00000011 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_EV 0x00000013 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_SP 0x00000014 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_PC 0x00000015 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_IMB 0x00000016 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_DMB 0x00000017 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_CSW 0x00000018 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_CCR 0x00000019 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_SEC 0x0000001a /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_CTX 0x0000001b /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_EXCI 0x0000001c /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_SEC1 0x0000001e /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_IMB1 0x0000001e /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_DMB1 0x0000001f /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_RSTAT0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_RSTAT1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_RSTAT2 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_RSTAT3 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_RSTAT4 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_RSTAT5 0x00000005 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_WB0 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_WB1 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_WB2 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_IDX_WB3 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_ERROR 14:14 /* R--VF */
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#define NV_PPWR_FALCON_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_ICD_CMD_ERROR_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_ICD_CMD_RDVLD 15:15 /* R--VF */
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#define NV_PPWR_FALCON_ICD_CMD_RDVLD_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_ICD_CMD_RDVLD_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_ICD_CMD_PARM 31:16 /* */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK 31:16 /* */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_TRAP0 16:16 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_TRAP0_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_TRAP0_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_TRAP1 17:17 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_TRAP1_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_TRAP1_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_TRAP2 18:18 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_TRAP2_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_TRAP2_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_TRAP3 19:19 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_TRAP3_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_TRAP3_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_EXC_UNIMP 20:20 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_EXC_UNIMP_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_EXC_UNIMP_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_EXC_IMISS 21:21 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_EXC_IMISS_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_EXC_IMISS_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_EXC_IMHIT 22:22 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_EXC_IMHIT_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_EXC_IMHIT_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_EXC_IBREAK 23:23 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_EXC_IBREAK_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_EXC_IBREAK_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_IV0 24:24 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_IV0_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_IV0_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_IV1 25:25 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_IV1_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_IV1_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_IV2 26:26 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_IV2_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_IV2_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_ICD_CMD_EMASK_EXT 31:27 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_ADDR 0x0010a204 /* RW-4R */
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#define NV_PPWR_FALCON_ICD_ADDR__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_ICD_ADDR__PRIV_LEVEL_MASK 0x0010a220 /* */
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#define NV_PPWR_FALCON_ICD_ADDR_ADDR 31:0 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_WDATA 0x0010a208 /* RW-4R */
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#define NV_PPWR_FALCON_ICD_WDATA__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_ICD_WDATA__PRIV_LEVEL_MASK 0x0010a220 /* */
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#define NV_PPWR_FALCON_ICD_WDATA_DATA 31:0 /* RWXVF */
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#define NV_PPWR_FALCON_ICD_RDATA 0x0010a20c /* R--4R */
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#define NV_PPWR_FALCON_ICD_RDATA__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_ICD_RDATA__PRIV_LEVEL_MASK 0x0010a220 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_DATA 31:0 /* R--VF */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_MEM_STALL 0:0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_MEM_STALL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL 1:1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL 2:2 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_FENCE_STALL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DIV_STALL 3:3 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DIV_STALL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ 4:4 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMAQ_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING 5:5 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_DMWAITING_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING 6:6 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_DMA_STALL_IMWAITING_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_ANY_STALL 7:7 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_ANY_STALL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL 8:8 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_SBFULL_STALL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL 9:9 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_SBHIT_STALL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL 10:10 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_FLOW_STALL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_SP_STALL 11:11 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_SP_STALL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_SP_STALL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_BL_STALL 12:12 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_BL_STALL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_BL_STALL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_IPND_STALL 13:13 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_IPND_STALL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL 14:14 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_LDSTQ_STALL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL 16:16 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_NOINSTR_STALL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH 20:20 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_HALTSTOP_FLUSH_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH 21:21 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_AFILL_FLUSH_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH 22:22 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_EXC_FLUSH_FASLE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_IRQ_FLUSH 25:23 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_VALIDRD 28:28 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_VALIDRD_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_VALIDRD_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_WAITING 29:29 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_WAITING_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_WAITING_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_HALTED 30:30 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_HALTED_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_HALTED_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL 31:31 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT0_MTHD_FULL_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB_ALLOC 3:0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB_VALID 7:4 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB0_SZ 9:8 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_BYTE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_HALFWORD 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB0_SZ_IS_WORD 2 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB1_SZ 11:10 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_BYTE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_HALFWORD 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB1_SZ_IS_WORD 2 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB2_SZ 13:12 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_BYTE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_HALFWORD 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB2_SZ_IS_WORD 2 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB3_SZ 15:14 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_BYTE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_HALFWORD 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB3_SZ_IS_WORD 2 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB0_IDX 19:16 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB1_IDX 23:20 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB2_IDX 27:24 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT1_WB3_IDX 31:28 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT2_DMA_ENABLE 4:4 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT2_LDSTQ_NUM 7:5 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT2_DMAQ_NUM 12:8 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT2_EM_BUSY 19:16 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT2_EM_ACKED 23:20 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT2_EM_ISWR 27:24 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT2_EM_DVLD 31:28 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE 0:0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_MTHD_IDLE_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE 1:1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_IDLE_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE 2:2 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_IDLE_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE 3:3 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_SCP_IDLE_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE 4:4 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_LDST_IDLE_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY 5:5 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_SBWB_EMPTY_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CSWIE 8:6 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CSWE 10:10 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE 14:12 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_IDLE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_CHECK 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE 2 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_SAVE_WAIT 3 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_BLK_BIND 4 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESET 5 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_RESETWAIT 6 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_STATE_SM_ACK 7 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND 15:15 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_CTXSW_PEND_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE 17:17 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_FBREQ_IDLE_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_ACKQ_EMPTY_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY 19:19 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_RDQ_EMPTY_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY 20:20 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_WR_BUSY_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY 21:21 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_DMA_RD_BUSY_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY 22:22 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BUSY_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK 23:23 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_LDST_XT_BLOCK_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE 24:24 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT3_ENG_IDLE_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_STATE 1:0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_NORMAL 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_ISSUE_CLEAR 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_WAIT_EXLDQ_CLEAR 2 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_STATE_FULL_DBG_MODE 3 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_MODE 3:2 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_SUPPRESSICD 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_IBRK 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_MODE_ENTERICD_STEP 2 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK 31:16 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0 16:16 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP0_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1 17:17 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP1_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2 18:18 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP2_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3 19:19 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_TRAP3_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP 20:20 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_UNIMP_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS 21:21 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMISS_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT 22:22 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IMHIT_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK 23:23 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXC_IBREAK_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0 24:24 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV0_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1 25:25 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV1_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2 26:26 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_TRUE 1 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_IV2_FALSE 0 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT4_ICD_EMASK_EXT 31:27 /* */
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#define NV_PPWR_FALCON_ICD_RDATA_RSTAT5_LRU_STATE 7:0 /* */
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#define NV_PPWR_FALCON_RSTAT0 0x0010a0d8 /* R--4R */
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#define NV_PPWR_FALCON_RSTAT0__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_RSTAT0__PRIV_LEVEL_MASK 0x0010a224 /* */
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#define NV_PPWR_FALCON_RSTAT0_MEM_STALL 0:0 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_DMA_STALL 1:1 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_FENCE_STALL 2:2 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_DIV_STALL 3:3 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_SB_FULL_STALL 8:8 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_SB_HIT_STALL 9:9 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_FLOW_STALL 10:10 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_SP_STALL 11:11 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_BL_STALL 12:12 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_NO_INSTR_STALL 16:16 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_HALTSTOP_FLUSH 20:20 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_AFILL_FLUSH 21:21 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_EXC_FLUSH 22:22 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_IRQ_FLUSH 25:23 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_VALID 28:28 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_WAITING 29:29 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT0_HALTED 30:30 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3 0x0010a0dc /* R--4R */
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#define NV_PPWR_FALCON_RSTAT3__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_FALCON_RSTAT3_MTHD_IDLE 0:0 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_CTXSW_IDLE 1:1 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_DMA_IDLE 2:2 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_SCP_IDLE 3:3 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_LDST_IDLE 4:4 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_SBWB_EMPTY 5:5 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_CSWIE 8:6 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_CSWE 10:10 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_CTXSW_STATE 14:12 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_CTXSW_PEND 15:15 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_DMA_FBREQ_IDLE 17:17 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_DMA_ACKQ_EMPTY 18:18 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_DMA_RDQ_EMPTY 19:19 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_DMA_WR_BUSY 20:20 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_DMA_RD_BUSY 21:21 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_LDST_XT_BUSY 22:22 /* R-XVF */
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#define NV_PPWR_FALCON_RSTAT3_LDST_XT_BLOCK 23:23 /* R-XVF */
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#define NV_PPWR_FALCON_TRACEIDX 0x0010a148 /* RW-4R */
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#define NV_PPWR_FALCON_TRACEIDX__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_TRACEIDX__PRIV_LEVEL_MASK 0x0010a19c /* */
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#define NV_PPWR_FALCON_TRACEIDX_CNT 31:24 /* R-IVF */
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#define NV_PPWR_FALCON_TRACEIDX_CNT_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_TRACEIDX_MAXIDX 23:16 /* R--VF */
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#define NV_PPWR_FALCON_TRACEIDX_IDX 7:0 /* RWIVF */
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#define NV_PPWR_FALCON_TRACEIDX_IDX_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_TRACEPC 0x0010a14c /* R--4R */
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#define NV_PPWR_FALCON_TRACEPC__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_TRACEPC__PRIV_LEVEL_MASK 0x0010a19c /* */
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#define NV_PPWR_FALCON_TRACEPC_PC 23:0 /* R--VF */
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#define NV_PPWR_FALCON_TRACEINFO 0x0010a17c /* R--4R */
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#define NV_PPWR_FALCON_TRACEINFO__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_TRACEINFO__PRIV_LEVEL_MASK 0x0010a19c /* */
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#define NV_PPWR_FALCON_TRACEINFO_COUNT 15:0 /* R--VF */
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#define NV_PPWR_FALCON_IMCTL 0x0010a140 /* RW-4R */
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#define NV_PPWR_FALCON_IMCTL__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IMCTL__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_IMCTL_ADDR_BLK 23:0 /* RWXVF */
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#define NV_PPWR_FALCON_IMCTL_CMD 26:24 /* RWXVF */
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#define NV_PPWR_FALCON_IMCTL_CMD_NOP 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IMCTL_CMD_IMINV 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_IMCTL_CMD_IMBLK 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_IMCTL_CMD_IMTAG 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_IMCTL_CMD_IMTAG_SETVLD 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_IMCTL_DEBUG 0x0010a15c /* RW-4R */
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#define NV_PPWR_FALCON_IMCTL_DEBUG__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IMCTL_DEBUG_ADDR_BLK 23:0 /* RWXVF */
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#define NV_PPWR_FALCON_IMCTL_DEBUG_CMD 26:24 /* RWXVF */
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#define NV_PPWR_FALCON_IMCTL_DEBUG_CMD_NOP 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_IMCTL_DEBUG_CMD_IMBLK 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_IMCTL_DEBUG_CMD_IMTAG 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_IMSTAT 0x0010a144 /* RW-4R */
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#define NV_PPWR_FALCON_IMSTAT__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IMSTAT__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_IMSTAT_VAL 31:0 /* RWXVF */
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#define NV_PPWR_FALCON_IMFILLRNG0 0x0010a150 /* RW-4R */
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#define NV_PPWR_FALCON_IMFILLRNG0__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IMFILLRNG0__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_IMFILLRNG0_TAG_LO 15:0 /* RWIVF */
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#define NV_PPWR_FALCON_IMFILLRNG0_TAG_LO_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IMFILLRNG0_TAG_HI 31:16 /* RWIVF */
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#define NV_PPWR_FALCON_IMFILLRNG0_TAG_HI_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IMFILLRNG1 0x0010a154 /* RW-4R */
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#define NV_PPWR_FALCON_IMFILLRNG1__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IMFILLRNG1__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_IMFILLRNG1_TAG_LO 15:0 /* RWIVF */
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#define NV_PPWR_FALCON_IMFILLRNG1_TAG_LO_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IMFILLRNG1_TAG_HI 31:16 /* RWIVF */
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#define NV_PPWR_FALCON_IMFILLRNG1_TAG_HI_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_IMFILLCTL 0x0010a158 /* RW-4R */
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#define NV_PPWR_FALCON_IMFILLCTL__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_IMFILLCTL__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_IMFILLCTL_NBLOCKS 8:0 /* RWIVF */
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#define NV_PPWR_FALCON_IMFILLCTL_NBLOCKS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMCTL 0x0010a260 /* RW-4R */
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#define NV_PPWR_FALCON_DMCTL__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_DMCTL__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_DMCTL_ADDR_BLK 23:0 /* RWXVF */
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#define NV_PPWR_FALCON_DMCTL_CMD 26:24 /* RWXVF */
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#define NV_PPWR_FALCON_DMCTL_CMD_NOP 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMCTL_CMD_DMINV 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMCTL_CMD_DMBLK 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_DMCTL_CMD_DMTAG 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_DMCTL_CMD_DMTAG_SETVLD 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_DMCTL_CMD_DMCLEAN 0x00000005 /* RW--V */
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#define NV_PPWR_FALCON_DMCTL_CMD_DMLVL 0x00000006 /* RW--V */
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#define NV_PPWR_FALCON_DMSTAT 0x0010a264 /* RW-4R */
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#define NV_PPWR_FALCON_DMSTAT__DEVICE_MAP 0x00000012 /* */
|
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#define NV_PPWR_FALCON_DMSTAT__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_DMSTAT_VAL 31:0 /* RWXVF */
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#define NV_PPWR_FALCON_DMVACTL 0x0010a268 /* RW-4R */
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#define NV_PPWR_FALCON_DMVACTL__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_DMVACTL__PRIV_LEVEL_MASK 0x0010a198 /* */
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#define NV_PPWR_FALCON_DMVACTL_BOUND 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMVACTL_BOUND_INIT 0x00000100 /* RWI-V */
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#define NV_PPWR_FALCON_DMCYA 0x0010a26c /* RW-4R */
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#define NV_PPWR_FALCON_DMCYA__DEVICE_MAP 0x00000012 /* */
|
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#define NV_PPWR_FALCON_DMCYA__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_DMCYA_LDSTVA_DIS 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMCYA_LDSTVA_DIS_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMCYA_LDSTVA_DIS_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMCYA_ROB_DIS 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_DMCYA_ROB_DIS_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMCYA_ROB_DIS_TRUE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMCYA_ROBWB_DIS 2:2 /* RWIVF */
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#define NV_PPWR_FALCON_DMCYA_ROBWB_DIS_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMCYA_ROBWB_DIS_TRUE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_DMCYA_ROBSPR_DIS 3:3 /* RWIVF */
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#define NV_PPWR_FALCON_DMCYA_ROBSPR_DIS_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMCYA_ROBSPR_DIS_TRUE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CMEMBASE 0x0010a160 /* RW-4R */
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#define NV_PPWR_FALCON_CMEMBASE__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_CMEMBASE__PRIV_LEVEL_MASK 0x0010a198 /* */
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#define NV_PPWR_FALCON_CMEMBASE_VAL 31:18 /* RWIVF */
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#define NV_PPWR_FALCON_CMEMBASE_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMEMAPERT 0x0010a164 /* RW-4R */
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#define NV_PPWR_FALCON_DMEMAPERT__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_DMEMAPERT__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_FALCON_DMEMAPERT_TIME_OUT 7:0 /* RWIVF */
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#define NV_PPWR_FALCON_DMEMAPERT_TIME_OUT__PROD 0x000000ff /* RW--V */
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#define NV_PPWR_FALCON_DMEMAPERT_TIME_OUT_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMEMAPERT_TIME_UNIT 11:8 /* RWIVF */
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#define NV_PPWR_FALCON_DMEMAPERT_TIME_UNIT_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMEMAPERT_ENABLE 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_DMEMAPERT_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_DMEMAPERT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_DMEMAPERT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_DMEMAPERT_LDSTQ_NUM 19:17 /* R--VF */
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#define NV_PPWR_FALCON_EXTERRSTAT 0x0010a16c /* RW-4R */
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#define NV_PPWR_FALCON_EXTERRSTAT__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_EXTERRSTAT__PRIV_LEVEL_MASK 0x0010a228 /* */
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#define NV_PPWR_FALCON_EXTERRSTAT_PC 23:0 /* R--VF */
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#define NV_PPWR_FALCON_EXTERRSTAT_STAT 27:24 /* R--VF */
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#define NV_PPWR_FALCON_EXTERRSTAT_STAT_ACK_POS 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXTERRSTAT_STAT_ACK_TOUT 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_EXTERRSTAT_VALID 31:31 /* RWIVF */
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#define NV_PPWR_FALCON_EXTERRSTAT_VALID_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_EXTERRSTAT_VALID_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_EXTERRSTAT_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_EXTERRADDR 0x0010a168 /* R--4R */
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#define NV_PPWR_FALCON_EXTERRADDR__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_EXTERRADDR__PRIV_LEVEL_MASK 0x0010a228 /* */
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#define NV_PPWR_FALCON_EXTERRADDR_ADDR 31:0 /* R--VF */
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#define NV_PPWR_FALCON_EXTERR_INFO 0x0010a25c /* R--4R */
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#define NV_PPWR_FALCON_EXTERR_INFO__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_EXTERR_INFO__PRIV_LEVEL_MASK 0x0010a228 /* */
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#define NV_PPWR_FALCON_EXTERR_INFO_VAL 31:0 /* R--VF */
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#define NV_PPWR_FALCON_CSBERRSTAT 0x0010a244 /* RW-4R */
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#define NV_PPWR_FALCON_CSBERRSTAT__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_CSBERRSTAT__PRIV_LEVEL_MASK 0x0010a22c /* */
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#define NV_PPWR_FALCON_CSBERRSTAT_PC 23:0 /* R--VF */
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#define NV_PPWR_FALCON_CSBERRSTAT_ENABLE 30:30 /* RWIVF */
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#define NV_PPWR_FALCON_CSBERRSTAT_ENABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_CSBERRSTAT_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_CSBERRSTAT_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CSBERRSTAT_VALID 31:31 /* RWIVF */
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#define NV_PPWR_FALCON_CSBERRSTAT_VALID_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_CSBERRSTAT_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_CSBERRSTAT_VALID_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_CSBERR_ADDR 0x0010a24c /* R--4R */
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#define NV_PPWR_FALCON_CSBERR_ADDR__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_CSBERR_ADDR__PRIV_LEVEL_MASK 0x0010a22c /* */
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#define NV_PPWR_FALCON_CSBERR_ADDR_VAL 31:0 /* R--VF */
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#define NV_PPWR_FALCON_CSBERR_INFO 0x0010a248 /* R--4R */
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#define NV_PPWR_FALCON_CSBERR_INFO__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_CSBERR_INFO__PRIV_LEVEL_MASK 0x0010a22c /* */
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#define NV_PPWR_FALCON_CSBERR_INFO_VAL 31:0 /* R--VF */
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#define NV_PPWR_FALCON_KMEM_PDUK_IDX 0
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#define NV_PPWR_FALCON_KMEM_PMUK_IDX 1
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#define NV_PPWR_FALCON_KMEM_KEK_IDX 2
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#define NV_PPWR_FALCON_KMEM_EK_LOW_IDX 3
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#define NV_PPWR_FALCON_KMEM_EK_HIGH_IDX 4
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#define NV_PPWR_FALCON_KMEM_MPK_LOW_IDX 6
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#define NV_PPWR_FALCON_KMEM_MPK_HIGH_IDX 7
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL0_READ 0:0
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL0_READ_ENABLE 0x00000001
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL0_READ_DISABLE 0x00000000
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL0_WRITE 1:1
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL0_WRITE_ENABLE 0x00000001
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL0_WRITE_DISABLE 0x00000000
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL1_READ 2:2
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL1_READ_ENABLE 0x00000001
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL1_READ_DISABLE 0x00000000
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL1_WRITE 3:3
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL1_WRITE_ENABLE 0x00000001
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL1_WRITE_DISABLE 0x00000000
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL2_READ 4:4
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL2_READ_ENABLE 0x00000001
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL2_READ_DISABLE 0x00000000
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL2_WRITE 5:5
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL2_WRITE_ENABLE 0x00000001
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL2_WRITE_DISABLE 0x00000000
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL3_READ 6:6
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL3_READ_ENABLE 0x00000001
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL3_READ_DISABLE 0x00000000
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL3_WRITE 7:7
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL3_WRITE_ENABLE 0x00000001
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LEVEL3_WRITE_DISABLE 0x00000000
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_ACL_K0 8:8
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_ACL_K3 9:9
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_RECYCLABLE 10:10
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_PRIV_EN 11:11
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_NS_63LOADABLE 12:12
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_LS_63LOADABLE 13:13
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_HS_63LOADABLE 14:14
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#define NV_PPWR_FALCON_KMEM_PROTECTINFO_UCODEIDMASK 31:15
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK 0x0010b250 /* RWI4R */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_BR_PARAMS_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK 0x0010b25c /* RWI4R */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK 0x0010b254 /* RWI4R */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_KMEM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK 0x0010b128 /* RWI4R */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK__SETLVL_SIGNAL "setlvlm" /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK__CLRLVL_SIGNAL "clrlvlm" /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_RESET_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE__FUSE_SIGNAL "reg_init_val_flip_fuse5" /* */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE0 0x000fffff /* RWI-V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_RESET_FUSE1 0x00080000 /* RW--V */
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#define NV_PPWR_FALCON_SHA_RAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PPWR_FALCON_SHA_CONFIG 0x0010b004 /* RW-4R */
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#define NV_PPWR_FALCON_SHA_CONFIG__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_CONFIG_ENC_MODE 31:24 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA1 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA224 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA256 0x00000005 /* RW--V */
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#define NV_PPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA384 0x00000006 /* RW--V */
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#define NV_PPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA512 0x00000007 /* RW--V */
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#define NV_PPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA512_224 0x00000007 /* RW--V */
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#define NV_PPWR_FALCON_SHA_CONFIG_ENC_MODE_SHA512_256 0x00000007 /* RW--V */
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#define NV_PPWR_FALCON_SHA_CONFIG_ENC_ALG 15:12 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_CONFIG_ENC_ALG_SHA 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_SHA_CONFIG_ENC_ALG_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_CONFIG_DST 4:2 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_CONFIG_DST_HASH_REG 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_CONFIG_DST_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_CONFIG__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_TASK_CONFIG 0x0010b008 /* RWI4R */
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#define NV_PPWR_FALCON_SHA_TASK_CONFIG__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SHA_TASK_CONFIG_HW_INIT_HASH_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_TASK_CONFIG__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_IN_ADDR 0x0010b00c /* RW-4R */
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#define NV_PPWR_FALCON_SHA_IN_ADDR__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_IN_ADDR_VAL 31:0 /* RWXVF */
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#define NV_PPWR_FALCON_SHA_IN_ADDR__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_IN_ADDR_HI 0x0010b010 /* RW-4R */
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#define NV_PPWR_FALCON_SHA_IN_ADDR_HI__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_IN_ADDR_HI_MSB 31:24 /* RWXVF */
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#define NV_PPWR_FALCON_SHA_IN_ADDR_HI_SZ 23:0 /* RWXVF */
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#define NV_PPWR_FALCON_SHA_IN_ADDR_HI__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_MSG_LENGTH(i) (0x0010b01c+(i)*4) /* RW-4A */
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#define NV_PPWR_FALCON_SHA_MSG_LENGTH__SIZE_1 4 /* */
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#define NV_PPWR_FALCON_SHA_MSG_LENGTH__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_MSG_LENGTH_VAL 31:0 /* RW-VF */
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#define NV_PPWR_FALCON_SHA_MSG_LENGTH__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_MSG_LEFT(i) (0x0010b02c+(i)*4) /* RW-4A */
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#define NV_PPWR_FALCON_SHA_MSG_LEFT__SIZE_1 4 /* */
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#define NV_PPWR_FALCON_SHA_MSG_LEFT__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_MSG_LEFT_VAL 31:0 /* RW-VF */
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#define NV_PPWR_FALCON_SHA_MSG_LEFT__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_HASH_RESULT(i) (0x0010b03c+(i)*4) /* RW-4A */
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#define NV_PPWR_FALCON_SHA_HASH_RESULT__SIZE_1 16 /* */
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#define NV_PPWR_FALCON_SHA_HASH_RESULT__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_HASH_RESULT_VAL 31:0 /* RW-VF */
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#define NV_PPWR_FALCON_SHA_HASH_RESULT__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_OPERATION 0x0010b07c /* RWI4R */
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#define NV_PPWR_FALCON_SHA_OPERATION__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_OPERATION_LAST_BUF 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_OPERATION_LAST_BUF_TRUE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_OPERATION_LAST_BUF_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SHA_OPERATION_SOFTRESET 6:6 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_OPERATION_SOFTRESET_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_OPERATION_SOFTRESET_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_OPERATION_HALT 5:5 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_OPERATION_HALT_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_OPERATION_HALT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_OPERATION_OP 2:0 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_OPERATION_OP_NOP 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SHA_OPERATION_OP_START 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_OPERATION_OP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_OPERATION__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_STATUS 0x0010b080 /* R-I4R */
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#define NV_PPWR_FALCON_SHA_STATUS__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_STATUS__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_STATUS_STATE 2:0 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_STATUS_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_STATUS_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_SHA_STATUS_STATE_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_SHA_STATUS_STATE_HALTED 0x00000007 /* R---V */
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#define NV_PPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR 0x0010b084 /* R--4R */
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#define NV_PPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_VAL 31:0 /* R-XVF */
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#define NV_PPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI 0x0010b088 /* R--4R */
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#define NV_PPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI_MSB 31:24 /* R-XVF */
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#define NV_PPWR_FALCON_SHA_IN_REQ_CUR_BYTE_ADDR_HI__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_PRIV_LOCKDOWN 0x0010b08c /* RW-4R */
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#define NV_PPWR_FALCON_SHA_PRIV_LOCKDOWN__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_SET 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_PRIV_LOCKDOWN_WR_LOCK_UNSET 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_SET 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_PRIV_LOCKDOWN_RD_LOCK_UNSET 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR 0x0010b090 /* R--4R */
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#define NV_PPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_VAL 31:0 /* R-XVF */
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#define NV_PPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI 0x0010b094 /* R--4R */
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#define NV_PPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI_MSB 31:24 /* R-XVF */
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#define NV_PPWR_FALCON_SHA_IN_RESP_CUR_BYTE_ADDR_HI__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS 0x0010b130 /* RWI4R */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_LEVEL_ERR 12:12 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_LEVEL_ERR_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_LEVEL_ERR_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_LEVEL_ERR_CLEAR 1 /* */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_MULTI_HIT 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_MULTI_HIT_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_MULTI_HIT_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_MULTI_HIT_CLEAR 1 /* */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_MISS 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_MISS_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_MISS_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_MISS_CLEAR 1 /* */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_PA_FAULT 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_PA_FAULT_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_PA_FAULT_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_PA_FAULT_CLEAR 1 /* */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_FBIF_ERR 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_FBIF_ERR_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_FBIF_ERR_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_FBIF_ERR_CLEAR 1 /* */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_ILLEGAL_CFG_CLEAR 1 /* */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_NS_ACCESS 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_NS_ACCESS_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_NS_ACCESS_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS_NS_ACCESS_CLEAR 1 /* */
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#define NV_PPWR_FALCON_SHA_ERR_STATUS__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_ERR_ADDR 0x0010b120 /* R--4R */
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#define NV_PPWR_FALCON_SHA_ERR_ADDR__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_ERR_ADDR_VAL 31:0 /* R-XVF */
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#define NV_PPWR_FALCON_SHA_ERR_ADDR__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_ERR_ADDR_HI 0x0010b124 /* R--4R */
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#define NV_PPWR_FALCON_SHA_ERR_ADDR_HI__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_ERR_ADDR_HI_MSB 31:24 /* R-XVF */
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#define NV_PPWR_FALCON_SHA_ERR_ADDR_HI__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_INT_STATUS 0x0010b134 /* RWI4R */
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#define NV_PPWR_FALCON_SHA_INT_STATUS__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_INT_STATUS_ERR_STATUS 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_INT_STATUS_ERR_STATUS_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_INT_STATUS_ERR_STATUS_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_INT_STATUS_ERR_STATUS_CLEAR 1 /* */
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#define NV_PPWR_FALCON_SHA_INT_STATUS_OP_DONE 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_INT_STATUS_OP_DONE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_INT_STATUS_OP_DONE_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_INT_STATUS_OP_DONE_CLEAR 1 /* */
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#define NV_PPWR_FALCON_SHA_INT_STATUS__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_INT_ENABLE 0x0010b138 /* RWI4R */
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#define NV_PPWR_FALCON_SHA_INT_ENABLE__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_INT_ENABLE_ERR_STATUS 16:16 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_INT_ENABLE_ERR_STATUS_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_INT_ENABLE_ERR_STATUS_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_INT_ENABLE_OP_DONE 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_INT_ENABLE_OP_DONE_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_INT_ENABLE_OP_DONE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_INT_ENABLE__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_MUTEX 0x0010b100 /* -W-4R */
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#define NV_PPWR_FALCON_SHA_MUTEX__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_MUTEX_VAL 7:0 /* -W-VF */
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#define NV_PPWR_FALCON_SHA_MUTEX__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_MUTEX_RELEASE 0x0010b104 /* -W-4R */
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#define NV_PPWR_FALCON_SHA_MUTEX_RELEASE__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_MUTEX_RELEASE_VAL 7:0 /* -W-VF */
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#define NV_PPWR_FALCON_SHA_MUTEX_RELEASE__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_MUTEX_STATUS 0x0010b108 /* R-I4R */
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#define NV_PPWR_FALCON_SHA_MUTEX_STATUS__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_MUTEX_STATUS__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_MUTEX_STATUS_LOCKED 7:0 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_MUTEX_STATUS_LOCKED_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_SRC_CONFIG 0x0010b110 /* RW-4R */
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#define NV_PPWR_FALCON_SHA_SRC_CONFIG__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_SRC_CONFIG_FB_BASE 24:16 /* RWXVF */
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#define NV_PPWR_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION 7:7 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_SRC_CONFIG_TCM_NO_TRANSLATION_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_SRC_CONFIG_CTXDMA 6:4 /* RWXVF */
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#define NV_PPWR_FALCON_SHA_SRC_CONFIG_SRC 1:0 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_SRC_CONFIG_SRC_DMEM 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_SRC_CONFIG_SRC_IMEM 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_SRC_CONFIG_SRC_FB 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_SHA_SRC_CONFIG__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_REQ_CTRL 0x0010b114 /* RW-4R */
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#define NV_PPWR_FALCON_SHA_REQ_CTRL__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_REQ_CTRL_WINDOW 31:16 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_REQ_CTRL_WINDOW_INIT 0x00001000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_REQ_CTRL_LIMIT 15:0 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_REQ_CTRL_LIMIT_INIT 0x00000800 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_REQ_CTRL__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_CTRL 0x0010b098 /* RWI4R */
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#define NV_PPWR_FALCON_SHA_CTRL__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_FALCON_SHA_CTRL__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_CTRL_FB_DIS 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_CTRL_FB_DIS_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_CTRL_FB_DIS_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_CYA 0x0010b118 /* RWI4R */
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#define NV_PPWR_FALCON_SHA_CYA__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_CYA_BW_THROTTLE_DIS 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_SHA_CYA_BW_THROTTLE_DIS_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_SHA_CYA_BW_THROTTLE_DIS_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_SHA_CYA__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_DBG_INFO 0x0010b11c /* R-I4R */
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#define NV_PPWR_FALCON_SHA_DBG_INFO__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_DBG_INFO__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_PW_HALTED 13:13 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_PW_HALTED_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_PW_HALTED_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_IDMA_HALTED 12:12 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_IDMA_HALTED_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_IDMA_HALTED_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_ALU_HALTED 11:11 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_ALU_HALTED_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_ALU_HALTED_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_PW_IDLE 10:10 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_PW_IDLE_TRUE 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_PW_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_IDMA_IDLE 9:9 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_IDMA_IDLE_TRUE 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_IDMA_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_ALU_IDLE 8:8 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_ALU_IDLE_TRUE 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_ALU_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_CORE_STATUS 6:4 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_CORE_STATUS_IDLE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_CORE_STATUS_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_SECURE_LEVEL 1:0 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_INFO_SECURE_LEVEL_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_0 0x0010b140 /* R--4R */
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#define NV_PPWR_FALCON_SHA_DBG_REG_0__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_0__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_0_SHA_SHA_PREPROC_STATE 11:10 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_0_SHA_WD_NUMBER 9:6 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_0_SHA_SHA_HASH_STATE 5:3 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_0_SHA_BYTE_COUNTER 2:0 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_1 0x0010b144 /* R-I4R */
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#define NV_PPWR_FALCON_SHA_DBG_REG_1__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_1__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN 18:18 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_REQ_RUN_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN 17:17 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_RESP_RUN_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS 14:14 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_1_SHA_IDMA_NO_INFLIGHTS_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_2 0x0010b148 /* R--4R */
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#define NV_PPWR_FALCON_SHA_DBG_REG_2__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_2__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_2_SHA_IDMA_RESP_DMA_SIZE 23:0 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_2_SHA_IDMA_RESP_DMA_ADDR 31:24 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_3 0x0010b14c /* R--4R */
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#define NV_PPWR_FALCON_SHA_DBG_REG_3__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_3__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_3_SHA_IDMA_RESP_DMA_ADDR 31:0 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_4 0x0010b150 /* R--4R */
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#define NV_PPWR_FALCON_SHA_DBG_REG_4__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_4__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_4_SHA_IDMA_RESP_DMA_ADDR 8:0 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_4_SHA_IDMA_CORRECTED_RESP_DMA_SIZE 31:11 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_5 0x0010b154 /* R--4R */
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#define NV_PPWR_FALCON_SHA_DBG_REG_5__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_5__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_5_SHA_IDMA_CORRECTED_RESP_DMA_ADDR 31:0 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6 0x0010b158 /* R--4R */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_IDMA_CORRECTED_RESP_DMA_ADDR 12:0 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_IDMA_FREE_COUNT 21:16 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH 24:24 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_WILL_NOT_FINISH_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE 25:25 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE_TRUE 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_SHA_HASH_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE 26:26 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE_TRUE 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_SHA_PREPROC_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA 27:27 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA_TRUE 0x00000001 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_IDMA_NO_PACKING_DATA_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_LASTBUF 28:28 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_LASTBUF_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_LASTBUF_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0 29:29 /* R-IVF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_6_SHA_MSG_LEFT_NON0_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7 0x0010b15c /* R--4R */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7__DEVICE_MAP 0x0000000a /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7__PRIV_LEVEL_MASK 0x0010b128 /* */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_SHA_AGENT_TREQ_PVLD 25:25 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_SHA_AGENT_TREQ_READ 24:24 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_IDMA_REQ_TBUF_PRDY 23:23 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_IDMA_REQ_TBUF_PVLD 22:22 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_IDMA_RESP_TBUF_PRDY 21:21 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_IDMA_RESP_TBUF_PVLD 20:20 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_BLK_WD_VALID 15:15 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_BLK_WD_STALL 14:14 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_IDMA2ENG_PVLD 9:9 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_IDMA2ENG_STALL 8:8 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA2FBIF_SREQ_PVLD 7:7 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA2FBIF_SREQ_PRDY 6:6 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA_FBIF2PDMA_RDAT_PVLD 5:5 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_NV_SE_SHA2DATA_FBIF2PDMA_RDAT_PRDY 4:4 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_PE2AFBIF_RD_REQ 1:1 /* R--VF */
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#define NV_PPWR_FALCON_SHA_DBG_REG_7_SHA_PE2AFBIF_RD_BUSY 0:0 /* R--VF */
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#define NV_PPWR_FALCON_VER 0x0010b188 /* R-I4R */
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#define NV_PPWR_FALCON_VER_MAJOR 3:0 /* R-IVF */
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#define NV_PPWR_FALCON_VER_MAJOR_DEFT 0x00000002 /* R-I-V */
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#define NV_PPWR_FALCON_VER_MINOR 17:4 /* R-IVF */
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#define NV_PPWR_FALCON_VER_MINOR_DEFT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_VER_BUGFIX 31:18 /* R-IVF */
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#define NV_PPWR_FALCON_VER_BUGFIX_DEFT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_MOD_SEL 0x0010b180 /* RWI4R */
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#define NV_PPWR_FALCON_MOD_SEL__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_MOD_SEL_ALGO 7:0 /* RWIVF */
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#define NV_PPWR_FALCON_MOD_SEL_ALGO_AES 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_MOD_SEL_ALGO_RSA3K 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_MOD_EN 0x0010b184 /* RW-4R */
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#define NV_PPWR_FALCON_MOD_EN__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_MOD_EN_AES 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_MOD_EN_AES_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_MOD_EN_AES_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_MOD_EN_RSA3K 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_MOD_EN_RSA3K_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_MOD_EN_RSA3K_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_PKCBROM_VER 0x0010b18c /* R--4R */
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#define NV_PPWR_FALCON_PKCBROM_VER__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_PKCBROM_VER_DEV 11:0 /* R--VF */
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#define NV_PPWR_FALCON_PKCBROM_VER_ECO 15:12 /* R--VF */
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#define NV_PPWR_FALCON_PKCBROM_VER_MINOR 23:16 /* R--VF */
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#define NV_PPWR_FALCON_PKCBROM_VER_MAJOR 31:24 /* R--VF */
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#define NV_PPWR_FALCON_VHRCFG_BASE 0x0010b190 /* R-I4R */
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#define NV_PPWR_FALCON_VHRCFG_BASE_VAL 31:0 /* R-IVF */
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#define NV_PPWR_FALCON_VHRCFG_BASE_VAL_SEC 0x00008200 /* R---V */
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#define NV_PPWR_FALCON_VHRCFG_BASE_VAL_PWR_PMU 0x000083f0 /* R---V */
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#define NV_PPWR_FALCON_VHRCFG_BASE_VAL_NVDEC 0x00008490 /* R---V */
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#define NV_PPWR_FALCON_VHRCFG_BASE_VAL_GSP 0x000087a0 /* R---V */
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#define NV_PPWR_FALCON_VHRCFG_BASE_VAL_SOE 0x00008200 /* R---V */
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#define NV_PPWR_FALCON_VHRCFG_BASE_VAL_PSC 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_VHRCFG_BASE_VAL_DEFT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_VHRCFG_ENTNUM 0x0010b1e8 /* R-I4R */
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#define NV_PPWR_FALCON_VHRCFG_ENTNUM_VAL 31:0 /* R-IVF */
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#define NV_PPWR_FALCON_VHRCFG_ENTNUM_VAL_SEC 0x0000000a /* R---V */
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#define NV_PPWR_FALCON_VHRCFG_ENTNUM_VAL_PWR_PMU 0x00000003 /* R---V */
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#define NV_PPWR_FALCON_VHRCFG_ENTNUM_VAL_NVDEC 0x00000010 /* R---V */
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#define NV_PPWR_FALCON_VHRCFG_ENTNUM_VAL_GSP 0x00000003 /* R---V */
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#define NV_PPWR_FALCON_VHRCFG_ENTNUM_VAL_SOE 0x0000000a /* R---V */
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#define NV_PPWR_FALCON_VHRCFG_ENTNUM_VAL_PSC 0x00000000 /* R---V */
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#define NV_PPWR_FALCON_VHRCFG_ENTNUM_VAL_DEFT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_BMEMBASE 0x0010b194 /* R-I4R */
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#define NV_PPWR_FALCON_BMEMBASE__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_BMEMBASE_VAL 31:0 /* R-IVF */
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#define NV_PPWR_FALCON_BMEMBASE_VAL_DEFT 0x02100000 /* R-I-V */
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#define NV_PPWR_FALCON_BROM_CURR_UCODE_ID 0x0010b198 /* RWI4R */
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#define NV_PPWR_FALCON_BROM_CURR_UCODE_ID__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_BROM_CURR_UCODE_ID__PRIV_LEVEL_MASK 0x0010b250 /* */
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#define NV_PPWR_FALCON_BROM_CURR_UCODE_ID_VAL 7:0 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_CURR_UCODE_ID_VAL_DEFT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_CURR_UCODE_ID_VAL_MAX 0x00000010 /* RW--V */
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#define NV_PPWR_FALCON_UCODE_VERSION(i) (0x0010b1a8+(i)*4) /* R-I4A */
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#define NV_PPWR_FALCON_UCODE_VERSION__SIZE_1 16 /* */
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#define NV_PPWR_FALCON_UCODE_VERSION__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_FALCON_UCODE_VERSION_VER 7:0 /* R-IVF */
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#define NV_PPWR_FALCON_UCODE_VERSION_VER_DEF 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK 0x0010b19c /* RWI4R */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK__PRIV_LEVEL_MASK 0x0010b250 /* */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_SEC 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_SEC_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_SEC_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_DPU 1:1 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_DPU_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_DPU_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_NVDEC 2:2 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_NVDEC_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_NVDEC_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_PMU 3:3 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_PMU_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_PMU_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_FBFALCON 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_FBFALCON_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_FBFALCON_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_NVENC 5:5 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_NVENC_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_NVENC_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_GPCCS 6:6 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_GPCCS_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_GPCCS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_FECS 7:7 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_FECS_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_FECS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_MINION 8:8 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_MINION_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_MINION_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_XUSB 9:9 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_XUSB_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_XUSB_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_GSP 10:10 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_GSP_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_GSP_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_NVJPG 11:11 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_NVJPG_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_NVJPG_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_OFA 12:12 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_OFA_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_OFA_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_PSC 13:13 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_PSC_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_PSC_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_SOE 14:14 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_SOE_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_ENGIDMASK_SOE_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL 0x0010b1ec /* RWI4R */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL__PRIV_LEVEL_MASK 0x0010b25c /* */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_HWVER_VALID 0:0 /* R-IVF */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_HWVER_VALID_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_HWVER_VALID_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY 1:1 /* R-IVF */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_HWVER_BUSY_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_HWVER_RELOAD 4:4 /* RWIVF */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_HWVER_RELOAD_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_CTKID_VALID 8:8 /* R-IVF */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_CTKID_VALID_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_CTKID_VALID_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY 9:9 /* R-IVF */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_CTKID_BUSY_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_CTKID_RELOAD 12:12 /* RWIVF */
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#define NV_PPWR_FALCON_KFUSE_LOAD_CTL_CTKID_RELOAD_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_PR_CTKID 0x0010b1f0 /* R-I4R */
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#define NV_PPWR_FALCON_PR_CTKID__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_FALCON_PR_CTKID_VAL 7:0 /* R-IVF */
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#define NV_PPWR_FALCON_PR_CTKID_VAL_DEF 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_BROM_FUNID 0x0010b1a0 /* R-I4R */
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#define NV_PPWR_FALCON_BROM_FUNID__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_BROM_FUNID_ID 7:0 /* R-IVF */
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#define NV_PPWR_FALCON_BROM_FUNID_ID_DEFT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_BROM_FUNID_ID_DECFUSEKEY 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_BROM_FUNID_ID_GENTK 0x00000002 /* R---V */
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#define NV_PPWR_FALCON_BROM_FUNID_ID_DECMPK 0x00000003 /* R---V */
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#define NV_PPWR_FALCON_BROM_FUNID_ID_SIGBYMPK 0x00000004 /* R---V */
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#define NV_PPWR_FALCON_BROM_FUNID_ID_CLRMPK 0x00000005 /* R---V */
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#define NV_PPWR_FALCON_BROM_FUNID_ID_ECDSASIGN 0x00000006 /* R---V */
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#define NV_PPWR_FALCON_BROM_FUNID_ID_ECDSAVERIF 0x00000007 /* R---V */
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#define NV_PPWR_FALCON_BROM_FUNID_CALLER_LVL 9:8 /* R-IVF */
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#define NV_PPWR_FALCON_BROM_FUNID_CALLER_LVL_0 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_BROM_FUNID_CALLER_LVL_1 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_BROM_FUNID_CALLER_LVL_2 0x00000002 /* R---V */
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#define NV_PPWR_FALCON_BROM_FUNID_CALLER_LVL_3 0x00000003 /* R---V */
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#define NV_PPWR_FALCON_BROM_PARAADDR(i) (0x0010b210+(i)*4) /* RWI4A */
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#define NV_PPWR_FALCON_BROM_PARAADDR__SIZE_1 1 /* */
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#define NV_PPWR_FALCON_BROM_PARAADDR__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_BROM_PARAADDR__PRIV_LEVEL_MASK 0x0010b250 /* */
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#define NV_PPWR_FALCON_BROM_PARAADDR_VAL 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_PARAADDR_VAL_DEFT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_RETCODE 0x0010b1a4 /* RW-4R */
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#define NV_PPWR_FALCON_BROM_RETCODE__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR 7:0 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_SUCCESS 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_ILLFUNID 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_PA_FAULT 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_NOT_IN_DMEM 0x00000003 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_NO_ENOUGH_SPACE 0x00000004 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_VA_NOT_VALID 0x00000005 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_4BYTES 0x00000006 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_16BYTES 0x00000007 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_32BYTES 0x00000008 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_OUTPUT_NOT_ALLOWED 0x00000009 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_TK_PTR_IS_NS_READABLE 0x0000000a /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_NOT_CALLED_BY_HS 0x0000000b /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_CALL_FROM_LVL0 0x0000000c /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_ILLUCODEID 0x0000000d /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_DISPOSE_MPK_FAIL 0x0000000e /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_CTKID_INVALID 0x0000000f /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_ILLTKID 0x00000010 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_INVLDPMUK 0x00000011 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_INVLDPDUK 0x00000012 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_INVLDMPK 0x00000013 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_SIGFAIL 0x00000014 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_PDI_INVALID 0x00000015 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_LOAD_KMEM2SCP_FAIL 0x00000016 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_WRONG_PROTECTINFO 0x00000017 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_KSLT_K3_IS_0 0x00000018 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_NUMOF16B 0x00000019 /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_NUMOF32B 0x0000001a /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_WRONG_HEADER_RSVD_ZEROS 0x0000001b /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_MPK_IS_VALID 0x0000001c /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_SCP_ERR 0x0000001d /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERR_ILLDMEMPTR_MISALIGN_256BYTES 0x0000001e /* RW--V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERRID 19:8 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERRID_DEFT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_RETCODE_FUNID 23:20 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_RETCODE_FUNID_DEFT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERRINFO 31:24 /* RWIVF */
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#define NV_PPWR_FALCON_BROM_RETCODE_ERRINFO_DEFT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_KMEMBASE 0x0010b1f4 /* R-I4R */
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#define NV_PPWR_FALCON_KMEMBASE__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_KMEMBASE_VAL 31:0 /* R-IVF */
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#define NV_PPWR_FALCON_KMEMBASE_VAL_DEF 0x02000000 /* R-I-V */
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#define NV_PPWR_FALCON_KMEMC(i) (0x0010b1f8+(i)*4) /* RWI4A */
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#define NV_PPWR_FALCON_KMEMC__SIZE_1 2 /* */
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#define NV_PPWR_FALCON_KMEMC__DEVICE_MAP 0x0000000b /* */
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#define NV_PPWR_FALCON_KMEMC__PRIV_LEVEL_MASK 0x0010b254 /* */
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#define NV_PPWR_FALCON_KMEMC_OFFS 15:2 /* RWIVF */
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#define NV_PPWR_FALCON_KMEMC_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_KMEMC_OFFS_PROTINFO 0x00000400 /* RW--V */
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#define NV_PPWR_FALCON_KMEMC_OFFS_MAX 0x000005ff /* RW--V */
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#define NV_PPWR_FALCON_KMEMC_AINCW 24:24 /* RWIVF */
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#define NV_PPWR_FALCON_KMEMC_AINCW_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_KMEMC_AINCW_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_KMEMC_AINCR 25:25 /* RWIVF */
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#define NV_PPWR_FALCON_KMEMC_AINCR_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_KMEMC_AINCR_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_KMEMC_ERR 28:26 /* R-IVF */
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#define NV_PPWR_FALCON_KMEMC_ERR_SUCCESS 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_KMEMC_ERR_1 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_KMEMC_ERR_2 0x00000002 /* R---V */
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#define NV_PPWR_FALCON_KMEMC_ERR_3 0x00000003 /* R---V */
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#define NV_PPWR_FALCON_KMEMC_ERR_4 0x00000004 /* R---V */
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#define NV_PPWR_FALCON_KMEMC_ERR_5 0x00000005 /* R---V */
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#define NV_PPWR_FALCON_KMEMC_ERR_6 0x00000006 /* R---V */
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#define NV_PPWR_FALCON_KMEMC_ERR_7 0x00000007 /* R---V */
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#define NV_PPWR_FALCON_KMEMD(i) (0x0010b200+(i)*4) /* RW-4A */
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#define NV_PPWR_FALCON_KMEMD__SIZE_1 2 /* */
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#define NV_PPWR_FALCON_KMEMD__DEVICE_MAP 0x0000000b /* */
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#define NV_PPWR_FALCON_KMEMD__PRIV_LEVEL_MASK 0x0010b254 /* */
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#define NV_PPWR_FALCON_KMEMD_DATA 31:0 /* RW-VF */
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#define NV_PPWR_FALCON_KMEM_CTL 0x0010b208 /* RWI4R */
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#define NV_PPWR_FALCON_KMEM_CTL__DEVICE_MAP 0x0000000b /* */
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#define NV_PPWR_FALCON_KMEM_CTL__PRIV_LEVEL_MASK 0x0010b254 /* */
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#define NV_PPWR_FALCON_KMEM_CTL_IDX 7:0 /* RWIVF */
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#define NV_PPWR_FALCON_KMEM_CTL_IDX_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_KMEM_CTL_CMD 19:16 /* RWIVF */
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#define NV_PPWR_FALCON_KMEM_CTL_CMD_NOP 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_KMEM_CTL_CMD_DISPOSE 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_KMEM_CTL_CMD_LOADTO63 0x00000002 /* RW--V */
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#define NV_PPWR_FALCON_KMEM_CTL_RESULT 23:20 /* R-IVF */
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#define NV_PPWR_FALCON_KMEM_CTL_RESULT_NOP 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_KMEM_CTL_RESULT_DISPOSE_DONE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_RECYCLABLE_IS_0 0x00000002 /* R---V */
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#define NV_PPWR_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_PRIVDISABLED 0x00000003 /* R---V */
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#define NV_PPWR_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_NOTWRITEABLE 0x00000004 /* R---V */
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#define NV_PPWR_FALCON_KMEM_CTL_RESULT_LOADTO63_DONE 0x00000005 /* R---V */
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#define NV_PPWR_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_LOADABLE_IS_0 0x00000006 /* R---V */
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#define NV_PPWR_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_PRIVDISABLED 0x00000007 /* R---V */
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#define NV_PPWR_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_UCODIDMASK_IS_0 0x00000008 /* R---V */
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#define NV_PPWR_FALCON_KMEM_CTL_RESULT_DISPOSE_FAILED_BY_SLOT_MASK 0x00000009 /* R---V */
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#define NV_PPWR_FALCON_KMEM_CTL_RESULT_LOADTO63_FAILED_BY_SLOT_MASK 0x0000000a /* R---V */
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#define NV_PPWR_FALCON_KMEMCFG 0x0010b20c /* R-I4R */
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#define NV_PPWR_FALCON_KMEMCFG_NUMOFKSLT 15:0 /* R-IVF */
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#define NV_PPWR_FALCON_KMEMCFG_NUMOFKSLT_DEFT 0x00000100 /* R-I-V */
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#define NV_PPWR_FALCON_KMEMCFG_KSLT_LENGTH 21:16 /* R-IVF */
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#define NV_PPWR_FALCON_KMEMCFG_KSLT_LENGTH_DEFT 0x00000010 /* R-I-V */
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#define NV_PPWR_FALCON_KMEMCFG_PROTECTINFO_LENGTH 25:22 /* R-IVF */
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#define NV_PPWR_FALCON_KMEMCFG_PROTECTINFO_LENGTH_DEFT 0x00000008 /* R-I-V */
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#define NV_PPWR_FALCON_KMEMCFG_BROM_USED_SLOTS 31:26 /* R-IVF */
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#define NV_PPWR_FALCON_KMEMCFG_BROM_USED_SLOTS_DEFT 0x00000010 /* R-I-V */
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#define NV_PPWR_FALCON_KMEM_VALID(i) (0x0010b218+(i)*4) /* R-I4A */
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#define NV_PPWR_FALCON_KMEM_VALID__SIZE_1 8 /* */
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#define NV_PPWR_FALCON_KMEM_VALID__DEVICE_MAP 0x0000000b /* */
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#define NV_PPWR_FALCON_KMEM_VALID__PRIV_LEVEL_MASK 0x0010b254 /* */
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#define NV_PPWR_FALCON_KMEM_VALID_VAL 31:0 /* R-IVF */
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#define NV_PPWR_FALCON_KMEM_VALID_VAL_DEFT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_KMEM_VIOLATION_CTL 0x0010b238 /* RWI4R */
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#define NV_PPWR_FALCON_KMEM_VIOLATION_CTL__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_KMEM_VIOLATION_CTL__PRIV_LEVEL_MASK 0x0010b254 /* */
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#define NV_PPWR_FALCON_KMEM_VIOLATION_CTL_ACT 0:0 /* RWIVF */
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#define NV_PPWR_FALCON_KMEM_VIOLATION_CTL_ACT_HALT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_KMEM_VIOLATION_CTL_ACT_EXC 0x00000001 /* RW--V */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF 0x0010b23c /* R-I4R */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF__DEVICE_MAP 0x00000012 /* */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP 0:0 /* R-IVF */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP_READ 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_OP_WRITE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_LVL 5:4 /* R-IVF */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_LVL_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_UCODID 15:8 /* R-IVF */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_MASTER_UCODID_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_KSLT_IDX 23:16 /* R-IVF */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_KSLT_IDX_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET 24:24 /* R-IVF */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET_KSLT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_EXCI_KMEM_VIOLATION_DBGINF_TARGET_PROTINFO 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_KMEM_SLOT_MASK 0x0010b240 /* RWI4R */
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#define NV_PPWR_FALCON_KMEM_SLOT_MASK__DEVICE_MAP 0x00000008 /* */
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#define NV_PPWR_FALCON_KMEM_SLOT_MASK__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_FALCON_KMEM_SLOT_MASK_VAL 31:0 /* RWIVF */
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#define NV_PPWR_FALCON_KMEM_SLOT_MASK_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FALCON_KEYGLOB_CTRL 0x0010b248 /* RWI4R */
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#define NV_PPWR_FALCON_KEYGLOB_CTRL__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_FALCON_KEYGLOB_CTRL__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_FALCON_KEYGLOB_CTRL_INDEX 7:0 /* R-IVF */
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#define NV_PPWR_FALCON_KEYGLOB_CTRL_INDEX_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_KEYGLOB_CTRL_STAT_VALID 16:16 /* R-IVF */
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#define NV_PPWR_FALCON_KEYGLOB_CTRL_STAT_VALID_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_KEYGLOB_CTRL_STAT_VALID_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_KEYGLOB_CTRL_STAT_BUSY 17:17 /* R-IVF */
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#define NV_PPWR_FALCON_KEYGLOB_CTRL_STAT_BUSY_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_FALCON_KEYGLOB_CTRL_STAT_BUSY_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FALCON_KEYGLOB_CTRL_STAT_RELOAD 20:20 /* RWIVF */
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#define NV_PPWR_FALCON_KEYGLOB_CTRL_STAT_RELOAD_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FALCON_KEYGLOB_DATA 0x0010b24c /* R--4R */
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#define NV_PPWR_FALCON_KEYGLOB_DATA__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_FALCON_KEYGLOB_DATA__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_FALCON_KEYGLOB_DATA_VAL 31:0 /* R-XVF */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK 0x0010b304 /* RWI4R */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_RISCV_EXE_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK 0x0010b308 /* RWI4R */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_RISCV_CPUCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK 0x0010b300 /* RWI4R */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_RISCV_IRQ_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK 0x0010b314 /* RWI4R */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK 0x0010b310 /* RWI4R */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_RISCV_BOOTVEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK 0x0010b664 /* RWI4R */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK 0x0010b690 /* RWI4R */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK 0x0010b30c /* RWI4R */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK 0x0010b318 /* RWI4R */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000018 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_RISCV_TRACEBUF_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK 0x0010b31c /* RWI4R */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_RISCV_MSIP_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_RISCV_IRQMSET 0x0010b520 /* -W-4R */
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#define NV_PPWR_RISCV_IRQMSET__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_RISCV_IRQMSET__PRIV_LEVEL_MASK 0x0010a290 /* */
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#define NV_PPWR_RISCV_IRQMSET_GPTMR 0:0 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMSET_WDTMR 1:1 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMSET_MTHD 2:2 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMSET_CTXSW 3:3 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMSET_HALT 4:4 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_HALT_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMSET_EXTERR 5:5 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMSET_SWGEN0 6:6 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMSET_SWGEN1 7:7 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMSET_EXT 15:8 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_EXT_CTXE 8:8 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_CTXE_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_LIMITV 9:9 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_LIMITV_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_ECC 10:10 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_ECC_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_SECOND 11:11 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_SECOND_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_THERM 12:12 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_THERM_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_MISCIO 13:13 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_MISCIO_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_RTTIMER 14:14 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_RTTIMER_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_RSVD8 15:15 /* */
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#define NV_PPWR_RISCV_IRQMSET_EXT_RSVD8_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMSET_DMA 16:16 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_DMA_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMSET_SHA 17:17 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_SHA_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMSET_MEMERR 18:18 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_MEMERR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMSET_ICD 22:22 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_ICD_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMSET_IOPMP 23:23 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_IOPMP_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMSET_CORE_MISMATCH 24:24 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMSET_CORE_MISMATCH_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMCLR 0x0010b524 /* -W-4R */
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#define NV_PPWR_RISCV_IRQMCLR__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_RISCV_IRQMCLR__PRIV_LEVEL_MASK 0x0010a290 /* */
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#define NV_PPWR_RISCV_IRQMCLR_GPTMR 0:0 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_GPTMR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMCLR_WDTMR 1:1 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_WDTMR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMCLR_MTHD 2:2 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_MTHD_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMCLR_CTXSW 3:3 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_CTXSW_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMCLR_HALT 4:4 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_HALT_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMCLR_EXTERR 5:5 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_EXTERR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMCLR_SWGEN0 6:6 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_SWGEN0_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMCLR_SWGEN1 7:7 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_SWGEN1_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMCLR_EXT 15:8 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_CTXE 8:8 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_CTXE_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_LIMITV 9:9 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_LIMITV_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_ECC 10:10 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_ECC_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_SECOND 11:11 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_SECOND_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_THERM 12:12 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_THERM_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_MISCIO 13:13 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_MISCIO_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_RTTIMER 14:14 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_RTTIMER_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_RSVD8 15:15 /* */
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#define NV_PPWR_RISCV_IRQMCLR_EXT_RSVD8_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMCLR_DMA 16:16 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_DMA_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMCLR_SHA 17:17 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_SHA_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMCLR_MEMERR 18:18 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_MEMERR_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMCLR_ICD 22:22 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_ICD_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMCLR_IOPMP 23:23 /* -WXVF */
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#define NV_PPWR_RISCV_IRQMCLR_IOPMP_SET 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_IRQMASK 0x0010b528 /* R-I4R */
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#define NV_PPWR_RISCV_IRQMASK__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_RISCV_IRQMASK_GPTMR 0:0 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_GPTMR_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_GPTMR_SET 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IRQMASK_WDTMR 1:1 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_WDTMR_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_WDTMR_SET 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IRQMASK_MTHD 2:2 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_MTHD_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_MTHD_SET 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IRQMASK_CTXSW 3:3 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_CTXSW_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_CTXSW_SET 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IRQMASK_HALT 4:4 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_HALT_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_HALT_SET 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IRQMASK_EXTERR 5:5 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_EXTERR_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_EXTERR_SET 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IRQMASK_SWGEN0 6:6 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_SWGEN0_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_SWGEN0_SET 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IRQMASK_SWGEN1 7:7 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_SWGEN1_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_SWGEN1_SET 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IRQMASK_EXT 15:8 /* */
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#define NV_PPWR_RISCV_IRQMASK_EXT_CTXE 8:8 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_EXT_CTXE_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_EXT_CTXE_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMASK_EXT_LIMITV 9:9 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_EXT_LIMITV_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_EXT_LIMITV_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMASK_EXT_ECC 10:10 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_EXT_ECC_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_EXT_ECC_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMASK_EXT_SECOND 11:11 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_EXT_SECOND_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_EXT_SECOND_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMASK_EXT_THERM 12:12 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_EXT_THERM_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_EXT_THERM_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMASK_EXT_MISCIO 13:13 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_EXT_MISCIO_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_EXT_MISCIO_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMASK_EXT_RTTIMER 14:14 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_EXT_RTTIMER_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_EXT_RTTIMER_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMASK_EXT_RSVD8 15:15 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_EXT_RSVD8_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_EXT_RSVD8_SET 1 /* */
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#define NV_PPWR_RISCV_IRQMASK_DMA 16:16 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_DMA_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_DMA_SET 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IRQMASK_SHA 17:17 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_SHA_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_SHA_SET 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IRQMASK_MEMERR 18:18 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_MEMERR_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_MEMERR_SET 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IRQMASK_ICD 22:22 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_ICD_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_ICD_SET 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IRQMASK_IOPMP 23:23 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_IOPMP_UNSET 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_IOPMP_SET 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IRQMASK_CORE_MISMATCH 24:24 /* R-IVF */
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#define NV_PPWR_RISCV_IRQMASK_CORE_MISMATCH_ENABLE 0x00000001 /* R-I-V */
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#define NV_PPWR_RISCV_IRQMASK_CORE_MISMATCH_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_IRQDEST 0x0010b52c /* RW-4R */
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#define NV_PPWR_RISCV_IRQDEST__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_RISCV_IRQDEST__PRIV_LEVEL_MASK 0x0010a290 /* */
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#define NV_PPWR_RISCV_IRQDEST_GPTMR 0:0 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_GPTMR_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_GPTMR_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_WDTMR 1:1 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_WDTMR_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_WDTMR_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_MTHD 2:2 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_MTHD_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_MTHD_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_CTXSW 3:3 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_CTXSW_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_CTXSW_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_HALT 4:4 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_HALT_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_HALT_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_EXTERR 5:5 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_EXTERR_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_EXTERR_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_SWGEN0 6:6 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_SWGEN0_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_SWGEN0_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_SWGEN1 7:7 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_SWGEN1_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_SWGEN1_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_EXT 15:8 /* */
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#define NV_PPWR_RISCV_IRQDEST_EXT_CTXE 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_EXT_CTXE_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_CTXE_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_LIMITV 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_EXT_LIMITV_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_LIMITV_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_ECC 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_EXT_ECC_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_ECC_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_SECOND 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_EXT_SECOND_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_SECOND_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_THERM 12:12 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_EXT_THERM_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_THERM_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_MISCIO 13:13 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_EXT_MISCIO_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_MISCIO_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_RTTIMER 14:14 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_EXT_RTTIMER_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_RTTIMER_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_RSVD8 15:15 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_EXT_RSVD8_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_EXT_RSVD8_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_DMA 16:16 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_DMA_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_DMA_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_SHA 17:17 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_SHA_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_SHA_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_MEMERR 18:18 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_MEMERR_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_MEMERR_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_ICD 22:22 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_ICD_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_ICD_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_IOPMP 23:23 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDEST_IOPMP_RISCV 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDEST_IOPMP_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDEST_CORE_MISMATCH 24:24 /* R-IVF */
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#define NV_PPWR_RISCV_IRQDEST_CORE_MISMATCH_RISCV 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_IRQDEST_CORE_MISMATCH_HOST 0x00000001 /* R-I-V */
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#define NV_PPWR_RISCV_IRQTYPE 0x0010b530 /* RWI4R */
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#define NV_PPWR_RISCV_IRQTYPE__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_RISCV_IRQTYPE__PRIV_LEVEL_MASK 0x0010a290 /* */
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#define NV_PPWR_RISCV_IRQTYPE_GPTMR 0:0 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_GPTMR_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_GPTMR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_WDTMR 1:1 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_WDTMR_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_WDTMR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_MTHD 2:2 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_MTHD_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_MTHD_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_CTXSW 3:3 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_CTXSW_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_CTXSW_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_HALT 4:4 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_HALT_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_HALT_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_EXTERR 5:5 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_EXTERR_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_EXTERR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_SWGEN0 6:6 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_SWGEN0_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_SWGEN0_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_SWGEN1 7:7 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_SWGEN1_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_SWGEN1_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT 15:8 /* */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_CTXE 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_CTXE_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_CTXE_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_LIMITV 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_LIMITV_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_LIMITV_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_ECC 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_ECC_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_ECC_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_SECOND 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_SECOND_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_SECOND_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_THERM 12:12 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_THERM_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_THERM_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_MISCIO 13:13 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_MISCIO_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_MISCIO_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_RTTIMER 14:14 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_RTTIMER_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_RTTIMER_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_RSVD8 15:15 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_RSVD8_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_EXT_RSVD8_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_DMA 16:16 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_DMA_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_DMA_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_SHA 17:17 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_SHA_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_SHA_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_MEMERR 18:18 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_MEMERR_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_MEMERR_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_ICD 22:22 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_ICD_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_ICD_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_IOPMP 23:23 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_IOPMP_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_IOPMP_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQTYPE_CORE_MISMATCH 24:24 /* RWIVF */
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#define NV_PPWR_RISCV_IRQTYPE_CORE_MISMATCH_HOST_NORMAL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQTYPE_CORE_MISMATCH_HOST_NONSTALL 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG 0x0010b534 /* RWI4R */
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#define NV_PPWR_RISCV_IRQDELEG__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_RISCV_IRQDELEG__PRIV_LEVEL_MASK 0x0010a290 /* */
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#define NV_PPWR_RISCV_IRQDELEG_GPTMR 0:0 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_GPTMR_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_GPTMR_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_WDTMR 1:1 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_WDTMR_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_WDTMR_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_MTHD 2:2 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_MTHD_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_MTHD_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_CTXSW 3:3 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_CTXSW_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_CTXSW_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_HALT 4:4 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_HALT_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_HALT_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_EXTERR 5:5 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_EXTERR_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_EXTERR_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_SWGEN0 6:6 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_SWGEN0_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_SWGEN0_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_SWGEN1 7:7 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_SWGEN1_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_SWGEN1_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT 15:8 /* */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_CTXE 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_CTXE_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_CTXE_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_LIMITV 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_LIMITV_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_LIMITV_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_ECC 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_ECC_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_ECC_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_SECOND 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_SECOND_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_SECOND_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_THERM 12:12 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_THERM_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_THERM_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_MISCIO 13:13 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_MISCIO_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_MISCIO_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_RTTIMER 14:14 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_RTTIMER_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_RTTIMER_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_RSVD8 15:15 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_RSVD8_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_EXT_RSVD8_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_DMA 16:16 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_DMA_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_DMA_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_SHA 17:17 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_SHA_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_SHA_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_MEMERR 18:18 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_MEMERR_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_MEMERR_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_ICD 22:22 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_ICD_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_ICD_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_IOPMP 23:23 /* RWIVF */
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#define NV_PPWR_RISCV_IRQDELEG_IOPMP_RISCV_MEIP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IRQDELEG_IOPMP_RISCV_SEIP 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IRQDELEG_CORE_MISMATCH 24:24 /* R-IVF */
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#define NV_PPWR_RISCV_IRQDELEG_CORE_MISMATCH_RISCV_MEIP 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IRQDELEG_CORE_MISMATCH_RISCV_SEIP 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_BOOT_VECTOR_HI 0x0010b384 /* RWI4R */
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#define NV_PPWR_RISCV_BOOT_VECTOR_HI__PRIV_LEVEL_MASK 0x0010b310 /* */
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#define NV_PPWR_RISCV_BOOT_VECTOR_HI_VECTOR 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_BOOT_VECTOR_HI_VECTOR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BOOT_VECTOR_LO 0x0010b380 /* RWI4R */
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#define NV_PPWR_RISCV_BOOT_VECTOR_LO__PRIV_LEVEL_MASK 0x0010b310 /* */
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#define NV_PPWR_RISCV_BOOT_VECTOR_LO_VECTOR 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_BOOT_VECTOR_LO_VECTOR_INIT 0x00080000 /* RWI-V */
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#define NV_PPWR_RISCV_CPUCTL 0x0010b388 /* RWI4R */
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#define NV_PPWR_RISCV_CPUCTL__PRIV_LEVEL_MASK 0x0010b308 /* */
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#define NV_PPWR_RISCV_CPUCTL_STARTCPU 0:0 /* -WIVF */
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#define NV_PPWR_RISCV_CPUCTL_STARTCPU_FALSE 0x00000000 /* -WI-V */
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#define NV_PPWR_RISCV_CPUCTL_STARTCPU_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_RISCV_CPUCTL_HALTED 4:4 /* R-IVF */
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#define NV_PPWR_RISCV_CPUCTL_HALTED_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_CPUCTL_STOPPED 5:5 /* R-IVF */
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#define NV_PPWR_RISCV_CPUCTL_STOPPED_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_CPUCTL_ACTIVE_STAT 7:7 /* R-IVF */
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#define NV_PPWR_RISCV_CPUCTL_ACTIVE_STAT_INACTIVE 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_CPUCTL_ACTIVE_STAT_ACTIVE 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_NVCONFIG 0x0010b390 /* RWI4R */
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#define NV_PPWR_RISCV_NVCONFIG__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_RISCV_NVCONFIG__PRIV_LEVEL_MASK 0x0010b30c /* */
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#define NV_PPWR_RISCV_NVCONFIG_WR_ALLOC_EN 0:0 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_WR_ALLOC_EN_RST 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_LD_MERGE_EN 1:1 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_LD_MERGE_EN_RST 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_ST_WAIT_CSB_ACK_EN 2:2 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_ST_WAIT_CSB_ACK_EN_RST 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_ST_WAIT_FBIF_ACK_EN 3:3 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_ST_WAIT_FBIF_ACK_EN_RST 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_VB_FWD_EN 4:4 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_VB_FWD_EN_RST 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_WRITE_BACK_EN 6:6 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_WRITE_BACK_EN_RST 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_ST_COMMIT_ISSUE_EN 7:7 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_ST_COMMIT_ISSUE_EN_RST 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_TLB_FIX_SIZE_EN 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_NVCONFIG_TLB_FIX_SIZE_EN_RST 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_NVCONFIG_SYSOP_CSR_EN 9:9 /* R-IVF */
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#define NV_PPWR_RISCV_NVCONFIG_SYSOP_CSR_EN_RST 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_NVCONFIG_FENCE_FBFLUSH_EN 10:10 /* R-IVF */
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#define NV_PPWR_RISCV_NVCONFIG_FENCE_FBFLUSH_EN_RST 0x00000001 /* R-I-V */
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#define NV_PPWR_RISCV_CG 0x0010b398 /* RWI4R */
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#define NV_PPWR_RISCV_CG__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_RISCV_CG__PRIV_LEVEL_MASK 0x0010b304 /* */
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#define NV_PPWR_RISCV_CG_SLCG 0:0 /* RWIVF */
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#define NV_PPWR_RISCV_CG_SLCG_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_CG_SLCG_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_CG_SLCG_DISABLED 0 /* */
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#define NV_PPWR_RISCV_CG_SLCG_ENABLED 1 /* */
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#define NV_PPWR_RISCV_CG_SLCG__PROD 1 /* */
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#define NV_PPWR_RISCV_CG_CORE_SLCG 1:1 /* RWIVF */
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#define NV_PPWR_RISCV_CG_CORE_SLCG_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_CG_CORE_SLCG_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_CG_RSVD 31:2 /* R-IVF */
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#define NV_PPWR_RISCV_CG_RSVD_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_CYA 0x0010b39c /* RWI4R */
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#define NV_PPWR_RISCV_CYA__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_RISCV_CYA__PRIV_LEVEL_MASK 0x0010b304 /* */
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#define NV_PPWR_RISCV_CYA_RSVD 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_CYA_RSVD_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL 0x0010b3c8 /* RW-4R */
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#define NV_PPWR_RISCV_DBGCTL__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_RISCV_DBGCTL__PRIV_LEVEL_MASK 0x0010b314 /* */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_STOP 0:0 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_STOP_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_STOP_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RUN 1:1 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RUN_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RUN_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_RSVD1 2:2 /* R-IVF */
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#define NV_PPWR_RISCV_DBGCTL_RSVD1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_STEP 3:3 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_STEP_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_STEP_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_J 4:4 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_J_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_J_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_EMASK 5:5 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_EMASK_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_EMASK_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RREG 6:6 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RREG_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RREG_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_WREG 7:7 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_WREG_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_WREG_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RDM 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RDM_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RDM_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_WDM 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_WDM_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_WDM_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RSTAT 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RSTAT_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RSTAT_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_IBRKPT 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_IBRKPT_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_IBRKPT_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RCSR 12:12 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RCSR_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RCSR_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_WCSR 13:13 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_WCSR_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_WCSR_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RPC 14:14 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RPC_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RPC_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RFREG 15:15 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RFREG_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_RFREG_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_WFREG 16:16 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_WFREG_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_ICD_CMDWL_WFREG_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_RSVD 29:17 /* R-IVF */
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#define NV_PPWR_RISCV_DBGCTL_RSVD_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_DBGCTL_START_IN_ICD 30:30 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_START_IN_ICD_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_START_IN_ICD_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_SINGLE_STEP_MODE 31:31 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_SINGLE_STEP_MODE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_SINGLE_STEP_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK 0x0010b3cc /* RW-4R */
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#define NV_PPWR_RISCV_DBGCTL_LOCK__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_RISCV_DBGCTL_LOCK__PRIV_LEVEL_MASK 0x0010b314 /* */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_STOP 0:0 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_STOP_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_STOP_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RUN 1:1 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RUN_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RUN_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_RSVD1 2:2 /* R-IVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_RSVD1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_STEP 3:3 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_STEP_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_STEP_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_J 4:4 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_J_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_J_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_EMASK 5:5 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_EMASK_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_EMASK_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RREG 6:6 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RREG_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RREG_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WREG 7:7 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WREG_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WREG_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RDM 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RDM_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RDM_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WDM 9:9 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WDM_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WDM_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RSTAT 10:10 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RSTAT_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RSTAT_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_IBRKPT 11:11 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_IBRKPT_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_IBRKPT_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RCSR 12:12 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RCSR_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RCSR_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WCSR 13:13 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WCSR_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WCSR_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RPC 14:14 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RPC_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RPC_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RFREG 15:15 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RFREG_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_RFREG_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WFREG 16:16 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WFREG_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_ICD_CMDWL_WFREG_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_RSVD 30:17 /* R-IVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_RSVD_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_SINGLE_STEP_MODE 31:31 /* RWIVF */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_SINGLE_STEP_MODE_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DBGCTL_LOCK_SINGLE_STEP_MODE_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD 0x0010b3d0 /* RW-4R */
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#define NV_PPWR_RISCV_ICD_CMD__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_RISCV_ICD_CMD_OPC 4:0 /* RWIVF */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_STOP 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_RUN 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_STEP 0x00000005 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_J 0x00000006 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_EMASK 0x00000007 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_RREG 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_WREG 0x00000009 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_RDM 0x0000000a /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_WDM 0x0000000b /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_RSTAT 0x0000000e /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_RCSR 0x00000010 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_WCSR 0x00000011 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_RPC 0x00000012 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_RFREG 0x00000013 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_OPC_WFREG 0x00000014 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_SZ 7:6 /* RWIVF */
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#define NV_PPWR_RISCV_ICD_CMD_SZ_B 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_ICD_CMD_SZ_HW 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_SZ_W 0x00000002 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_SZ_DW 0x00000003 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX 12:8 /* RWIVF */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG0 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG1 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG2 0x00000002 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG3 0x00000003 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG4 0x00000004 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG5 0x00000005 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG6 0x00000006 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG7 0x00000007 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG8 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG9 0x00000009 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG10 0x0000000a /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG11 0x0000000b /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG12 0x0000000c /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG13 0x0000000d /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG14 0x0000000e /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG15 0x0000000f /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG16 0x00000010 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG17 0x00000011 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG18 0x00000012 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG19 0x00000013 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG20 0x00000014 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG21 0x00000015 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG22 0x00000016 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG23 0x00000017 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG24 0x00000018 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG25 0x00000019 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG26 0x0000001a /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG27 0x0000001b /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG28 0x0000001c /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG29 0x0000001e /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG30 0x0000001e /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_REG31 0x0000001f /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_RSTAT3 0x00000003 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_IDX_RSTAT4 0x00000004 /* RW--V */
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#define NV_PPWR_RISCV_ICD_CMD_ERROR 14:14 /* R-IVF */
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#define NV_PPWR_RISCV_ICD_CMD_ERROR_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_CMD_ERROR_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_ICD_CMD_BUSY 15:15 /* R-IVF */
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#define NV_PPWR_RISCV_ICD_CMD_BUSY_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_ICD_CMD_BUSY_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_CMD_PARM 31:16 /* RWIVF */
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#define NV_PPWR_RISCV_ICD_CMD_PARM_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_ICD_ADDR0 0x0010b3d4 /* RW-4R */
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#define NV_PPWR_RISCV_ICD_ADDR0__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_RISCV_ICD_ADDR0_ADDR 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_ICD_ADDR0_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_ICD_ADDR1 0x0010b3d8 /* RW-4R */
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#define NV_PPWR_RISCV_ICD_ADDR1__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_RISCV_ICD_ADDR1_ADDR 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_ICD_ADDR1_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_ICD_WDATA0 0x0010b3dc /* RW-4R */
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#define NV_PPWR_RISCV_ICD_WDATA0__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_RISCV_ICD_WDATA0_DATA 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_ICD_WDATA0_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_ICD_WDATA1 0x0010b3e0 /* RW-4R */
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#define NV_PPWR_RISCV_ICD_WDATA1__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_RISCV_ICD_WDATA1_DATA 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_ICD_WDATA1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_ICD_RDATA0 0x0010b3e4 /* R--4R */
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#define NV_PPWR_RISCV_ICD_RDATA0__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_RISCV_ICD_RDATA0_DATA 31:0 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_ROB_FULL 0:0 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_IFU_INSTBUF_FULL 1:1 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_IFU_LINEFILL_FULL 2:2 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_LSU_STB_FULL 3:3 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_LSU_MEM_WACK_FULL 4:4 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_LSU_IO_WACK_FULL 5:5 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_LSU_LINEFILL_FULL 6:6 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_LSU_VICBUF_FULL 7:7 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_LSU_CB_FULL 8:8 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_ALU_RS_FULL 9:9 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_IMD_RS_FULL 10:10 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_FPU_RS_FULL 11:11 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_IOWR_INFLIGHT 23:16 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT0_MEMWR_INFLIGHT 31:24 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_SSINT 1:1 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_SSINT_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_SSINT_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_MSINT 3:3 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_MSINT_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_MSINT_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_STINT 5:5 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_STINT_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_STINT_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_MTINT 7:7 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_MTINT_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_MTINT_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_SEINT 9:9 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_SEINT_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_SEINT_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_MEINT 11:11 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_MEINT_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT3_MEINT_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE 1:0 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE_ACTIVE 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE_INACTIVE 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT4_ICD_STATE_ICD 0x00000002 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT4_RS0 3:2 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT4_RS0_VALUE 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT4_TRIGGER_HIT_INDEX 10:4 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT4_RS1 31:11 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA0_RSTAT4_RS1_VALUE 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1 0x0010b3e8 /* R--4R */
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#define NV_PPWR_RISCV_ICD_RDATA1__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_RISCV_ICD_RDATA1_DATA 31:0 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_IAMA 0:0 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_IAMA_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_IAMA_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_IFAULT 1:1 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_IFAULT_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_IFAULT_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_ILL 2:2 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_ILL_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_ILL_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_BKPT 3:3 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_BKPT_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_BKPT_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_LAMA 4:4 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_LAMA_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_LAMA_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_LFAULT 5:5 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_LFAULT_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_LFAULT_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_SAMA 6:6 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_SAMA_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_SAMA_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_SFAULT 7:7 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_SFAULT_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_SFAULT_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_UCALL 8:8 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_UCALL_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_UCALL_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_SCALL 9:9 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_SCALL_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_SCALL_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_MCALL 11:11 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_MCALL_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_MCALL_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_IPFAULT 12:12 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_IPFAULT_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_IPFAULT_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_LPFAULT 13:13 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_LPFAULT_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_LPFAULT_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_SPFAULT 15:15 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_SPFAULT_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_SPFAULT_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_U_SINGLE_STEP 28:28 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_U_SINGLE_STEP_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_U_SINGLE_STEP_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_S_SINGLE_STEP 29:29 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_S_SINGLE_STEP_ENTER_ICD 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT3_S_SINGLE_STEP_EXPT 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT4_RS 31:0 /* R--VF */
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#define NV_PPWR_RISCV_ICD_RDATA1_RSTAT4_RS_VALUE 0x00000000 /* R---V */
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#define NV_PPWR_RISCV_RPC 0x0010b3ec /* R--4R */
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#define NV_PPWR_RISCV_RPC__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_RISCV_RPC_PC_LO 31:0 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0 0x0010b3f0 /* R--4R */
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#define NV_PPWR_RISCV_RSTAT0__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_RISCV_RSTAT0_ROB_FULL 0:0 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0_IFU_INSTBUF_FULL 1:1 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0_IFU_LINEFILL_FULL 2:2 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0_LSU_STB_FULL 3:3 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0_LSU_MEM_WACK_FULL 4:4 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0_LSU_IO_WACK_FULL 5:5 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0_LSU_LINEFILL_FULL 6:6 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0_LSU_VICBUF_FULL 7:7 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0_LSU_CB_FULL 8:8 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0_ALU_RS_FULL 9:9 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0_IMD_RS_FULL 10:10 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0_FPU_RS_FULL 11:11 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0_IOWR_INFLIGHT 23:16 /* R--VF */
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#define NV_PPWR_RISCV_RSTAT0_MEMWR_INFLIGHT 31:24 /* R--VF */
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#define NV_PPWR_RISCV_TRACECTL 0x0010b400 /* RW-4R */
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#define NV_PPWR_RISCV_TRACECTL__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_RISCV_TRACECTL__PRIV_LEVEL_MASK 0x0010b318 /* */
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#define NV_PPWR_RISCV_TRACECTL_LOW_THSHD 7:0 /* RWIVF */
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#define NV_PPWR_RISCV_TRACECTL_LOW_THSHD_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_TRACECTL_HIGH_THSHD 15:8 /* RWIVF */
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#define NV_PPWR_RISCV_TRACECTL_HIGH_THSHD_INIT 0x000000ff /* RWI-V */
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#define NV_PPWR_RISCV_TRACECTL_UMODE_ENABLE 20:20 /* RWIVF */
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#define NV_PPWR_RISCV_TRACECTL_UMODE_ENABLE_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_TRACECTL_UMODE_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_TRACECTL_SMODE_ENABLE 21:21 /* RWIVF */
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#define NV_PPWR_RISCV_TRACECTL_SMODE_ENABLE_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_TRACECTL_SMODE_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_TRACECTL_MMODE_ENABLE 23:23 /* RWIVF */
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#define NV_PPWR_RISCV_TRACECTL_MMODE_ENABLE_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_TRACECTL_MMODE_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_TRACECTL_MODE 25:24 /* RWIVF */
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#define NV_PPWR_RISCV_TRACECTL_MODE_FULL 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_TRACECTL_MODE_REDUCED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_TRACECTL_MODE_STACK 0x00000002 /* RW--V */
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#define NV_PPWR_RISCV_TRACECTL_BELOW_LO 27:27 /* RWIVF */
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#define NV_PPWR_RISCV_TRACECTL_BELOW_LO_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_TRACECTL_ABOVE_HI 28:28 /* RWIVF */
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#define NV_PPWR_RISCV_TRACECTL_ABOVE_HI_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_TRACECTL_INTR_ENABLE 29:29 /* R-IVF */
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#define NV_PPWR_RISCV_TRACECTL_INTR_ENABLE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_TRACECTL_INTR_ENABLE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_TRACECTL_FULL 30:30 /* RWIVF */
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#define NV_PPWR_RISCV_TRACECTL_FULL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_TRACECTL_EMPTY 31:31 /* RWIVF */
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#define NV_PPWR_RISCV_TRACECTL_EMPTY_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_TRACE_RDIDX 0x0010b404 /* RW-4R */
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#define NV_PPWR_RISCV_TRACE_RDIDX__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_RISCV_TRACE_RDIDX__PRIV_LEVEL_MASK 0x0010b318 /* */
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#define NV_PPWR_RISCV_TRACE_RDIDX_RDIDX 7:0 /* RWIVF */
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#define NV_PPWR_RISCV_TRACE_RDIDX_RDIDX_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_TRACE_RDIDX_RSVD0 15:8 /* R-IVF */
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#define NV_PPWR_RISCV_TRACE_RDIDX_RSVD0_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_TRACE_RDIDX_MAXIDX 23:16 /* R-IVF */
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#define NV_PPWR_RISCV_TRACE_RDIDX_MAXIDX_INIT 0x0000003f /* R-I-V */
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#define NV_PPWR_RISCV_TRACE_RDIDX_RSVD1 31:24 /* R-IVF */
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#define NV_PPWR_RISCV_TRACE_RDIDX_RSVD1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_TRACE_WTIDX 0x0010b408 /* RW-4R */
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#define NV_PPWR_RISCV_TRACE_WTIDX__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_RISCV_TRACE_WTIDX__PRIV_LEVEL_MASK 0x0010b318 /* */
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#define NV_PPWR_RISCV_TRACE_WTIDX_WTIDX 31:24 /* RWIVF */
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#define NV_PPWR_RISCV_TRACE_WTIDX_WTIDX_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_TRACE_WTIDX_RSVD1 23:0 /* R-IVF */
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#define NV_PPWR_RISCV_TRACE_WTIDX_RSVD1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_TRACEPC_HI 0x0010b410 /* RW-4R */
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#define NV_PPWR_RISCV_TRACEPC_HI__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_RISCV_TRACEPC_HI__PRIV_LEVEL_MASK 0x0010b318 /* */
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#define NV_PPWR_RISCV_TRACEPC_HI_PC 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_TRACEPC_HI_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_TRACEPC_LO 0x0010b40c /* RW-4R */
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#define NV_PPWR_RISCV_TRACEPC_LO__DEVICE_MAP 0x00000009 /* */
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#define NV_PPWR_RISCV_TRACEPC_LO__PRIV_LEVEL_MASK 0x0010b318 /* */
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#define NV_PPWR_RISCV_TRACEPC_LO_PC 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_TRACEPC_LO_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_MTIMECMP_HI 0x0010b3c4 /* RWI4R */
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#define NV_PPWR_RISCV_MTIMECMP_HI__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_RISCV_MTIMECMP_HI__PRIV_LEVEL_MASK 0x0010b300 /* */
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#define NV_PPWR_RISCV_MTIMECMP_HI_VALUE 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_MTIMECMP_HI_VALUE_INIT 0xffffffff /* RWI-V */
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#define NV_PPWR_RISCV_MTIMECMP_LO 0x0010b3c0 /* RWI4R */
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#define NV_PPWR_RISCV_MTIMECMP_LO__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_RISCV_MTIMECMP_LO__PRIV_LEVEL_MASK 0x0010b300 /* */
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#define NV_PPWR_RISCV_MTIMECMP_LO_VALUE 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_MTIMECMP_LO_VALUE_INIT 0xffffffff /* RWI-V */
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#define NV_PPWR_RISCV_INTR_STATUS 0x0010b394 /* R-I4R */
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#define NV_PPWR_RISCV_INTR_STATUS__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_RISCV_INTR_STATUS__PRIV_LEVEL_MASK 0x0010b300 /* */
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#define NV_PPWR_RISCV_INTR_STATUS_S_SOFTWARE_INTR 5:5 /* R-IVF */
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#define NV_PPWR_RISCV_INTR_STATUS_S_SOFTWARE_INTR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_INTR_STATUS_S_EXTERNAL_INTR 4:4 /* R-IVF */
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#define NV_PPWR_RISCV_INTR_STATUS_S_EXTERNAL_INTR_INT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_INTR_STATUS_S_TIMER_INTR 3:3 /* R-IVF */
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#define NV_PPWR_RISCV_INTR_STATUS_S_TIMER_INTR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_INTR_STATUS_SOFTWARE_INTR 2:2 /* R-IVF */
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#define NV_PPWR_RISCV_INTR_STATUS_SOFTWARE_INTR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_INTR_STATUS_M_SOFTWARE_INTR 2:2 /* */
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#define NV_PPWR_RISCV_INTR_STATUS_M_SOFTWARE_INTR_INIT 0 /* */
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#define NV_PPWR_RISCV_INTR_STATUS_EXTERNAL_INTR 1:1 /* R-IVF */
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#define NV_PPWR_RISCV_INTR_STATUS_EXTERNAL_INTR_INT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_INTR_STATUS_M_EXTERNAL_INTR 1:1 /* */
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#define NV_PPWR_RISCV_INTR_STATUS_M_EXTERNAL_INTR_INT 0 /* */
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#define NV_PPWR_RISCV_INTR_STATUS_TIMER_INTR 0:0 /* R-IVF */
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#define NV_PPWR_RISCV_INTR_STATUS_TIMER_INTR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_INTR_STATUS_M_TIMER_INTR 0:0 /* */
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#define NV_PPWR_RISCV_INTR_STATUS_M_TIMER_INTR_INIT 0 /* */
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#define NV_PPWR_RISCV_MSIP 0x0010b38c /* RWI4R */
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#define NV_PPWR_RISCV_MSIP__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_RISCV_MSIP__PRIV_LEVEL_MASK 0x0010b31c /* */
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#define NV_PPWR_RISCV_MSIP_VLD 0:0 /* RWIVF */
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#define NV_PPWR_RISCV_MSIP_VLD_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_MSIP_VLD_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_PRIV_ERR_STAT 0x0010b500 /* RWI4R */
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#define NV_PPWR_RISCV_PRIV_ERR_STAT__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_RISCV_PRIV_ERR_STAT__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_RISCV_PRIV_ERR_STAT_VALID 31:31 /* RWIVF */
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#define NV_PPWR_RISCV_PRIV_ERR_STAT_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_PRIV_ERR_STAT_VALID_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_PRIV_ERR_STAT_RESERVED 30:0 /* R-IVF */
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#define NV_PPWR_RISCV_PRIV_ERR_STAT_RESERVED_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_PRIV_ERR_INFO 0x0010b504 /* R-I4R */
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#define NV_PPWR_RISCV_PRIV_ERR_INFO__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_RISCV_PRIV_ERR_INFO__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_RISCV_PRIV_ERR_INFO_ERROR_INFO 31:0 /* R-IVF */
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#define NV_PPWR_RISCV_PRIV_ERR_INFO_ERROR_INFO_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_PRIV_ERR_ADDR 0x0010b508 /* R-I4R */
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#define NV_PPWR_RISCV_PRIV_ERR_ADDR__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_RISCV_PRIV_ERR_ADDR__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_RISCV_PRIV_ERR_ADDR_ADDR 31:0 /* R-IVF */
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#define NV_PPWR_RISCV_PRIV_ERR_ADDR_ADDR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_PRIV_ERR_ADDR_HI 0x0010b50c /* R-I4R */
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#define NV_PPWR_RISCV_PRIV_ERR_ADDR_HI__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_RISCV_PRIV_ERR_ADDR_HI__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_RISCV_PRIV_ERR_ADDR_HI_ADDR 31:0 /* R-IVF */
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#define NV_PPWR_RISCV_PRIV_ERR_ADDR_HI_ADDR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_HUB_ERR_STAT 0x0010b510 /* RWI4R */
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#define NV_PPWR_RISCV_HUB_ERR_STAT__DEVICE_MAP 0x00000002 /* */
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#define NV_PPWR_RISCV_HUB_ERR_STAT__PRIV_LEVEL_MASK 0x0010a28c /* */
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#define NV_PPWR_RISCV_HUB_ERR_STAT_VALID 31:31 /* RWIVF */
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#define NV_PPWR_RISCV_HUB_ERR_STAT_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_HUB_ERR_STAT_VALID_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_HUB_ERR_STAT_RESERVED 30:0 /* RWIVF */
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#define NV_PPWR_RISCV_HUB_ERR_STAT_RESERVED_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_INDEX 0x0010b590 /* RWI4R */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_INDEX__DEVICE_MAP 0x0000000d /* */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_INDEX_INDEX 4:0 /* RWIVF */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_INDEX_INDEX_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_ADDR_VALID 0x0010b594 /* RWI4R */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_ADDR_VALID__DEVICE_MAP 0x0000000d /* */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_ADDR_VALID_ADDR 17:0 /* RWIVF */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_ADDR_VALID_ADDR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_ADDR_VALID_VALID 31:31 /* RWIVF */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_ADDR_VALID_VALID_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_DATA 0x0010b598 /* RWI4R */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_DATA__DEVICE_MAP 0x0000000d /* */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_DATA_DATA 15:0 /* RWIVF */
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#define NV_PPWR_RISCV_IROM_PATCH_CAM_DATA_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IROM_PATCH_SECURE 0x0010b59c /* RWI4R */
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#define NV_PPWR_RISCV_IROM_PATCH_SECURE__DEVICE_MAP 0x0000000d /* */
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#define NV_PPWR_RISCV_IROM_PATCH_SECURE_IPATCH_LOCK 0:0 /* RWIVF */
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#define NV_PPWR_RISCV_IROM_PATCH_SECURE_IPATCH_LOCK_INIT 0x00000001 /* R-I-V */
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#define NV_PPWR_RISCV_IOPMP_INDEX 0x0010b5b0 /* RWI4R */
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#define NV_PPWR_RISCV_IOPMP_INDEX__DEVICE_MAP 0x0000000e /* */
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#define NV_PPWR_RISCV_IOPMP_INDEX__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_IOPMP_INDEX_VAL 4:0 /* RWIVF */
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#define NV_PPWR_RISCV_IOPMP_INDEX_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IOPMP_CFG 0x0010b5b4 /* RWI4R */
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#define NV_PPWR_RISCV_IOPMP_CFG__DEVICE_MAP 0x0000000e /* */
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#define NV_PPWR_RISCV_IOPMP_CFG__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_READ 0:0 /* RWIVF */
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#define NV_PPWR_RISCV_IOPMP_CFG_READ_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IOPMP_CFG_READ_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IOPMP_CFG_WRITE 1:1 /* RWIVF */
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#define NV_PPWR_RISCV_IOPMP_CFG_WRITE_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IOPMP_CFG_WRITE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER 15:4 /* RWIVF */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_ALL_MASTERS_ENABLED 0x00000ff7 /* RWI-V */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_FBDMA 4:4 /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_FBDMA_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_FBDMA_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_CPDMA 5:5 /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_CPDMA_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_CPDMA_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_SHA 6:6 /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_SHA_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_SHA_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_PMB(i) (8+(i)):(8+(i)) /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_PMB__SIZE_1 8 /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_PMB_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_MASTER_PMB_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IOPMP_CFG_LOCK 31:31 /* RWIVF */
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#define NV_PPWR_RISCV_IOPMP_CFG_LOCK_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IOPMP_CFG_LOCK_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IOPMP_ADDR_HI 0x0010b5bc /* RWI4R */
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#define NV_PPWR_RISCV_IOPMP_ADDR_HI__DEVICE_MAP 0x0000000e /* */
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#define NV_PPWR_RISCV_IOPMP_ADDR_HI__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_IOPMP_ADDR_HI_VAL 28:0 /* RWIVF */
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#define NV_PPWR_RISCV_IOPMP_ADDR_HI_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IOPMP_ADDR_LO 0x0010b5b8 /* RWI4R */
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#define NV_PPWR_RISCV_IOPMP_ADDR_LO__DEVICE_MAP 0x0000000e /* */
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#define NV_PPWR_RISCV_IOPMP_ADDR_LO__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_IOPMP_ADDR_LO_VAL 31:0 /* */
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#define NV_PPWR_RISCV_IOPMP_ADDR_LO_ABOVE1K 31:7 /* RWIVF */
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#define NV_PPWR_RISCV_IOPMP_ADDR_LO_ABOVE1K_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IOPMP_ADDR_LO_1K 6:0 /* R-IVF */
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#define NV_PPWR_RISCV_IOPMP_ADDR_LO_1K_INIT 0x0000007f /* R-I-V */
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#define NV_PPWR_RISCV_IOPMP_MODE(i) (0x0010b5c0+(i)*4) /* RWI4A */
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#define NV_PPWR_RISCV_IOPMP_MODE__SIZE_1 2 /* */
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#define NV_PPWR_RISCV_IOPMP_MODE__DEVICE_MAP 0x0000000e /* */
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#define NV_PPWR_RISCV_IOPMP_MODE__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_IOPMP_MODE_VAL 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_IOPMP_MODE_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IOPMP_MODE_VAL_ENTRY(i) (1+2*(i)):(2*(i)) /* */
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#define NV_PPWR_RISCV_IOPMP_MODE_VAL_ENTRY__SIZE_1 16 /* */
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#define NV_PPWR_RISCV_IOPMP_MODE_VAL_ENTRY_OFF 0x00000000 /* */
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#define NV_PPWR_RISCV_IOPMP_MODE_VAL_ENTRY_NAPOT 0x00000003 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_STAT 0x0010b5e0 /* RWI4R */
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#define NV_PPWR_RISCV_IOPMP_ERR_STAT__DEVICE_MAP 0x0000000e /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_STAT__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_STAT_VALID 31:31 /* RWIVF */
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#define NV_PPWR_RISCV_IOPMP_ERR_STAT_VALID_TURE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_IOPMP_ERR_STAT_VALID_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO 0x0010b5e4 /* R-I4R */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO__DEVICE_MAP 0x0000000e /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_MASTER 3:0 /* R-IVF */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_MASTER_FBDMA 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_MASTER_CPDMA 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_MASTER_SHA 0x00000002 /* R---V */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB0 0x00000004 /* R---V */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB1 0x00000005 /* R---V */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB2 0x00000006 /* R---V */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB3 0x00000007 /* R---V */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB4 0x00000008 /* R---V */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB5 0x00000009 /* R---V */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB6 0x0000000a /* R---V */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_MASTER_PMB7 0x0000000b /* R---V */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_READ 4:4 /* R-IVF */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_READ_TRUE 0x00000001 /* R---V */
|
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_READ_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_ENTRY 21:16 /* R-IVF */
|
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#define NV_PPWR_RISCV_IOPMP_ERR_INFO_ENTRY_INIT 0x00000000 /* R-I-V */
|
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#define NV_PPWR_RISCV_IOPMP_ERR_ADDR_HI 0x0010b5ec /* R-I4R */
|
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#define NV_PPWR_RISCV_IOPMP_ERR_ADDR_HI__DEVICE_MAP 0x0000000e /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_ADDR_HI__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_ADDR_HI_ADDR 31:0 /* R-IVF */
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#define NV_PPWR_RISCV_IOPMP_ERR_ADDR_HI_ADDR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IOPMP_ERR_ADDR_LO 0x0010b5e8 /* R-I4R */
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#define NV_PPWR_RISCV_IOPMP_ERR_ADDR_LO__DEVICE_MAP 0x0000000e /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_ADDR_LO__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_ADDR_LO_ADDR 31:0 /* R-IVF */
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#define NV_PPWR_RISCV_IOPMP_ERR_ADDR_LO_ADDR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN 0x0010b5f0 /* RWI4R */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN__DEVICE_MAP 0x0000000e /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER 11:0 /* RWIVF */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_ALL_MASTERS_ENABLED 0x00000fff /* RWI-V */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_FBDMA 0:0 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_FBDMA_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_FBDMA_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_CPDMA 1:1 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_CPDMA_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_CPDMA_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_SHA 2:2 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_SHA_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_SHA_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB(i) (4+(i)):(4+(i)) /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB__SIZE_1 8 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_IOPMP_ERR_CAPEN_MASTER_PMB_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_SCPDMATRFMOFFS 0x0010b570 /* RWI4R */
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#define NV_PPWR_RISCV_SCPDMATRFMOFFS__DEVICE_MAP 0x00000010 /* */
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#define NV_PPWR_RISCV_SCPDMATRFMOFFS__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_SCPDMATRFMOFFS_OFFS 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_SCPDMATRFMOFFS_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_SCPDMATRFCMD 0x0010b574 /* RWI4R */
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#define NV_PPWR_RISCV_SCPDMATRFCMD__DEVICE_MAP 0x00000010 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_SUPPRESS 2:2 /* RWIVF */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_SUPPRESS_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_SUPPRESS_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_SHORTCUT 3:3 /* RWIVF */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_SHORTCUT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_SHORTCUT_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_IMEM 4:4 /* RWIVF */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_IMEM_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_IMEM_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_WRITE 5:5 /* RWIVF */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_WRITE_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_WRITE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_GPR 8:6 /* RWIVF */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_GPR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_SIZE 8:6 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_SIZE_16B 2 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_SIZE_32B 3 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_SIZE_64B 4 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_SIZE_128B 5 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_SIZE_256B 6 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_CCI_EX 15:15 /* RWIVF */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_CCI_EX_SCPDMA 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_CCI_EX_CCI 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_CCI_CMD 31:16 /* RWIVF */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_CCI_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_RY 19:16 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_RX_OR_IMM 25:20 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE 31:26 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_NOP 0 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_MOV 1 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_PUSH 2 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_FETCH 3 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_RAND 4 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_LOAD_TRACE0 5 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_LOOP_TRACE0 6 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_LOAD_TRACE1 7 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_LOOP_TRACE1 8 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_CHMOD 10 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_XOR 11 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_ADD 12 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_AND 13 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_BSWAP 14 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_CMAC_SK 15 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_SECRET 16 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_KEY 17 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_RKEY10 18 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_RKEY1 19 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_ENCRYPT 20 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_DECRYPT 21 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_COMPARE_SIG 22 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_ENCRYPT_SIG 23 /* */
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#define NV_PPWR_RISCV_SCPDMATRFCMD_OPCODE_FORGET_SIG 24 /* */
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#define NV_PPWR_RISCV_SCPDMAPOLL 0x0010b578 /* RWI4R */
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#define NV_PPWR_RISCV_SCPDMAPOLL__DEVICE_MAP 0x00000010 /* */
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#define NV_PPWR_RISCV_SCPDMAPOLL__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_SCPDMAPOLL_DMA_ACTIVE 0:0 /* R-IVF */
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#define NV_PPWR_RISCV_SCPDMAPOLL_DMA_ACTIVE_IDLE 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_SCPDMAPOLL_DMA_ACTIVE_ACTIVE 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_SCPDMAPOLL_ERROR_CLR 4:4 /* -WXVF */
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#define NV_PPWR_RISCV_SCPDMAPOLL_ERROR_CODE 9:8 /* R-IVF */
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#define NV_PPWR_RISCV_SCPDMAPOLL_ERROR_CODE_NO_ERROR 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_SCPDMAPOLL_ERROR_CODE_NOT_SIZE_ALIGNED 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_SCPDMAPOLL_ERROR_CODE_SECRET_NOT_ALLOWED 0x00000002 /* R---V */
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#define NV_PPWR_RISCV_SCPDMAPOLL_WCOUNT 19:16 /* R-IVF */
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#define NV_PPWR_RISCV_SCPDMAPOLL_WCOUNT_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_SCPDMAPOLL_RCOUNT 23:20 /* R-IVF */
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#define NV_PPWR_RISCV_SCPDMAPOLL_RCOUNT_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_SCPDMAPOLL_REQQ_NUM 27:24 /* R-IVF */
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#define NV_PPWR_RISCV_SCPDMAPOLL_REQQ_NUM_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_SCPDMAPOLL_REQQ_DEPTH 31:28 /* R-XVF */
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#define NV_PPWR_RISCV_SCP_SECRET_MASK(i) (0x0010b580+(i)*4) /* RWI4A */
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#define NV_PPWR_RISCV_SCP_SECRET_MASK__SIZE_1 2 /* */
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#define NV_PPWR_RISCV_SCP_SECRET_MASK__DEVICE_MAP 0x00000008 /* */
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#define NV_PPWR_RISCV_SCP_SECRET_MASK__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_SCP_SECRET_MASK_VAL 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_SCP_SECRET_MASK_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_SCP_SECRET_MASK_LOCK(i) (0x0010b588+(i)*4) /* RWI4A */
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#define NV_PPWR_RISCV_SCP_SECRET_MASK_LOCK__SIZE_1 2 /* */
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#define NV_PPWR_RISCV_SCP_SECRET_MASK_LOCK__DEVICE_MAP 0x00000008 /* */
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#define NV_PPWR_RISCV_SCP_SECRET_MASK_LOCK__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_SCP_SECRET_MASK_LOCK_VAL 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_SCP_SECRET_MASK_LOCK_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BR_RETCODE 0x0010b65c /* RWI4R */
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#define NV_PPWR_RISCV_BR_RETCODE_RESULT 1:0 /* RWIVF */
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#define NV_PPWR_RISCV_BR_RETCODE_RESULT_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BR_RETCODE_RESULT_RUNNING 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_RESULT_FAIL 0x00000002 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_RESULT_PASS 0x00000003 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE 7:2 /* RWIVF */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_ENTRY 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_INIT_DEVICE 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_LOAD_PUBLIC_KEY 0x00000002 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_LOAD_PKC_BOOT_PARAM 0x00000003 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_SHA_MANIFEST 0x00000004 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_VERIFY_MANIFEST_SIGNATURE 0x00000005 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_DECRYPT_MANIFEST 0x00000006 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_SANITIZE_MANIFEST 0x00000007 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_LOAD_FMC 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_VERIFY_FMC_DIGEST 0x00000009 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_DECRYPT_FMC 0x0000000a /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_DECRYPT_FUSEKEY 0x0000000b /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_REVOKE_RESOURCE 0x0000000c /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_PHASE_CONFIGURE_FMC_ENV 0x0000000d /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME 17:8 /* RWIVF */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_DMA_FB_ADDRESS_ERROR 0x00000020 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_DMA_NACK_ERROR 0x00000021 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_SHA_ACQUIRE_MUTEX_ERROR 0x00000040 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_SHA_EXECUTION_ERROR 0x00000041 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_DIO_READ_ERROR 0x00000060 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_DIO_WRITE_ERROR 0x00000061 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_SE_PDI_INVALID_ERROR 0x00000080 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_SE_PKEYHASH_INVALID_ERROR 0x00000081 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_SW_PKEY_DIGEST_ERROR 0x00000082 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_SE_PKA_RETURN_CODE_ERROR 0x00000083 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_SCP_LOAD_SECRET_ERROR 0x000000a0 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_SCP_TRAPPED_DMA_NOT_ALIGNED_ERROR 0x000000a1 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_CODE_SIZE_ERROR 0x000000c0 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_CORE_PMP_RESERVATION_ERROR 0x000000c1 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_DATA_SIZE_ERROR 0x000000c2 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_DEVICEMAP_BR_UNLOCK_ERROR 0x000000c3 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_FAMILY_ID_ERROR 0x000000c4 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_MSPM_VALUE_ERROR 0x000000c5 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_PAD_INFO_MASK_ERROR 0x000000c6 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_REG_PAIR_ADDRESS_ERROR 0x000000c7 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_REG_PAIR_ENTRY_NUM_ERROR 0x000000c8 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_SECRET_MASK_ERROR 0x000000c9 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_SECRET_MASK_LOCK_ERROR 0x000000ca /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_SIGNATURE_ERROR 0x000000cb /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_UCODE_ID_ERROR 0x000000cc /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MANIFEST_UCODE_VERSION_ERROR 0x000000cd /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_FMC_DIGEST_ERROR 0x000000e0 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_BAD_HEADER_ERROR 0x00000100 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_KEYGLOB_INVALID_ERROR 0x00000101 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_PROTECT_INFO_ERROR 0x00000102 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_FUSEKEY_SIGNATURE_ERROR 0x00000103 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_KMEM_DISPOSE_KSLOT_ERROR 0x00000120 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_KMEM_KEY_SLOT_K3_ERROR 0x00000121 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_KMEM_LOAD_KSLOT2SCP_ERROR 0x00000122 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_KMEM_READ_ERROR 0x00000123 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_KMEM_WRITE_ERROR 0x00000124 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_IOPMP_ERROR 0x00000141 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_MMIO_ERROR 0x00000142 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_SYNDROME_OK 0x000003ff /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO 31:18 /* RWIVF */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_DMA_WAIT_FOR_IDLE_HANG 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_SHA_HANG 0x00000002 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_DIO_READ_HANG 0x00000004 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_DIO_WAIT_FREE_ENTRY_HANG 0x00000008 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_DIO_WRITE_HANG 0x00000010 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_SE_ACQUIRE_MUTEX_HANG 0x00000020 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_SE_PDI_LOAD_HANG 0x00000040 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_SE_PKEYHASH_LOAD_HANG 0x00000080 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_PKA_POLL_RESULT_HANG 0x00000100 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_SCP_PIPELINE_RESET_HANG 0x00000200 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_TRAPPED_DMA_HANG 0x00000400 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_FUSEKEY_KEYGLOB_LOAD_HANG 0x00000800 /* RW--V */
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#define NV_PPWR_RISCV_BR_RETCODE_INFO_KMEM_CMD_EXECUTE_HANG 0x00001000 /* RW--V */
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#define NV_PPWR_RISCV_BR_PRIV_LOCKDOWN 0x0010b660 /* RWI4R */
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#define NV_PPWR_RISCV_BR_PRIV_LOCKDOWN__DEVICE_MAP 0x00000000 /* */
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#define NV_PPWR_RISCV_BR_PRIV_LOCKDOWN__PRIV_LEVEL_MASK 0x0010a1b8 /* */
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#define NV_PPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK 0:0 /* RW-VF */
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#define NV_PPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK_UNLOCKED 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_FALSE_CORESELECT_FALSE 0x00000000 /* */
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#define NV_PPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_FALSE_CORESELECT_TRUE 0x00000001 /* */
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#define NV_PPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_TRUE_CORESELECT_FALSE 0x00000001 /* */
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#define NV_PPWR_RISCV_BR_PRIV_LOCKDOWN_LOCK_INIT_DEBUGDIS_TRUE_CORESELECT_TRUE 0x00000001 /* */
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#define NV_PPWR_RISCV_BCR_CTRL 0x0010b668 /* RWI4R */
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#define NV_PPWR_RISCV_BCR_CTRL__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_RISCV_BCR_CTRL__PRIV_LEVEL_MASK 0x0010b664 /* */
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#define NV_PPWR_RISCV_BCR_CTRL_VALID 0:0 /* R-IVF */
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#define NV_PPWR_RISCV_BCR_CTRL_VALID_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_RISCV_BCR_CTRL_VALID_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_RISCV_BCR_CTRL_CORE_SELECT 4:4 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_CTRL_CORE_SELECT_FALCON 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_CTRL_CORE_SELECT_RISCV 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_BCR_CTRL_BRFETCH 8:8 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_CTRL_BRFETCH_TRUE 0x00000001 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_CTRL_BRFETCH_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_RISCV_BCR_DMACFG 0x0010b66c /* RWI4R */
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#define NV_PPWR_RISCV_BCR_DMACFG__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_RISCV_BCR_DMACFG__PRIV_LEVEL_MASK 0x0010b664 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_TARGET 1:0 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMACFG_TARGET_LOCAL_FB 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMACFG_TARGET_COHERENT_SYSMEM 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_BCR_DMACFG_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* RW--V */
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#define NV_PPWR_RISCV_BCR_DMACFG_LOCK 31:31 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMACFG_LOCK_UNLOCKED 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMACFG_LOCK_LOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC 0x0010b694 /* RWI4R */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC__PRIV_LEVEL_MASK 0x0010b690 /* */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_WPRID 1:0 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMACFG_SEC_WPRID_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PKCPARAM_LO 0x0010b670 /* RWI4R */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PKCPARAM_LO__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PKCPARAM_LO__PRIV_LEVEL_MASK 0x0010b664 /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PKCPARAM_LO_VAL 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PKCPARAM_LO_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PKCPARAM_HI 0x0010b674 /* RWI4R */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PKCPARAM_HI__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PKCPARAM_HI__PRIV_LEVEL_MASK 0x0010b664 /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PKCPARAM_HI_VAL 6:0 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PKCPARAM_HI_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCCODE_LO 0x0010b678 /* RWI4R */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCCODE_LO__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCCODE_LO__PRIV_LEVEL_MASK 0x0010b664 /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCCODE_LO_VAL 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCCODE_LO_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCCODE_HI 0x0010b67c /* RWI4R */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCCODE_HI__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCCODE_HI__PRIV_LEVEL_MASK 0x0010b664 /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCCODE_HI_VAL 6:0 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCCODE_HI_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCDATA_LO 0x0010b680 /* RWI4R */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCDATA_LO__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCDATA_LO__PRIV_LEVEL_MASK 0x0010b664 /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCDATA_LO_VAL 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCDATA_LO_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCDATA_HI 0x0010b684 /* RWI4R */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCDATA_HI__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCDATA_HI__PRIV_LEVEL_MASK 0x0010b664 /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCDATA_HI_VAL 6:0 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMAADDR_FMCDATA_HI_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PUBKEY_LO 0x0010b688 /* RWI4R */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PUBKEY_LO__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PUBKEY_LO__PRIV_LEVEL_MASK 0x0010b664 /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PUBKEY_LO_VAL 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PUBKEY_LO_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PUBKEY_HI 0x0010b68c /* RWI4R */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PUBKEY_HI__DEVICE_MAP 0x0000000c /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PUBKEY_HI__PRIV_LEVEL_MASK 0x0010b664 /* */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PUBKEY_HI_VAL 6:0 /* RWIVF */
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#define NV_PPWR_RISCV_BCR_DMAADDR_PUBKEY_HI_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE(i) (0x0010b610+(i)*8) /* RWI4A */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE__SIZE_1 4 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_VAL 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_VAL_INIT 0x33333333 /* RWI-V */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_READ(i) (0+4*(i)):(0+4*(i)) /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_READ__SIZE_1 8 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_READ_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_READ_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_WRITE(i) (1+4*(i)):(1+4*(i)) /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_WRITE__SIZE_1 8 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_WRITE_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_WRITE_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_LOCK(i) (3+4*(i)):(3+4*(i)) /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_LOCK__SIZE_1 8 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_LOCK_LOCKED 0x00000001 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVMMODE_LOCK_UNLOCKED 0x00000000 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVSUBMMODE(i) (0x0010b614+(i)*8) /* RWI4A */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVSUBMMODE__SIZE_1 4 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_VAL 31:0 /* RWIVF */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_VAL_INIT 0x33333333 /* RWI-V */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_READ(i) (0+4*(i)):(0+4*(i)) /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_READ__SIZE_1 8 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_READ_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_READ_DISABLE 0x00000000 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE(i) (1+4*(i)):(1+4*(i)) /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE__SIZE_1 8 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE_ENABLE 0x00000001 /* */
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#define NV_PPWR_RISCV_DEVICEMAP_RISCVSUBMMODE_WRITE_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK 0x0010ab60 /* RW-4R */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_rst" /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_PMU_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK 0x0010ab18 /* RW-4R */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED 0x00000008 /* RWI-V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RW--V */
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#define NV_PPWR_PMU_SFT_RST_THERM_PRIV_LEVEL_MASK_SOURCE_ENABLE_IFF_GSP_ENABLED 0x00000048 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK 0x0010ab0c /* RW-4R */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_idle_count" /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_COUNT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK 0x0010ab10 /* RW-4R */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpc_deglitch_cfg" /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK 0x0010a87c /* RW-4R */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_intr_1" /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_INTR_1_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK 0x0010a878 /* RW-4R */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_intr_0" /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_INTR_0_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK 0x0010a53c /* RW-4R */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpio_output" /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK 0x0010a538 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpio_general" /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_GENERAL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK 0x0010a400 /* RW-4R */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_cmd_head_intr" /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK(i) (0x0010bd00+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK__SIZE_1 8 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK(i) (0x0010bd20+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK__SIZE_1 8 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK 0x0010bf78 /* RW-4R */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_HEAD_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK 0x0010bf7c /* RW-4R */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_MSGQ_TAIL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK 0x0010ab1c /* RW-4R */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_secure_reset_ctrl" /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_RESET_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK 0x0010a65c /* RW-4R */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_ctrl" /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK 0x0010a5e0 /* RW-4R */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_secure_interlock" /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_INTERLOCK_CTRL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK 0x0010a5e4 /* RW-4R */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_secure_interlock" /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_SECURE_INTERLOCK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK 0x0010a5e8 /* RW-4R */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_secure_gpc_pri_err" /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_GPC_PRI_ERR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK 0x0010a5ec /* RW-4R */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_secure_gpc_pri_err" /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PPWR_PMU_MEMSYS_MTHD_LOCK_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK 0x0010a788 /* RW-4R */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_TRIGGER_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK 0x0010a7dc /* RW-4R */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg" /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_CTRL_PRECONDITION_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0 0x0010ab38 /* RW-4R */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION__FUSE_SIGNAL "pmu_sw_client" /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_0_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1 0x0010ab3c /* RW-4R */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION__FUSE_SIGNAL "pmu_sw_client" /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_1_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2 0x0010ab40 /* RW-4R */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION__FUSE_SIGNAL "pmu_sw_client" /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_2_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3 0x0010ab44 /* RW-4R */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_3_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4 0x0010ab48 /* RW-4R */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_4_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5 0x0010ab4c /* RW-4R */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_5_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6 0x0010ab50 /* RW-4R */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_6_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7 0x0010ab54 /* RW-4R */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_SW_CLIENT_PRIV_LEVEL_MASK_7_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK 0x0010aa78 /* RW-4R */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_elpg_dbg" /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED_FUSE1 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_DBG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK 0x0010a7fc /* RW-4R */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_ELPG_STAT_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK 0x0010ab80 /* RW-4R */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_power_control" /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CONTROL_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWE-V */
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#define NV_PPWR_PMU_RESET_COUNTER 0x0010a404 /* RW-4R */
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#define NV_PPWR_PMU_RESET_COUNTER__PRIV_LEVEL_MASK 0x0010ab60 /* */
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#define NV_PPWR_PMU_RESET_COUNTER_VAL 31:0 /* RWIVF */
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#define NV_PPWR_PMU_RESET_COUNTER_VAL_INIT 0x0000ffff /* RWI-V */
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#define NV_PPWR_PMU_RESET_PMU 0x0010a408 /* RW-4R */
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#define NV_PPWR_PMU_RESET_PMU__PRIV_LEVEL_MASK 0x0010ab60 /* */
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#define NV_PPWR_PMU_RESET_PMU_EN 0:0 /* RWIVF */
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#define NV_PPWR_PMU_RESET_PMU_EN_ENABLE 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_RESET_PMU_EN_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_RESET_THERM 0x0010a410 /* RW-4R */
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#define NV_PPWR_PMU_RESET_THERM__PRIV_LEVEL_MASK 0x0010ab18 /* */
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#define NV_PPWR_PMU_RESET_THERM_EN 0:0 /* RWIVF */
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#define NV_PPWR_PMU_RESET_THERM_EN_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_RESET_THERM_EN_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PMU2BSI_RDY4TRANS 0x0010a40c /* RW-4R */
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#define NV_PPWR_PMU_PMU2BSI_RDY4TRANS_STATUS 0:0 /* RWIVF */
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#define NV_PPWR_PMU_PMU2BSI_RDY4TRANS_STATUS_EN 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_PMU2BSI_RDY4TRANS_STATUS_DIS 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_FORCE_BUSY 0x0010a420 /* RW-4R */
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#define NV_PPWR_PMU_FORCE_BUSY_STATE 0:0 /* RWIUF */
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#define NV_PPWR_PMU_FORCE_BUSY_STATE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_FORCE_BUSY_STATE_IDLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_FORCE_BUSY_STATE_BUSY 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_NEW_INSTBLK 0x0010a480 /* RW-4R */
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#define NV_PPWR_PMU_NEW_INSTBLK_PTR 27:0 /* RWIUF */
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#define NV_PPWR_PMU_NEW_INSTBLK_PTR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_NEW_INSTBLK_TARGET 29:28 /* RWIVF */
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#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_FB 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_COH 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_NEW_INSTBLK_TARGET_SYS_NONCOH 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_NEW_INSTBLK_VALID 30:30 /* RWIVF */
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#define NV_PPWR_PMU_NEW_INSTBLK_VALID_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_NEW_INSTBLK_STATUS 31:31 /* R-IVF */
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#define NV_PPWR_PMU_NEW_INSTBLK_STATUS_DONE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_NEW_INSTBLK_STATUS_NOT_DONE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_FALCON_ICD_CTRL 0x0010a424 /* RW-4R */
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#define NV_PPWR_PMU_FALCON_ICD_CTRL_MODE 0:0 /* RWIUF */
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#define NV_PPWR_PMU_FALCON_ICD_CTRL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_FALCON_ICD_CTRL_MODE_JTAG 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_FALCON_ICD_CTRL_MODE_UART 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_ECO 0x0010a428 /* RW-4R */
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#define NV_PPWR_PMU_ECO_BIT0 0:0 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_ECO_CFG_ERR_CYA 0:0 /* RWIVF */
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#define NV_PPWR_PMU_ECO_CFG_ERR_CYA_EN 0x00000000 /* --I-V */
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#define NV_PPWR_PMU_ECO_CFG_ERR_CYA_DIS 0x00000001 /* ----V */
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#define NV_PPWR_PMU_ECO_BIT1 1:1 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_ECO_IDLE_SNAP_CYA 1:1 /* RWIVF */
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#define NV_PPWR_PMU_ECO_IDLE_SNAP_CYA_EN 0x00000000 /* --I-V */
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#define NV_PPWR_PMU_ECO_IDLE_SNAP_CYA_DIS 0x00000001 /* ----V */
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#define NV_PPWR_PMU_ECO_BIT2 2:2 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT2_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_ECO_BIT3 3:3 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT3_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_ECO_BIT4 4:4 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT4_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_ECO_BIT5 5:5 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT5_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_ECO_BIT6 6:6 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT6_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_ECO_BIT7 7:7 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT7_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_ECO_BIT8 8:8 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT8_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ECO_BIT9 9:9 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT9_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ECO_BIT10 10:10 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT10_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ECO_BIT11 11:11 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT11_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ECO_BIT12 12:12 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT12_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ECO_BIT13 13:13 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT13_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ECO_BIT14 14:14 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT14_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_ECO_BIT15 15:15 /* RWIVF */
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#define NV_PPWR_PMU_ECO_BIT15_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG 0x0010a434 /* RW-4R */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG__PRIV_LEVEL_MASK 0x0010ab10 /* */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_LOW_BOUNDARY 9:0 /* RWIUF */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_LOW_BOUNDARY_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_HIGH_BOUNDARY 19:10 /* RWIUF */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_HIGH_BOUNDARY_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_MAX 29:20 /* RWIUF */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_MAX_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_CNT_EN 31:31 /* RWIUF */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_CNT_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_CNT_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPC_DEGLITCH_CFG_CNT_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_TPC_DEGLITCH_CFG 0x0010a438 /* RW-4R */
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#define NV_PPWR_PMU_TPC_DEGLITCH_CFG_LOW_BOUNDARY 9:0 /* RWIUF */
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#define NV_PPWR_PMU_TPC_DEGLITCH_CFG_LOW_BOUNDARY_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_TPC_DEGLITCH_CFG_HIGH_BOUNDARY 19:10 /* RWIUF */
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#define NV_PPWR_PMU_TPC_DEGLITCH_CFG_HIGH_BOUNDARY_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_TPC_DEGLITCH_CFG_MAX 29:20 /* RWIUF */
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#define NV_PPWR_PMU_TPC_DEGLITCH_CFG_MAX_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_TPC_DEGLITCH_CFG_CNT_EN 31:31 /* RWIUF */
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#define NV_PPWR_PMU_TPC_DEGLITCH_CFG_CNT_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_TPC_DEGLITCH_CFG_CNT_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_TPC_DEGLITCH_CFG_CNT_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS 0x0010a43c /* R--4R */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC0 0:0 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC0_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC0_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC1 1:1 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC1_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC1_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC2 2:2 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC2_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC2_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC3 3:3 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC3_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC3_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC4 4:4 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC4_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC4_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC5 5:5 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC5_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC5_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC6 6:6 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC6_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC6_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC7 7:7 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC7_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC7_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC 7:0 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC0 8:8 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC0_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC0_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC1 9:9 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC1_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC1_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC2 10:10 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC2_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC2_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC3 11:11 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC3_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC3_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC4 12:12 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC4_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC4_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC5 13:13 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC5_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC5_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC6 14:14 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC6_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC6_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC7 15:15 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC7_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC7_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC 15:8 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GR 16:16 /* R--VF */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GR_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GR_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC(i) (i):(i) /* */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC__SIZE_1 8 /* */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC_BUSY 0 /* */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_GPC_GPC_IDLE 1 /* */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC(i) (8+(i)):(8+(i)) /* */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC__SIZE_1 8 /* */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC_BUSY 0 /* */
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#define NV_PPWR_PMU_GPC_TPC_IDLE_STATUS_TPC_GPC_IDLE 1 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0 0x0010a440 /* RW-4R */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC0 0:0 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC0_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC1 1:1 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC2 2:2 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC2_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC3 3:3 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC3_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC3_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC4 4:4 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC4_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC4_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC5 5:5 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC5_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC5_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC5_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC6 6:6 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC6_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC6_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC6_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC7 7:7 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC7_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC7_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC7_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING 7:0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC0 8:8 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC0_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC1 9:9 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC2 10:10 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC2_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC3 11:11 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC3_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC3_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC4 12:12 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC4_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC4_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC5 13:13 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC5_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC5_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC5_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC6 14:14 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC6_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC6_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC6_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC7 15:15 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC7_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC7_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC7_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING 15:8 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC0 16:16 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC0_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC1 17:17 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC2 18:18 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC2_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC3 19:19 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC3_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC3_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC4 20:20 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC4_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC4_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC5 21:21 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC5_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC5_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC5_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC6 22:22 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC6_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC6_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC6_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC7 23:23 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC7_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC7_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC7_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING 23:16 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC0 24:24 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC0_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC0_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC1 25:25 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC1_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC2 26:26 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC2_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC2_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC3 27:27 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC3_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC3_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC3_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC4 28:28 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC4_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC4_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC4_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC5 29:29 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC5_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC5_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC5_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC5_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC6 30:30 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC6_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC6_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC6_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC6_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC7 31:31 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC7_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC7_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC7_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC7_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING 31:24 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC(i) (i):(i) /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC__SIZE_1 8 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC_INIT 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC_NOT_PENDING 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC_PENDING 1 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_RISING_GPC_CLEAR 1 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC(i) (8+(i)):(8+(i)) /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC__SIZE_1 8 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC_INIT 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC_NOT_PENDING 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC_PENDING 1 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_GPC_FALLING_GPC_CLEAR 1 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC(i) (16+(i)):(16+(i)) /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC__SIZE_1 8 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC_INIT 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC_NOT_PENDING 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC_PENDING 1 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_RISING_GPC_CLEAR 1 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC(i) (24+(i)):(24+(i)) /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC__SIZE_1 8 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC_INIT 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC_NOT_PENDING 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC_PENDING 1 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_0_TPC_FALLING_GPC_CLEAR 1 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_1 0x0010a444 /* RW-4R */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_RISING 0:0 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_RISING_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_RISING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_RISING_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_RISING_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_FALLING 1:1 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_FALLING_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_FALLING_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_FALLING_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_STAT_1_GR_IDLE_FALLING_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0 0x0010a448 /* RW-4R */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC0 0:0 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC0_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC1 1:1 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC1_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC2 2:2 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC2_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC2_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC3 3:3 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC3_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC3_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC4 4:4 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC4_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC4_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC5 5:5 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC5_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC5_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC6 6:6 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC6_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC6_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC7 7:7 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC7_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC7_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING 7:0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC0 8:8 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC0_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC1 9:9 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC1_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC2 10:10 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC2_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC2_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC3 11:11 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC3_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC3_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC4 12:12 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC4_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC4_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC5 13:13 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC5_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC5_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC6 14:14 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC6_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC6_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC7 15:15 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC7_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC7_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING 15:8 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC0 16:16 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC0_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC1 17:17 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC1_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC2 18:18 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC2_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC2_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC3 19:19 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC3_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC3_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC4 20:20 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC4_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC4_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC5 21:21 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC5_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC5_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC6 22:22 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC6_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC6_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC7 23:23 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC7_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC7_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING 23:16 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC0 24:24 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC0_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC1 25:25 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC1_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC2 26:26 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC2_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC2_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC3 27:27 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC3_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC3_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC4 28:28 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC4_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC4_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC5 29:29 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC5_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC5_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC6 30:30 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC6_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC6_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC7 31:31 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC7_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC7_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING 31:24 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC(i) (i):(i) /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC__SIZE_1 8 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC_INIT 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC_DISABLED 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_RISING_GPC_ENABLED 1 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC(i) (8+(i)):(8+(i)) /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC__SIZE_1 8 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC_INIT 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC_DISABLED 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_GPC_FALLING_GPC_ENABLED 1 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC(i) (16+(i)):(16+(i)) /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC__SIZE_1 8 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC_INIT 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC_DISABLED 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_RISING_GPC_ENABLED 1 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC(i) (24+(i)):(24+(i)) /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC__SIZE_1 8 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC_INIT 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC_DISABLED 0 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_0_TPC_FALLING_GPC_ENABLED 1 /* */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_1 0x0010a44c /* RW-4R */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_RISING 0:0 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_RISING_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_RISING_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_RISING_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_FALLING 1:1 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_FALLING_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_FALLING_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_DETECT_INTR_EN_1_GR_IDLE_FALLING_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_MUTEX_ID 0x0010a488 /* R--4R */
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#define NV_PPWR_PMU_MUTEX_ID_VALUE 7:0 /* R-IUF */
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#define NV_PPWR_PMU_MUTEX_ID_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_MUTEX_ID_VALUE_NOT_AVAIL 0x000000ff /* R---V */
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#define NV_PPWR_PMU_MUTEX_ID_RELEASE 0x0010a48c /* RW-4R */
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#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE 7:0 /* RWIUF */
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#define NV_PPWR_PMU_MUTEX_ID_RELEASE_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_MUTEX(i) (0x0010a580+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_MUTEX__SIZE_1 16 /* */
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#define NV_PPWR_PMU_MUTEX_VALUE 7:0 /* RWIUF */
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#define NV_PPWR_PMU_MUTEX_VALUE_INITIAL_LOCK 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_PM 0x0010a4f0 /* RW-4R */
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#define NV_PPWR_PMU_PM_SELECT 5:0 /* RWIVF */
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#define NV_PPWR_PMU_PM_SELECT_INTR 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_PM_SELECT_BAR0 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_CSBREG 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_GPIO 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_TPRIV 0x00000004 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_ENG_EN_DIS 0x00000005 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_FB_STOP 0x00000006 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_CLK_GATE 0x00000007 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_SLOWDOWN 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_ELPG_0_1 0x00000009 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_INTR_SC 0x00000010 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_BAR0_SC 0x00000011 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_CSBREG_SC 0x00000012 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_GPIO_SC 0x00000013 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_TPRIV_SC 0x00000014 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_ENG_EN_DIS_SC 0x00000015 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_FB_STOP_SC 0x00000016 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_CLK_GATE_SC 0x00000017 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_SLOWDOWN_SC 0x00000018 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_ELPG_0_1_SC 0x00000019 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_SLOWDOWN_GPCCLK 0x0000000a /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_SLOWDOWN_GPCCLK_SC 0x0000000b /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_ELPG_2_3 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_ELPG_2_3_SC 0x0000000d /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_WSP_0 0x0000000e /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_WSP_0_SC 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_WSP_1 0x0000001a /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_WSP_1_SC 0x0000001b /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_SOFT_PM_0 0x0000001c /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_SOFT_PM_0_SC 0x0000001d /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_SOFT_PM_1 0x0000001e /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_SOFT_PM_1_SC 0x0000001f /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_ENG_EN_DIS_CE 0x00000020 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_ENG_EN_DIS_CE_SC 0x00000021 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_GR_VD_INTR 0x00000022 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_GR_VD_INTR_SC 0x00000023 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_CPM_SUM 0x00000024 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_CPM_SUM_SC 0x00000025 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_SCP 0x00000026 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_SCP_SC 0x00000027 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_ELPG_4 0x00000030 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_ELPG_4_SC 0x00000031 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_DI_INTR 0x00000032 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_DI_INTR_SC 0x00000033 /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_STATIC_PATTERN_5555_16_GROUP 0x0000002a /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_STATIC_PATTERN_5555_16_GROUP_SC 0x0000002b /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_STATIC_PATTERN_AAAA_16_GROUP 0x0000002c /* RW--V */
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#define NV_PPWR_PMU_PM_SELECT_STATIC_PATTERN_AAAA_16_GROUP_SC 0x0000002d /* RW--V */
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#define NV_PPWR_PMU_PM_FIFO_OVERRUN 28:28 /* RWIVF */
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#define NV_PPWR_PMU_PM_FIFO_OVERRUN_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_PM_FIFO_OVERRUN_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PM_FIFO_OVERRUN_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_PM_CTRL_ENABLE 31:31 /* RWIVF */
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#define NV_PPWR_PMU_PM_CTRL_ENABLE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_PM_CTRL_ENABLE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SOFT_PM 0x0010a5fc /* RW-4R */
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#define NV_PPWR_PMU_SOFT_PM_VALUE 31:0 /* RWIVF */
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#define NV_PPWR_PMU_SOFT_PM_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_CRC_UPDATE 0x0010a490 /* RW-4R */
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#define NV_PPWR_PMU_CRC_UPDATE_DATA 31:0 /* RWIVF */
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#define NV_PPWR_PMU_CRC_UPDATE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_CRC_VALUE 0x0010a494 /* RW-4R */
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#define NV_PPWR_PMU_CRC_VALUE_DATA 31:0 /* RWIVF */
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#define NV_PPWR_PMU_CRC_VALUE_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_HEAD(i) (0x0010a800+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_QUEUE_HEAD__SIZE_1 8 /* */
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#define NV_PPWR_PMU_QUEUE_HEAD__PRIV_LEVEL_MASK NV_PPWR_PMU_QUEUE_HEAD_PRIV_LEVEL_MASK /* */
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#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_HEAD_ADDRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_QUEUE_TAIL(i) (0x0010a820+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_QUEUE_TAIL__SIZE_1 8 /* */
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#define NV_PPWR_PMU_QUEUE_TAIL__PRIV_LEVEL_MASK NV_PPWR_PMU_QUEUE_TAIL_PRIV_LEVEL_MASK /* */
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#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS 31:0 /* RWIVF */
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#define NV_PPWR_PMU_QUEUE_TAIL_ADDRESS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT 0x0010a4c0 /* RW-4R */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT__PRIV_LEVEL_MASK 0x0010a400 /* */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_0 0:0 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_0_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_0_UPDATED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_1 1:1 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_1_UPDATED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_2 2:2 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_2_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_2_UPDATED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_3 3:3 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_3_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_3_UPDATED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_4 4:4 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_4_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_4_UPDATED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_5 5:5 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_5_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_5_UPDATED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_5_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_6 6:6 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_6_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_6_UPDATED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_6_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_7 7:7 /* RWIVF */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_7_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_7_UPDATED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_CMD_HEAD_INTRSTAT_7_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_CMD_INTREN 0x0010a4c4 /* RW-4R */
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#define NV_PPWR_PMU_CMD_INTREN__PRIV_LEVEL_MASK 0x0010a400 /* */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_0_UPDATE 0:0 /* RWIVF */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_0_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_0_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_0_UPDATE_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_1_UPDATE 1:1 /* RWIVF */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_1_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_1_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_1_UPDATE_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_2_UPDATE 2:2 /* RWIVF */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_2_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_2_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_2_UPDATE_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_3_UPDATE 3:3 /* RWIVF */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_3_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_3_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_3_UPDATE_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_4_UPDATE 4:4 /* RWIVF */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_4_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_4_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_4_UPDATE_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_5_UPDATE 5:5 /* RWIVF */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_5_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_5_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_5_UPDATE_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_6_UPDATE 6:6 /* RWIVF */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_6_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_6_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_6_UPDATE_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_7_UPDATE 7:7 /* RWIVF */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_7_UPDATE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_7_UPDATE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_CMD_INTREN_HEAD_7_UPDATE_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_MSGQ_HEAD 0x0010a4c8 /* RW-4R */
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#define NV_PPWR_PMU_MSGQ_HEAD__PRIV_LEVEL_MASK 0x0010bf78 /* */
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#define NV_PPWR_PMU_MSGQ_HEAD_VAL 31:0 /* RWIUF */
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#define NV_PPWR_PMU_MSGQ_HEAD_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_MSGQ_TAIL 0x0010a4cc /* RW-4R */
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#define NV_PPWR_PMU_MSGQ_TAIL__PRIV_LEVEL_MASK 0x0010bf7c /* */
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#define NV_PPWR_PMU_MSGQ_TAIL_VAL 31:0 /* RWIUF */
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#define NV_PPWR_PMU_MSGQ_TAIL_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_TIMER_0_INTERVAL 0x0010a4e0 /* RW-4R */
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#define NV_PPWR_PMU_TIMER_0_INTERVAL_VALUE 31:0 /* RWIVF */
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#define NV_PPWR_PMU_TIMER_0_INTERVAL_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_TIMER_0_COUNT 0x0010a4e4 /* R--4R */
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#define NV_PPWR_PMU_TIMER_0_COUNT_VALUE 31:0 /* R--VF */
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#define NV_PPWR_PMU_TIMER_0_COUNT_VALUE_INIT 0xffffffff /* R---V */
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#define NV_PPWR_PMU_TIMER_CTRL 0x0010a4e8 /* RW-4R */
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#define NV_PPWR_PMU_TIMER_CTRL_GATE 0:0 /* RWIVF */
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#define NV_PPWR_PMU_TIMER_CTRL_GATE_STOP 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_TIMER_CTRL_GATE_RUN 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_TIMER_CTRL_SOURCE 4:4 /* RWIVF */
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#define NV_PPWR_PMU_TIMER_CTRL_SOURCE_PMU_CLK 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_TIMER_CTRL_SOURCE_PTIMER_1US 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_TIMER_CTRL_MODE 8:8 /* RWIVF */
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#define NV_PPWR_PMU_TIMER_CTRL_MODE_ONE_SHOT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_TIMER_CTRL_MODE_CONTINUOUS 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_TIMER_CTRL_RESET 12:12 /* RWIVF */
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#define NV_PPWR_PMU_TIMER_CTRL_RESET_DONE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_TIMER_CTRL_RESET_NOT_DONE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_TIMER_CTRL_RESET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_DP1_SEL0 0x0010a5d0 /* RW-4R */
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#define NV_PPWR_PMU_DP1_SEL0_BIT_0 7:0 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL0_BIT_0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL0_BIT_1 15:8 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL0_BIT_1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL0_BIT_2 23:16 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL0_BIT_2_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL0_BIT_3 31:24 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL0_BIT_3_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL1 0x0010a5d4 /* RW-4R */
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#define NV_PPWR_PMU_DP1_SEL1_BIT_4 7:0 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL1_BIT_4_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL1_BIT_5 15:8 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL1_BIT_5_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL1_BIT_6 23:16 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL1_BIT_6_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL1_BIT_7 31:24 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL1_BIT_7_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL2 0x0010a5d8 /* RW-4R */
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#define NV_PPWR_PMU_DP1_SEL2_BIT_8 7:0 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL2_BIT_8_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL2_BIT_9 15:8 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL2_BIT_9_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL2_BIT_10 23:16 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL2_BIT_10_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL2_BIT_11 31:24 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL2_BIT_11_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL3 0x0010a5dc /* RW-4R */
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#define NV_PPWR_PMU_DP1_SEL3_BIT_12 7:0 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL3_BIT_12_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL3_BIT_13 15:8 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL3_BIT_13_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL3_BIT_14 23:16 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL3_BIT_14_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DP1_SEL3_BIT_15 31:24 /* RWIVF */
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#define NV_PPWR_PMU_DP1_SEL3_BIT_15_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPCRG_CONTROL 0x0010a414 /* RW-4R */
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#define NV_PPWR_PMU_GPCRG_CONTROL__PRIV_LEVEL_MASK 0x0010a65c /* */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_CLAMP 0:0 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_CLAMP_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_CLAMP_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_CLK_CLAMP 1:1 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_CLK_CLAMP_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_CLK_CLAMP_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_RESET_INT_CLAMP 2:2 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_RESET_INT_CLAMP_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_RESET_INT_CLAMP_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_RESET_INT_CLAMPVAL 3:3 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_RESET_INT_CLAMPVAL_ZERO 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_RESET_INT_CLAMPVAL_ONE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_BLOCK_EXT_RESET 4:4 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_BLOCK_EXT_RESET_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_BLOCK_EXT_RESET_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_BLOCK_EXT_RESET_CLAMPVAL 5:5 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_BLOCK_EXT_RESET_CLAMPVAL_ZERO 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RG_BLOCK_EXT_RESET_CLAMPVAL_ONE 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_XV2ALL_RESET 8:8 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_XV2ALL_RESET_DISABLE 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_XV2ALL_RESET_ENABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_HOST2XBAR_RESET 9:9 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_HOST2XBAR_RESET_DISABLE 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_HOST2XBAR_RESET_ENABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_HOST2PERFMON_RESET 10:10 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_HOST2PERFMON_RESET_DISABLE 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_HOST2PERFMON_RESET_ENABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_RESET2CLK_DIRECT_RESET 12:12 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_RESET2CLK_DIRECT_RESET_DISABLE 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_RESET2CLK_DIRECT_RESET_ENABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_XV2CLK_RESET 13:13 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_XV2CLK_RESET_DISABLE 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_XV2CLK_RESET_ENABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_CYA_XV2CLK_RESET 14:14 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_CYA_XV2CLK_RESET_DISABLE 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_CONTROL_RESET_OVERRIDE_CYA_XV2CLK_RESET_ENABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL 0x0010a54c /* RW-4R */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL__PRIV_LEVEL_MASK 0x0010a5e0 /* */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_RESET 0:0 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_RESET_DIS 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_RESET_EN 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_PGOOD 4:4 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_PGOOD_DIS 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_PGOOD_EN 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_MTHD_INTERLOCK 8:8 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_MTHD_INTERLOCK_DIS 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_MTHD_INTERLOCK_EN 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_PRI_INTERLOCK 12:12 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_PRI_INTERLOCK_DIS 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_CTRL_PRI_INTERLOCK_EN 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_GPC_PRI_ERR 0x0010a540 /* RW-4R */
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#define NV_PPWR_PMU_GPCRG_GPC_PRI_ERR__PRIV_LEVEL_MASK 0x0010a5e8 /* */
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#define NV_PPWR_PMU_GPCRG_GPC_PRI_ERR_SW 0:0 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_GPC_PRI_ERR_SW_DIS 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_GPC_PRI_ERR_SW_EN 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_MTHD_LOCK 0x0010a544 /* RW-4R */
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#define NV_PPWR_PMU_GPCRG_MTHD_LOCK__PRIV_LEVEL_MASK 0x0010a5ec /* */
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#define NV_PPWR_PMU_GPCRG_MTHD_LOCK_SW 0:0 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_MTHD_LOCK_SW_DIS 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_MTHD_LOCK_SW_EN 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK 0x0010a548 /* RW-4R */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK__PRIV_LEVEL_MASK 0x0010a5e4 /* */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_MTHD_HW 30:30 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_MTHD_HW_DIS 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_MTHD_HW_EN 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_PRI_HW 31:31 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_PRI_HW_DIS 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_SECURE_INTERLOCK_PRI_HW_EN 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CTRL 0x0010ab30 /* RW-4R */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CTRL__PRIV_LEVEL_MASK 0x0010ab1c /* */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CTRL_RESET 0:0 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CTRL_RESET_DIS 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CTRL_RESET_EN 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CTRL_CLAMP_RST_COUPLER_DIS_CYA 4:4 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CTRL_CLAMP_RST_COUPLER_DIS_CYA_EN 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CTRL_CLAMP_RST_COUPLER_DIS_CYA_DIS 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CNT 0x0010ab14 /* RW-4R */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CNT__PRIV_LEVEL_MASK 0x0010ab1c /* */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CNT_VALUE 31:0 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CNT_VALUE_INIT 0x0000021c /* RWE-V */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CLAMP_CNT 0x0010ab58 /* RW-4R */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CLAMP_CNT__PRIV_LEVEL_MASK 0x0010ab1c /* */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CLAMP_CNT_VALUE 31:0 /* RWEVF */
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#define NV_PPWR_PMU_GPCRG_SECURE_RESET_CLAMP_CNT_VALUE_INIT 0x0000021c /* RWE-V */
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#define NV_PPWR_PMU_ELPG_SEQ_CG 0x0010ab34 /* RW-4R */
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#define NV_PPWR_PMU_ELPG_SEQ_CG_EN 0:0 /* RWEUF */
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#define NV_PPWR_PMU_ELPG_SEQ_CG_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_ELPG_SEQ_CG_EN_DISABLED 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_ELPG_SEQ_CG_EN__PROD 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA 0x0010a970 /* R--4R */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_0 0:0 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_0_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_0_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_1 1:1 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_1_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_1_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_2 2:2 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_2_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_2_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_3 3:3 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_3_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_3_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_4 4:4 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_4_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_4_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_5 5:5 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_5_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_5_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_6 6:6 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_6_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_7 7:7 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_7_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_8 8:8 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_8_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_9 9:9 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_9_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_10 10:10 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_10_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_11 11:11 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_11_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_12 12:12 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_12_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_13 13:13 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_13_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_14 14:14 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_14_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_15 15:15 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_15_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_16 16:16 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_16_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_17 17:17 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_17_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_18 18:18 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_18_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_19 19:19 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_19_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_20 20:20 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_20_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_21 21:21 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_21_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_22 22:22 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_22_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_23 23:23 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_23_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_24 24:24 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_24_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_25 25:25 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_25_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_26 26:26 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_26_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_27 27:27 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_27_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_28 28:28 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_28_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_29 29:29 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_29_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_30 30:30 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_30_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_31 31:31 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FOR_FB_PA_NOT_USED_31_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS 0x0010a500 /* R--4R */
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#define NV_PPWR_PMU_IDLE_STATUS_GR_FE 0:0 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_GR_FE_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_GR_FE_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE_SYS 1:1 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE_SYS_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE_SYS_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE_GPC 2:2 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE_GPC_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE_GPC_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_GR_PRIV_IDLE 2:1 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_NOT_USED_3 3:3 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_NOT_USED_3_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_SEC 4:4 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_SEC_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_SEC_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_VD_NVDEC 5:5 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_VD_NVDEC_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_VD_NVDEC_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_NOT_USED_6 6:6 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_NOT_USED_6_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FB_NOREQ 7:7 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FB_NOREQ_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FB_NOREQ_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FB_PA 8:8 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FB_PA_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FB_PA_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_HSHUB_ALL 9:9 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_HSHUB_ALL_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_HSHUB_ALL_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_HSHUB_NISO 10:10 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_HSHUB_NISO_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_HSHUB_NISO_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FB_ASR 11:11 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_FB_ASR_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_FB_ASR_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_LTC_IDLE 12:12 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_LTC_IDLE_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_LTC_IDLE_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_AZA_IDLE 13:13 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_AZA_IDLE_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_AZA_IDLE_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_HOST_ESCHED0 14:14 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_HOST_ESCHED0_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_HOST_ESCHED0_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_NOT_USED_15 15:15 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_NOT_USED_15_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_HSHUB_NISO_EX_ISO 16:16 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_HSHUB_NISO_EX_ISO_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_HSHUB_NISO_EX_ISO_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_VD_NVENC0 17:17 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_VD_NVENC0_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_VD_NVENC0_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XBAR_IDLE 18:18 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_XBAR_IDLE_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XBAR_IDLE_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_CE_0 19:19 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_CE_0_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_CE_0_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_CE_1 20:20 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_CE_1_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_CE_1_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_CE_2 21:21 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_CE_2_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_CE_2_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_NOT_USED_22 22:22 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_NOT_USED_22_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XP_L0S 23:23 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_XP_L0S_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XP_L0S_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XP_L1 24:24 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_XP_L1_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XP_L1_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XVE_XCLK 25:25 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_XVE_XCLK_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XVE_XCLK_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XVXP_COMMON 26:26 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_XVXP_COMMON_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XVXP_COMMON_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XVXP_DEEP 27:27 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_XVXP_DEEP_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XVXP_DEEP_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XVXP_XP 28:28 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_XVXP_XP_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XVXP_XP_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XVXP_XVE 29:29 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_XVXP_XVE_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XVXP_XVE_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_XVXP 29:26 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_HOST_ESCHED1 30:30 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_HOST_ESCHED1_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_HOST_ESCHED1_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_HOST_ESCHED2 31:31 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_HOST_ESCHED2_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_HOST_ESCHED2_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_VD_NVENC(i) (17+5*(i)):(17+5*(i)) /* */
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#define NV_PPWR_PMU_IDLE_STATUS_VD_NVENC__SIZE_1 1 /* */
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#define NV_PPWR_PMU_IDLE_STATUS_VD_NVENC_BUSY 0 /* */
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#define NV_PPWR_PMU_IDLE_STATUS_VD_NVENC_IDLE 1 /* */
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#define NV_PPWR_PMU_IDLE_STATUS_1 0x0010a9e4 /* RW-4R */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HSHUB_MMU 0:0 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HSHUB_MMU_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HSHUB_MMU_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_GSP 1:1 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_GSP_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_GSP_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_FBHUB_ALL 2:2 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_FBHUB_ALL_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_FBHUB_ALL_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_FBHUB_NONPMU_INTERFACE 3:3 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_FBHUB_NONPMU_INTERFACE_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_FBHUB_NONPMU_INTERFACE_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_MS_MMU 4:4 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_MS_MMU_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_MS_MMU_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED3 5:5 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED3_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED3_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED4 6:6 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED4_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED4_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED5 7:7 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED5_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED5_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED6 8:8 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED6_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED6_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED7 9:9 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED7_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED7_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED8 10:10 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED8_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_HOST_ESCHED8_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_11 11:11 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_11_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_12 12:12 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_12_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_13 13:13 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_13_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_14 14:14 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_14_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_15 15:15 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_15_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_16 16:16 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_16_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_17 17:17 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_17_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_18 18:18 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_18_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_PMU2FB_TRAFFIC 19:19 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_PMU2FB_TRAFFIC_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_PMU2FB_TRAFFIC_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_CE_3 20:20 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_CE_3_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_CE_3_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_CE_4 21:21 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_CE_4_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_CE_4_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_22 22:22 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_22_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_23 23:23 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_23_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_24 24:24 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_24_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_25 25:25 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_25_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_26 26:26 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_26_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_SEC_FBIF 27:27 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_SEC_FBIF_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_SEC_FBIF_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_28 28:28 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_28_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_29 29:29 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_NOT_USED_29_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_SW0 30:30 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_SW0_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_SW0_IDLE 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_SW1 31:31 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_STATUS_1_SW1_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_SW1_IDLE 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_STATUS_2 0x0010a68c /* RW-4R */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_0 0:0 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_0_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_1 1:1 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_1_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_2 2:2 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_2_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_3 3:3 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_3_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_4 4:4 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_4_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_5 5:5 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_5_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_GSP_FB 6:6 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_GSP_FB_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_GSP_FB_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_7 7:7 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_7_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_VD_NVDEC1 8:8 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_VD_NVDEC1_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_VD_NVDEC1_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_9 9:9 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_9_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_10 10:10 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_10_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_11 11:11 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_11_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_12 12:12 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_12_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_13 13:13 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_13_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_GSP_PRIV_BLOCKER_GR 14:14 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_GSP_PRIV_BLOCKER_GR_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_GSP_PRIV_BLOCKER_GR_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_GSP_PRIV_BLOCKER_MS 15:15 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_GSP_PRIV_BLOCKER_MS_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_GSP_PRIV_BLOCKER_MS_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_SEC_PRIV_BLOCKER_GR 16:16 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_SEC_PRIV_BLOCKER_GR_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_SEC_PRIV_BLOCKER_GR_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_SEC_PRIV_BLOCKER_MS 17:17 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_SEC_PRIV_BLOCKER_MS_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_SEC_PRIV_BLOCKER_MS_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_18 18:18 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_18_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_19 19:19 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_19_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_20 20:20 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_20_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_21 21:21 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_21_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_22 22:22 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_22_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_23 23:23 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_23_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_24 24:24 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_24_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_25 25:25 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_25_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_26 26:26 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_26_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_27 27:27 /* C--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_NOT_USED_27_TIEHIGH 0x00000001 /* C---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_VD_OFA 28:28 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_VD_OFA_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_VD_OFA_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_XVE_BAR_BLK_MS 29:29 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_XVE_BAR_BLK_MS_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_XVE_BAR_BLK_MS_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_XVE_BAR_BLK_GR 30:30 /* R--VF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_XVE_BAR_BLK_GR_BUSY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_XVE_BAR_BLK_GR_IDLE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_SW2 31:31 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_STATUS_2_SW2_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_STATUS_2_SW2_IDLE 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK(i) (0x0010be40+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_IDLE_MASK__SIZE_1 16 /* */
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#define NV_PPWR_PMU_IDLE_MASK__PRIV_LEVEL_MASK 0x0010ab0c /* */
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#define NV_PPWR_PMU_IDLE_MASK_GR 0:0 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_GR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_GR_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_GR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_GR_SYS 1:1 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_GR_SYS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_GR_SYS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_GR_SYS_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_GR_GPC 2:2 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_GR_GPC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_GR_GPC_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_GR_GPC_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_SEC 4:4 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_SEC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_SEC_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_SEC_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_VD_NVDEC 5:5 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_VD_NVDEC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_VD_NVDEC_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_VD_NVDEC_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_FB_NOREQ 7:7 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_FB_NOREQ_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_FB_NOREQ_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_FB_NOREQ_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_FB_PA 8:8 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_FB_PA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_FB_PA_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_FB_PA_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_HSHUB_ALL 9:9 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_HSHUB_ALL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_HSHUB_ALL_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_HSHUB_ALL_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_HSHUB_NISO 10:10 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_HSHUB_NISO_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_HSHUB_NISO_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_HSHUB_NISO_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_FB_ASR 11:11 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_FB_ASR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_FB_ASR_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_FB_ASR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_LTC_IDLE 12:12 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_LTC_IDLE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_LTC_IDLE_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_LTC_IDLE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_AZA_IDLE 13:13 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_AZA_IDLE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_AZA_IDLE_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_AZA_IDLE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_HOST_ESCHED0 14:14 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_HOST_ESCHED0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_HOST_ESCHED0_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_HOST_ESCHED0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_HSHUB_NISO_EX_ISO 16:16 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_HSHUB_NISO_EX_ISO_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_HSHUB_NISO_EX_ISO_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_HSHUB_NISO_EX_ISO_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_VD_NVENC0 17:17 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_VD_NVENC0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_VD_NVENC0_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_VD_NVENC0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XBAR_IDLE 18:18 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_XBAR_IDLE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_XBAR_IDLE_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XBAR_IDLE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_CE_0 19:19 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_CE_0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_CE_0_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_CE_0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_CE_1 20:20 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_CE_1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_CE_1_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_CE_1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_CE_2 21:21 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_CE_2_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_CE_2_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_CE_2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XP_L0S 23:23 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_XP_L0S_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_XP_L0S_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XP_L0S_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XP_L1 24:24 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_XP_L1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_XP_L1_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XP_L1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XVE_XCLK 25:25 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_XVE_XCLK_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_XVE_XCLK_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XVE_XCLK_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_COMMON 26:26 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_COMMON_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_COMMON_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_COMMON_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_DEEP 27:27 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_DEEP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_DEEP_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_DEEP_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_XP 28:28 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_XP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_XP_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_XP_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_XVE 29:29 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_XVE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_XVE_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_XVXP_XVE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_HOST_ESCHED1 30:30 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_HOST_ESCHED1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_HOST_ESCHED1_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_HOST_ESCHED1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_HOST_ESCHED2 31:31 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_HOST_ESCHED2_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_HOST_ESCHED2_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_HOST_ESCHED2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_CE_IDX(i) (19+(i)):(19+(i)) /* */
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#define NV_PPWR_PMU_IDLE_MASK_CE_IDX__SIZE_1 3 /* */
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#define NV_PPWR_PMU_IDLE_MASK_CE_IDX_DISABLED 0 /* */
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#define NV_PPWR_PMU_IDLE_MASK_CE_IDX_ENABLED 1 /* */
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#define NV_PPWR_PMU_IDLE_MASK_1(i) (0x0010be80+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_IDLE_MASK_1__SIZE_1 16 /* */
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#define NV_PPWR_PMU_IDLE_MASK_1__PRIV_LEVEL_MASK 0x0010ab0c /* */
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#define NV_PPWR_PMU_IDLE_MASK_1_HSHUB_MMU 0:0 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_HSHUB_MMU_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HSHUB_MMU_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HSHUB_MMU_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_GSP 1:1 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_GSP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_GSP_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_GSP_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_FBHUB_ALL 2:2 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_FBHUB_ALL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_FBHUB_ALL_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_FBHUB_ALL_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_FBHUB_HNONPMU_INTERFACE 3:3 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_FBHUB_HNONPMU_INTERFACE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_FBHUB_HNONPMU_INTERFACE_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_FBHUB_HNONPMU_INTERFACE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_MS_MMU 4:4 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_MS_MMU_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_MS_MMU_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_MS_MMU_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED3 5:5 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED3_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED3_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED4 6:6 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED4_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED4_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED5 7:7 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED5_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED5_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED6 8:8 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED6_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED6_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED7 9:9 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED7_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED7_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED8 10:10 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED8_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED8_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_HOST_ESCHED8_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_PMU2FB_TRAFFIC 19:19 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_PMU2FB_TRAFFIC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_PMU2FB_TRAFFIC_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_PMU2FB_TRAFFIC_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_CE_3 20:20 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_CE_3_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_CE_3_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_CE_3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_CE_4 21:21 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_CE_4_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_CE_4_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_CE_4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_SEC_FBIF 27:27 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_SEC_FBIF_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_SEC_FBIF_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_SEC_FBIF_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_SW0 30:30 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_SW0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_SW0_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_SW0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_SW1 31:31 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_SW1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_SW1_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_1_SW1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2(i) (0x0010bec0+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_IDLE_MASK_2__SIZE_1 16 /* */
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#define NV_PPWR_PMU_IDLE_MASK_2__PRIV_LEVEL_MASK 0x0010ab0c /* */
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#define NV_PPWR_PMU_IDLE_MASK_2_GSP_FB 6:6 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_2_GSP_FB_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_2_GSP_FB_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_GSP_FB_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_VD_NVDEC1 8:8 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_2_VD_NVDEC1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_2_VD_NVDEC1_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_VD_NVDEC1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_GR 14:14 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_GR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_GR_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_GR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_MS 15:15 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_MS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_MS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_GSP_PRIV_BLOCKER_MS_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_GR 16:16 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_GR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_GR_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_GR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_MS 17:17 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_MS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_MS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_SEC_PRIV_BLOCKER_MS_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_VD_OFA 28:28 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_2_VD_OFA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_2_VD_OFA_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_VD_OFA_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_MS 29:29 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_MS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_MS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_MS_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_GR 30:30 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_GR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_GR_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_XVE_BAR_BLK_GR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_SW2 31:31 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_2_SW2_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_2_SW2_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_MASK_2_SW2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_COUNT(i) (0x0010bf80+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_IDLE_COUNT__SIZE_1 16 /* */
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#define NV_PPWR_PMU_IDLE_COUNT__PRIV_LEVEL_MASK 0x0010ab0c /* */
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#define NV_PPWR_PMU_IDLE_COUNT_VALUE 30:0 /* R-IVF */
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#define NV_PPWR_PMU_IDLE_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_COUNT_RESET 31:31 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_COUNT_RESET_DONE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_COUNT_RESET_NOT_DONE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_IDLE_COUNT_RESET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_IDLE_CTRL(i) (0x0010bfc0+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_IDLE_CTRL__SIZE_1 16 /* */
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#define NV_PPWR_PMU_IDLE_CTRL__PRIV_LEVEL_MASK 0x0010ab0c /* */
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#define NV_PPWR_PMU_IDLE_CTRL_VALUE 1:0 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_CTRL_VALUE_NEVER 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_CTRL_VALUE_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_CTRL_VALUE_BUSY 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_IDLE_CTRL_VALUE_ALWAYS 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_IDLE_CTRL_FILTER 2:2 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_CTRL_FILTER_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_CTRL_FILTER_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_CTRL_FILTER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_THRESHOLD(i) (0x0010be00+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_IDLE_THRESHOLD__SIZE_1 16 /* */
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#define NV_PPWR_PMU_IDLE_THRESHOLD_VALUE 30:0 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_THRESHOLD_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_INTR 0x0010a9e8 /* RW-4R */
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#define NV_PPWR_PMU_IDLE_INTR_EN 0:0 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_INTR_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_INTR_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_IDLE_INTR_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_INTR_STATUS 0x0010a9ec /* RW-4R */
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#define NV_PPWR_PMU_IDLE_INTR_STATUS_INTR 0:0 /* RWIUF */
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#define NV_PPWR_PMU_IDLE_INTR_STATUS_INTR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IDLE_INTR_STATUS_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IDLE_INTR_STATUS_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_IDLE_MASK_SUPP(i) (0x0010a9f0+(i)*8) /* RW-4A */
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#define NV_PPWR_PMU_IDLE_MASK_SUPP__SIZE_1 8 /* */
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#define NV_PPWR_PMU_IDLE_MASK_SUPP__PRIV_LEVEL_MASK 0x0010a7dc /* */
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#define NV_PPWR_PMU_IDLE_MASK_SUPP_IDX_GR 0 /* */
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#define NV_PPWR_PMU_IDLE_MASK_SUPP_IDX_VID 1 /* */
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#define NV_PPWR_PMU_IDLE_MASK_SUPP_IDX_HISTOGRAM_0 2 /* */
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#define NV_PPWR_PMU_IDLE_MASK_SUPP_IDX_HISTOGRAM_1 3 /* */
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#define NV_PPWR_PMU_IDLE_MASK_SUPP_IDX_MS 4 /* */
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#define NV_PPWR_PMU_IDLE_MASK_SUPP_IDX_HISTOGRAM_2 5 /* */
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#define NV_PPWR_PMU_IDLE_MASK_SUPP_IDX_HISTOGRAM_3 6 /* */
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#define NV_PPWR_PMU_IDLE_MASK_SUPP_IDX_DI 7 /* */
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#define NV_PPWR_PMU_IDLE_MASK_SUPP_VALUE 31:0 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_SUPP_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_1_SUPP(i) (0x0010a9f4+(i)*8) /* RW-4A */
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#define NV_PPWR_PMU_IDLE_MASK_1_SUPP__SIZE_1 8 /* */
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#define NV_PPWR_PMU_IDLE_MASK_1_SUPP_VALUE 31:0 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_1_SUPP_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_MASK_2_SUPP(i) (0x0010a690+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_IDLE_MASK_2_SUPP__SIZE_1 8 /* */
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#define NV_PPWR_PMU_IDLE_MASK_2_SUPP_VALUE 31:0 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_MASK_2_SUPP_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP(i) (0x0010aa30+(i)*8) /* RW-4A */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP__SIZE_1 8 /* */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP_IDX_GR 0 /* */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP_IDX_VID 1 /* */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP_IDX_HISTOGRAM_0 2 /* */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP_IDX_HISTOGRAM_1 3 /* */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP_IDX_MS 4 /* */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP_IDX_HISTOGRAM_2 5 /* */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP_IDX_HISTOGRAM_3 6 /* */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP_IDX_DI 7 /* */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP_VALUE 1:0 /* RWIVF */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP_VALUE_NEVER 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP_VALUE_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP_VALUE_BUSY 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_IDLE_CTRL_SUPP_VALUE_ALWAYS 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL(i) (0x0010a8c0+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_START 0:0 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_START_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_START_OFF 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_START_PAUSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_START_ON 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_START_RESUME 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_RESET 4:4 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_RESET_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_RESET_OFF 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_RESET_ON 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_SHIFTWINDOW 12:8 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_SHIFTWINDOW_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_SHIFTWINDOW_MIN 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_SHIFTWINDOW_MAX 0x00000010 /* -W--V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_LOAD 16:16 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_LOAD_INIT 0x00000000 /* --I-V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_LOAD_TRIG 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_MODE 20:20 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_MODE_FIXED 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_HISTOGRAM_CTRL_MODE_FLOAT 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_HISTOGRAM_COUNT(i) (0x0010a8d0+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_HISTOGRAM_COUNT__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_COUNT_VALUE 31:0 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_COUNT_VALUE_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_COUNT_INCR(i) (0x0010a960+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_HISTOGRAM_COUNT_INCR__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_COUNT_INCR__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_HISTOGRAM_COUNT_INCR_VALUE 31:0 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_COUNT_INCR_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS3TO0(i) (0x0010a600+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS3TO0__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS3TO0__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS3TO0_00 7:0 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS3TO0_00_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS3TO0_01 15:8 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS3TO0_01_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS3TO0_02 23:16 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS3TO0_02_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS3TO0_03 31:24 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS3TO0_03_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS7TO4(i) (0x0010a610+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS7TO4__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS7TO4__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS7TO4_04 7:0 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS7TO4_04_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS7TO4_05 15:8 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS7TO4_05_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS7TO4_06 23:16 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS7TO4_06_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS7TO4_07 31:24 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS7TO4_07_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS11TO8(i) (0x0010a620+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS11TO8__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS11TO8__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS11TO8_08 7:0 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS11TO8_08_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS11TO8_09 15:8 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS11TO8_09_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS11TO8_10 23:16 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS11TO8_10_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS11TO8_11 31:24 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS11TO8_11_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS15TO12(i) (0x0010a630+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS15TO12__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS15TO12__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS15TO12_12 7:0 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS15TO12_12_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS15TO12_13 15:8 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS15TO12_13_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS15TO12_14 23:16 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS15TO12_14_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS15TO12_15 31:24 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_FLOORS15TO12_15_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS1TO0(i) (0x0010a8e0+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_HISTOGRAM_BINS1TO0__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_BINS1TO0_00 15:0 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS1TO0_00_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS1TO0_01 31:16 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS1TO0_01_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS3TO2(i) (0x0010a8f0+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_HISTOGRAM_BINS3TO2__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_BINS3TO2_02 15:0 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS3TO2_02_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS3TO2_03 31:16 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS3TO2_03_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS5TO4(i) (0x0010a900+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_HISTOGRAM_BINS5TO4__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_BINS5TO4_04 15:0 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS5TO4_04_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS5TO4_05 31:16 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS5TO4_05_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS7TO6(i) (0x0010a910+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_HISTOGRAM_BINS7TO6__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_BINS7TO6_06 15:0 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS7TO6_06_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS7TO6_07 31:16 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS7TO6_07_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS9TO8(i) (0x0010a920+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_HISTOGRAM_BINS9TO8__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_BINS9TO8_08 15:0 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS9TO8_08_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS9TO8_09 31:16 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS9TO8_09_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS11TO10(i) (0x0010a930+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_HISTOGRAM_BINS11TO10__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_BINS11TO10_10 15:0 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS11TO10_10_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS11TO10_11 31:16 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS11TO10_11_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS13TO12(i) (0x0010a940+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_HISTOGRAM_BINS13TO12__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_BINS13TO12_12 15:0 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS13TO12_12_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS13TO12_13 31:16 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS13TO12_13_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS15TO14(i) (0x0010a950+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_HISTOGRAM_BINS15TO14__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_BINS15TO14_14 15:0 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS15TO14_14_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS15TO14_15 31:16 /* R-IUF */
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#define NV_PPWR_PMU_HISTOGRAM_BINS15TO14_15_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_HISTOGRAM_SCALING 0x0010a9e0 /* RW-4R */
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#define NV_PPWR_PMU_HISTOGRAM_SCALING__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_HISTOGRAM_SCALING_EN 0:0 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_SCALING_EN_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_SCALING_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_HISTOGRAM_SCALING_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_HISTOGRAM_SCALING_X 11:8 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_SCALING_X_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_HISTOGRAM_SCALING_Y 15:12 /* RWIUF */
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#define NV_PPWR_PMU_HISTOGRAM_SCALING_Y_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_IP_VER 0x0010a430 /* R--4R */
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#define NV_PPWR_PMU_IP_VER_DEV 7:0 /* R-IVF */
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#define NV_PPWR_PMU_IP_VER_DEV_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IP_VER_ECO 15:8 /* R-IVF */
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#define NV_PPWR_PMU_IP_VER_ECO_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_IP_VER_MINOR 23:16 /* R-IVF */
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#define NV_PPWR_PMU_IP_VER_MINOR_INIT 0x00000002 /* R-I-V */
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#define NV_PPWR_PMU_IP_VER_MINOR_GF119 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IP_VER_MINOR_GF117 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IP_VER_MINOR_GK104 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IP_VER_MINOR_GK110 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IP_VER_MINOR_GK208 0x00000002 /* R---V */
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#define NV_PPWR_PMU_IP_VER_MINOR_GK20A 0x00000000 /* R---V */
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#define NV_PPWR_PMU_IP_VER_MAJOR 31:24 /* R-IVF */
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#define NV_PPWR_PMU_IP_VER_MAJOR_INIT 0x00000002 /* R-I-V */
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#define NV_PPWR_PMU_IP_VER_MAJOR_GF119 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IP_VER_MAJOR_GF117 0x00000001 /* R---V */
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#define NV_PPWR_PMU_IP_VER_MAJOR_GK104 0x00000002 /* R---V */
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#define NV_PPWR_PMU_IP_VER_MAJOR_GK110 0x00000002 /* R---V */
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#define NV_PPWR_PMU_IP_VER_MAJOR_GK208 0x00000002 /* R---V */
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#define NV_PPWR_PMU_IP_VER_MAJOR_GK20A 0x00000003 /* R---V */
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#define NV_PPWR_PMU_DEBUG(i) (0x0010a5c0+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_DEBUG__SIZE_1 4 /* */
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#define NV_PPWR_PMU_DEBUG_VAL 31:0 /* R-IVF */
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#define NV_PPWR_PMU_DEBUG_VAL_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_MAILBOX(i) (0x0010a450+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_MAILBOX__SIZE_1 12 /* */
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#define NV_PPWR_PMU_MAILBOX_VAL 31:0 /* RWIVF */
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#define NV_PPWR_PMU_MAILBOX_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_DEBUG_TAG 0x0010a5f0 /* RW-4R */
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#define NV_PPWR_PMU_DEBUG_TAG_VAL 31:0 /* RWIVF */
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#define NV_PPWR_PMU_DEBUG_TAG_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_TPRIV_WRBE 0x0010a5f4 /* RW-4R */
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#define NV_PPWR_PMU_TPRIV_WRBE_VAL 3:0 /* RWIVF */
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#define NV_PPWR_PMU_TPRIV_WRBE_VAL_INIT 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_WSP_GP_MSGBOX 0x0010a5f8 /* RW-4R */
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#define NV_PPWR_PMU_WSP_GP_MSGBOX_VAL 31:0 /* RWIVF */
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#define NV_PPWR_PMU_WSP_GP_MSGBOX_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_WSP_GP_MSGBOX_1 0x0010ab78 /* RW-4R */
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#define NV_PPWR_PMU_WSP_GP_MSGBOX_1_VAL 31:0 /* RWIVF */
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#define NV_PPWR_PMU_WSP_GP_MSGBOX_1_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_WSP_GP_MSGBOX_2 0x0010ab7c /* RW-4R */
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#define NV_PPWR_PMU_WSP_GP_MSGBOX_2_VAL 31:0 /* RWIVF */
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#define NV_PPWR_PMU_WSP_GP_MSGBOX_2_VAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT 0x0010a7c0 /* R--4R */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PMU_2_FECS_REQ 0:0 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PMU_2_FECS_REQ_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PMU_2_FECS_REQ_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_PMU_2_FECS_REQ_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_FECS_2_PMU_ACK 1:1 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_FECS_2_PMU_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_FECS_2_PMU_ACK_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_FECS_2_PMU_ACK_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_FB_STOP_REQ 2:2 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_FB_STOP_REQ_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_FB_STOP_REQ_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_FB_STOP_REQ_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLK(i) (3+(i)):(3+(i)) /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLK__SIZE_1 3 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLK_INIT 0 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLK_FALSE 0 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLK_TRUE 1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLOCKS 3:3 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLOCKS_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLOCKS_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLOCKS_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLOCKS1 4:4 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLOCKS1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLOCKS1_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLOCKS1_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLOCKS2 5:5 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLOCKS2_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLOCKS2_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_STOPCLOCKS2_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL0 10:10 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL0_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL0_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL0_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL1 11:11 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL1_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL1_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL2 12:12 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL2_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL2_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL2_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL3 13:13 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL3_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL3_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL3_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL4 14:14 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL4_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL4_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL4_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL5 15:15 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL5_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL5_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL5_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL6 16:16 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL6_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL6_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL6_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL7 17:17 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL7_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL7_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL7_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL8 18:18 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL8_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL8_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL8_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL9 19:19 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL9_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL9_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL9_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL 19:10 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA0 20:20 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA0_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA0_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA0_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA1 21:21 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA1_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA1_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA2 22:22 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA2_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA2_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA2_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA3 23:23 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA3_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA3_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA3_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA4 24:24 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA4_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA4_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA4_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA5 25:25 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA5_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA5_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA5_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA6 26:26 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA6_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA6_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA6_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA7 27:27 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA7_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA7_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA7_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA8 28:28 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA8_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA8_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA8_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA9 29:29 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA9_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA9_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA9_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA 29:20 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL_IDX_FALSE 0 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SCL_IDX_TRUE 1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA_IDX_FALSE 0 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_I2C_SDA_IDX_TRUE 1 /* */
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#define NV_PPWR_PMU_GPIO_INPUT 0x0010a7c4 /* R--4R */
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#define NV_PPWR_PMU_GPIO_INPUT_PMU_2_FECS_ACK 0:0 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_PMU_2_FECS_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_PMU_2_FECS_ACK_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_PMU_2_FECS_ACK_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_FECS_2_PMU_REQ 1:1 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_FECS_2_PMU_REQ_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_FECS_2_PMU_REQ_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_FECS_2_PMU_REQ_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_FB_STOP_ACK 2:2 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_FB_STOP_ACK_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_FB_STOP_ACK_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_FB_STOP_ACK_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_XVE_INTR 3:3 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_XVE_INTR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_XVE_INTR_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_XVE_INTR_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_PMGR_INTR 8:8 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_PMGR_INTR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_PMGR_INTR_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_PMGR_INTR_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL0 10:10 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL0_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL0_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL0_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL1 11:11 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL1_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL1_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL2 12:12 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL2_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL2_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL2_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL3 13:13 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL3_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL3_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL3_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL4 14:14 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL4_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL4_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL4_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL5 15:15 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL5_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL5_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL5_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL6 16:16 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL6_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL6_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL6_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL7 17:17 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL7_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL7_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL7_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL8 18:18 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL8_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL8_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL8_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL9 19:19 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL9_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL9_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL9_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL 19:10 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA0 20:20 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA0_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA0_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA0_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA1 21:21 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA1_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA1_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA2 22:22 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA2_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA2_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA2_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA3 23:23 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA3_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA3_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA3_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA4 24:24 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA4_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA4_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA4_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA5 25:25 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA5_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA5_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA5_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA6 26:26 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA6_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA6_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA6_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA7 27:27 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA7_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA7_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA7_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA8 28:28 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA8_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA8_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA8_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA9 29:29 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA9_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA9_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA9_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA 29:20 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_DISP_2PMU_INTR 30:30 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_DISP_2PMU_INTR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_DISP_2PMU_INTR_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_DISP_2PMU_INTR_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_XVXP_DEEP_IDLE 31:31 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_INPUT_XVXP_DEEP_IDLE_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INPUT_XVXP_DEEP_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_XVXP_DEEP_IDLE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL_IDX_FALSE 0 /* */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SCL_IDX_TRUE 1 /* */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA_IDX_FALSE 0 /* */
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#define NV_PPWR_PMU_GPIO_INPUT_I2C_SDA_IDX_TRUE 1 /* */
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#define NV_PPWR_PMU_GPIO_1_INPUT 0x0010a7e8 /* R--4R */
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#define NV_PPWR_PMU_GPIO_1_INPUT_FBH_DWCF 1:1 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_FBH_DWCF_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_FBH_DWCF_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_FBH_DWCF_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_IHUB_OK_TO_SWITCH 3:3 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_IHUB_OK_TO_SWITCH_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_IHUB_OK_TO_SWITCH_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_IHUB_OK_TO_SWITCH_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_HSHUB1_FB_BLOCKER 11:11 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_HSHUB1_FB_BLOCKER_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_HSHUB1_FB_BLOCKER_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_HSHUB1_FB_BLOCKER_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_HSHUB_FB_BLOCKER 12:12 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_HSHUB_FB_BLOCKER_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_HSHUB_FB_BLOCKER_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_HSHUB_FB_BLOCKER_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_MEMPOOL_DRAINING 13:13 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_MEMPOOL_DRAINING_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_MEMPOOL_DRAINING_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_MEMPOOL_DRAINING_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_MSPG_WAKE 14:14 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_MSPG_WAKE_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_MSPG_WAKE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_MSPG_WAKE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XVE_BAR_GR_BLOCKER 15:15 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XVE_BAR_GR_BLOCKER_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XVE_BAR_GR_BLOCKER_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XVE_BAR_GR_BLOCKER_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XVE_BAR_BLOCKER 16:16 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XVE_BAR_BLOCKER_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XVE_BAR_BLOCKER_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XVE_BAR_BLOCKER_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_PERF_FB_BLOCKER 17:17 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_PERF_FB_BLOCKER_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_PERF_FB_BLOCKER_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_PERF_FB_BLOCKER_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_SEC_FB_BLOCKER 19:19 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_SEC_FB_BLOCKER_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_SEC_FB_BLOCKER_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_SEC_FB_BLOCKER_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_ISO_FB_BLOCKER 20:20 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_ISO_FB_BLOCKER_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_ISO_FB_BLOCKER_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_ISO_FB_BLOCKER_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_DNISO_FB_BLOCKER 21:21 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_DNISO_FB_BLOCKER_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_DNISO_FB_BLOCKER_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_DNISO_FB_BLOCKER_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_1 23:23 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_1_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_1_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_2 24:24 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_2_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_2_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_XP2PMU_STATE_IS_L1_2_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_SEC_PRIV_BLOCKER 25:25 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_SEC_PRIV_BLOCKER_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_SEC_PRIV_BLOCKER_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_SEC_PRIV_BLOCKER_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_GSP_FB_BLOCKER 26:26 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_GSP_FB_BLOCKER_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_GSP_FB_BLOCKER_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_GSP_FB_BLOCKER_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_GSP_PRIV_BLOCKER 27:27 /* R-IVF */
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#define NV_PPWR_PMU_GPIO_1_INPUT_GSP_PRIV_BLOCKER_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_GSP_PRIV_BLOCKER_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INPUT_GSP_PRIV_BLOCKER_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_BYPASS 0x0010a7c8 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_BYPASS__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_BYPASS_FECS_2_PMU 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_FECS_2_PMU_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_FECS_2_PMU_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL0 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL0_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL1 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL2 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL3 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL3_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL4 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL4_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL5 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL5_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL6 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL6_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL7 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL7_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL8 18:18 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL8_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL8_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL9 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL9_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL9_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL 19:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA0 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA0_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA1 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA2 22:22 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA3 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA3_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA4 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA4_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA5 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA5_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA6 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA6_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA7 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA7_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA8 28:28 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA8_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA8_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA9 29:29 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA9_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA9_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA 29:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL_IDX_DISABLED 0 /* */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SCL_IDX_ENABLED 1 /* */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA_IDX_DISABLED 0 /* */
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#define NV_PPWR_PMU_GPIO_BYPASS_I2C_SDA_IDX_ENABLED 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING 0x0010a7cc /* RW-4R */
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#define NV_PPWR_PMU_GPIO_INTR_RISING__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_PMU_2_FECS_ACK 0:0 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_PMU_2_FECS_ACK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_PMU_2_FECS_ACK_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_PMU_2_FECS_ACK_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_FECS_2_PMU_REQ 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_FECS_2_PMU_REQ_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_FECS_2_PMU_REQ_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_FECS_2_PMU_REQ_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_FB_STOP_ACK 2:2 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_FB_STOP_ACK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_FB_STOP_ACK_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_FB_STOP_ACK_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_XVE_INTR 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_XVE_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_XVE_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_XVE_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_PMGR_INTR 8:8 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_PMGR_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_PMGR_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_PMGR_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL0 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL1 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL2 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL3 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL3_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL4 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL4_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL5 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL5_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL5_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL6 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL6_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL6_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL7 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL7_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL7_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL8 18:18 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL8_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL8_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL9 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL9_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL9_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL 19:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA0 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA1 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA2 22:22 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA3 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA3_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA4 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA4_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA5 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA5_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA5_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA6 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA6_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA6_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA7 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA7_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA7_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA8 28:28 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA8_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA8_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA9 29:29 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA9_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA9_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA 29:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_DISP_2PMU_INTR 30:30 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_DISP_2PMU_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_DISP_2PMU_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_DISP_2PMU_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_XVXP_DEEP_IDLE 31:31 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_XVXP_DEEP_IDLE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_XVXP_DEEP_IDLE_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_XVXP_DEEP_IDLE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL_IDX_NOT_PENDING 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL_IDX_PENDING 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SCL_IDX_CLEAR 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA_IDX_NOT_PENDING 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA_IDX_PENDING 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_I2C_SDA_IDX_CLEAR 1 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING 0x0010a7ec /* RW-4R */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_FBH_DWCF 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_FBH_DWCF_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_FBH_DWCF_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_FBH_DWCF_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_IHUB_OK_TO_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_IHUB_OK_TO_SWITCH_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_IHUB_OK_TO_SWITCH_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_HSHUB1_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_HSHUB1_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_HSHUB1_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_HSHUB_FB_BLOCKER 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_HSHUB_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_HSHUB_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_HSHUB_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_MEMPOOL_DRAINING 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_MEMPOOL_DRAINING_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_MEMPOOL_DRAINING_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_MEMPOOL_DRAINING_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_MSPG_WAKE 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_MSPG_WAKE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_MSPG_WAKE_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_MSPG_WAKE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_GR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_GR_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_GR_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_BLOCKER 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XVE_BAR_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_PERF_FB_BLOCKER 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_PERF_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_PERF_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_PERF_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_SEC_FB_BLOCKER 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_SEC_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_SEC_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_SEC_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_ISO_FB_BLOCKER 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_ISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_ISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_ISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_DNISO_FB_BLOCKER 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_DNISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_DNISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_DNISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_XP2PMU_STATE_IS_L1_2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_SEC_PRIV_BLOCKER 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_SEC_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_SEC_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_SEC_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_GSP_FB_BLOCKER 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_GSP_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_GSP_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_GSP_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_GSP_PRIV_BLOCKER 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_GSP_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_GSP_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_GSP_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING 0x0010a7d0 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_PMU_2_FECS_ACK 0:0 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_PMU_2_FECS_ACK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_PMU_2_FECS_ACK_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_PMU_2_FECS_ACK_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_FECS_2_PMU_REQ 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_FECS_2_PMU_REQ_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_FECS_2_PMU_REQ_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_FECS_2_PMU_REQ_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_FB_STOP_ACK 2:2 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_FB_STOP_ACK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_FB_STOP_ACK_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_FB_STOP_ACK_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_XVE_INTR 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_XVE_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_XVE_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_XVE_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_PMGR_INTR 8:8 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_PMGR_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_PMGR_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_PMGR_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL0 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL1 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL2 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL3 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL3_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL4 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL4_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL5 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL5_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL5_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL6 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL6_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL6_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL7 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL7_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL7_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL8 18:18 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL8_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL8_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL9 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL9_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL9_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL 19:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA0 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA1 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA2 22:22 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA3 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA3_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA4 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA4_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA5 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA5_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA5_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA6 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA6_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA6_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA7 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA7_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA7_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA8 28:28 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA8_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA8_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA9 29:29 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA9_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA9_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA 29:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_DISP_2PMU_INTR 30:30 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_DISP_2PMU_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_DISP_2PMU_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_DISP_2PMU_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_XVXP_DEEP_IDLE 31:31 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_XVXP_DEEP_IDLE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_XVXP_DEEP_IDLE_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_XVXP_DEEP_IDLE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL_IDX_NOT_PENDING 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL_IDX_PENDING 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SCL_IDX_CLEAR 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA_IDX_NOT_PENDING 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA_IDX_PENDING 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_I2C_SDA_IDX_CLEAR 1 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING 0x0010a7f0 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_FBH_DWCF 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_FBH_DWCF_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_FBH_DWCF_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_FBH_DWCF_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_IHUB_OK_TO_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_IHUB_OK_TO_SWITCH_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_IHUB_OK_TO_SWITCH_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_HSHUB1_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_HSHUB1_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_HSHUB1_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_HSHUB_FB_BLOCKER 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_HSHUB_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_HSHUB_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_HSHUB_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_MEMPOOL_DRAINING 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_MEMPOOL_DRAINING_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_MEMPOOL_DRAINING_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_MEMPOOL_DRAINING_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_MSPG_WAKE 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_MSPG_WAKE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_MSPG_WAKE_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_MSPG_WAKE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_GR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_GR_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_GR_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_BLOCKER 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XVE_BAR_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_PERF_FB_BLOCKER 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_PERF_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_PERF_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_PERF_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_SEC_FB_BLOCKER 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_SEC_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_SEC_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_SEC_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_ISO_FB_BLOCKER 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_ISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_ISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_ISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_DNISO_FB_BLOCKER 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_DNISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_DNISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_DNISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_XP2PMU_STATE_IS_L1_2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_SEC_PRIV_BLOCKER 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_SEC_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_SEC_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_SEC_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_GSP_FB_BLOCKER 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_GSP_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_GSP_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_GSP_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_GSP_PRIV_BLOCKER 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_GSP_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_GSP_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_GSP_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN 0x0010a7d4 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_PMU_2_FECS_ACK 0:0 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_PMU_2_FECS_ACK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_PMU_2_FECS_ACK_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_FECS_2_PMU_REQ 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_FECS_2_PMU_REQ_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_FECS_2_PMU_REQ_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_FB_STOP_ACK 2:2 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_FB_STOP_ACK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_FB_STOP_ACK_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_XVE_INTR 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_XVE_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_XVE_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_PMGR_INTR 8:8 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_PMGR_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_PMGR_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL0 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL0_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL1 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL2 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL3 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL3_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL4 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL4_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL5 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL5_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL6 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL6_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL7 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL7_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL8 18:18 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL8_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL8_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL9 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL9_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL9_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL 19:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA0 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA0_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA1 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA2 22:22 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA3 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA3_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA4 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA4_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA5 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA5_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA6 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA6_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA7 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA7_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA8 28:28 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA8_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA8_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA9 29:29 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA9_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA9_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA 29:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_DISP_2PMU_INTR 30:30 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_DISP_2PMU_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_DISP_2PMU_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_XVXP_DEEP_IDLE 31:31 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_XVXP_DEEP_IDLE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_XVXP_DEEP_IDLE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL_IDX_DISABLED 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SCL_IDX_ENABLED 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA_IDX_DISABLED 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_RISING_EN_I2C_SDA_IDX_ENABLED 1 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN 0x0010a7f4 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_FBH_DWCF 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_FBH_DWCF_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_FBH_DWCF_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_IHUB_OK_TO_SWITCH_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_IHUB_OK_TO_SWITCH_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_HSHUB1_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_HSHUB1_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_HSHUB_FB_BLOCKER 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_HSHUB_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_HSHUB_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_MEMPOOL_DRAINING 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_MEMPOOL_DRAINING_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_MEMPOOL_DRAINING_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_MSPG_WAKE 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_MSPG_WAKE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_MSPG_WAKE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_XVE_BAR_GR_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_XVE_BAR_GR_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_XVE_BAR_BLOCKER 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_XVE_BAR_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_XVE_BAR_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_PERF_FB_BLOCKER 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_PERF_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_PERF_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_SEC_FB_BLOCKER 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_SEC_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_SEC_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_ISO_FB_BLOCKER 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_ISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_ISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_DNISO_FB_BLOCKER 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_DNISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_DNISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_XP2PMU_STATE_IS_L1_1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_XP2PMU_STATE_IS_L1_1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_XP2PMU_STATE_IS_L1_2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_XP2PMU_STATE_IS_L1_2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_SEC_PRIV_BLOCKER 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_SEC_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_SEC_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_GSP_FB_BLOCKER 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_GSP_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_GSP_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_GSP_PRIV_BLOCKER 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_GSP_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_RISING_EN_GSP_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN 0x0010a7d8 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_PMU_2_FECS_ACK 0:0 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_PMU_2_FECS_ACK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_PMU_2_FECS_ACK_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_FECS_2_PMU_REQ 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_FECS_2_PMU_REQ_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_FECS_2_PMU_REQ_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_FB_STOP_ACK 2:2 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_FB_STOP_ACK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_FB_STOP_ACK_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_XVE_INTR 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_XVE_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_XVE_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_PMGR_INTR 8:8 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_PMGR_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_PMGR_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL0 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL0_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL1 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL2 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL3 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL3_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL4 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL4_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL5 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL5_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL6 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL6_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL7 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL7_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL8 18:18 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL8_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL8_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL9 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL9_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL9_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL 19:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA0 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA0_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA1 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA2 22:22 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA3 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA3_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA4 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA4_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA5 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA5_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA6 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA6_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA7 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA7_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA8 28:28 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA8_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA8_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA9 29:29 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA9_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA9_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA 29:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_DISP_2PMU_INTR 30:30 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_DISP_2PMU_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_DISP_2PMU_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_XVXP_DEEP_IDLE 31:31 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_XVXP_DEEP_IDLE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_XVXP_DEEP_IDLE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL_IDX_DISABLED 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SCL_IDX_ENABLED 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA_IDX_DISABLED 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_FALLING_EN_I2C_SDA_IDX_ENABLED 1 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN 0x0010a7f8 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_FBH_DWCF 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_FBH_DWCF_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_FBH_DWCF_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_IHUB_OK_TO_SWITCH_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_IHUB_OK_TO_SWITCH_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_HSHUB1_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_HSHUB1_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_HSHUB_FB_BLOCKER 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_HSHUB_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_HSHUB_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_MEMPOOL_DRAINING 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_MEMPOOL_DRAINING_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_MEMPOOL_DRAINING_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_MSPG_WAKE 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_MSPG_WAKE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_MSPG_WAKE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_XVE_BAR_GR_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_XVE_BAR_GR_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_XVE_BAR_BLOCKER 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_XVE_BAR_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_XVE_BAR_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_PERF_FB_BLOCKER 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_PERF_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_PERF_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_SEC_FB_BLOCKER 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_SEC_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_SEC_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_ISO_FB_BLOCKER 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_ISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_ISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_DNISO_FB_BLOCKER 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_DNISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_DNISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_XP2PMU_STATE_IS_L1_1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_XP2PMU_STATE_IS_L1_1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_XP2PMU_STATE_IS_L1_2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_XP2PMU_STATE_IS_L1_2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_SEC_PRIV_BLOCKER 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_SEC_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_SEC_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_GSP_FB_BLOCKER 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_GSP_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_GSP_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_GSP_PRIV_BLOCKER 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_GSP_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_FALLING_EN_GSP_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET 0x0010a7e0 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET__PRIV_LEVEL_MASK 0x0010a53c /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_PMU_2_FECS_REQ 0:0 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_PMU_2_FECS_REQ_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_PMU_2_FECS_REQ_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_PMU_2_FECS_REQ_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_PMU_2_FECS_REQ_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_FECS_2_PMU_ACK 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_FECS_2_PMU_ACK_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_FECS_2_PMU_ACK_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_FECS_2_PMU_ACK_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_FECS_2_PMU_ACK_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_FB_STOP_REQ 2:2 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_FB_STOP_REQ_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_FB_STOP_REQ_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_FB_STOP_REQ_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_FB_STOP_REQ_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLK(i) (3+(i)):(3+(i)) /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLK__SIZE_1 3 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLK_INIT 0 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLK_FALSE 0 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLK_TRUE 1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLK_TRIGGER 1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS1 4:4 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS1_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS1_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS1_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS1_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS2 5:5 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS2_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS2_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS2_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_STOPCLOCKS2_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL0 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL0_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL0_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL0_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL0_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL1 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL1_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL1_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL1_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL1_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL2 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL2_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL2_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL2_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL2_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL3 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL3_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL3_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL3_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL3_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL4 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL4_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL4_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL4_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL4_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL5 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL5_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL5_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL5_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL5_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL6 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL6_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL6_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL6_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL6_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL7 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL7_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL7_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL7_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL7_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL8 18:18 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL8_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL8_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL8_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL8_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL9 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL9_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL9_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL9_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL9_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL 19:10 /* -WIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA0 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA0_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA0_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA0_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA0_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA1 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA1_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA1_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA1_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA1_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA2 22:22 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA2_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA2_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA2_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA2_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA3 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA3_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA3_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA3_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA3_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA4 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA4_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA4_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA4_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA4_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA5 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA5_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA5_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA5_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA5_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA6 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA6_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA6_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA6_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA6_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA7 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA7_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA7_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA7_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA7_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA8 28:28 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA8_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA8_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA8_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA8_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA9 29:29 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA9_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA9_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA9_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA9_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA 29:20 /* -WIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL_IDX_FALSE 0 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL_IDX_TRUE 1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SCL_IDX_TRIGGER 1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA_IDX_FALSE 0 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA_IDX_TRUE 1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_SET_I2C_SDA_IDX_TRIGGER 1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR 0x0010a7e4 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR__PRIV_LEVEL_MASK 0x0010a53c /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_PMU_2_FECS_REQ 0:0 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_PMU_2_FECS_REQ_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_PMU_2_FECS_REQ_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_PMU_2_FECS_REQ_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_PMU_2_FECS_REQ_CLEAR 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_FECS_2_PMU_ACK 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_FECS_2_PMU_ACK_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_FECS_2_PMU_ACK_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_FECS_2_PMU_ACK_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_FECS_2_PMU_ACK_CLEAR 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_FB_STOP_REQ 2:2 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_FB_STOP_REQ_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_FB_STOP_REQ_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_FB_STOP_REQ_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_FB_STOP_REQ_CLEAR 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLK(i) (3+(i)):(3+(i)) /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLK__SIZE_1 3 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLK_INIT 0 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLK_FALSE 0 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLK_TRUE 1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLK_CLEAR 1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS_CLEAR 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS1 4:4 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS1_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS1_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS1_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS1_CLEAR 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS2 5:5 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS2_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS2_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS2_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_STOPCLOCKS2_CLEAR 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL0 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL0_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL0_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL0_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL0_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL1 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL1_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL1_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL1_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL1_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL2 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL2_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL2_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL2_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL2_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL3 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL3_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL3_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL3_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL3_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL4 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL4_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL4_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL4_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL4_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL5 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL5_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL5_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL5_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL5_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL6 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL6_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL6_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL6_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL6_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL7 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL7_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL7_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL7_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL7_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL8 18:18 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL8_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL8_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL8_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL8_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL9 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL9_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL9_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL9_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL9_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL 19:10 /* -WIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA0 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA0_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA0_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA0_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA0_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA1 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA1_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA1_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA1_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA1_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA2 22:22 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA2_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA2_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA2_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA2_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA3 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA3_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA3_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA3_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA3_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA4 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA4_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA4_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA4_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA4_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA5 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA5_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA5_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA5_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA5_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA6 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA6_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA6_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA6_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA6_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA7 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA7_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA7_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA7_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA7_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA8 28:28 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA8_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA8_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA8_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA8_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA9 29:29 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA9_INIT 0x00000000 /* -WI-V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA9_FALSE 0x00000000 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA9_TRUE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA9_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA 29:20 /* -WIVF */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL_IDX_FALSE 0 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL_IDX_TRUE 1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SCL_IDX_CLEAR 1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA_IDX_FALSE 0 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA_IDX_TRUE 1 /* */
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#define NV_PPWR_PMU_GPIO_OUTPUT_CLEAR_I2C_SDA_IDX_CLEAR 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH 0x0010a550 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_PMU_2_FECS_ACK 0:0 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_PMU_2_FECS_ACK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_PMU_2_FECS_ACK_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_PMU_2_FECS_ACK_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_FECS_2_PMU_REQ 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_FECS_2_PMU_REQ_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_FECS_2_PMU_REQ_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_FECS_2_PMU_REQ_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_FB_STOP_ACK 2:2 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_FB_STOP_ACK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_FB_STOP_ACK_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_FB_STOP_ACK_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_XVE_INTR 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_XVE_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_XVE_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_XVE_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_PMGR_INTR 8:8 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_PMGR_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_PMGR_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_PMGR_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL0 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL1 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL2 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL3 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL3_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL4 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL4_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL5 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL5_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL5_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL6 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL6_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL6_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL7 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL7_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL7_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL8 18:18 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL8_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL8_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL9 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL9_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL9_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL 19:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA0 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA1 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA2 22:22 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA3 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA3_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA4 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA4_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA5 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA5_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA5_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA6 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA6_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA6_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA7 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA7_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA7_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA8 28:28 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA8_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA8_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA9 29:29 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA9_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA9_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA 29:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_DISP_2PMU_INTR 30:30 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_DISP_2PMU_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_DISP_2PMU_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_DISP_2PMU_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_XVXP_DEEP_IDLE 31:31 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_XVXP_DEEP_IDLE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_XVXP_DEEP_IDLE_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_XVXP_DEEP_IDLE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL_IDX_NOT_PENDING 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL_IDX_PENDING 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SCL_IDX_CLEAR 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA_IDX_NOT_PENDING 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA_IDX_PENDING 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_I2C_SDA_IDX_CLEAR 1 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH 0x0010a554 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_FBH_DWCF 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_FBH_DWCF_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_FBH_DWCF_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_FBH_DWCF_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_IHUB_OK_TO_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_IHUB_OK_TO_SWITCH_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_IHUB_OK_TO_SWITCH_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_HSHUB1_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_HSHUB1_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_HSHUB1_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_HSHUB_FB_BLOCKER 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_HSHUB_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_HSHUB_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_HSHUB_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_MEMPOOL_DRAINING 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_MEMPOOL_DRAINING_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_MEMPOOL_DRAINING_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_MEMPOOL_DRAINING_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_MSPG_WAKE 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_MSPG_WAKE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_MSPG_WAKE_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_MSPG_WAKE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_GR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_GR_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_GR_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_BLOCKER 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XVE_BAR_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_PERF_FB_BLOCKER 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_PERF_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_PERF_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_PERF_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_SEC_FB_BLOCKER 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_SEC_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_SEC_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_SEC_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_ISO_FB_BLOCKER 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_ISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_ISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_ISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_DNISO_FB_BLOCKER 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_DNISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_DNISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_DNISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_XP2PMU_STATE_IS_L1_2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_SEC_PRIV_BLOCKER 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_SEC_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_SEC_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_SEC_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_GSP_FB_BLOCKER 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_GSP_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_GSP_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_GSP_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_GSP_PRIV_BLOCKER 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_GSP_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_GSP_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_GSP_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW 0x0010a558 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_INTR_LOW__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_PMU_2_FECS_ACK 0:0 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_PMU_2_FECS_ACK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_PMU_2_FECS_ACK_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_PMU_2_FECS_ACK_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_FECS_2_PMU_REQ 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_FECS_2_PMU_REQ_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_FECS_2_PMU_REQ_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_FECS_2_PMU_REQ_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_FB_STOP_ACK 2:2 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_FB_STOP_ACK_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_FB_STOP_ACK_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_FB_STOP_ACK_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_XVE_INTR 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_XVE_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_XVE_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_XVE_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_PMGR_INTR 8:8 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_PMGR_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_PMGR_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_PMGR_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL0 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL1 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL2 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL3 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL3_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL4 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL4_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL5 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL5_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL5_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL6 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL6_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL6_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL7 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL7_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL7_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL8 18:18 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL8_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL8_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL9 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL9_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL9_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL 19:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA0 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA0_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA1 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA2 22:22 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA3 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA3_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA3_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA4 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA4_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA4_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA5 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA5_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA5_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA5_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA6 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA6_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA6_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA6_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA7 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA7_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA7_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA7_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA8 28:28 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA8_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA8_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA8_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA9 29:29 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA9_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA9_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA9_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA 29:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_DISP_2PMU_INTR 30:30 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_DISP_2PMU_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_DISP_2PMU_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_DISP_2PMU_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_XVXP_DEEP_IDLE 31:31 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_XVXP_DEEP_IDLE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_XVXP_DEEP_IDLE_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_XVXP_DEEP_IDLE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL_IDX_NOT_PENDING 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL_IDX_PENDING 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SCL_IDX_CLEAR 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA_IDX_NOT_PENDING 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA_IDX_PENDING 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_I2C_SDA_IDX_CLEAR 1 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW 0x0010a55c /* RW-4R */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_FBH_DWCF 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_FBH_DWCF_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_FBH_DWCF_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_FBH_DWCF_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_IHUB_OK_TO_SWITCH_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_IHUB_OK_TO_SWITCH_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_IHUB_OK_TO_SWITCH_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_HSHUB1_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_HSHUB1_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_HSHUB1_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_HSHUB_FB_BLOCKER 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_HSHUB_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_HSHUB_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_HSHUB_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_MEMPOOL_DRAINING 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_MEMPOOL_DRAINING_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_MEMPOOL_DRAINING_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_MEMPOOL_DRAINING_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_MSPG_WAKE 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_MSPG_WAKE_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_MSPG_WAKE_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_MSPG_WAKE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_GR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_GR_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_GR_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_BLOCKER 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XVE_BAR_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_PERF_FB_BLOCKER 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_PERF_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_PERF_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_PERF_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_SEC_FB_BLOCKER 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_SEC_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_SEC_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_SEC_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_ISO_FB_BLOCKER 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_ISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_ISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_ISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_DNISO_FB_BLOCKER 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_DNISO_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_DNISO_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_DNISO_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_1_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_2_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_XP2PMU_STATE_IS_L1_2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_SEC_PRIV_BLOCKER 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_SEC_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_SEC_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_SEC_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_GSP_FB_BLOCKER 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_GSP_FB_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_GSP_FB_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_GSP_FB_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_GSP_PRIV_BLOCKER 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_GSP_PRIV_BLOCKER_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_GSP_PRIV_BLOCKER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_GSP_PRIV_BLOCKER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN 0x0010a560 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_PMU_2_FECS_ACK 0:0 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_PMU_2_FECS_ACK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_PMU_2_FECS_ACK_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_FECS_2_PMU_REQ 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_FECS_2_PMU_REQ_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_FECS_2_PMU_REQ_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_FB_STOP_ACK 2:2 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_FB_STOP_ACK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_FB_STOP_ACK_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_XVE_INTR 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_XVE_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_XVE_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_PMGR_INTR 8:8 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_PMGR_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_PMGR_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL0 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL0_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL1 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL2 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL3 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL3_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL4 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL4_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL5 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL5_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL6 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL6_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL7 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL7_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL8 18:18 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL8_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL8_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL9 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL9_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL9_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL 19:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA0 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA0_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA1 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA2 22:22 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA3 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA3_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA4 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA4_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA5 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA5_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA6 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA6_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA7 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA7_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA8 28:28 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA8_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA8_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA9 29:29 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA9_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA9_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA 29:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_DISP_2PMU_INTR 30:30 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_DISP_2PMU_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_DISP_2PMU_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_XVXP_DEEP_IDLE 31:31 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_XVXP_DEEP_IDLE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_XVXP_DEEP_IDLE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL_IDX_DISABLED 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SCL_IDX_ENABLED 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA_IDX_DISABLED 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_HIGH_EN_I2C_SDA_IDX_ENABLED 1 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN 0x0010a564 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_FBH_DWCF 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_FBH_DWCF_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_FBH_DWCF_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_IHUB_OK_TO_SWITCH_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_IHUB_OK_TO_SWITCH_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_HSHUB1_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_HSHUB1_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_HSHUB_FB_BLOCKER 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_HSHUB_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_HSHUB_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_MEMPOOL_DRAINING 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_MEMPOOL_DRAINING_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_MEMPOOL_DRAINING_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_MSPG_WAKE 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_MSPG_WAKE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_MSPG_WAKE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_XVE_BAR_GR_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_XVE_BAR_GR_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_XVE_BAR_BLOCKER 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_XVE_BAR_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_XVE_BAR_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_PERF_FB_BLOCKER 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_PERF_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_PERF_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_SEC_FB_BLOCKER 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_SEC_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_SEC_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_ISO_FB_BLOCKER 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_ISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_ISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_DNISO_FB_BLOCKER 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_DNISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_DNISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_XP2PMU_STATE_IS_L1_1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_XP2PMU_STATE_IS_L1_1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_XP2PMU_STATE_IS_L1_2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_XP2PMU_STATE_IS_L1_2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_SEC_PRIV_BLOCKER 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_SEC_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_SEC_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_GSP_FB_BLOCKER 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_GSP_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_GSP_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_GSP_PRIV_BLOCKER 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_GSP_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_HIGH_EN_GSP_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN 0x0010a568 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_PMU_2_FECS_ACK 0:0 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_PMU_2_FECS_ACK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_PMU_2_FECS_ACK_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_FECS_2_PMU_REQ 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_FECS_2_PMU_REQ_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_FECS_2_PMU_REQ_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_FB_STOP_ACK 2:2 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_FB_STOP_ACK_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_FB_STOP_ACK_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_XVE_INTR 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_XVE_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_XVE_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_PMGR_INTR 8:8 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_PMGR_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_PMGR_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL0 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL0_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL1 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL2 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL3 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL3_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL4 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL4_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL5 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL5_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL6 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL6_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL7 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL7_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL8 18:18 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL8_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL8_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL9 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL9_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL9_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL 19:10 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA0 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA0_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA0_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA1 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA2 22:22 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA3 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA3_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA3_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA4 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA4_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA4_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA5 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA5_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA5_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA6 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA6_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA6_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA7 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA7_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA7_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA8 28:28 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA8_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA8_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA9 29:29 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA9_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA9_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA 29:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_DISP_2PMU_INTR 30:30 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_DISP_2PMU_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_DISP_2PMU_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_XVXP_DEEP_IDLE 31:31 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_XVXP_DEEP_IDLE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_XVXP_DEEP_IDLE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL_IDX(i) (10+(i)):(10+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL_IDX_DISABLED 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SCL_IDX_ENABLED 1 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA_IDX(i) (20+(i)):(20+(i)) /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA_IDX__SIZE_1 10 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA_IDX_DISABLED 0 /* */
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#define NV_PPWR_PMU_GPIO_INTR_LOW_EN_I2C_SDA_IDX_ENABLED 1 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN 0x0010a56c /* RW-4R */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_FBH_DWCF 1:1 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_FBH_DWCF_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_FBH_DWCF_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_IHUB_OK_TO_SWITCH 3:3 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_IHUB_OK_TO_SWITCH_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_IHUB_OK_TO_SWITCH_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_HSHUB1_FB_BLOCKER 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_HSHUB1_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_HSHUB1_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_HSHUB_FB_BLOCKER 12:12 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_HSHUB_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_HSHUB_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_MEMPOOL_DRAINING 13:13 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_MEMPOOL_DRAINING_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_MEMPOOL_DRAINING_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_MSPG_WAKE 14:14 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_MSPG_WAKE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_MSPG_WAKE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_XVE_BAR_GR_BLOCKER 15:15 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_XVE_BAR_GR_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_XVE_BAR_GR_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_XVE_BAR_BLOCKER 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_XVE_BAR_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_XVE_BAR_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_PERF_FB_BLOCKER 17:17 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_PERF_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_PERF_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_SEC_FB_BLOCKER 19:19 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_SEC_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_SEC_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_ISO_FB_BLOCKER 20:20 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_ISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_ISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_DNISO_FB_BLOCKER 21:21 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_DNISO_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_DNISO_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_XP2PMU_STATE_IS_L1_1 23:23 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_XP2PMU_STATE_IS_L1_1_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_XP2PMU_STATE_IS_L1_1_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_XP2PMU_STATE_IS_L1_2 24:24 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_XP2PMU_STATE_IS_L1_2_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_XP2PMU_STATE_IS_L1_2_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_SEC_PRIV_BLOCKER 25:25 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_SEC_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_SEC_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_GSP_FB_BLOCKER 26:26 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_GSP_FB_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_GSP_FB_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_GSP_PRIV_BLOCKER 27:27 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_GSP_PRIV_BLOCKER_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_1_INTR_LOW_EN_GSP_PRIV_BLOCKER_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_2_INPUT 0x0010a88c /* R--4R */
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#define NV_PPWR_PMU_GPIO_2_INPUT_XVE_MARGINING_INTR 16:16 /* R--VF */
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#define NV_PPWR_PMU_GPIO_2_INPUT_XVE_MARGINING_INTR_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_GPIO_2_INPUT_XVE_MARGINING_INTR_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_2_INTR_RISING 0x0010a890 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_2_INTR_RISING__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_2_INTR_RISING_XVE_MARGINING_INTR 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_2_INTR_RISING_XVE_MARGINING_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_2_INTR_RISING_XVE_MARGINING_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_2_INTR_RISING_XVE_MARGINING_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_2_INTR_FALLING 0x0010a894 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_2_INTR_FALLING__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_2_INTR_FALLING_XVE_MARGINING_INTR 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_2_INTR_FALLING_XVE_MARGINING_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_2_INTR_FALLING_XVE_MARGINING_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_2_INTR_FALLING_XVE_MARGINING_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_2_INTR_RISING_EN 0x0010a898 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_2_INTR_RISING_EN__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_2_INTR_RISING_EN_XVE_MARGINING_INTR 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_2_INTR_RISING_EN_XVE_MARGINING_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_2_INTR_RISING_EN_XVE_MARGINING_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_2_INTR_FALLING_EN 0x0010a89c /* RW-4R */
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#define NV_PPWR_PMU_GPIO_2_INTR_FALLING_EN__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_2_INTR_FALLING_EN_XVE_MARGINING_INTR 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_2_INTR_FALLING_EN_XVE_MARGINING_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_2_INTR_FALLING_EN_XVE_MARGINING_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_2_INTR_HIGH 0x0010a570 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_2_INTR_HIGH__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_2_INTR_HIGH_XVE_MARGINING_INTR 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_2_INTR_HIGH_XVE_MARGINING_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_2_INTR_HIGH_XVE_MARGINING_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_2_INTR_HIGH_XVE_MARGINING_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_2_INTR_LOW 0x0010a574 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_2_INTR_LOW__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_2_INTR_LOW_XVE_MARGINING_INTR 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_2_INTR_LOW_XVE_MARGINING_INTR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_GPIO_2_INTR_LOW_XVE_MARGINING_INTR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_GPIO_2_INTR_LOW_XVE_MARGINING_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_GPIO_2_INTR_HIGH_EN 0x0010a578 /* RW-4R */
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#define NV_PPWR_PMU_GPIO_2_INTR_HIGH_EN__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_2_INTR_HIGH_EN_XVE_MARGINING_INTR 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_2_INTR_HIGH_EN_XVE_MARGINING_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_2_INTR_HIGH_EN_XVE_MARGINING_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_GPIO_2_INTR_LOW_EN 0x0010a57c /* RW-4R */
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#define NV_PPWR_PMU_GPIO_2_INTR_LOW_EN__PRIV_LEVEL_MASK 0x0010a538 /* */
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#define NV_PPWR_PMU_GPIO_2_INTR_LOW_EN_XVE_MARGINING_INTR 16:16 /* RWIVF */
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#define NV_PPWR_PMU_GPIO_2_INTR_LOW_EN_XVE_MARGINING_INTR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_GPIO_2_INTR_LOW_EN_XVE_MARGINING_INTR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_CSBMASTER_NULL_REQ 0x0010a880 /* RW-4R */
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#define NV_PPWR_PMU_CSBMASTER_NULL_REQ_ADDR 15:0 /* RWIVF */
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#define NV_PPWR_PMU_CSBMASTER_NULL_REQ_ADDR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_CSBMASTER_NULL_REQ_ADDR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_CSBMASTER_NULL_REQ_WRITE 16:16 /* RWIVF */
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#define NV_PPWR_PMU_CSBMASTER_NULL_REQ_WRITE_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_CSBMASTER_NULL_REQ_WRITE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_CSBMASTER_INTR_EN 0x0010a884 /* RW-4R */
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#define NV_PPWR_PMU_CSBMASTER_INTR_EN_NULL_REQ 0:0 /* RWIVF */
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#define NV_PPWR_PMU_CSBMASTER_INTR_EN_NULL_REQ_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_CSBMASTER_INTR_EN_NULL_REQ_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_CSBMASTER_INTR_EN_NULL_REQ_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_CSBMASTER_INTR 0x0010a888 /* RW-4R */
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#define NV_PPWR_PMU_CSBMASTER_INTR_NULL_REQ 0:0 /* RWIVF */
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#define NV_PPWR_PMU_CSBMASTER_INTR_NULL_REQ_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_CSBMASTER_INTR_NULL_REQ_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_CSBMASTER_INTR_NULL_REQ_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_0 0x0010a680 /* RW-4R */
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#define NV_PPWR_PMU_INTR_0__PRIV_LEVEL_MASK 0x0010a878 /* */
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#define NV_PPWR_PMU_INTR_0_TIMER 8:8 /* RWIUF */
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#define NV_PPWR_PMU_INTR_0_TIMER_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_0_TIMER_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_0_TIMER_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_0_EN 0x0010a684 /* RW-4R */
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#define NV_PPWR_PMU_INTR_0_EN__PRIV_LEVEL_MASK 0x0010a878 /* */
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#define NV_PPWR_PMU_INTR_0_EN_TIMER 8:8 /* RWIUF */
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#define NV_PPWR_PMU_INTR_0_EN_TIMER_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_INTR_1 0x0010a688 /* RW-4R */
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#define NV_PPWR_PMU_INTR_1__PRIV_LEVEL_MASK 0x0010a87c /* */
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#define NV_PPWR_PMU_INTR_1_CMD 1:1 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_CMD_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_CMD_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_CMD_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_1_ELPG_0 2:2 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_ELPG_0_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_ELPG_0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_ELPG_0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_1_ELPG_1 3:3 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_ELPG_1_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_ELPG_1_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_ELPG_1_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_1_BAR0 4:4 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_BAR0_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_BAR0_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_BAR0_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_1_BAU 7:7 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_BAU_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_BAU_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_BAU_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_1_UART 8:8 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_UART_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_UART_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_UART_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_1_ELPG_2 5:5 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_ELPG_2_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_ELPG_2_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_ELPG_2_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_1_HOLDOFF 9:9 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_HOLDOFF_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_HOLDOFF_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_HOLDOFF_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_1_ELPG_3 10:10 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_ELPG_3_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_ELPG_3_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_ELPG_3_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_1_CSBM 13:13 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_CSBM_INTT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_CSBM_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_CSBM_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_1_IDLE 14:14 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_IDLE_INTT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_IDLE_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_IDLE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_1_ELPG_4 15:15 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_ELPG_4_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_ELPG_4_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_ELPG_4_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_1_IDLE_EDGE 16:16 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_IDLE_EDGE_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_IDLE_EDGE_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_IDLE_EDGE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_INTR_1_SCP 17:17 /* RWIUF */
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#define NV_PPWR_PMU_INTR_1_SCP_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_INTR_1_SCP_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_INTR_1_SCP_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_UART_TX 0x0010a660 /* RW-4R */
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#define NV_PPWR_PMU_UART_TX_DATA 7:0 /* RWIVF */
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#define NV_PPWR_PMU_UART_TX_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_UART_TX_PUSH 8:8 /* RWIVF */
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#define NV_PPWR_PMU_UART_TX_PUSH_DONE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_UART_TX_PUSH_NOT_DONE 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_UART_TX_PUSH_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_UART_RX 0x0010a664 /* RW-4R */
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#define NV_PPWR_PMU_UART_RX_DATA 7:0 /* R--VF */
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#define NV_PPWR_PMU_UART_RX_POP 8:8 /* RWIVF */
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#define NV_PPWR_PMU_UART_RX_POP_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_UART_RX_POP_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_UART_RX_POP_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_UART_CTL 0x0010a668 /* RW-4R */
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#define NV_PPWR_PMU_UART_CTL_CONNECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_UART_CTL_CONNECTION_NONE 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_UART_CTL_CONNECTION_DDC0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CONNECTION_DDC1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CONNECTION_DDC2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CONNECTION_I2C 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CONNECTION_DDC4 0x00000004 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CONNECTION_DDC5 0x00000005 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CONNECTION_DDC6 0x00000006 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CONNECTION_DDC7 0x00000007 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CONNECTION_DDC8 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CONNECTION_DDC9 0x00000009 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CLIENT 4:4 /* RWIVF */
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#define NV_PPWR_PMU_UART_CTL_CLIENT_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_UART_CTL_CLIENT_PMU_UCODE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CLIENT_FALCON_ICD 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CLKDIV 20:8 /* RWIUF */
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#define NV_PPWR_PMU_UART_CTL_CLKDIV_HZ_115200 0x00000010 /* RWI-V */
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#define NV_PPWR_PMU_UART_CTL_CLKDIV_HZ_57600 0x00000021 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CLKDIV_HZ_38400 0x00000032 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CLKDIV_HZ_19200 0x00000065 /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CLKDIV_HZ_9600 0x000000cb /* RW--V */
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#define NV_PPWR_PMU_UART_CTL_CLKSRC 24:24 /* RWIVF */
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#define NV_PPWR_PMU_UART_CTL_CLKSRC_PTIMER 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_UART_CTL_CLKSRC_PWRCLK 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_UART_THRESHOLD 0x0010a66c /* RW-4R */
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#define NV_PPWR_PMU_UART_THRESHOLD_VALUE 23:0 /* RWIVF */
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#define NV_PPWR_PMU_UART_THRESHOLD_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_UART_INTR 0x0010a670 /* RW-4R */
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#define NV_PPWR_PMU_UART_INTR_RX_READY 0:0 /* RWIVF */
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#define NV_PPWR_PMU_UART_INTR_RX_READY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_UART_INTR_RX_READY_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_UART_INTR_RX_READY_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_UART_INTR_TX_READY 4:4 /* RWIVF */
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#define NV_PPWR_PMU_UART_INTR_TX_READY_NOT_PENDING 0x00000000 /* R---V */
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#define NV_PPWR_PMU_UART_INTR_TX_READY_PENDING 0x00000001 /* R-I-V */
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#define NV_PPWR_PMU_UART_INTR_TX_READY_CLEAR 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_UART_INTR_RX_OVERRUN 8:8 /* RWIVF */
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#define NV_PPWR_PMU_UART_INTR_RX_OVERRUN_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_UART_INTR_RX_OVERRUN_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_UART_INTR_RX_OVERRUN_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_UART_INTR_RX_BAD_START_BIT 16:16 /* RWIVF */
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#define NV_PPWR_PMU_UART_INTR_RX_BAD_START_BIT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_UART_INTR_RX_BAD_START_BIT_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_UART_INTR_RX_BAD_START_BIT_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_UART_INTR_RX_BAD_STOP_BIT 20:20 /* RWIVF */
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#define NV_PPWR_PMU_UART_INTR_RX_BAD_STOP_BIT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_UART_INTR_RX_BAD_STOP_BIT_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_UART_INTR_RX_BAD_STOP_BIT_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_UART_INTR_EN 0x0010a674 /* RW-4R */
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#define NV_PPWR_PMU_UART_INTR_EN_RX_READY 0:0 /* RWIVF */
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#define NV_PPWR_PMU_UART_INTR_EN_RX_READY_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_UART_INTR_EN_RX_READY_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_UART_INTR_EN_TX_READY 4:4 /* RWIVF */
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#define NV_PPWR_PMU_UART_INTR_EN_TX_READY_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_UART_INTR_EN_TX_READY_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_UART_INTR_EN_RX_OVERRUN 8:8 /* RWIVF */
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#define NV_PPWR_PMU_UART_INTR_EN_RX_OVERRUN_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_UART_INTR_EN_RX_OVERRUN_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_UART_INTR_EN_RX_BAD_START_BIT 16:16 /* RWIVF */
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#define NV_PPWR_PMU_UART_INTR_EN_RX_BAD_START_BIT_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_UART_INTR_EN_RX_BAD_START_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_UART_INTR_EN_RX_BAD_STOP_BIT 20:20 /* RWIVF */
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#define NV_PPWR_PMU_UART_INTR_EN_RX_BAD_STOP_BIT_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_UART_INTR_EN_RX_BAD_STOP_BIT_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_UART_DEBUG 0x0010a678 /* R--4R */
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#define NV_PPWR_PMU_UART_DEBUG_VALUE 31:0 /* R--VF */
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#define NV_PPWR_PMU_UART_DEBUG_CTL 0x0010a67c /* RW-4R */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL 3:0 /* RWIVF */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL_RX_BUF_31_0 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL_RX_BUF_63_32 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL_RX_BUF_79_64 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL_TX_BUF_31_0 0x00000004 /* RW--V */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL_TX_BUF_63_32 0x00000005 /* RW--V */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL_TX_BUF_79_64 0x00000006 /* RW--V */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL_RX_BUF_ERR 0x00000007 /* RW--V */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL_UART_CTRL 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL_TX_DAT 0x00000009 /* RW--V */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL_FSM 0x0000000a /* RW--V */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL_ICDC_STAT_CRTL 0x0000000b /* RW--V */
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#define NV_PPWR_PMU_UART_DEBUG_CTL_SEL_ICDC_TIMER 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_BAR0_ADDR 0x0010a7a0 /* RW-4R */
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#define NV_PPWR_PMU_BAR0_ADDR_VALUE 25:0 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_ADDR_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_ADDR_BLOCKING 26:26 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_ADDR_BLOCKING_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_ADDR_BLOCKING_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_BAR0_ADDR_TARGET 27:27 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_ADDR_TARGET_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_ADDR_TARGET_HOST 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_BAR0_ADDR_TARGET_FECS 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_BAR0_DATA 0x0010a7a4 /* RW-4R */
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#define NV_PPWR_PMU_BAR0_DATA_VALUE 31:0 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_DATA_VALUE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_CTL 0x0010a7ac /* RW-4R */
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#define NV_PPWR_PMU_BAR0_CTL_CMD 1:0 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_CTL_CMD_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_CTL_CMD_READ 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_BAR0_CTL_CMD_WRITE 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_BAR0_CTL_CMD_RSVD 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_BAR0_CTL_WRBE 7:4 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_CTL_WRBE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_CTL_INCR_ADDR 8:8 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_CTL_INCR_ADDR_NO 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_CTL_INCR_ADDR_YES 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_BAR0_CTL_STATUS 14:12 /* R-IUF */
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#define NV_PPWR_PMU_BAR0_CTL_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_CTL_STATUS_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_BAR0_CTL_STATUS_TOUT 0x00000002 /* R---V */
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#define NV_PPWR_PMU_BAR0_CTL_STATUS_DIS 0x00000003 /* R---V */
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#define NV_PPWR_PMU_BAR0_CTL_STATUS_ERROR 0x00000004 /* R---V */
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#define NV_PPWR_PMU_BAR0_CTL_TRIG 16:16 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_CTL_TRIG_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_CTL_TRIG_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_BAR0_CTL_TRIG_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_BAR0_CTL_BAR0_PRIV_LEVEL 21:20 /* R-IUF */
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#define NV_PPWR_PMU_BAR0_CTL_BAR0_PRIV_LEVEL_0 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_CTL_BAR0_PRIV_LEVEL_1 0x00000001 /* R---V */
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#define NV_PPWR_PMU_BAR0_CTL_BAR0_PRIV_LEVEL_2 0x00000002 /* R---V */
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#define NV_PPWR_PMU_BAR0_TIMEOUT 0x0010a7a8 /* RW-4R */
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#define NV_PPWR_PMU_BAR0_TIMEOUT_VALUE 30:0 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_TIMEOUT_VALUE_INIT 0x10000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_TIMEOUT_EN 31:31 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_TIMEOUT_EN_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS 0x0010a7b0 /* RW-4R */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_HOST 0:0 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_HOST_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_HOST_DETECTED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_HOST_CLEAR 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_FECS 1:1 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_FECS_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_FECS_DETECTED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_TIMEOUT_FECS_CLEAR 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_CMD_HWERR 2:2 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_CMD_HWERR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_CMD_HWERR_DETECTED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_CMD_HWERR_CLEAR 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_ERROR_CMD 3:3 /* R-IUF */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_ERROR_CMD_READ 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_ERROR_CMD_WRITE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_ERROR_ADDR 29:4 /* R-IUF */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_ERROR_ADDR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_HOSTERR 30:30 /* RWIVF */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_HOSTERR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_HOSTERR_DETECTED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_HOSTERR_CLEAR 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_FECSERR 31:31 /* RWIVF */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_FECSERR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_FECSERR_DETECTED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_BAR0_ERROR_STATUS_FECSERR_CLEAR 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR 0x0010a988 /* RW-4R */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_EXTRA 7:0 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_EXTRA_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_EXTRA_CLEAR 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_EXTRA_ASYNC_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_EXTRA_ASYNC_REQ 0x00000000 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_EXTRA_ASYNC_RDAT_WAIT 0x00000000 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_EXTRA_ASYNC_HOLD 0x00000000 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_EXTRA_ASYNC_WAIT_ACK 0x00000000 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_EXTRA_SYNC_REQ 0x00000000 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_EXTRA_SYNC_RDAT_WAIT 0x00000000 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE 31:8 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_CLEAR 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_TIMEOUT 0x00badf10 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_DECODE 0x00badf11 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_RESET 0x00badf12 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_FLOORSWEEP 0x00badf13 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_STUCK_ACK 0x00badf14 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_0_EXPECTED_ACK 0x00badf15 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_FENCE_ERROR 0x00badf16 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_ORPHAN 0x00badf20 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_DEAD_RING 0x00badf30 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_TRAP 0x00badf40 /* R---V */
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#define NV_PPWR_PMU_BAR0_FECS_ERROR_CODE_PRI_CLIENT_ERR 0x00badf50 /* R---V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR 0x0010a990 /* RW-4R */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_EXTRA 7:0 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_EXTRA_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_EXTRA_CLEAR 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE 31:8 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE_CLEAR 0x00000001 /* -W--V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_TIMEOUT 0x00badf10 /* R---V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_DECODE 0x00badf11 /* R---V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_RESET 0x00badf12 /* R---V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_FLOORSWEEP 0x00badf13 /* R---V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_STUCK_ACK 0x00badf14 /* R---V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_0_EXPECTED_ACK 0x00badf15 /* R---V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_FENCE_ERROR 0x00badf16 /* R---V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_ORPHAN 0x00badf20 /* R---V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE_DEAD_RING 0x00badf30 /* R---V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE_TRAP 0x00badf40 /* R---V */
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#define NV_PPWR_PMU_BAR0_HOST_ERROR_CODE_PRI_CLIENT_ERR 0x00badf50 /* R---V */
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#define NV_PPWR_PMU_BAR0_EXT 0x0010a98c /* R--4R */
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#define NV_PPWR_PMU_BAR0_EXT_STATUS 1:0 /* R-IUF */
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#define NV_PPWR_PMU_BAR0_EXT_STATUS_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_EXT_STATUS_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_BAR0_EXT_STATUS_DIS 0x00000002 /* R---V */
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#define NV_PPWR_PMU_BAR0_INTR 0x0010a7b4 /* RW-4R */
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#define NV_PPWR_PMU_BAR0_INTR_HW_ERR 0:0 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_INTR_HW_ERR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_INTR_HW_ERR_DETECTED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_BAR0_INTR_HW_ERR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_BAR0_INTEN 0x0010a7b8 /* RW-4R */
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#define NV_PPWR_PMU_BAR0_INTEN_HW_ERR 0:0 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_INTEN_HW_ERR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_INTEN_HW_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_BAR0_INTEN_HW_ERR_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_BAR0_EN 0x0010a7bc /* RW-4R */
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#define NV_PPWR_PMU_BAR0_EN_CTL 0:0 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_EN_CTL_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_EN_CTL_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_BAR0_EN_CTL_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_BAR0_EN_AUTO_TRIGGER 1:1 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_EN_AUTO_TRIGGER_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_EN_AUTO_TRIGGER_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_BAR0_CYA 0x0010a980 /* RW-4R */
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#define NV_PPWR_PMU_BAR0_CYA_BLOCKING_OVERRIDE 1:0 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_CYA_BLOCKING_OVERRIDE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_CYA_BLOCKING_OVERRIDE_BLOCK 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_BAR0_CYA_BLOCKING_OVERRIDE_NONBLOCK 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_BAR0_CYA_TARGET_OVERRIDE 3:2 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_CYA_TARGET_OVERRIDE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_CYA_TARGET_OVERRIDE_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_BAR0_CYA_TARGET_OVERRIDE_FECS 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_BAR0_CYA_LOCAL_ORDERING 4:4 /* RWIUF */
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#define NV_PPWR_PMU_BAR0_CYA_LOCAL_ORDERING_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_BAR0_CYA_LOCAL_ORDERING_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_BAR0_DBG 0x0010a984 /* R--4R */
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#define NV_PPWR_PMU_BAR0_DBG_FSM_STATE 3:0 /* R-IUF */
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#define NV_PPWR_PMU_BAR0_DBG_FSM_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_DBG_FSM_STATE_NO_TRANSACTION 0x00000000 /* R---V */
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#define NV_PPWR_PMU_BAR0_DBG_FSM_STATE_CSB2FECS 0x00000001 /* R---V */
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#define NV_PPWR_PMU_BAR0_DBG_FSM_STATE_EXT2FECS 0x00000002 /* R---V */
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#define NV_PPWR_PMU_BAR0_DBG_FSM_STATE_CSB2HOST 0x00000003 /* R---V */
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#define NV_PPWR_PMU_BAR0_DBG_FSM_STATE_EXT2HOST 0x00000004 /* R---V */
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#define NV_PPWR_PMU_BAR0_DBG_FSM_STATE_FECS_BUSY 0x00000005 /* R---V */
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#define NV_PPWR_PMU_BAR0_DBG_FSM_STATE_HOST_BUSY 0x00000006 /* R---V */
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#define NV_PPWR_PMU_BAR0_DBG_FSM_STATE_TIMEOUT 0x00000007 /* R---V */
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#define NV_PPWR_PMU_BAR0_DBG_FSM_STATE_ERROR 0x00000008 /* R---V */
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#define NV_PPWR_PMU_BAR0_DBG_BAR0_DISABLED 4:4 /* R-IUF */
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#define NV_PPWR_PMU_BAR0_DBG_BAR0_DISABLED_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_BAR0_DBG_BAR0_DISABLED_NO 0x00000000 /* R---V */
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#define NV_PPWR_PMU_BAR0_DBG_BAR0_DISABLED_YES 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_CTRL(i) (0x0010aad0+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_PG_CTRL__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_CTRL__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_PG_CTRL_ENG 0:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_CTRL_ENG_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_CTRL_ENG_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_CTRL_ENG_TYPE 1:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_CTRL_ENG_TYPE_PG 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_CTRL_ENG_TYPE_LPWR 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_CTRL_CFG_RDY 4:4 /* RWEVF */
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#define NV_PPWR_PMU_PG_CTRL_CFG_RDY_FALSE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_CTRL_CFG_RDY_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_CTRL_SOFT_RST 5:5 /* RWEVF */
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#define NV_PPWR_PMU_PG_CTRL_SOFT_RST_FALSE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_CTRL_SOFT_RST_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_CTRL_PGOFF_ENG 6:6 /* RWEVF */
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#define NV_PPWR_PMU_PG_CTRL_PGOFF_ENG_DONE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_CTRL_PGOFF_ENG_START 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_CTRL_PGOFF_REQSRC 7:7 /* RWEVF */
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#define NV_PPWR_PMU_PG_CTRL_PGOFF_REQSRC_RM 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_CTRL_PGOFF_REQSRC_HOST 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_CTRL_IDLE_MASK_VALUE 9:8 /* RWEVF */
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#define NV_PPWR_PMU_PG_CTRL_IDLE_MASK_VALUE_NEVER 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_CTRL_IDLE_MASK_VALUE_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_CTRL_IDLE_MASK_VALUE_BUSY 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_CTRL_IDLE_MASK_VALUE_ALWAYS 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_CTRL_AUTO_WAKEUP 12:12 /* RWEVF */
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#define NV_PPWR_PMU_PG_CTRL_AUTO_WAKEUP_DIS 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_CTRL_AUTO_WAKEUP_EN 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_CTRL_PGOFF_DONE 16:16 /* RWEVF */
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#define NV_PPWR_PMU_PG_CTRL_PGOFF_DONE_INVALID 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_CTRL_PGOFF_DONE_VALID 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_WAKEUP_INTERVAL(i) (0x0010a9c8+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_PG_WAKEUP_INTERVAL__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_WAKEUP_INTERVAL__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_PG_WAKEUP_INTERVAL_VAL 23:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_WAKEUP_INTERVAL_VAL_INIT 0x004c4b40 /* RWE-V */
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#define NV_PPWR_PMU_PWRCLK_FREQ 0x0010ab5c /* RW-4R */
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#define NV_PPWR_PMU_PWRCLK_FREQ__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_PWRCLK_FREQ_VAL 31:0 /* RWEVF */
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#define NV_PPWR_PMU_PWRCLK_FREQ_VAL_INIT 0x0000021c /* RWE-V */
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#define NV_PPWR_PMU_PG_CLAMP_DELAY(i) (0x0010aaf8+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_PG_CLAMP_DELAY__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_CLAMP_DELAY_PWRDOWN_VAL 15:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_CLAMP_DELAY_PWRDOWN_VAL_INIT 0x000000ff /* RWE-V */
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#define NV_PPWR_PMU_PG_CLAMP_DELAY_PWRUP_VAL 31:16 /* RWEVF */
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#define NV_PPWR_PMU_PG_CLAMP_DELAY_PWRUP_VAL_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_MISC 0x0010a4f8 /* RW-4R */
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#define NV_PPWR_PMU_PG_MISC__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_PG_MISC_IDLE_SNAP_READ 0:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_MISC_IDLE_SNAP_READ_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_MISC_IDLE_SNAP_READ_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_MISC_IDLE_SNAP_IDX 3:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_MISC_IDLE_SNAP_IDX_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_MISC_IDLE_FLIP_STATUS_IDX 6:4 /* RWEVF */
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#define NV_PPWR_PMU_PG_MISC_IDLE_FLIP_STATUS_IDX_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_MISC_SOFT_RST_DBGEN 28:28 /* RWEVF */
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#define NV_PPWR_PMU_PG_MISC_SOFT_RST_DBGEN_FALSE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_MISC_SOFT_RST_DBGEN_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_MISC_SOFT_RST_DBG 31:31 /* RWEVF */
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#define NV_PPWR_PMU_PG_MISC_SOFT_RST_DBG_FALSE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_MISC_SOFT_RST_DBG_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS 0x0010a78c /* RW-4R */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_VALUE 31:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_VALUE_INIT 0xffffffff /* RWE-V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_GR_FE 0:0 /* RWXVF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_GR_FE_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_GR_FE_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE_SYS 1:1 /* RWXVF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE_SYS_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE_SYS_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE_GPC 2:2 /* RWXVF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE_GPC_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE_GPC_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_GR_PRIV_IDLE 2:1 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_SEC 4:4 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_SEC_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_SEC_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_VD_NVDEC 5:5 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_VD_NVDEC_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_VD_NVDEC_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_NOT_USED_6 6:6 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_NOT_USED_6_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_FB_NOREQ 7:7 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_FB_NOREQ_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_FB_NOREQ_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_FB_PA 8:8 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_FB_PA_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_FB_PA_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_ALL 9:9 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_ALL_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_ALL_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_NISO 10:10 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_NISO_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_NISO_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_FB_ASR 11:11 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_FB_ASR_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_FB_ASR_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_LTC_IDLE 12:12 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_LTC_IDLE_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_LTC_IDLE_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_AZA_IDLE 13:13 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_AZA_IDLE_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_AZA_IDLE_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED0 14:14 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED0_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED0_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_NOT_USED_15 15:15 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_NOT_USED_15_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_NISO_EX_ISO 16:16 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_NISO_EX_ISO_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HSHUB_NISO_EX_ISO_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_VD_NVENC0 17:17 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_VD_NVENC0_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_VD_NVENC0_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XBAR_IDLE 18:18 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XBAR_IDLE_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XBAR_IDLE_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_CE_0 19:19 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_CE_0_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_CE_0_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_CE_1 20:20 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_CE_1_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_CE_1_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_CE_2 21:21 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_CE_2_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_CE_2_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_NOT_USED_22 22:22 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_NOT_USED_22_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XP_L0S 23:23 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XP_L0S_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XP_L0S_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XP_L1 24:24 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XP_L1_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XP_L1_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVE_XCLK 25:25 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVE_XCLK_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVE_XCLK_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_COMMON 26:26 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_COMMON_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_COMMON_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_DEEP 27:27 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_DEEP_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_DEEP_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_XP 28:28 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_XP_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_XP_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_XVE 29:29 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_XVE_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP_XVE_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_XVXP 29:26 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED1 30:30 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED1_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED1_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED2 31:31 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED2_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_HOST_ESCHED2_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1 0x0010a790 /* RW-4R */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_VALUE 31:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_VALUE_INIT 0xffffffff /* RWE-V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HSHUB_MMU 0:0 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HSHUB_MMU_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HSHUB_MMU_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_GSP 1:1 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_GSP_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_GSP_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_FBHUB_ALL 2:2 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_FBHUB_ALL_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_FBHUB_ALL_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_FBHUB_NONPMU_INTERFACE 3:3 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_FBHUB_NONPMU_INTERFACE_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_FBHUB_NONPMU_INTERFACE_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_MS_MMU 4:4 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_MS_MMU_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_MS_MMU_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED3 5:5 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED3_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED3_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED4 6:6 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED4_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED4_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED5 7:7 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED5_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED5_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED6 8:8 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED6_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED6_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED7 9:9 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED7_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED7_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED8 10:10 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED8_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_HOST_ESCHED8_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_11 11:11 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_11_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_12 12:12 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_12_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_13 13:13 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_13_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_14 14:14 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_14_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_15 15:15 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_15_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_16 16:16 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_16_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_17 17:17 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_17_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_18 18:18 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_18_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_PMU2FB_TRAFFIC 19:19 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_PMU2FB_TRAFFIC_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_PMU2FB_TRAFFIC_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_CE_3 20:20 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_CE_3_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_CE_3_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_CE_4 21:21 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_CE_4_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_CE_4_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_22 22:22 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_22_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_23 23:23 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_23_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_24 24:24 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_24_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_25 25:25 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_25_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_26 26:26 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_26_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_SEC_FBIF 27:27 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_SEC_FBIF_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_SEC_FBIF_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_28 28:28 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_28_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_29 29:29 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_NOT_USED_29_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_SW0 30:30 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_SW0_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_SW0_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_SW1 31:31 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_SW1_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_1_SW1_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2 0x0010a794 /* RW-4R */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_VALUE 31:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_VALUE_INIT 0xffffffff /* RWE-V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_0 0:0 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_0_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_1 1:1 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_1_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_2 2:2 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_2_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_3 3:3 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_3_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_4 4:4 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_4_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_5 5:5 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_5_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_FB 6:6 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_FB_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_FB_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_7 7:7 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_7_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_VD_NVDEC1 8:8 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_VD_NVDEC1_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_VD_NVDEC1_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_9 9:9 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_9_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_10 10:10 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_10_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_11 11:11 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_11_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_12 12:12 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_12_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_13 13:13 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_13_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_PRIV_BLOCKER_GR 14:14 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_PRIV_BLOCKER_GR_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_PRIV_BLOCKER_GR_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_PRIV_BLOCKER_MS 15:15 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_PRIV_BLOCKER_MS_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_GSP_PRIV_BLOCKER_MS_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_SEC_PRIV_BLOCKER_GR 16:16 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_SEC_PRIV_BLOCKER_GR_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_SEC_PRIV_BLOCKER_GR_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_SEC_PRIV_BLOCKER_MS 17:17 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_SEC_PRIV_BLOCKER_MS_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_SEC_PRIV_BLOCKER_MS_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_18 18:18 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_18_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_19 19:19 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_19_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_20 20:20 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_20_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_21 21:21 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_21_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_22 22:22 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_22_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_23 23:23 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_23_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_24 24:24 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_24_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_25 25:25 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_25_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_26 26:26 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_26_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_27 27:27 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_NOT_USED_27_TIEHIGH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_VD_OFA 28:28 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_VD_OFA_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_VD_OFA_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_XVE_BAR_BLK_MS 29:29 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_XVE_BAR_BLK_MS_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_XVE_BAR_BLK_MS_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_XVE_BAR_BLK_GR 30:30 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_XVE_BAR_BLK_GR_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_XVE_BAR_BLK_GR_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_SW2 31:31 /* RW-VF */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_SW2_BUSY 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLE_FLIP_STATUS_2_SW2_IDLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_IDLEFILTH(i) (0x0010a6c0+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_PG_IDLEFILTH__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_IDLEFILTH__PRIV_LEVEL_MASK 0x0010a7dc /* */
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#define NV_PPWR_PMU_PG_IDLEFILTH_VALUE 31:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_IDLEFILTH_VALUE_INIT 0x00001000 /* RWE-V */
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#define NV_PPWR_PMU_PG_PPUIDLEFILTH(i) (0x0010a6e8+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_PG_PPUIDLEFILTH__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_PPUIDLEFILTH__PRIV_LEVEL_MASK 0x0010a7dc /* */
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#define NV_PPWR_PMU_PG_PPUIDLEFILTH_VALUE 31:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_PPUIDLEFILTH_VALUE_INIT 0x01000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_IDLE_CNT(i) (0x0010a710+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_PG_IDLE_CNT__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_IDLE_CNT_VALUE 31:0 /* R-EVF */
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#define NV_PPWR_PMU_PG_IDLE_CNT_VALUE_INIT 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_SWCTRL(i) (0x0010a738+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_PG_SWCTRL__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_SWCTRL__PRIV_LEVEL_MASK 0x0010aa78 /* */
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#define NV_PPWR_PMU_PG_SWCTRL_PWR 0:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_SWCTRL_PWR_OFF 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_SWCTRL_PWR_ON 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_SWCTRL_OVERWR 3:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_SWCTRL_OVERWR_POWERON_ENGIDLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_SWCTRL_OVERWR_POWERINGDOWN 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_SWCTRL_OVERWR_ACTIVE 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_SWCTRL_OVERWR_POWERON_ENGBUSY 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_SWCTRL_OVERWR_POWERINGUP 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_SWCTRL_OVERWR_PWROFF 0x00000004 /* RW--V */
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#define NV_PPWR_PMU_PG_SWCTRL_OVERWR_PWROFF_ACTIVE 0x00000006 /* RW--V */
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#define NV_PPWR_PMU_PG_SWCTRL_CLAMPSWITCH 4:4 /* RWEVF */
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#define NV_PPWR_PMU_PG_SWCTRL_CLAMPSWITCH_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_SWCTRL_CLAMPSWITCH_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_SWCTRL_CLAMPSWITCH_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_SWCTRL_CLAMP 5:5 /* RWEVF */
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#define NV_PPWR_PMU_PG_SWCTRL_CLAMP_OFF 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_SWCTRL_CLAMP_ON 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_SWCTRL_ENABLE 31:31 /* RWEVF */
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#define NV_PPWR_PMU_PG_SWCTRL_ENABLE_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_SWCTRL_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_SWCTRL_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN(i) (0x0010a760+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_PG_INTREN__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_INTREN__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_PG_INTREN_PG_ON 0:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTREN_PG_ON_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTREN_PG_ON_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN_PG_ON_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN_PG_ON_DONE 4:4 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTREN_PG_ON_DONE_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTREN_PG_ON_DONE_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN_PG_ON_DONE_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN_CTX_RESTORE 8:8 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTREN_CTX_RESTORE_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTREN_CTX_RESTORE_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN_CTX_RESTORE_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN_CFG_ERR 12:12 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTREN_CFG_ERR_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTREN_CFG_ERR_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN_CFG_ERR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN_ENG_RST 16:16 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTREN_ENG_RST_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTREN_ENG_RST_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN_ENG_RST_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN_IDLE_SNAP 20:20 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTREN_IDLE_SNAP_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTREN_IDLE_SNAP_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN_IDLE_SNAP_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN_WAKEUP 20:20 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTREN_WAKEUP_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTREN_WAKEUP_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_INTREN_WAKEUP_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_INTRSTAT(i) (0x0010aa80+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_PG_INTRSTAT__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_INTRSTAT__PRIV_LEVEL_MASK 0x0010a7fc /* */
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#define NV_PPWR_PMU_PG_INTRSTAT_INTR 0:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTRSTAT_INTR_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTRSTAT_INTR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_PG_INTRSTAT_INTR_SET 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_INTR_RESET 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_PG_ON 4:4 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTRSTAT_PG_ON_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTRSTAT_PG_ON_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_PG_INTRSTAT_PG_ON_SET 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_PG_ON_RESET 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_PG_ON_DONE 8:8 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTRSTAT_PG_ON_DONE_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTRSTAT_PG_ON_DONE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_PG_INTRSTAT_PG_ON_DONE_SET 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_PG_ON_DONE_RESET 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_CTX_RESTORE 12:12 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTRSTAT_CTX_RESTORE_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTRSTAT_CTX_RESTORE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_PG_INTRSTAT_CTX_RESTORE_SET 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_CTX_RESTORE_RESET 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_CFG_ERR 16:16 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTRSTAT_CFG_ERR_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTRSTAT_CFG_ERR_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_PG_INTRSTAT_CFG_ERR_SET 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_CFG_ERR_RESET 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_ENG_RST 20:20 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTRSTAT_ENG_RST_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTRSTAT_ENG_RST_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_PG_INTRSTAT_ENG_RST_SET 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_ENG_RST_RESET 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_IDLE_SNAP 24:24 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTRSTAT_IDLE_SNAP_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTRSTAT_IDLE_SNAP_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_PG_INTRSTAT_IDLE_SNAP_SET 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_IDLE_SNAP_RESET 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_WAKEUP 24:24 /* RWEVF */
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#define NV_PPWR_PMU_PG_INTRSTAT_WAKEUP_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_INTRSTAT_WAKEUP_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_PG_INTRSTAT_WAKEUP_SET 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_INTRSTAT_WAKEUP_RESET 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_STAT(i) (0x0010aaa8+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_PG_STAT__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_STAT_EST 2:0 /* R-EVF */
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#define NV_PPWR_PMU_PG_STAT_EST_IDLE 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_STAT_EST_POWERON_ENGIDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_EST_POWERINGDOWN 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_EST_ACTIVE 0x00000002 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_EST_POWERON_ENGBUSY 0x00000002 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_EST_POWERINGUP 0x00000003 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_EST_PWROFF 0x00000004 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_EST_PWROFF_ACTIVE 0x00000006 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_PGST 6:3 /* R-EVF */
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#define NV_PPWR_PMU_PG_STAT_PGST_IDLE 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_STAT_PGST_PG_ON 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_PGST_CLAMP_ON 0x00000002 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_PGST_CLAMP_ON_DELAY 0x00000003 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_PGST_PWROFF_SEQ 0x00000004 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_PGST_PG_ON_DONE 0x00000005 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_PGST_PWRON_SEQ 0x00000006 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_PGST_ENG_RST 0x00000007 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_PGST_CLAMP_OFF 0x00000008 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_PGST_CLAMP_OFF_DELAY 0x00000009 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_PGST_DAT_RESTORE 0x0000000a /* R---V */
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#define NV_PPWR_PMU_PG_STAT_PGST_PG_OFF 0x0000000b /* R---V */
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#define NV_PPWR_PMU_PG_STAT_AUTO_WAKEUP 8:8 /* R-EVF */
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#define NV_PPWR_PMU_PG_STAT_AUTO_WAKEUP_DEASSERTED 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_STAT_AUTO_WAKEUP_ASSERTED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_SW_CLIENT 9:9 /* R-EVF */
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#define NV_PPWR_PMU_PG_STAT_SW_CLIENT_DEASSERTED 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_STAT_SW_CLIENT_ASSERTED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_IDLE_FLIPPED_PWR_OFF 10:10 /* R-EVF */
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#define NV_PPWR_PMU_PG_STAT_IDLE_FLIPPED_PWR_OFF_DEASSERTED 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_STAT_IDLE_FLIPPED_PWR_OFF_ASSERTED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_THRESHOLD_ERR 15:15 /* R-EVF */
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#define NV_PPWR_PMU_PG_STAT_THRESHOLD_ERR_CLEAR 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_STAT_THRESHOLD_ERR_SET 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_RUNTIME_CFG_ERR 16:16 /* R-EVF */
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#define NV_PPWR_PMU_PG_STAT_RUNTIME_CFG_ERR_CLEAR 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_STAT_RUNTIME_CFG_ERR_SET 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_PPU_IDLE_PERIOD 19:19 /* R-EVF */
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#define NV_PPWR_PMU_PG_STAT_PPU_IDLE_PERIOD_FALSE 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_STAT_PPU_IDLE_PERIOD_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_IDLE_FLIPPED 20:20 /* R-EVF */
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#define NV_PPWR_PMU_PG_STAT_IDLE_FLIPPED_DEASSERTED 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_STAT_IDLE_FLIPPED_ASSERTED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_STAT_IDLE_FLIPPED_NON_PMU 21:21 /* R-EVF */
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#define NV_PPWR_PMU_PG_STAT_IDLE_FLIPPED_NON_PMU_DEASSERTED 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_STAT_IDLE_FLIPPED_NON_PMU_ASSERTED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_DBG(i) (0x0010a860+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_PG_DBG__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_DBG_VALUE 31:0 /* R--VF */
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#define NV_PPWR_PMU_PG_DBG_IDX(i) (0x0010ab64+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_PG_DBG_IDX__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_DBG_IDX_PT 7:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_DBG_IDX_PT_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_DBG_IDX_PT_IDLE_CNT 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_DBG_IDX_PT_CYAEN_BYPASS_CLAMP 0x00000010 /* RW--V */
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#define NV_PPWR_PMU_PG_DBG_IDX_PT_STATUS 0x00000020 /* RW--V */
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#define NV_PPWR_PMU_PG_DBG_IDX_PT_CFGERR 0x00000030 /* RW--V */
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#define NV_PPWR_PMU_PG_DBG_IDX_PT_PT_DBG_RESET 0x000000ff /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT(i) (0x0010abac+(i)*4) /* R--4A */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG0_OFF 0:0 /* R-EVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG0_OFF_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG0_OFF_FALSE 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG1_OFF 1:1 /* R-EVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG1_OFF_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG1_OFF_FALSE 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG2_OFF 2:2 /* R-EVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG2_OFF_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG2_OFF_FALSE 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG3_OFF 3:3 /* R-EVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG3_OFF_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG3_OFF_FALSE 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG4_OFF 4:4 /* R-EVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG4_OFF_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_ENG4_OFF_FALSE 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_DEEPL1_ENGAGED 5:5 /* R-EVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_DEEPL1_ENGAGED_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_DEEPL1_ENGAGED_FALSE 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_L1_1_ENGAGED 6:6 /* R-EVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_L1_1_ENGAGED_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_L1_1_ENGAGED_FALSE 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_L1_2_ENGAGED 7:7 /* R-EVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_L1_2_ENGAGED_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_L1_2_ENGAGED_FALSE 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_MSPG_OK 8:8 /* R-EVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_MSPG_OK_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_MSPG_OK_FALSE 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_TS_PD_READY 10:10 /* R-EVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_TS_PD_READY_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_STAT_TS_PD_READY_FALSE 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK(i) (0x0010abc0+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK__PRIV_LEVEL_MASK 0x0010a7dc /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_AND 0:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_AND_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_AND_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_OR 1:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_OR_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_OR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_GROUP 4:2 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_GROUP_NONE 0x00000004 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_GROUP_0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_GROUP_1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_GROUP_2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG0_OFF_GROUP_3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_AND 8:8 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_AND_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_AND_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_OR 9:9 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_OR_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_OR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_GROUP 12:10 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_GROUP_NONE 0x00000004 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_GROUP_0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_GROUP_1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_GROUP_2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG1_OFF_GROUP_3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_AND 16:16 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_AND_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_AND_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_OR 17:17 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_OR_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_OR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_GROUP 20:18 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_GROUP_NONE 0x00000004 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_GROUP_0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_GROUP_1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_GROUP_2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG2_OFF_GROUP_3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_AND 24:24 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_AND_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_AND_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_OR 25:25 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_OR_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_OR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_GROUP 28:26 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_GROUP_NONE 0x00000004 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_GROUP_0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_GROUP_1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_GROUP_2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG3_OFF_GROUP_3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_AND(i) (8*(i)):(8*(i)) /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_AND__SIZE_1 4 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_OR(i) (1+8*(i)):(1+8*(i)) /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_OR__SIZE_1 4 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_AND_DISABLE 0 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_AND_ENABLE 1 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_OR_DISABLE 0 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_OR_ENABLE 1 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_GROUP(i) (4+8*(i)):(2+8*(i)) /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_GROUP__SIZE_1 4 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_GROUP_0 0 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_GROUP_1 1 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_GROUP_2 2 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_ENG_OFF_GROUP_3 3 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1(i) (0x0010abd4+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1__PRIV_LEVEL_MASK 0x0010a7dc /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_AND 0:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_AND_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_AND_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_OR 1:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_OR_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_OR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_GROUP 4:2 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_GROUP_INIT 0x00000004 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_GROUP_0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_GROUP_1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_GROUP_2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG4_OFF_GROUP_3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_AND 8:8 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_AND_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_AND_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_OR 9:9 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_OR_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_OR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_GROUP 12:10 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_GROUP_INIT 0x00000004 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_GROUP_0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_GROUP_1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_GROUP_2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_DEEP_L1_GROUP_3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_AND 16:16 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_AND_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_AND_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_OR 17:17 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_OR_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_OR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_GROUP 20:18 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_GROUP_INIT 0x00000004 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_GROUP_0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_GROUP_1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_GROUP_2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_1_GROUP_3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_AND 24:24 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_AND_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_AND_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_OR 25:25 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_OR_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_OR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_GROUP 28:26 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_GROUP_INIT 0x00000004 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_GROUP_0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_GROUP_1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_GROUP_2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_PEX_L1_2_GROUP_3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_AND 0:0 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_OR 1:1 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_AND_DISABLE 0 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_AND_ENABLE 1 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_OR_DISABLE 0 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_OR_ENABLE 1 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_GROUP 4:2 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_GROUP_0 0 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_GROUP_1 1 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_GROUP_2 2 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_1_ENG_OFF_GROUP_3 3 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2(i) (0x0010abe8+(i)*4) /* RW-4A */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2__PRIV_LEVEL_MASK 0x0010a7dc /* */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_AND 0:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_AND_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_AND_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_OR 1:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_OR_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_OR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_GROUP 4:2 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_GROUP_INIT 0x00000004 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_GROUP_0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_GROUP_1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_GROUP_2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_MSPG_OK_GROUP_3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_AND 16:16 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_AND_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_AND_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_OR 17:17 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_OR_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_OR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_GROUP 20:18 /* RWEVF */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_GROUP_INIT 0x00000004 /* RWE-V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_GROUP_0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_GROUP_1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_GROUP_2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_ON_TRIGGER_MASK_2_TS_PD_READY_GROUP_3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0 0x0010a508 /* RW-4R */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0__PRIV_LEVEL_MASK 0x0010ab38 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG0_ST 0:0 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG0_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG0_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG0_BUSY_SET 1:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG0_BUSY_CLR 2:2 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG1_ST 4:4 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG1_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG1_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG1_BUSY_SET 5:5 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG1_BUSY_CLR 6:6 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG2_ST 8:8 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG2_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG2_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG2_BUSY_SET 9:9 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG2_BUSY_CLR 10:10 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG3_ST 12:12 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG3_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG3_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG3_BUSY_SET 13:13 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG3_BUSY_CLR 14:14 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG4_ST 16:16 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG4_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG4_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG4_BUSY_SET 17:17 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG4_BUSY_CLR 18:18 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_0_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1 0x0010a50c /* RW-4R */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1__PRIV_LEVEL_MASK 0x0010ab3c /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG0_ST 0:0 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG0_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG0_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG0_BUSY_SET 1:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG0_BUSY_CLR 2:2 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG1_ST 4:4 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG1_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG1_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG1_BUSY_SET 5:5 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG1_BUSY_CLR 6:6 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG2_ST 8:8 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG2_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG2_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG2_BUSY_SET 9:9 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG2_BUSY_CLR 10:10 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG3_ST 12:12 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG3_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG3_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG3_BUSY_SET 13:13 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG3_BUSY_CLR 14:14 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG4_ST 16:16 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG4_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG4_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG4_BUSY_SET 17:17 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG4_BUSY_CLR 18:18 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_1_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2 0x0010a510 /* RW-4R */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2__PRIV_LEVEL_MASK 0x0010ab40 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG0_ST 0:0 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG0_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG0_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG0_BUSY_SET 1:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG0_BUSY_CLR 2:2 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG1_ST 4:4 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG1_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG1_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG1_BUSY_SET 5:5 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG1_BUSY_CLR 6:6 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG2_ST 8:8 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG2_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG2_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG2_BUSY_SET 9:9 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG2_BUSY_CLR 10:10 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG3_ST 12:12 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG3_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG3_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG3_BUSY_SET 13:13 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG3_BUSY_CLR 14:14 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG4_ST 16:16 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG4_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG4_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG4_BUSY_SET 17:17 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG4_BUSY_CLR 18:18 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_2_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3 0x0010a514 /* RW-4R */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3__PRIV_LEVEL_MASK 0x0010ab44 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG0_ST 0:0 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG0_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG0_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG0_BUSY_SET 1:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG0_BUSY_CLR 2:2 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG1_ST 4:4 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG1_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG1_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG1_BUSY_SET 5:5 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG1_BUSY_CLR 6:6 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG2_ST 8:8 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG2_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG2_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG2_BUSY_SET 9:9 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG2_BUSY_CLR 10:10 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG3_ST 12:12 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG3_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG3_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG3_BUSY_SET 13:13 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG3_BUSY_CLR 14:14 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG4_ST 16:16 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG4_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG4_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG4_BUSY_SET 17:17 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG4_BUSY_CLR 18:18 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_3_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4 0x0010a518 /* RW-4R */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4__PRIV_LEVEL_MASK 0x0010ab48 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG0_ST 0:0 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG0_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG0_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG0_BUSY_SET 1:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG0_BUSY_CLR 2:2 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG1_ST 4:4 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG1_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG1_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG1_BUSY_SET 5:5 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG1_BUSY_CLR 6:6 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG2_ST 8:8 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG2_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG2_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG2_BUSY_SET 9:9 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG2_BUSY_CLR 10:10 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG3_ST 12:12 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG3_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG3_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG3_BUSY_SET 13:13 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG3_BUSY_CLR 14:14 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG4_ST 16:16 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG4_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG4_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG4_BUSY_SET 17:17 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG4_BUSY_CLR 18:18 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_4_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5 0x0010a51c /* RW-4R */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5__PRIV_LEVEL_MASK 0x0010ab4c /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG0_ST 0:0 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG0_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG0_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG0_BUSY_SET 1:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG0_BUSY_CLR 2:2 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG1_ST 4:4 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG1_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG1_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG1_BUSY_SET 5:5 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG1_BUSY_CLR 6:6 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG2_ST 8:8 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG2_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG2_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG2_BUSY_SET 9:9 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG2_BUSY_CLR 10:10 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG3_ST 12:12 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG3_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG3_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG3_BUSY_SET 13:13 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG3_BUSY_CLR 14:14 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG4_ST 16:16 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG4_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG4_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG4_BUSY_SET 17:17 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG4_BUSY_CLR 18:18 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_5_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6 0x0010a520 /* RW-4R */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6__PRIV_LEVEL_MASK 0x0010ab50 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG0_ST 0:0 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG0_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG0_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG0_BUSY_SET 1:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG0_BUSY_CLR 2:2 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG1_ST 4:4 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG1_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG1_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG1_BUSY_SET 5:5 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG1_BUSY_CLR 6:6 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG2_ST 8:8 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG2_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG2_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG2_BUSY_SET 9:9 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG2_BUSY_CLR 10:10 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG3_ST 12:12 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG3_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG3_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG3_BUSY_SET 13:13 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG3_BUSY_CLR 14:14 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG4_ST 16:16 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG4_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG4_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG4_BUSY_SET 17:17 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG4_BUSY_CLR 18:18 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_6_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7 0x0010a524 /* RW-4R */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7__PRIV_LEVEL_MASK 0x0010ab54 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG0_ST 0:0 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG0_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG0_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG0_BUSY_SET 1:1 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG0_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG0_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG0_BUSY_CLR 2:2 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG0_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG0_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG1_ST 4:4 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG1_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG1_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG1_BUSY_SET 5:5 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG1_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG1_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG1_BUSY_CLR 6:6 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG1_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG1_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG2_ST 8:8 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG2_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG2_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG2_BUSY_SET 9:9 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG2_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG2_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG2_BUSY_CLR 10:10 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG2_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG2_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG3_ST 12:12 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG3_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG3_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG3_BUSY_SET 13:13 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG3_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG3_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG3_BUSY_CLR 14:14 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG3_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG3_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG4_ST 16:16 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG4_ST_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG4_ST_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG4_BUSY_SET 17:17 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG4_BUSY_SET_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG4_BUSY_SET_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG4_BUSY_CLR 18:18 /* RWEVF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG4_BUSY_CLR_INIT 0x00000000 /* -WE-V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_7_ENG4_BUSY_CLR_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS 0x0010aa7c /* R--4R */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG0 0:0 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG0_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG0_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG1 1:1 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG1_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG1_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG2 2:2 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG2_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG2_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG3 3:3 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG3_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG3_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG4 4:4 /* R--VF */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG4_BUSY 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ENG4_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ST_ENG(i) (i):(i) /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ST_ENG__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ST_ENG_BUSY 1 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_STATUS_ST_ENG_IDLE 0 /* */
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#define NV_PPWR_PMU_PG_IDLE_MASK(i) (0x0010af00+(i)*12) /* RW-4A */
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#define NV_PPWR_PMU_PG_IDLE_MASK__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_IDLE_MASK__PRIV_LEVEL_MASK 0x0010a7dc /* */
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#define NV_PPWR_PMU_PG_IDLE_MASK_VALUE 31:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_IDLE_MASK_VALUE_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_IDLE_MASK_1(i) (0x0010af04+(i)*12) /* RW-4A */
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#define NV_PPWR_PMU_PG_IDLE_MASK_1__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_IDLE_MASK_1__PRIV_LEVEL_MASK 0x0010a7dc /* */
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#define NV_PPWR_PMU_PG_IDLE_MASK_1_VALUE 31:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_IDLE_MASK_1_VALUE_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_IDLE_MASK_2(i) (0x0010af08+(i)*12) /* RW-4A */
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#define NV_PPWR_PMU_PG_IDLE_MASK_2__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_IDLE_MASK_2__PRIV_LEVEL_MASK 0x0010a7dc /* */
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#define NV_PPWR_PMU_PG_IDLE_MASK_2_VALUE 31:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_IDLE_MASK_2_VALUE_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK 0x0010a79c /* RW-4R */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK__PRIV_LEVEL_MASK 0x0010a7dc /* */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_0 2:0 /* RWEVF */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_0_ENG0 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_0_ENG1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_0_ENG2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_0_ENG3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_0_ENG4 0x00000004 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_1 6:4 /* RWEVF */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_1_ENG0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_1_ENG1 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_1_ENG2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_1_ENG3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_1_ENG4 0x00000004 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_2 10:8 /* RWEVF */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_2_ENG0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_2_ENG1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_2_ENG2 0x00000002 /* RWE-V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_2_ENG3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_2_ENG4 0x00000004 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_3 14:12 /* RWEVF */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_3_ENG0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_3_ENG1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_3_ENG2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_3_ENG3 0x00000003 /* RWE-V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_3_ENG4 0x00000004 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_4 18:16 /* RWEVF */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_4_ENG0 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_4_ENG1 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_4_ENG2 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_4_ENG3 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_PG_SEQ_SEL_MASK_SEQ_4_ENG4 0x00000004 /* RWE-V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK 0x0010a974 /* RW-4R */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "pmu_gpcrg_secure_gpc_pri_err" /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLED_FUSE1 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLED 0x0000000c /* RW--V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_PMU_GR_PRI_ERROR_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_PMU_GR_PRI_ERROR 0x0010a658 /* RW-4R */
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#define NV_PPWR_PMU_GR_PRI_ERROR__PRIV_LEVEL_MASK 0x0010a974 /* */
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#define NV_PPWR_PMU_GR_PRI_ERROR_CONFIG 0:0 /* RWEVF */
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#define NV_PPWR_PMU_GR_PRI_ERROR_CONFIG_DISABLE 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_GR_PRI_ERROR_CONFIG_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_RAM_TARGET 0x0010ab8c /* RW-4R */
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#define NV_PPWR_PMU_RAM_TARGET__PRIV_LEVEL_MASK 0x0010a788 /* */
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#define NV_PPWR_PMU_RAM_TARGET_SEQ(i) (4*(i)+3):(4*(i)) /* */
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#define NV_PPWR_PMU_RAM_TARGET_SEQ__SIZE_1 2 /* */
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#define NV_PPWR_PMU_RAM_TARGET_SEQ_POWER_ON 0x00000000 /* */
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#define NV_PPWR_PMU_RAM_TARGET_SEQ_PROFILE0 0x00000001 /* */
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#define NV_PPWR_PMU_RAM_TARGET_SEQ_PROFILE1 0x00000002 /* */
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#define NV_PPWR_PMU_RAM_TARGET_SEQ_PROFILE2 0x00000004 /* */
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#define NV_PPWR_PMU_RAM_TARGET_SEQ_PROFILE3 0x00000008 /* */
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#define NV_PPWR_PMU_RAM_TARGET_GR 3:0 /* RWEVF */
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#define NV_PPWR_PMU_RAM_TARGET_GR_POWER_ON 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_RAM_TARGET_GR_PROFILE0 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_RAM_TARGET_GR_PROFILE1 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_RAM_TARGET_GR_PROFILE2 0x00000004 /* RW--V */
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#define NV_PPWR_PMU_RAM_TARGET_GR_PROFILE3 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_RAM_TARGET_MS 7:4 /* RWEVF */
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#define NV_PPWR_PMU_RAM_TARGET_MS_POWER_ON 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_RAM_TARGET_MS_PROFILE0 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_RAM_TARGET_MS_PROFILE1 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_RAM_TARGET_MS_PROFILE2 0x00000004 /* RW--V */
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#define NV_PPWR_PMU_RAM_TARGET_MS_PROFILE3 0x00000008 /* RW--V */
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#define NV_PPWR_PMU_RAM_STATUS 0x0010ab90 /* R--4R */
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#define NV_PPWR_PMU_RAM_STATUS__PRIV_LEVEL_MASK 0x0010a788 /* */
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#define NV_PPWR_PMU_RAM_STATUS_FSM_SEQ(i) (8*(i)+1):(8*(i)) /* */
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#define NV_PPWR_PMU_RAM_STATUS_FSM_SEQ__SIZE_1 2 /* */
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#define NV_PPWR_PMU_RAM_STATUS_FSM_SEQ_POWER_ON 0 /* */
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#define NV_PPWR_PMU_RAM_STATUS_FSM_SEQ_LOW_POWER_ENTERING 1 /* */
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#define NV_PPWR_PMU_RAM_STATUS_FSM_SEQ_LOW_POWER 2 /* */
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#define NV_PPWR_PMU_RAM_STATUS_FSM_SEQ_LOW_POWER_EXITING 3 /* */
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#define NV_PPWR_PMU_RAM_STATUS_PROFILE_SEQ(i) (8*(i)+7):(8*(i)+4) /* */
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#define NV_PPWR_PMU_RAM_STATUS_PROFILE_SEQ__SIZE_1 2 /* */
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#define NV_PPWR_PMU_RAM_STATUS_PROFILE_SEQ_POWER_ON 0x00000000 /* */
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#define NV_PPWR_PMU_RAM_STATUS_PROFILE_SEQ_PROFILE0 0x00000001 /* */
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#define NV_PPWR_PMU_RAM_STATUS_PROFILE_SEQ_PROFILE1 0x00000002 /* */
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#define NV_PPWR_PMU_RAM_STATUS_PROFILE_SEQ_PROFILE2 0x00000004 /* */
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#define NV_PPWR_PMU_RAM_STATUS_PROFILE_SEQ_PROFILE3 0x00000008 /* */
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#define NV_PPWR_PMU_RAM_STATUS_GR_FSM 1:0 /* R-EVF */
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#define NV_PPWR_PMU_RAM_STATUS_GR_FSM_POWER_ON 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_RAM_STATUS_GR_FSM_LOW_POWER_ENTERING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_GR_FSM_LOW_POWER 0x00000002 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_GR_FSM_LOW_POWER_EXITING 0x00000003 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_GR_PROFILE 7:4 /* R-EVF */
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#define NV_PPWR_PMU_RAM_STATUS_GR_PROFILE_POWER_ON 0x00000000 /* R-E-V */
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#define NV_PPWR_PMU_RAM_STATUS_GR_PROFILE_PROFILE0 0x00000001 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_GR_PROFILE_PROFILE1 0x00000002 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_GR_PROFILE_PROFILE2 0x00000004 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_GR_PROFILE_PROFILE3 0x00000008 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_MS_FSM 9:8 /* R--VF */
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#define NV_PPWR_PMU_RAM_STATUS_MS_FSM_POWER_ON 0x00000000 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_MS_FSM_LOW_POWER_ENTERING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_MS_FSM_LOW_POWER 0x00000002 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_MS_FSM_LOW_POWER_EXITING 0x00000003 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_MS_PROFILE 15:12 /* R--VF */
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#define NV_PPWR_PMU_RAM_STATUS_MS_PROFILE_POWER_ON 0x00000000 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_MS_PROFILE_PROFILE0 0x00000001 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_MS_PROFILE_PROFILE1 0x00000002 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_MS_PROFILE_PROFILE2 0x00000004 /* R---V */
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#define NV_PPWR_PMU_RAM_STATUS_MS_PROFILE_PROFILE3 0x00000008 /* R---V */
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#define NV_PPWR_PMU_RAM_STAGGER_CONFIG 0x0010ab98 /* RW-4R */
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#define NV_PPWR_PMU_RAM_STAGGER_CONFIG__PRIV_LEVEL_MASK 0x0010ab80 /* */
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#define NV_PPWR_PMU_RAM_STAGGER_CONFIG_ZONE_DELAY 3:0 /* RWEVF */
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#define NV_PPWR_PMU_RAM_STAGGER_CONFIG_ZONE_DELAY_INIT 0x00000003 /* RWE-V */
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#define NV_PPWR_PMU_RAM_STAGGER_CONFIG_FAST_MODE 4:4 /* RWEVF */
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#define NV_PPWR_PMU_RAM_STAGGER_CONFIG_FAST_MODE_EN 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_RAM_STAGGER_CONFIG_FAST_MODE_DIS 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_RAM_STAGGER_CONFIG_RET_EN_DELAY 13:8 /* RWEVF */
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#define NV_PPWR_PMU_RAM_STAGGER_CONFIG_RET_EN_DELAY_INIT 0x00000003 /* RWE-V */
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#define NV_PPWR_PMU_GROUP_TOP_ORDER 0x0010ab9c /* RW-4R */
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#define NV_PPWR_PMU_GROUP_TOP_ORDER__PRIV_LEVEL_MASK 0x0010ab80 /* */
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#define NV_PPWR_PMU_GROUP_TOP_ORDER_GR_RAM 13:8 /* RWEVF */
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#define NV_PPWR_PMU_GROUP_TOP_ORDER_GR_RAM_INIT 0x0000003f /* RWE-V */
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#define NV_PPWR_PMU_GROUP_TOP_ORDER_MS_RAM 21:16 /* RWEVF */
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#define NV_PPWR_PMU_GROUP_TOP_ORDER_MS_RAM_INIT 0x00000035 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX 0x0010aba0 /* RW-4R */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010ab80 /* */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX 0:0 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MIN 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MAX 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR 8:8 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_ENABLED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR 9:9 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_ENABLED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION 0x0010aba4 /* RW-4R */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION__APERTURE_INDEX_OFFSET (0x00000BA0-0x00000BA4) /* */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION__PRIV_LEVEL_MASK 0x0010ab80 /* */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_ORDER 5:0 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_0_ORDER_INIT 0x0000001f /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_1_ORDER_INIT 0x00000003 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL 9:8 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX 0x0010a528 /* RW-4R */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010a788 /* */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX 0:0 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MIN 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_INDEX_MAX 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR 8:8 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_READINCR_ENABLED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR 9:9 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1 0x0010a52c /* RW-4R */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1__APERTURE_INDEX_OFFSET (0x00000528-0x0000052C) /* */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1__PRIV_LEVEL_MASK 0x0010a788 /* */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0 1:0 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_POWER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPPG 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE0_RPG 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1 3:2 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_POWER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPPG 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE1_RPG 0x00000002 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2 5:4 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_POWER_ON 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPPG 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE2_RPG 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3 7:6 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_POWER_ON 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPPG 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_GR_RAM_PARTITION1_PROFILE3_RPG 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX 0x0010bd40 /* RW-4R */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX__PRIV_LEVEL_MASK 0x0010ab80 /* */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX 5:0 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MAX 0x00000020 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR 8:8 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR 9:9 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION 0x0010bd44 /* RW-4R */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION__APERTURE_INDEX_OFFSET (0x00001D40-0x00001D44) /* */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION__PRIV_LEVEL_MASK 0x0010ab80 /* */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_ORDER 5:0 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_0_ORDER_INIT 0x00000004 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_1_ORDER_INIT 0x00000010 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_2_ORDER_INIT 0x0000000e /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_3_ORDER_INIT 0x00000003 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_4_ORDER_INIT 0x0000000f /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_5_ORDER_INIT 0x00000017 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_6_ORDER_INIT 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_7_ORDER_INIT 0x0000001a /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_8_ORDER_INIT 0x00000020 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_9_ORDER_INIT 0x00000014 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_10_ORDER_INIT 0x0000001e /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_11_ORDER_INIT 0x00000015 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_12_ORDER_INIT 0x00000016 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_13_ORDER_INIT 0x00000021 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_14_ORDER_INIT 0x0000001f /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_15_ORDER_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_16_ORDER_INIT 0x00000002 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_17_ORDER_INIT 0x00000032 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_18_ORDER_INIT 0x00000033 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_19_ORDER_INIT 0x00000034 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_20_ORDER_INIT 0x00000018 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_21_ORDER_INIT 0x0000000d /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_22_ORDER_INIT 0x00000006 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_23_ORDER_INIT 0x00000008 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_24_ORDER_INIT 0x0000001d /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_25_ORDER_INIT 0x00000019 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_26_ORDER_INIT 0x0000000c /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_27_ORDER_INIT 0x00000007 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_28_ORDER_INIT 0x00000009 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_29_ORDER_INIT 0x0000001c /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_30_ORDER_INIT 0x00000013 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_31_ORDER_INIT 0x00000035 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_32_ORDER_INIT 0x0000000b /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL 9:8 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX 0x0010a530 /* RW-4R */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX__PRIV_LEVEL_MASK 0x0010a788 /* */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX 5:0 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MIN 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_INDEX_MAX 0x00000020 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR 8:8 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_READINCR_ENABLED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR 9:9 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_INDEX_WRITEINCR_ENABLED 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1 0x0010a534 /* RW-4R */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1__APERTURE_INDEX_OFFSET (0x00000530-0x00000534) /* */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1__PRIV_LEVEL_MASK 0x0010a788 /* */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0 1:0 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_POWER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPPG 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE0_RPG 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1 3:2 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_POWER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPPG 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE1_RPG 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2 5:4 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_POWER_ON 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPPG 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE2_RPG 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3 7:6 /* RWEVF */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_POWER_ON 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPPG 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_POWER_CTRL_MS_RAM_PARTITION1_PROFILE3_RPG 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE 0x0010bd50 /* RW-4R */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE__PRIV_LEVEL_MASK 0x0010ab80 /* */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX 2:0 /* RWEVF */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT 0x00000000 /* RWE-V */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX 6:4 /* RWEVF */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT 0x00000001 /* RWE-V */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX 10:8 /* RWEVF */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT 0x00000002 /* RWE-V */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX 14:12 /* RWEVF */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT 0x00000003 /* RWE-V */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX 18:16 /* RWEVF */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT 0x00000004 /* RWE-V */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX 22:20 /* RWEVF */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT 0x00000005 /* RWE-V */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX 26:24 /* RWEVF */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT 0x00000006 /* RWE-V */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX 30:28 /* RWEVF */
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#define NV_PPWR_PMU_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT 0x00000007 /* RWE-V */
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#define NV_PPWR_PMU_PRI_PWR_CG 0x0010aa70 /* RWI4R */
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#define NV_PPWR_PMU_PRI_PWR_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
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#define NV_PPWR_PMU_PRI_PWR_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_PRI_PWR_CG_IDLE_CG_DLY_CNT__PROD 0x00000005 /* RW--V */
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#define NV_PPWR_PMU_PRI_PWR_CG_IDLE_CG_EN 6:6 /* RWIVF */
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#define NV_PPWR_PMU_PRI_PWR_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PRI_PWR_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_PRI_PWR_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PRI_PWR_CG_STATE_CG_EN 7:7 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_STATE_CG_EN__PROD 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_STALL_CG_DLY_CNT 13:8 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_STALL_CG_DLY_CNT__PROD 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_STALL_CG_EN 14:14 /* RWIVF */
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#define NV_PPWR_PMU_PRI_PWR_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PRI_PWR_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_PRI_PWR_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PRI_PWR_CG_QUIESCENT_CG_EN 15:15 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_QUIESCENT_CG_EN__PROD 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
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#define NV_PPWR_PMU_PRI_PWR_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_PRI_PWR_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PRI_PWR_CG_THROT_CLK_CNT 23:20 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_DI_DT_SKEW_VAL 27:24 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_THROT_CLK_EN 28:28 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_THROT_CLK_EN__PROD 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_THROT_CLK_SW_OVER 29:29 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_PAUSE_CG_EN 30:30 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_HALT_CG_EN 31:31 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG_HALT_CG_EN__PROD 0x00000000 /* */
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#define NV_PPWR_PMU_PRI_PWR_CG1 0x0010aa74 /* RWI4R */
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#define NV_PPWR_PMU_PRI_PWR_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
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#define NV_PPWR_PMU_PRI_PWR_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_PRI_PWR_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_PRI_PWR_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PRI_PWR_CG1_SLCG 14:1 /* RWIVF */
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#define NV_PPWR_PMU_PRI_PWR_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_PRI_PWR_CG1_SLCG_DISABLED 0x00003fff /* RWI-V */
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#define NV_PPWR_PMU_PRI_PWR_CG1_SLCG__PROD 0x00003225 /* RW--V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK 0x0010ae70 /* RWI4R */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_PLM /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK 0x0010ae88 /* RWI4R */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_PLM /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_DEFAULT_PRIV_LEVEL 0x0000000f /* RWI-V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RW--V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_PPWR_FBIF_CTL2_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000fffff /* RWI-V */
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#define NV_PPWR_FBIF_TRANSCFG(i) (0x0010ae00+(i)*4) /* RW-4A */
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#define NV_PPWR_FBIF_TRANSCFG__SIZE_1 8 /* */
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#define NV_PPWR_FBIF_TRANSCFG__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_MMODE /* */
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#define NV_PPWR_FBIF_TRANSCFG__PRIV_LEVEL_MASK 0x0010ae70 /* */
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#define NV_PPWR_FBIF_TRANSCFG_TARGET 1:0 /* RWIVF */
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#define NV_PPWR_FBIF_TRANSCFG_TARGET_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_TRANSCFG_TARGET_LOCAL_FB 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_TRANSCFG_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_TRANSCFG_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */
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#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE 2:2 /* RWIVF */
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#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_VIRTUAL 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_TRANSCFG_MEM_TYPE_PHYSICAL 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_TRANSCFG_L2C_WR 5:4 /* RWIVF */
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#define NV_PPWR_FBIF_TRANSCFG_L2C_WR_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_TRANSCFG_L2C_WR_L2_EVICT_FIRST 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_TRANSCFG_L2C_WR_L2_EVICT_NORMAL 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_TRANSCFG_L2C_WR_L2_EVICT_LAST 0x00000002 /* R---V */
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#define NV_PPWR_FBIF_TRANSCFG_L2C_RD 9:8 /* RWIVF */
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#define NV_PPWR_FBIF_TRANSCFG_L2C_RD_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_TRANSCFG_L2C_RD_L2_EVICT_FIRST 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_TRANSCFG_L2C_RD_L2_EVICT_NORMAL 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_TRANSCFG_L2C_RD_L2_EVICT_LAST 0x00000002 /* R---V */
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#define NV_PPWR_FBIF_TRANSCFG_WACHK0 12:12 /* RWIVF */
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#define NV_PPWR_FBIF_TRANSCFG_WACHK0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_TRANSCFG_WACHK0_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_TRANSCFG_WACHK0_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_TRANSCFG_WACHK1 13:13 /* RWIVF */
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#define NV_PPWR_FBIF_TRANSCFG_WACHK1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_TRANSCFG_WACHK1_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_TRANSCFG_WACHK1_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_TRANSCFG_RACHK0 14:14 /* RWIVF */
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#define NV_PPWR_FBIF_TRANSCFG_RACHK0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_TRANSCFG_RACHK0_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_TRANSCFG_RACHK0_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_TRANSCFG_RACHK1 15:15 /* RWIVF */
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#define NV_PPWR_FBIF_TRANSCFG_RACHK1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_TRANSCFG_RACHK1_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_TRANSCFG_RACHK1_DISABLE 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_INSTBLK 0x0010ae20 /* R--4R */
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#define NV_PPWR_FBIF_INSTBLK__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_INSTBLK_PTR 27:0 /* R--VF */
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#define NV_PPWR_FBIF_INSTBLK_TARGET 29:28 /* R--VF */
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#define NV_PPWR_FBIF_INSTBLK_TARGET_LOCAL_FB 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_INSTBLK_TARGET_COHERENT_SYSMEM 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_INSTBLK_TARGET_NONCOHERENT_SYSMEM 0x00000002 /* R---V */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_LO 0x0010ae90 /* R--4R */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_LO__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_GPC 0:0 /* R-IVF */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_GPC_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_PDB 1:1 /* R-IVF */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_PDB_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_TARGET 3:2 /* R-IVF */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_TARGET_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_PDB_ADR_LO 31:4 /* R-IVF */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_LO_PDB_ADR_LO_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI 0x0010ae94 /* R--4R */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_PDB_ADR_HI 6:0 /* R-IVF */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_PDB_ADR_HI_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_PAGE_TABLE_LEVEL 9:7 /* R-IVF */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_PAGE_TABLE_LEVEL_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_TARGET_AVA 10:10 /* R-IVF */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_TARGET_AVA_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_MMU_REPLAY 13:11 /* R-IVF */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_MMU_REPLAY_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_CANCEL_TARGET_CLIENT_UNIT_ID 20:14 /* R-IVF */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_CANCEL_TARGET_CLIENT_UNIT_ID_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_CANCEL_TARGET_GPC_ID 23:21 /* R-IVF */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_CANCEL_TARGET_GPC_ID_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_SYS_MEMBAR 24:24 /* R-IVF */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_SYS_MEMBAR_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_ACK_TYPE 26:25 /* R-IVF */
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#define NV_PPWR_FBIF_TLB_INVALIDATE_PARAM1_HI_ACK_TYPE_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_FBIF_CTL 0x0010ae24 /* RW-4R */
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#define NV_PPWR_FBIF_CTL__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_CTL_FLUSH 0:0 /* RW-VF */
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#define NV_PPWR_FBIF_CTL_FLUSH_SET 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_CTL_FLUSH_CLEAR 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL_INVAL_CONTEXT 2:2 /* RW-VF */
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#define NV_PPWR_FBIF_CTL_INVAL_CONTEXT_SET 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_CTL_INVAL_CONTEXT_CLEAR 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL_CLR_BWCOUNT 3:3 /* RW-VF */
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#define NV_PPWR_FBIF_CTL_CLR_BWCOUNT_SET 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_CTL_CLR_BWCOUNT_CLEAR 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL_ENABLE 4:4 /* RWIVF */
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#define NV_PPWR_FBIF_CTL_ENABLE_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_CTL_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_CTL_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL_CLR_IDLEWDERR 5:5 /* RW-VF */
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#define NV_PPWR_FBIF_CTL_CLR_IDLEWDERR_SET 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_CTL_CLR_IDLEWDERR_CLEAR 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL_RESET 6:6 /* RW-VF */
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#define NV_PPWR_FBIF_CTL_RESET_SET 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_CTL_RESET_CLEAR 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL_ALLOW_PHYS_NO_CTX 7:7 /* RWIVF */
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#define NV_PPWR_FBIF_CTL_ALLOW_PHYS_NO_CTX_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_CTL_ALLOW_PHYS_NO_CTX_DISALLOW 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL_ALLOW_PHYS_NO_CTX_ALLOW 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_CTL_IDLE 8:8 /* R--VF */
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#define NV_PPWR_FBIF_CTL_IDLE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_CTL_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_CTL_IDLEWDERR 9:9 /* R--VF */
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#define NV_PPWR_FBIF_CTL_IDLEWDERR_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_CTL_IDLEWDERR_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_CTL_SRTOUT 10:10 /* R--VF */
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#define NV_PPWR_FBIF_CTL_SRTOUT_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_CTL_SRTOUT_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_CTL_CLR_SRTOUT 11:11 /* RW-VF */
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#define NV_PPWR_FBIF_CTL_CLR_SRTOUT_SET 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_CTL_CLR_SRTOUT_CLEAR 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CTL_SRTOVAL 19:16 /* RWIVF */
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#define NV_PPWR_FBIF_CTL_SRTOVAL_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_CTL2 0x0010ae84 /* RW-4R */
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#define NV_PPWR_FBIF_CTL2__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_CTL2__PRIV_LEVEL_MASK 0x0010ae88 /* */
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#define NV_PPWR_FBIF_CTL2_NACK_MODE 0:0 /* RWIVF */
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#define NV_PPWR_FBIF_CTL2_NACK_MODE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_CTL2_NACK_MODE_NACK_AS_ACK 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_THROTTLE 0x0010ae2c /* RW-4R */
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#define NV_PPWR_FBIF_THROTTLE__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_THROTTLE_BUCKET_SIZE 11:0 /* RWIVF */
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#define NV_PPWR_FBIF_THROTTLE_BUCKET_SIZE_INIT 0x00000064 /* RWI-V */
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#define NV_PPWR_FBIF_THROTTLE_LEAK_COUNT 27:16 /* RWIVF */
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#define NV_PPWR_FBIF_THROTTLE_LEAK_COUNT_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_THROTTLE_LEAK_SIZE 31:30 /* RWIVF */
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#define NV_PPWR_FBIF_THROTTLE_LEAK_SIZE_16B 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_THROTTLE_LEAK_SIZE_32B 0x00000001 /* RW--V */
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#define NV_PPWR_FBIF_THROTTLE_LEAK_SIZE_64B 0x00000002 /* RWI-V */
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#define NV_PPWR_FBIF_THROTTLE_LEAK_SIZE_128B 0x00000003 /* RW--V */
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#define NV_PPWR_FBIF_REGIONCFG 0x0010ae6c /* RW-4R */
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#define NV_PPWR_FBIF_REGIONCFG__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_MMODE /* */
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#define NV_PPWR_FBIF_REGIONCFG__PRIV_LEVEL_MASK 0x0010ae70 /* */
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#define NV_PPWR_FBIF_REGIONCFG_T0 3:0 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_T0_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_REGIONCFG_T1 7:4 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_T1_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_REGIONCFG_T2 11:8 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_T2_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_REGIONCFG_T3 15:12 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_T3_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_REGIONCFG_T4 19:16 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_T4_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_REGIONCFG_T5 23:20 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_T5_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_REGIONCFG_T6 27:24 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_T6_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_REGIONCFG_T7 31:28 /* RWIVF */
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#define NV_PPWR_FBIF_REGIONCFG_T7_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_FBIF_CG1 0x0010ae74 /* RW-4R */
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#define NV_PPWR_FBIF_CG1__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_MMODE /* */
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#define NV_PPWR_FBIF_CG1_SLCG 3:0 /* */
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#define NV_PPWR_FBIF_CG1_SLCG_ENABLED 0 /* */
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#define NV_PPWR_FBIF_CG1_SLCG_DISABLED 0xF /* */
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#define NV_PPWR_FBIF_CG1_SLCG__PROD 0x0 /* */
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#define NV_PPWR_FBIF_CG1_SLCG_MSD0 0:0 /* RWIVF */
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#define NV_PPWR_FBIF_CG1_SLCG_MSD0_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CG1_SLCG_MSD0_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_CG1_SLCG_MSD1 1:1 /* RWIVF */
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#define NV_PPWR_FBIF_CG1_SLCG_MSD1_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CG1_SLCG_MSD1_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_CG1_SLCG_FB0 2:2 /* RWIVF */
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#define NV_PPWR_FBIF_CG1_SLCG_FB0_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CG1_SLCG_FB0_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_CG1_SLCG_FB1 3:3 /* RWIVF */
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#define NV_PPWR_FBIF_CG1_SLCG_FB1_ENABLED 0x00000000 /* RW--V */
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#define NV_PPWR_FBIF_CG1_SLCG_FB1_DISABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_FBIF_ACHK_BLK(i) (0x0010ae30+(i)*8) /* RW-4A */
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#define NV_PPWR_FBIF_ACHK_BLK__SIZE_1 2 /* */
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#define NV_PPWR_FBIF_ACHK_BLK__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_ACHK_BLK_ADDR 31:0 /* RW-VF */
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#define NV_PPWR_FBIF_ACHK_CTL(i) (0x0010ae34+(i)*8) /* RW-4A */
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#define NV_PPWR_FBIF_ACHK_CTL__SIZE_1 2 /* */
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#define NV_PPWR_FBIF_ACHK_CTL__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_ACHK_CTL_SIZE 4:0 /* RW-VF */
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#define NV_PPWR_FBIF_ACHK_CTL_TYPE 6:6 /* RW-VF */
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#define NV_PPWR_FBIF_ACHK_CTL_TYPE_INSIDE 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_ACHK_CTL_TYPE_OUTSIDE 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_ACHK_CTL_STATE 7:7 /* RW-VF */
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#define NV_PPWR_FBIF_ACHK_CTL_STATE_DISABLE 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_ACHK_CTL_STATE_ENABLE 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_ACHK_CTL_COUNT 31:16 /* RW-VF */
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#define NV_PPWR_FBIF_DBG_STAT0 0x0010ae40 /* R--4R */
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#define NV_PPWR_FBIF_DBG_STAT0__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_DBG_STAT0__PRIV_LEVEL_MASK 0x0010ae70 /* */
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#define NV_PPWR_FBIF_DBG_STAT0_DSP_STATE 3:0 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_DSP_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_DSP_STATE_CHECK 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_DSP_STATE_ALLOC 0x00000002 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_DSP_STATE_ISSUE 0x00000003 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_DSP_STATE_WDAT 0x00000004 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_DSP_STATE_FLT_FLUSH 0x00000005 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_DSP_STATE_HALT 0x00000006 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_DSP_STATE_INST 0x00000007 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_DSP_STATE_INST_ACK 0x00000008 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_DSP_STATE_OBJ 0x00000009 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_DSP_STATE_FLUSH 0x0000000a /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_INST_VLD 4:4 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_INST_BOUND 5:5 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_RICF_HAS_DATA 6:6 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_ARQ_HAS_DATA 7:7 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_MRQ_HAS_DATA 8:8 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_FAULT_OR_HALT 9:9 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_ORQ_NOT_FULL 10:10 /* R-IUF */
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#define NV_PPWR_FBIF_DBG_STAT0_ORQ_NOT_FULL_TRUE 0x00000001 /* R-I-V */
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#define NV_PPWR_FBIF_DBG_STAT0_ORQ_NOT_FULL_FLASE 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_FLUSH_OUTSTANDING 11:11 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_DISPATCH_IDLE 12:12 /* R-IUF */
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#define NV_PPWR_FBIF_DBG_STAT0_DISPATCH_IDLE_TRUE 0x00000001 /* R-I-V */
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#define NV_PPWR_FBIF_DBG_STAT0_DISPATCH_IDLE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_MWF_FSM_STATE 17:16 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_MWF_FSM_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_MWF_FSM_STATE_COMMIT 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_MWF_FSM_STATE_ROLLBACK 0x00000002 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT0_MWF_HAS_DATA 18:18 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_MWF_COMMIT_COUNT 24:19 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_STALL_RQQ_FULL 25:25 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_STALL_WDF_FULL 26:26 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_STALL_FB_BUSY 27:27 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_STALL_ORQ_FULL 28:28 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_STALL_RDM_ALLOC 29:29 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_STALL_RDM_PORTQ 30:30 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT0_STALL_RDM_CLIENT 31:31 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1 0x0010ae44 /* R--4R */
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#define NV_PPWR_FBIF_DBG_STAT1__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_DBG_STAT1__PRIV_LEVEL_MASK 0x0010ae70 /* */
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#define NV_PPWR_FBIF_DBG_STAT1_FLT_STATE 1:0 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_FLT_FAULTED 2:2 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_FLT_BUSY 3:3 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_ACKF_HAS_DATA 4:4 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_ORQ_HAS_DATA 5:5 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_ALL_READS_DONE 6:6 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_FBR_IDLE 8:8 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_FBR_FAULTED 9:9 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_FBR_FB_BUSY 10:10 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_FBR_PKT2FB_VLD 11:11 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_FBR_RCV_DATA_VALID 12:12 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_FBR_RCV_DATA_TYPE 15:14 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_WDF_FSM_STATE 17:16 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_WDF_FSM_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT1_WDF_FSM_STATE_COMMIT 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT1_WDF_FSM_STATE_ROLLBACK 0x00000002 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT1_WDF_HAS_DATA 18:18 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_WDF_COMMIT_COUNT 23:19 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_RDM_STATE 25:24 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_RDM_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT1_RDM_STATE_WAITBUF 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT1_RDM_STATE_SAVEBUF 0x00000002 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT1_RDM_ANY_READY 26:26 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_RDM_DAQ_HAS_DATA 27:27 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_RDM_DEALLOC_COUNT 30:28 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT1_RDATA_WAIT 31:31 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT2 0x0010ae48 /* R--4R */
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#define NV_PPWR_FBIF_DBG_STAT2__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_DBG_STAT2__PRIV_LEVEL_MASK 0x0010ae70 /* */
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#define NV_PPWR_FBIF_DBG_STAT2_FAULTED_PORTID 5:0 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT2_FAULTED_SUBID 12:6 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT2_FAULTED_SRCQ 13:13 /* R--UF */
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#define NV_PPWR_FBIF_DBG_STAT2_FAULTED_SRCQ_ARQ 0x00000001 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT2_FAULTED_SRCQ_MRQ 0x00000000 /* R---V */
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#define NV_PPWR_FBIF_DBG_STAT2_FAULTED_VLD 14:14 /* R--UF */
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#define NV_PPWR_FBIF_DBG_RDCOUNT_LO 0x0010ae50 /* R--4R */
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#define NV_PPWR_FBIF_DBG_RDCOUNT_LO__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_DBG_RDCOUNT_LO__PRIV_LEVEL_MASK 0x0010ae70 /* */
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#define NV_PPWR_FBIF_DBG_RDCOUNT_LO_DATA 31:0 /* R--UF */
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#define NV_PPWR_FBIF_DBG_RDCOUNT_HI 0x0010ae54 /* R--4R */
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#define NV_PPWR_FBIF_DBG_RDCOUNT_HI__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_DBG_RDCOUNT_HI__PRIV_LEVEL_MASK 0x0010ae70 /* */
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#define NV_PPWR_FBIF_DBG_RDCOUNT_HI_DATA 31:0 /* R--UF */
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#define NV_PPWR_FBIF_DBG_WRCOUNT_LO 0x0010ae58 /* R--4R */
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#define NV_PPWR_FBIF_DBG_WRCOUNT_LO__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_DBG_WRCOUNT_LO__PRIV_LEVEL_MASK 0x0010ae70 /* */
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#define NV_PPWR_FBIF_DBG_WRCOUNT_LO_DATA 31:0 /* R--UF */
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#define NV_PPWR_FBIF_DBG_WRCOUNT_HI 0x0010ae5c /* R--4R */
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#define NV_PPWR_FBIF_DBG_WRCOUNT_HI__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_DBG_WRCOUNT_HI__PRIV_LEVEL_MASK 0x0010ae70 /* */
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#define NV_PPWR_FBIF_DBG_WRCOUNT_HI_DATA 31:0 /* R--UF */
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#define NV_PPWR_FBIF_BW_ALLOC 0x0010ae4c /* RW-4R */
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#define NV_PPWR_FBIF_BW_ALLOC__DEVICE_MAP NV_PPWR_FBIF_DEVICE_MAP_GROUP_FBIF /* */
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#define NV_PPWR_FBIF_BW_ALLOC_VAL 31:0 /* */
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#define NV_PPWR_FBIF_BW_ALLOC_INT_RD 7:0 /* RW-VF */
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#define NV_PPWR_FBIF_BW_ALLOC_INT_WR 15:8 /* RW-VF */
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#define NV_PPWR_FBIF_BW_ALLOC_EXT_RD 23:16 /* RW-VF */
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#define NV_PPWR_FBIF_BW_ALLOC_REQ_T 31:24 /* RW-VF */
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#define NV_PPWR_PMU_SCP_CTL0 0x0010ac00 /* RW-4R */
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#define NV_PPWR_PMU_SCP_CTL0__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_CTL0_CTL_EN 20:20 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL0_CTL_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL0_CTL_EN_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL0_SEQ_EN 16:16 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL0_SEQ_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL0_SEQ_EN_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL0_SF_CMD_IFACE_EN 14:14 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL0_SF_CMD_IFACE_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL0_SF_CMD_IFACE_EN_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL0_SF_PUSH_IFACE_EN 12:12 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL0_SF_PUSH_IFACE_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL0_SF_PUSH_IFACE_EN_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL0_SF_FETCH_IFACE_EN 10:10 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL0_SF_FETCH_IFACE_EN_DISABLED 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL0_SF_FETCH_IFACE_EN_ENABLED 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL1 0x0010ac04 /* RW-4R */
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#define NV_PPWR_PMU_SCP_CTL1__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_CTL1_SF_PUSH_BYPASS 24:24 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL1_SF_PUSH_BYPASS_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL1_SF_PUSH_BYPASS_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL1_SF_FETCH_BYPASS 20:20 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL1_SF_FETCH_BYPASS_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL1_SF_FETCH_BYPASS_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL1_SF_FETCH_AS_ZERO 16:16 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL1_SF_FETCH_AS_ZERO_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL1_SF_FETCH_AS_ZERO_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL1_RNG_EN 12:12 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL1_RNG_EN_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL1_RNG_EN_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL1_RNG_FAKE_MODE 11:11 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL1_RNG_FAKE_MODE_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL1_RNG_FAKE_MODE_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL1_PIPE_RESET 8:8 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL1_PIPE_RESET_IDLE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CTL1_PIPE_RESET_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL1_PIPE_RESET_TASK 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_SCP_CTL1_SEQ_CLEAR 0:0 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL1_SEQ_CLEAR_IDLE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CTL1_SEQ_CLEAR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL1_SEQ_CLEAR_TASK 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_SCP_CTL_STAT 0x0010ac08 /* R--4R */
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#define NV_PPWR_PMU_SCP_CTL_STAT__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_CTL_STAT_DEBUG_MODE 20:20 /* R--VF */
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#define NV_PPWR_PMU_SCP_CTL_STAT_DEBUG_MODE_DISABLED 0x00000000 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL_STAT_AES_SCC_DIS 2:2 /* R--VF */
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#define NV_PPWR_PMU_SCP_CTL_STAT_AES_SCC_DIS_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL_STAT_AES_SCC_DIS_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL_STAT_HSMODE 1:1 /* R--VF */
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#define NV_PPWR_PMU_SCP_CTL_STAT_HSMODE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL_STAT_HSMODE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL_STAT_SBOOT 0:0 /* R--VF */
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#define NV_PPWR_PMU_SCP_CTL_STAT_SBOOT_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL_STAT_SBOOT_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL_CFG 0x0010ac0c /* RW-4R */
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#define NV_PPWR_PMU_SCP_CTL_CFG__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN 0:0 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT 1:1 /* R-IVF */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_CLR_REQ_STAT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_PRE 2:2 /* R-IVF */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_PRE_ENABLED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_PRE_DISABLED 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_SCP 4:4 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_SCP_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_SCP_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_SCP_PRE 6:6 /* R-IVF */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_SCP_PRE_ENABLED 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL_CFG_LOCKDOWN_SCP_PRE_DISABLED 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CFG0 0x0010ac10 /* RW-4R */
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#define NV_PPWR_PMU_SCP_CFG0__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_CFG0_STALL_TIMEOUT 31:16 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CFG0_STALL_TIMEOUT_INIT 0x0000ffff /* RWI-V */
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#define NV_PPWR_PMU_SCP_CFG0_CARRY_CHAIN 13:12 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CFG0_CARRY_CHAIN_32 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_CFG0_CARRY_CHAIN_64 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CFG0_CARRY_CHAIN_96 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_SCP_CFG0_CARRY_CHAIN_128 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_SCP_CFG0_CMD_FLUSH 8:8 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CFG0_CMD_FLUSH_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CFG0_CMD_FLUSH_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_CFG0_AES_ENDIAN 4:4 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CFG0_AES_ENDIAN_BIG 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CFG0_AES_ENDIAN_LITTLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_CFG0_PUSH_ENDIAN 3:3 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CFG0_PUSH_ENDIAN_BIG 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_CFG0_PUSH_ENDIAN_LITTLE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CFG0_FETCH_ENDIAN 2:2 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CFG0_FETCH_ENDIAN_BIG 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_CFG0_FETCH_ENDIAN_LITTLE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CFG0_CMAC_ENDIAN 1:1 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CFG0_CMAC_ENDIAN_BIG 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CFG0_CMAC_ENDIAN_LITTLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_CFG0_ADD_ENDIAN 0:0 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CFG0_ADD_ENDIAN_BIG 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CFG0_ADD_ENDIAN_LITTLE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL_DEBUG 0x0010ac1c /* RW-4R */
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#define NV_PPWR_PMU_SCP_CTL_DEBUG__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_CTL_DEBUG_LOCKDOWN_CYA 4:4 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL_DEBUG_LOCKDOWN_CYA_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL_DEBUG_LOCKDOWN_CYA_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA 8:8 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_CTL_DEBUG_LOCKDOWN_SCP_CYA_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG0 0x0010ac20 /* RW-4R */
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#define NV_PPWR_PMU_SCP_DEBUG0__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_DEBUG0_PUSH_SECURE 31:31 /* RWIVF */
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#define NV_PPWR_PMU_SCP_DEBUG0_PUSH_SECURE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_DEBUG0_PUSH_SECURE_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG0_PUSH_VALID 30:30 /* RWIVF */
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#define NV_PPWR_PMU_SCP_DEBUG0_PUSH_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_DEBUG0_PUSH_VALID_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG0_PUSH_CNT 26:25 /* R-IVF */
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#define NV_PPWR_PMU_SCP_DEBUG0_PUSH_CNT_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_DEBUG0_FETCH_SECURE 24:24 /* RWIVF */
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#define NV_PPWR_PMU_SCP_DEBUG0_FETCH_SECURE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_DEBUG0_FETCH_SECURE_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG0_FETCH_VALID 23:23 /* RWIVF */
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#define NV_PPWR_PMU_SCP_DEBUG0_FETCH_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_DEBUG0_FETCH_VALID_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG0_FETCH_CNT 22:19 /* R-IVF */
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#define NV_PPWR_PMU_SCP_DEBUG0_FETCH_CNT_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_DEBUG0_SEQ_SECURE 18:18 /* R-IVF */
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#define NV_PPWR_PMU_SCP_DEBUG0_SEQ_SECURE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_DEBUG0_SEQ_SECURE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_DEBUG0_SEQ_VALID 17:17 /* RWIVF */
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#define NV_PPWR_PMU_SCP_DEBUG0_SEQ_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_DEBUG0_SEQ_VALID_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG0_SEQ_PC 16:13 /* RWIVF */
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#define NV_PPWR_PMU_SCP_DEBUG0_SEQ_PC_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG0_SEQ_DEPTH 12:8 /* RWIVF */
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#define NV_PPWR_PMU_SCP_DEBUG0_SEQ_DEPTH_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG0_TARGET 6:5 /* RWIVF */
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#define NV_PPWR_PMU_SCP_DEBUG0_TARGET_NONE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG0_TARGET_PUSH 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_DEBUG0_TARGET_FETCH 0x00000002 /* RW--V */
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#define NV_PPWR_PMU_SCP_DEBUG0_TARGET_SEQ 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_SCP_DEBUG0_INDEX_AUTOINCREMENT 4:4 /* RWIVF */
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#define NV_PPWR_PMU_SCP_DEBUG0_INDEX_AUTOINCREMENT_TRUE 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG0_INDEX_AUTOINCREMENT_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_DEBUG0_INDEX 3:0 /* RWIVF */
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#define NV_PPWR_PMU_SCP_DEBUG0_INDEX_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG1 0x0010ac24 /* RW-4R */
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#define NV_PPWR_PMU_SCP_DEBUG1__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_DEBUG1_DATA 31:0 /* RWIVF */
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#define NV_PPWR_PMU_SCP_DEBUG1_DATA_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG2 0x0010ac28 /* R--4R */
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#define NV_PPWR_PMU_SCP_DEBUG2__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_DEBUG2_KU 15:12 /* R-IVF */
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#define NV_PPWR_PMU_SCP_DEBUG2_KU_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_DEBUG2_SEQ_CNT 9:4 /* R-IVF */
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#define NV_PPWR_PMU_SCP_DEBUG2_SEQ_CNT_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_DEBUG2_SEQ_STATE 1:0 /* R-IVF */
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#define NV_PPWR_PMU_SCP_DEBUG2_SEQ_STATE_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_DEBUG2_SEQ_STATE_IDLE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_SCP_DEBUG2_SEQ_STATE_LOAD 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_DEBUG2_SEQ_STATE_LOOP 0x00000002 /* R---V */
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#define NV_PPWR_PMU_SCP_DEBUG_CMD 0x0010ac30 /* RW-4R */
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#define NV_PPWR_PMU_SCP_DEBUG_CMD__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_DEBUG_CMD_SECURE 31:31 /* RWIVF */
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#define NV_PPWR_PMU_SCP_DEBUG_CMD_SECURE_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG_CMD_SECURE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_DEBUG_CMD_VALID 28:28 /* RWIVF */
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#define NV_PPWR_PMU_SCP_DEBUG_CMD_VALID_FALSE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_DEBUG_CMD_VALID_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_DEBUG_CMD_OP 24:20 /* RWXVF */
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#define NV_PPWR_PMU_SCP_DEBUG_CMD_RX_IMM 13:8 /* RWXVF */
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#define NV_PPWR_PMU_SCP_DEBUG_CMD_RY 3:0 /* RWXVF */
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#define NV_PPWR_PMU_SCP_ACL_FETCH 0x0010ac40 /* R--4R */
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#define NV_PPWR_PMU_SCP_ACL_FETCH__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_ACL_FETCH_SECURE 23:16 /* R--VF */
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#define NV_PPWR_PMU_SCP_ACL_FETCH_INSECURE 7:0 /* R--VF */
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#define NV_PPWR_PMU_SCP_ACL_KEYABLE 0x0010ac44 /* R--4R */
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#define NV_PPWR_PMU_SCP_ACL_KEYABLE__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_ACL_KEYABLE_SECURE 23:16 /* R--VF */
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#define NV_PPWR_PMU_SCP_ACL_KEYABLE_INSECURE 7:0 /* R--VF */
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#define NV_PPWR_PMU_SCP_ACL_WRITE 0x0010ac48 /* R--4R */
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#define NV_PPWR_PMU_SCP_ACL_WRITE__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_ACL_WRITE_INSECURE 7:0 /* R--VF */
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#define NV_PPWR_PMU_SCP_STATUS 0x0010ac50 /* R--4R */
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#define NV_PPWR_PMU_SCP_STATUS__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_STATUS_SCP_ACTIVE 0:0 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STATUS_SCP_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STATUS_SCP_ACTIVE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STATUS_CMD_ACTIVE 2:2 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STATUS_CMD_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STATUS_CMD_ACTIVE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STATUS_PUSH_ACTIVE 4:4 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STATUS_PUSH_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STATUS_PUSH_ACTIVE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STATUS_SEQ_ACTIVE 6:6 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STATUS_SEQ_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STATUS_SEQ_ACTIVE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STATUS_CTL_ACTIVE 8:8 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STATUS_CTL_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STATUS_CTL_ACTIVE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STATUS_FETCH_ACTIVE 10:10 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STATUS_FETCH_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STATUS_FETCH_ACTIVE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STATUS_AES_ACTIVE 14:14 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STATUS_AES_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STATUS_AES_ACTIVE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STATUS_RNG_ACTIVE 16:16 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STATUS_RNG_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STATUS_RNG_ACTIVE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STATUS_SFK_LOADING_ACTIVE 20:20 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STATUS_SFK_LOADING_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STATUS_SFK_LOADING_ACTIVE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STATUS_SCC_TRNG_ACTIVE 26:26 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STATUS_SCC_TRNG_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STATUS_SCC_TRNG_ACTIVE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STATUS_SCC_PRNG_ACTIVE 28:28 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STATUS_SCC_PRNG_ACTIVE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STATUS_SCC_PRNG_ACTIVE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STAT0 0x0010ac54 /* R--4R */
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#define NV_PPWR_PMU_SCP_STAT0__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_STAT0_SF_CMD_VLD 14:14 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STAT0_SF_CMD_VLD_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT0_SF_CMD_VLD_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STAT0_SF_CMD_SECURE 12:12 /* R-XVF */
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#define NV_PPWR_PMU_SCP_STAT0_SF_CMD_SECURE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT0_SF_CMD_SECURE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT0_SF_PUSH_VLD 10:10 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STAT0_SF_PUSH_VLD_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT0_SF_PUSH_VLD_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STAT0_SF_PUSH_SECURE 8:8 /* R-XVF */
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#define NV_PPWR_PMU_SCP_STAT0_SF_PUSH_SECURE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT0_SF_PUSH_SECURE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT0_SF_FETCH_RDY 6:6 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STAT0_SF_FETCH_RDY_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT0_SF_FETCH_RDY_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STAT0_SF_FETCH_SECURE 4:4 /* R-XVF */
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#define NV_PPWR_PMU_SCP_STAT0_SF_FETCH_SECURE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT0_SF_FETCH_SECURE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT0_CMP 1:0 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STAT0_CMP_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STAT0_CMP_PASS 0x00000003 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT0_CMP_FAIL 0x00000002 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT1 0x0010ac58 /* R--4R */
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#define NV_PPWR_PMU_SCP_STAT1__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_STAT1_SEQ_OP 4:0 /* R-XVF */
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#define NV_PPWR_PMU_SCP_STAT1_SF_OP 9:5 /* R-XVF */
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#define NV_PPWR_PMU_SCP_STAT1_DISPATCH_OP 14:10 /* R-XVF */
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#define NV_PPWR_PMU_SCP_STAT1_AES_OP 17:15 /* R-XVF */
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#define NV_PPWR_PMU_SCP_STAT1_AES_OP_ENCRYPT 0x00000000 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT1_AES_OP_DECRYPT 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT1_AES_OP_RKEY 0x00000002 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT1_AES_OP_RKEYI 0x00000003 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT1_HAZARD_STALL 24:24 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STAT1_HAZARD_STALL_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STAT1_HAZARD_STALL_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT1_PUSH_STALL 25:25 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STAT1_PUSH_STALL_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STAT1_PUSH_STALL_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT1_FETCH_STALL 26:26 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STAT1_FETCH_STALL_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STAT1_FETCH_STALL_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT1_RNG_STALL 27:27 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STAT1_RNG_STALL_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STAT1_RNG_STALL_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT1_WB_STALL 28:28 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STAT1_WB_STALL_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STAT1_WB_STALL_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT1_AES_STALL 29:29 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STAT1_AES_STALL_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STAT1_AES_STALL_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_STAT1_SECRET_STALL 30:30 /* R-IVF */
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#define NV_PPWR_PMU_SCP_STAT1_SECRET_STALL_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_STAT1_SECRET_STALL_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_SECRET63_CTL 0x0010ac60 /* RW-4R */
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#define NV_PPWR_PMU_SCP_SECRET63_CTL__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_SECRET63_CTL_SEL 0:0 /* RWIVF */
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#define NV_PPWR_PMU_SCP_SECRET63_CTL_SEL_PKEY 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_SECRET63_CTL_SEL_KMEM 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0 0x0010ac70 /* RW-4R */
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#define NV_PPWR_PMU_SCP_RNG_STAT0__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_RAW_RAND_READY 0:0 /* R-IVF */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_RAW_RAND_READY_READY 0x00000000 /* R---V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_RAW_RAND_READY_PROCESSING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_RAW_RAND_READY_RANDBUF_NOTFULL 0x00000001 /* R-I-V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_AUTOCAL_TAP_A 7:4 /* R-IVF */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_AUTOCAL_TAP_A_INIT 0x0000000f /* R-I-V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_AUTOCAL_TAP_B 11:8 /* R-IVF */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_AUTOCAL_TAP_B_INIT 0x0000000f /* R-I-V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_LFSR_STAT_A 12:12 /* R-IVF */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_LFSR_STAT_A_LEGAL 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_LFSR_STAT_A_ILLEGAL 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_LFSR_STAT_B 13:13 /* R-IVF */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_LFSR_STAT_B_LEGAL 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_LFSR_STAT_B_ILLEGAL 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_A 16:16 /* RWIVF */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_A_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_A_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_A_CLEAR 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_B 20:20 /* RWIVF */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_B_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_B_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_RNG_STAT0_RCTR_SATURATED_B_CLEAR 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_SCP_RNG_STAT1 0x0010ac74 /* R--4R */
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#define NV_PPWR_PMU_SCP_RNG_STAT1__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_A 15:0 /* R-IUF */
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#define NV_PPWR_PMU_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_A_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_B 31:16 /* R-IUF */
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#define NV_PPWR_PMU_SCP_RNG_STAT1_AUTOCAL_RCLK_CTR_B_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_INTR 0x0010ac80 /* RW-4R */
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#define NV_PPWR_PMU_SCP_INTR__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_INTR_RAND_READY 0:0 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_RAND_READY_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_INTR_RAND_READY_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_INTR_RAND_READY_RESET 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_INTR_ACL_VIO 8:8 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_ACL_VIO_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_INTR_ACL_VIO_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_INTR_ACL_VIO_RESET 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_INTR_SECURITY_VIO 12:12 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_SECURITY_VIO_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_INTR_SECURITY_VIO_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_INTR_SECURITY_VIO_RESET 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_INTR_CMD_ERROR 16:16 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_CMD_ERROR_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_INTR_CMD_ERROR_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_INTR_CMD_ERROR_RESET 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_INTR_STEP 20:20 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_STEP_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_INTR_STEP_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_INTR_STEP_RESET 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_INTR_RNDHOLDOFF_REQUESTED 24:24 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_RNDHOLDOFF_REQUESTED_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_INTR_RNDHOLDOFF_REQUESTED_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_INTR_RNDHOLDOFF_REQUESTED_RESET 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_INTR_STALL_TIMEOUT 28:28 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_STALL_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_INTR_STALL_TIMEOUT_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_INTR_STALL_TIMEOUT_RESET 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_INTR_EN 0x0010ac84 /* RW-4R */
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#define NV_PPWR_PMU_SCP_INTR_EN__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_INTR_EN_RAND_READY 0:0 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_EN_RAND_READY_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_INTR_EN_RAND_READY_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_INTR_EN_ACL_VIO 8:8 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_EN_ACL_VIO_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_INTR_EN_ACL_VIO_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_INTR_EN_SECURITY_VIO 12:12 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_EN_SECURITY_VIO_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_INTR_EN_SECURITY_VIO_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_INTR_EN_CMD_ERROR 16:16 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_EN_CMD_ERROR_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_INTR_EN_CMD_ERROR_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_INTR_EN_STEP 20:20 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_EN_STEP_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_INTR_EN_STEP_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_INTR_EN_RNDHOLDOFF_REQUESTED 24:24 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_EN_RNDHOLDOFF_REQUESTED_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_INTR_EN_RNDHOLDOFF_REQUESTED_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_INTR_EN_STALL_TIMEOUT 28:28 /* RWIVF */
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#define NV_PPWR_PMU_SCP_INTR_EN_STALL_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_INTR_EN_STALL_TIMEOUT_ENABLED 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_ACL_VIO 0x0010ac90 /* RW-4R */
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#define NV_PPWR_PMU_SCP_ACL_VIO__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_ACL_VIO_VIOLATION 31:31 /* R-IVF */
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#define NV_PPWR_PMU_SCP_ACL_VIO_VIOLATION_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_ACL_VIO_VIOLATION_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_ACL_VIO_CHMOD_RELAX_VIO 8:8 /* RWIVF */
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#define NV_PPWR_PMU_SCP_ACL_VIO_CHMOD_RELAX_VIO_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_ACL_VIO_CHMOD_RELAX_VIO_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_ACL_VIO_CHMOD_RELAX_VIO_CLEAR 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_SCP_ACL_VIO_FETCH_VIO 4:4 /* RWIVF */
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#define NV_PPWR_PMU_SCP_ACL_VIO_FETCH_VIO_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_ACL_VIO_FETCH_VIO_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_ACL_VIO_FETCH_VIO_CLEAR 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_SCP_ACL_VIO_WR_VIO 0:0 /* RWIVF */
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#define NV_PPWR_PMU_SCP_ACL_VIO_WR_VIO_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_ACL_VIO_WR_VIO_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_ACL_VIO_WR_VIO_CLEAR 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO 0x0010ac94 /* R--4R */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_VIOLATION 31:31 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_VIOLATION_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_VIOLATION_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_PUSH_VIO_SC 26:25 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_PUSH_VIO_SC_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_PUSH_VIO 24:24 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_PUSH_VIO_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_PUSH_VIO_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_SC 22:21 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_SC_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_PUSH_CHANGE_VIO 20:20 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_PUSH_CHANGE_VIO_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_FETCH_VIO_SC 18:17 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_FETCH_VIO_SC_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_FETCH_VIO 16:16 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_FETCH_VIO_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_FETCH_VIO_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_LOAD_TRACE_VIO_SC 6:5 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_LOAD_TRACE_VIO_SC_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_LOAD_TRACE_VIO 4:4 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_LOAD_TRACE_VIO_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_LOAD_TRACE_VIO_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_LOOP_TRACE_VIO_SC 2:1 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_LOOP_TRACE_VIO_SC_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_LOOP_TRACE_VIO 0:0 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_LOOP_TRACE_VIO_NOT_PENDING 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_SECURITY_VIO_LOOP_TRACE_VIO_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR 0x0010ac98 /* RW-4R */
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#define NV_PPWR_PMU_SCP_CMD_ERROR__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_UNDEFINED 0:0 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_UNDEFINED_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_UNDEFINED_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_UNDEFINED_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SEQ_EMPTY 4:4 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SEQ_EMPTY_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SEQ_EMPTY_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SEQ_EMPTY_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SEQ_OVERFLOW 8:8 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SEQ_OVERFLOW_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SEQ_OVERFLOW_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SEQ_OVERFLOW_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING 12:12 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SEQ_INST_WHILE_LOADING_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SIG_INSECURE 16:16 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SIG_INSECURE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SIG_INSECURE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SIG_INSECURE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SIG_INVALID 20:20 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SIG_INVALID_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SIG_INVALID_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SIG_INVALID_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_CHMOD_INSECURE 24:24 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_CHMOD_INSECURE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_CHMOD_INSECURE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_CHMOD_INSECURE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SECRET_INSECURE 28:28 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SECRET_INSECURE_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SECRET_INSECURE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CMD_ERROR_SECRET_INSECURE_CLEAR 0x00000001 /* -W--C */
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#define NV_PPWR_PMU_SCP_RNDCTL0 0x0010ad00 /* RW-4R */
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#define NV_PPWR_PMU_SCP_RNDCTL0__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNDCTL0_HOLDOFF_INIT_LOWER 31:0 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL0_HOLDOFF_INIT_LOWER_INIT 0x01c9c380 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL1 0x0010ad04 /* RW-4R */
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#define NV_PPWR_PMU_SCP_RNDCTL1__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNDCTL1_HOLDOFF_INIT_UPPER 15:0 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL1_HOLDOFF_INIT_UPPER_ZERO 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL1_HOLDOFF_INTRA_MASK 31:16 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL1_HOLDOFF_INTRA_MASK_INIT 0x0000ffff /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL2 0x0010ad08 /* RW-4R */
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#define NV_PPWR_PMU_SCP_RNDCTL2__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNDCTL2_COMPRESS_CNT 15:0 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL2_COMPRESS_CNT_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL3 0x0010ad0c /* RW-4R */
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#define NV_PPWR_PMU_SCP_RNDCTL3__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A 12:12 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_RNDCTL3_TRIG_LFSR_RELOAD_A_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B 16:16 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B_INIT 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_RNDCTL3_TRIG_LFSR_RELOAD_B_TRIGGER 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_SCP_RNDCTL4 0x0010ad10 /* -W-4R */
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#define NV_PPWR_PMU_SCP_RNDCTL4__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNDCTL4_POLYNOMIAL_A 31:0 /* -WIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL4_POLYNOMIAL_A_INIT 0x80200003 /* -WI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL5 0x0010ad14 /* -W-4R */
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#define NV_PPWR_PMU_SCP_RNDCTL5__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNDCTL5_LFSR_INIT_A 31:0 /* -WIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL5_LFSR_INIT_A_INIT 0xdeadbeef /* -WI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL6 0x0010ad18 /* -W-4R */
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#define NV_PPWR_PMU_SCP_RNDCTL6__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNDCTL6_POLYNOMIAL_B 31:0 /* -WIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL6_POLYNOMIAL_B_INIT 0x80200003 /* -WI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL7 0x0010ad1c /* -W-4R */
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#define NV_PPWR_PMU_SCP_RNDCTL7__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNDCTL7_LFSR_INIT_B 31:0 /* -WIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL7_LFSR_INIT_B_INIT 0xbeefdead /* -WI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL8 0x0010ad20 /* RW-4R */
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#define NV_PPWR_PMU_SCP_RNDCTL8__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_A 15:0 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_B 31:16 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL8_AUTOCAL_LOW_TARGET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL9 0x0010ad24 /* RW-4R */
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#define NV_PPWR_PMU_SCP_RNDCTL9__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_A 15:0 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_A_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_B 31:16 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL9_AUTOCAL_HIGH_TARGET_B_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL10 0x0010ad28 /* RW-4R */
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#define NV_PPWR_PMU_SCP_RNDCTL10__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_A 15:0 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_A_INIT 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_B 31:16 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL10_AUTOCAL_SAMPLE_PERIOD_B_INIT 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL11 0x0010ad2c /* RW-4R */
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#define NV_PPWR_PMU_SCP_RNDCTL11__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_ENABLE 0:0 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_ENABLE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_ENABLE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_ENABLE_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE 1:1 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_MASTERSLAVE_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_A 2:2 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_A_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_A_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_A_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_B 3:3 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_B_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_B_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_SYNCH_RAND_B_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A 5:4 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_OSC 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_AUTOCAL 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_LFSR 0x00000002 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_A_ZERO 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B 7:6 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_OSC 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_AUTOCAL 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_LFSR 0x00000002 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_RAND_SAMPLE_SELECT_B_ZERO 0x00000003 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_A 11:8 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_A_INIT 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_B 15:12 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_STATIC_TAP_B_INIT 0x0000000f /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_MIN_AUTO_TAP 19:16 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL11_MIN_AUTO_TAP_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_HOLDOFF_DELAY 23:20 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_HOLDOFF_DELAY_INIT 0x00000001 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_ASYNCH_HOLD_DELAY 30:24 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_ASYNCH_HOLD_DELAY_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_SAFE_MODE 31:31 /* RWIUF */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_SAFE_MODE_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_RNDCTL11_AUTOCAL_SAFE_MODE_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_CTL_P2PRX 0x0010ad30 /* RW-4R */
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#define NV_PPWR_PMU_SCP_CTL_P2PRX__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_CTL_P2PRX_SFK_FALLBACK_MODE 0:0 /* R--VF */
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#define NV_PPWR_PMU_SCP_CTL_P2PRX_SFK_FALLBACK_MODE_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL_P2PRX_SFK_FALLBACK_MODE_FALSE 0x00000000 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD 2:2 /* RWIVF */
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#define NV_PPWR_PMU_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_IDLE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_PENDING 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_CTL_P2PRX_SFK_REQUEST_RELOAD_TASK 0x00000001 /* -W--T */
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#define NV_PPWR_PMU_SCP_CTL_P2PRX_SFK_LOADED 3:3 /* R-IVF */
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#define NV_PPWR_PMU_SCP_CTL_P2PRX_SFK_LOADED_FALSE 0x00000000 /* R-I-V */
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#define NV_PPWR_PMU_SCP_CTL_P2PRX_SFK_LOADED_TRUE 0x00000001 /* R---V */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG0 0x0010ad40 /* R--4R */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG0__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INIT 15:0 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INIT_INIT 0x00000020 /* R-I-V */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INTRA 31:16 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG0_RSEED_HOLDOFF_INTRA_INIT 0x0000000f /* R-I-V */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG1 0x0010ad44 /* R--4R */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG1__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG1_RSEED_TMOUT_MAX 31:0 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG1_RSEED_TMOUT_MAX_INIT 0x00000fff /* R-I-V */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG2 0x0010ad48 /* R--4R */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG2__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG2_PRNG_RESEED_PERIOD 31:0 /* R-IVF */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_HWCFG2_PRNG_RESEED_PERIOD_INIT 0x7fffffff /* R-I-V */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_STAT0 0x0010ad4c /* R--4R */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_STAT0__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_STAT0_RSEED_TMOUT_CNT 31:0 /* R--VF */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_STAT1 0x0010ad50 /* R--4R */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_STAT1__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_SCP /* */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_STAT1_RSEED_BIT_CNT 5:0 /* R--VF */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_STAT1_RSEED_VALID 8:8 /* R--VF */
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#define NV_PPWR_PMU_SCP_SCC_DEBUG_STAT1_RSEED_TMOUT 9:9 /* R--VF */
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#define NV_PPWR_PMU_SCP_PUBKEYC 0x0010ad60 /* RW-4R */
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#define NV_PPWR_PMU_SCP_PUBKEYC__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_KEY /* */
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#define NV_PPWR_PMU_SCP_PUBKEYC_RSA1_N_OFFS 0x00000000 /* */
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#define NV_PPWR_PMU_SCP_PUBKEYC_RSA1_N_SIZE 0x00000180 /* */
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#define NV_PPWR_PMU_SCP_PUBKEYC_RSA1_E_OFFS 0x00000180 /* */
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#define NV_PPWR_PMU_SCP_PUBKEYC_RSA1_E_SIZE 0x00000020 /* */
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#define NV_PPWR_PMU_SCP_PUBKEYC_ECC1_X_OFFS 0x000001a0 /* */
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#define NV_PPWR_PMU_SCP_PUBKEYC_ECC1_X_SIZE 0x00000020 /* */
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#define NV_PPWR_PMU_SCP_PUBKEYC_ECC1_Y_OFFS 0x000001c0 /* */
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#define NV_PPWR_PMU_SCP_PUBKEYC_ECC1_Y_SIZE 0x00000020 /* */
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#define NV_PPWR_PMU_SCP_PUBKEYC_OFFS 9:2 /* RWIVF */
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#define NV_PPWR_PMU_SCP_PUBKEYC_OFFS_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_PUBKEYC_AINCR 31:31 /* RWIVF */
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#define NV_PPWR_PMU_SCP_PUBKEYC_AINCR_INIT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_PUBKEYC_AINCR_TRUE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_PUBKEYC_AINCR_FALSE 0x00000000 /* RW--V */
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#define NV_PPWR_PMU_SCP_PUBKEYD 0x0010ad64 /* R--4R */
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#define NV_PPWR_PMU_SCP_PUBKEYD__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_KEY /* */
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#define NV_PPWR_PMU_SCP_PUBKEYD_DATA 31:0 /* R--VF */
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#define NV_PPWR_PMU_SCP_PK_ADDR 0x0010ad70 /* RWI4R */
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#define NV_PPWR_PMU_SCP_PK_ADDR__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_BROM /* */
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#define NV_PPWR_PMU_SCP_PK_ADDR_OFFSET 11:0 /* RWIVF */
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#define NV_PPWR_PMU_SCP_PK_ADDR_OFFSET_DEFT 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_PK_ADDR_AINCR 31:31 /* RWIVF */
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#define NV_PPWR_PMU_SCP_PK_ADDR_AINCR_ENABLE 0x00000001 /* RW--V */
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#define NV_PPWR_PMU_SCP_PK_ADDR_AINCR_DISABLE 0x00000000 /* RWI-V */
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#define NV_PPWR_PMU_SCP_PK_DATA 0x0010ad74 /* R--4R */
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#define NV_PPWR_PMU_SCP_PK_DATA__DEVICE_MAP NV_PPWR_PMU_DEVICE_MAP_GROUP_BROM /* */
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#define NV_PPWR_PMU_SCP_PK_DATA_VAL 31:0 /* R--VF */
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#define NV_PPWR_PMU_PG_ENG_NAMEMAP /* ----G */
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#define NV_PPWR_PMU_PG_ENG_NAMEMAP_INDEX 3:0 /* RW-VF */
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#define NV_PPWR_PMU_PG_ENG_NAMEMAP_INDEX_GR 0x00000000 /* R---V */
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#define NV_PPWR_PMU_PG_ENG_NAMEMAP_INDEX_VD 0x00000001 /* R---V */
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#define NV_PPWR_PMU_PG_ENG_NAMEMAP_INDEX_MSPG 0x00000004 /* R---V */
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#define NV_PPWR_PMU_PG_ENG_NAMEMAP_INDEX_DI 0x00000002 /* R---V */
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#define NV_PPWR_FALCON_EXTERRSTAT_STAT_SUCCEED 0x00000000 /* ----V */
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#define NV_PPWR_FALCON_EXTERRSTAT_STAT_FALCON_TOUT 0x00000001 /* ----V */
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#define NV_PPWR_FALCON_EXTERRSTAT_STAT_HOST_TOUT 0x00000002 /* ----V */
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#define NV_PPWR_FALCON_EXTERRSTAT_STAT_FECS_TOUT 0x00000003 /* ----V */
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#define NV_PPWR_FALCON_EXTERRSTAT_STAT_HOST_ERROR 0x00000004 /* ----V */
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#define NV_PPWR_FALCON_EXTERRSTAT_STAT_FECS_ERROR 0x00000005 /* ----V */
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#define NV_PPWR_FALCON_EMEM_APERTURE_OFFSET 0x10000000 /* ----V */
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#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY_GR_ELPG 1:1 /* ----F */
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#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY_VD_ELPG 2:2 /* ----F */
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#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY_FBIF 3:3 /* ----F */
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#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY_CSBREG 4:4 /* ----F */
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#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY_MS_ELPG 5:5 /* ----F */
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#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY_BAR0MASTER 6:6 /* ----F */
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#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY_SCP 7:7 /* ----F */
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#define NV_PPWR_FALCON_IDLESTATE_EXT_BUSY_TIE0 15:8 /* ----F */
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#define NV_PPWR_FALCON_FHSTATE_EXT_HALTED_GR_ELPG 1:1 /* ----F */
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#define NV_PPWR_FALCON_FHSTATE_EXT_HALTED_VD_ELPG 2:2 /* ----F */
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#define NV_PPWR_FALCON_FHSTATE_EXT_HALTED_FBIF 3:3 /* ----F */
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#define NV_PPWR_FALCON_FHSTATE_EXT_HALTED_CSBREG 4:4 /* ----F */
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#define NV_PPWR_FALCON_FHSTATE_EXT_HALTED_MS_ELPG 5:5 /* ----F */
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#define NV_PPWR_FALCON_FHSTATE_EXT_HALTED_BAR0MASTER 6:6 /* ----F */
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#define NV_PPWR_FALCON_FHSTATE_EXT_HALTED_TIE1 15:7 /* ----F */
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#define NV_PPWR_PMU_IDLE_STATUS_VD 6:4 /* ----F */
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#define NV_PPWR_PMU_IDLE_STATUS_FB 11:7 /* ----F */
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#define NV_PPWR_PMU_IDLE_STATUS_AZA 15:13 /* ----F */
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#define NV_PPWR_PMU_IDLE_STATUS_CE 21:19 /* ----F */
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#define NV_PPWR_PMU_IDLE_STATUS_1_MS 4:2 /* ----F */
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#define NV_PPWR_PMU_IDLE_STATUS_ENGINE 31:0 /* ----F */
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#define NV_PPWR_PMU_IDLE_STATUS_ENGINE_BUSY 0x00000000 /* ----V */
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#define NV_PPWR_PMU_IDLE_STATUS_ENGINE_IDLE 0xffffffff /* ----V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_ENGINE 31:0 /* ----F */
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#define NV_PPWR_PMU_IDLE_STATUS_1_ENGINE_BUSY 0x00000000 /* ----V */
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#define NV_PPWR_PMU_IDLE_STATUS_1_ENGINE_IDLE 0xffffffff /* ----V */
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#define NV_PPWR_PMU_HISTOGRAM_BINS_IDX(histogramIdx,regIdx) (0x000008e0+(regIdx)*16+(histogramIdx)*4) /* */
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#define NV_PPWR_PMU_HISTOGRAM_BINS_IDX__SIZE_1 4 /* */
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#define NV_PPWR_PMU_HISTOGRAM_BINS_IDX__SIZE_2 8 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_ENG_ST(i) (4*(i)):(4*(i)) /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_ENG_ST__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_ENG_BUSY_SET(i) (1+4*(i)):(1+4*(i)) /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_ENG_BUSY_SET__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_ENG_BUSY_CLR(i) (2+4*(i)):(2+4*(i)) /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_ENG_BUSY_CLR__SIZE_1 5 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_ENG_ST_IDLE 0 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_ENG_ST_BUSY 1 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_ENG_BUSY_SET_TRIGGER 1 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_ENG_BUSY_CLR_TRIGGER 1 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_ENG_BUSY_SET_INIT 0 /* */
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#define NV_PPWR_PMU_PG_SW_CLIENT_ENG_BUSY_CLR_INIT 0 /* */
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#define NV_PPWR_PMU_BAR0_EXT_STALL_ON_FECS_FAST_PATH 26:26 /* */
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#define NV_PPWR_PMU_BAR0_EXT_STALL_ON_FECS_FAST_PATH_NO 0 /* */
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#define NV_PPWR_PMU_BAR0_EXT_STALL_ON_FECS_FAST_PATH_YES 1 /* */
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#define NV_PPWR_PMU_BAR0_EXT_USE_FECS_FAST_PATH 27:27 /* */
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#define NV_PPWR_PMU_BAR0_EXT_USE_FECS_FAST_PATH_NO 0 /* */
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#define NV_PPWR_PMU_BAR0_EXT_USE_FECS_FAST_PATH_YES 1 /* */
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#define NV_PPWR_PMU_BAR0_EXT_USE_EMEM_APERTURE 28:28 /* */
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#define NV_PPWR_PMU_BAR0_EXT_USE_EMEM_APERTURE_NO 0 /* */
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#define NV_PPWR_PMU_BAR0_EXT_USE_EMEM_APERTURE_YES 1 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_ZONE_DELAY 3:0 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_ZONE_DELAY__WIDTH 4 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_FAST_MODE 4:4 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_FAST_MODE__WIDTH 1 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_FAST_MODE_EN 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_FAST_MODE_DIS 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_CLAMP_DELAY 13:8 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_LOGIC_STAGGER_CONFIG_CLAMP_DELAY__WIDTH 6 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_ZONE_DELAY 3:0 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_ZONE_DELAY__WIDTH 4 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_FAST_MODE 4:4 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_FAST_MODE__WIDTH 1 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_FAST_MODE_EN 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_FAST_MODE_DIS 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_RET_EN_DELAY 13:8 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_RAM_STAGGER_CONFIG_RET_EN_DELAY__WIDTH 6 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_GROUP_TOP_ORDER_GR_LOGIC 5:0 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_GROUP_TOP_ORDER_GR_RAM 13:8 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_GROUP_TOP_ORDER_MS_RAM 21:16 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_GROUP_TOP_ORDER_DI_RAM 28:24 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_INDEX 5:0 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_INDEX_MIN 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_READINCR 8:8 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_READINCR_DISABLED 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_READINCR_ENABLED 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_WRITEINCR 9:9 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_WRITEINCR_DISABLED 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_INDEX_WRITEINCR_ENABLED 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_ORDER 5:0 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_ZONE_ORDER_SEL 9:8 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_ZONE_ORDER_SEL_ASCENDING 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_ZONE_ORDER_SEL_DESCENDING 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_ZONE_ORDER_SEL_USER_DEFINE 0x00000002 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_EN 31:31 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_LOGIC_PARTITION_EN_INIT 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX 5:0 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_INDEX_MIN 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR 8:8 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_DISABLED 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_READINCR_ENABLED 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR 9:9 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_DISABLED 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_INDEX_WRITEINCR_ENABLED 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_ORDER 5:0 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL 9:8 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE 0x00000002 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_EN 31:31 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_GR_RAM_PARTITION_EN_INIT 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX 5:0 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_INDEX_MIN 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR 8:8 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_DISABLED 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_READINCR_ENABLED 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR 9:9 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_DISABLED 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_INDEX_WRITEINCR_ENABLED 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL 9:8 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE 0x00000002 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_EN 31:31 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_MS_RAM_PARTITION_EN_INIT 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_INDEX 4:0 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_INDEX_MIN 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_READINCR 8:8 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_READINCR_DISABLED 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_READINCR_ENABLED 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_WRITEINCR 9:9 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_WRITEINCR_DISABLED 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_INDEX_WRITEINCR_ENABLED 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_ZONE_ORDER_SEL 9:8 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_ZONE_ORDER_SEL_ASCENDING 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_ZONE_ORDER_SEL_DESCENDING 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_ZONE_ORDER_SEL_USER_DEFINE 0x00000002 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_EN 31:31 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_POWER_CTRL_DI_RAM_PARTITION_EN_INIT 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX 2:0 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE0_INDEX_INIT 0x00000000 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX 6:4 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE1_INDEX_INIT 0x00000001 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX 10:8 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE2_INDEX_INIT 0x00000002 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX 14:12 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE3_INDEX_INIT 0x00000003 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX 18:16 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE4_INDEX_INIT 0x00000004 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX 22:20 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE5_INDEX_INIT 0x00000005 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX 26:24 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE6_INDEX_INIT 0x00000006 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX 30:28 /* */
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#define NV_PWR_UNIFIED_POWER_CONTROL_ZONE_ORDER_USER_DEFINE_ZONE7_INDEX_INIT 0x00000007 /* */
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#endif // __ga102_dev_pwr_pri_h__
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