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Ole Algoritme
2022-09-05 21:52:22 +02:00
commit 698a8f7487
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217
include/ampere/ga100/dev_boot.h Normal file
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// --------------------------------------------------------------------------------
//
#define NV_PMC 0x00000fff:0x00000000 /* RW--D */
#define NV_PMC_BOOT_0 0x00000000 /* R--4R */
#define NV_PMC_BOOT_0_ID 31:0 /* */
#define NV_PMC_BOOT_0_MINOR_REVISION 3:0 /* R--VF */
#define NV_PMC_BOOT_0_MINOR_REVISION_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_4 0x00000004 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_5 0x00000005 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_6 0x00000006 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_7 0x00000007 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_8 0x00000008 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_9 0x00000009 /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_10 0x0000000A /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_11 0x0000000B /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_12 0x0000000C /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_13 0x0000000D /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_14 0x0000000E /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_15 0x0000000F /* R---V */
#define NV_PMC_BOOT_0_MINOR_REVISION_INIT 0x00000001 /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION 7:4 /* R--VF */
#define NV_PMC_BOOT_0_MAJOR_REVISION_A 0x0000000A /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION_B 0x0000000B /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION_C 0x0000000C /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION_D 0x0000000D /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION_E 0x0000000E /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION_F 0x0000000F /* R---V */
#define NV_PMC_BOOT_0_MAJOR_REVISION_INIT 0x00000000 /* R---V */
#define NV_PMC_BOOT_0_RESERVED_0 11:8 /* */
#define NV_PMC_BOOT_0_IMPLEMENTATION 23:20 /* R--VF */
#define NV_PMC_BOOT_0_IMPLEMENTATION_0 0x00000000 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_4 0x00000004 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_5 0x00000005 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_6 0x00000006 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_7 0x00000007 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_8 0x00000008 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_9 0x00000009 /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_A 0x0000000A /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_B 0x0000000B /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_C 0x0000000C /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_D 0x0000000D /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_E 0x0000000E /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_F 0x0000000F /* R---V */
#define NV_PMC_BOOT_0_IMPLEMENTATION_INIT 0x00000000 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE 28:24 /* R--VF */
#define NV_PMC_BOOT_0_ARCHITECTURE_GF100 0x0000000C /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GF110 0x0000000D /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GK100 0x0000000E /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GK110 0x0000000F /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GK200 0x00000010 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GM000 0x00000011 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GM100 0x00000011 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GM200 0x00000012 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GP100 0x00000013 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GV100 0x00000014 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GV110 0x00000015 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_TU100 0x00000016 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_TU110 0x00000016 /* R---V */
#define NV_PMC_BOOT_0_ARCHITECTURE_GA100 0x00000017 /* R---V */
#define NV_PMC_BOOT_1 0x00000004 /* C--4R */
#define NV_PMC_BOOT_1_VGPU8 8:8 /* C--VF */
#define NV_PMC_BOOT_1_VGPU8_REAL 0x00000000 /* C---V */
#define NV_PMC_BOOT_1_VGPU8_VIRTUAL 0x00000001 /* ----V */
#define NV_PMC_BOOT_1_VGPU16 16:16 /* */
#define NV_PMC_BOOT_1_VGPU16_REAL 0x00000000 /* */
#define NV_PMC_BOOT_1_VGPU16_VIRTUAL 0x00000001 /* */
#define NV_PMC_BOOT_1_VGPU 17:16 /* C--VF */
#define NV_PMC_BOOT_1_VGPU_REAL 0x00000000 /* C---V */
#define NV_PMC_BOOT_2 0x00000008 /* R--4R */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION 3:0 /* R-XVF */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_0 0x00000000 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_4 0x00000004 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_5 0x00000005 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_6 0x00000006 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_7 0x00000007 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_8 0x00000008 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_9 0x00000009 /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_A 0x0000000A /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_B 0x0000000B /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_C 0x0000000C /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_D 0x0000000D /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_E 0x0000000E /* R---V */
#define NV_PMC_BOOT_2_MINOR_EXTENDED_REVISION_F 0x0000000F /* R---V */
#define NV_PMC_BOOT_2_FAB_ID 7:4 /* R-XVF */
#define NV_PMC_BOOT_2_FAB_ID_0 0x00000000 /* R---V */
#define NV_PMC_BOOT_2_FAB_ID_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_2_FAB_ID_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_2_FAB_ID_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_42 0x00000A00 /* R--4R */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION 11:8 /* R-XVF */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_0 0x00000000 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_4 0x00000004 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_5 0x00000005 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_6 0x00000006 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_7 0x00000007 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_8 0x00000008 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_9 0x00000009 /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_A 0x0000000A /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_B 0x0000000B /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_C 0x0000000C /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_D 0x0000000D /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_E 0x0000000E /* R---V */
#define NV_PMC_BOOT_42_MINOR_EXTENDED_REVISION_F 0x0000000F /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION 15:12 /* R-XVF */
#define NV_PMC_BOOT_42_MINOR_REVISION_1 0x00000001 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_2 0x00000002 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_3 0x00000003 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_4 0x00000004 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_5 0x00000005 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_6 0x00000006 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_7 0x00000007 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_8 0x00000008 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_9 0x00000009 /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_10 0x0000000A /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_11 0x0000000B /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_12 0x0000000C /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_13 0x0000000D /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_14 0x0000000E /* R---V */
#define NV_PMC_BOOT_42_MINOR_REVISION_15 0x0000000F /* R---V */
#define NV_PMC_BOOT_42_MAJOR_REVISION 19:16 /* R-XVF */
#define NV_PMC_BOOT_42_MAJOR_REVISION_A 0x0000000A /* R---V */
#define NV_PMC_BOOT_42_MAJOR_REVISION_B 0x0000000B /* R---V */
#define NV_PMC_BOOT_42_MAJOR_REVISION_C 0x0000000C /* R---V */
#define NV_PMC_BOOT_42_MAJOR_REVISION_D 0x0000000D /* R---V */
#define NV_PMC_BOOT_42_MAJOR_REVISION_E 0x0000000E /* R---V */
#define NV_PMC_BOOT_42_MAJOR_REVISION_F 0x0000000F /* R---V */
#define NV_PMC_BOOT_42_IMPLEMENTATION 23:20 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_0 0x00000000 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_1 0x00000001 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_2 0x00000002 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_3 0x00000003 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_4 0x00000004 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_5 0x00000005 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_6 0x00000006 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_7 0x00000007 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_8 0x00000008 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_9 0x00000009 /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_A 0x0000000A /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_B 0x0000000B /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_C 0x0000000C /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_D 0x0000000D /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_E 0x0000000E /* */
#define NV_PMC_BOOT_42_IMPLEMENTATION_F 0x0000000F /* */
#define NV_PMC_BOOT_42_ARCHITECTURE 28:24 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GP100 0x00000013 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GV100 0x00000014 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GV110 0x00000015 /* */
#define NV_PMC_BOOT_42_ARCHITECTURE_GA100 0x00000017 /* */
#define NV_PMC_BOOT_42_CHIP_ID 28:20 /* R-XVF */
#define NV_PMC_BOOT_42_CHIP_ID_GP000 0x00000131 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP100 0x00000130 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP102 0x00000132 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP104 0x00000134 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP104V 0x00000139 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP106 0x00000136 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP107 0x00000137 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP108 0x00000138 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GP108V 0x0000013A /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GV100 0x00000140 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GV10B 0x0000014B /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU100 0x00000160 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU102 0x00000162 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU104 0x00000164 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU105 0x00000165 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU106 0x00000166 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU107 0x00000167 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU117 0x00000167 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_TU116 0x00000168 /* R---V */
#define NV_PMC_BOOT_42_CHIP_ID_GA100 0x00000170 /* R---V */
#define NV_PMC_ENABLE 0x00000200 /* RW-4R */
#define NV_PMC_ENABLE_DEVICE(i) (i):(i) /* */
#define NV_PMC_ENABLE_DEVICE__SIZE_1 32 /* */
#define NV_PMC_ENABLE_DEVICE_DISABLE 0x00000000 /* */
#define NV_PMC_ENABLE_DEVICE_ENABLE 0x00000001 /* */
#define NV_PMC_ENABLE_ZPW 26:26 /* RWIVF */
#define NV_PMC_ENABLE_ZPW_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_ZPW_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_BLG 27:27 /* */
#define NV_PMC_ENABLE_BLG_DISABLED 0x00000000 /* */
#define NV_PMC_ENABLE_BLG_ENABLED 0x00000001 /* */
#define NV_PMC_ENABLE_PERFMON 28:28 /* RWIVF */
#define NV_PMC_ENABLE_PERFMON_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_ENABLE_PERFMON_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_ENABLE_PDISP 30:30 /* RWIVF */
#define NV_PMC_ENABLE_PDISP_DISABLED 0x00000000 /* RW--V */
#define NV_PMC_ENABLE_PDISP_ENABLED 0x00000001 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE(i) (0x000000600+(i)*4) /* RW-4A */
#define NV_PMC_DEVICE_ENABLE__SIZE_1 1 /* */
#define NV_PMC_DEVICE_ENABLE__PRIV_LEVEL_MASK 0x00000084 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS 31:0 /* RWIVF */
#define NV_PMC_DEVICE_ENABLE_STATUS_DISABLE_ALL 0x00000000 /* RWI-V */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT(i) (i):(i) /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT__SIZE_1 32 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_DISABLE 0x00000000 /* */
#define NV_PMC_DEVICE_ENABLE_STATUS_BIT_ENABLE 0x00000001 /* */
#define NV_PMC_PRI_PMC_CG1 0x00000800 /* RW-4R */
#define NV_PMC_PRI_PMC_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_PMC_PRI_PMC_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PMC_PRI_PMC_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_PMC_PRI_PMC_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_PMC_PRI_PMC_CG1_SLCG 1:1 /* RWIVF */
#define NV_PMC_PRI_PMC_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_PMC_PRI_PMC_CG1_SLCG_DISABLED 0x00000001 /* RWI-V */
#define NV_PMC_PRI_PMC_CG1_SLCG__PROD 0x00000001 /* RW--V */
//
// --------------------------------------------------------------------------------

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include/ampere/ga100/dev_bus.h Normal file
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// --------------------------------------------------------------------------------
//
#define NV_MEMORY 0xFFFFFFFF:0x00000000 /* RW--D */
#define NV_IO 0xFFFFFFFF:0x00000000 /* RW--D */
#define NV_EXPROM 0x0007FFFF:0x00000000 /* R---D */
#define NV_SPACE 0x01FFFFFF:0x00000000 /* RW--D */
#define NV_RSPACE 0x00FFFFFF:0x00000000 /* RW--D */
#define NV_MSPACE 0x1FFFFFFF:0x00000000 /* RW--D */
#define NV_ISPACE 0x01FFFFFF:0x00000000 /* RW--D */
#define NV_IOBAR 0x0000007F:0x00000000 /* RW--D */
#define NV_IFB 0x00060FFF:0x00060000 /* RW--D */
#define NV_PRMIO 0x00007FFF:0x00007000 /* RW--D */
#define NV_PBUS 0x00001FFF:0x00001000 /* RW--D */
#define NV_PBUS_SW_SCRATCH(i) (0x00001400+(i)*4) /* RW-4A */
#define NV_PBUS_SW_SCRATCH__SIZE_1 64 /* */
#define NV_PBUS_SW_SCRATCH_FIELD 31:0 /* RWIVF */
#define NV_PBUS_SW_SCRATCH_FIELD_INIT 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_0 0x00001100 /* RW-4R */
#define NV_PBUS_INTR_0_PRI_FECSERR 2:2 /* RWIVF */
#define NV_PBUS_INTR_0_PRI_FECSERR_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_PRI_FECSERR_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_PRI_FECSERR_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_PRI_TIMEOUT 3:3 /* RWIVF */
#define NV_PBUS_INTR_0_PRI_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_PRI_TIMEOUT_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_PRI_TIMEOUT_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_FB_REQ_TIMEOUT 4:4 /* RWIVF */
#define NV_PBUS_INTR_0_FB_REQ_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_FB_REQ_TIMEOUT_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_FB_REQ_TIMEOUT_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT 5:5 /* RWIVF */
#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_FB_ACK_TIMEOUT_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_FB_ACK_EXTRA 6:6 /* RWIVF */
#define NV_PBUS_INTR_0_FB_ACK_EXTRA_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_FB_ACK_EXTRA_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_FB_ACK_EXTRA_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_FB_RDATA_TIMEOUT 7:7 /* RWIVF */
#define NV_PBUS_INTR_0_FB_RDATA_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_FB_RDATA_TIMEOUT_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_FB_RDATA_TIMEOUT_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_FB_RDATA_EXTRA 8:8 /* RWIVF */
#define NV_PBUS_INTR_0_FB_RDATA_EXTRA_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_FB_RDATA_EXTRA_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_FB_RDATA_EXTRA_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_SW 26:26 /* RWIVF */
#define NV_PBUS_INTR_0_SW_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_SW_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_SW_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_POSTED_DEADLOCK_TIMEOUT 27:27 /* RWIVF */
#define NV_PBUS_INTR_0_POSTED_DEADLOCK_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_POSTED_DEADLOCK_TIMEOUT_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_POSTED_DEADLOCK_TIMEOUT_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_0_ACCESS_TIMEOUT 31:31 /* RWIVF */
#define NV_PBUS_INTR_0_ACCESS_TIMEOUT_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_PBUS_INTR_0_ACCESS_TIMEOUT_PENDING 0x00000001 /* R---V */
#define NV_PBUS_INTR_0_ACCESS_TIMEOUT_RESET 0x00000001 /* -W--C */
#define NV_PBUS_INTR_EN_0 0x00001140 /* RW-4R */
#define NV_PBUS_INTR_EN_0_PRI_FECSERR 2:2 /* RWIVF */
#define NV_PBUS_INTR_EN_0_PRI_FECSERR_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_PRI_FECSERR_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT 3:3 /* RWIVF */
#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_PRI_TIMEOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_0_FB_REQ_TIMEOUT 4:4 /* RWIVF */
#define NV_PBUS_INTR_EN_0_FB_REQ_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_FB_REQ_TIMEOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_0_FB_ACK_TIMEOUT 5:5 /* RWIVF */
#define NV_PBUS_INTR_EN_0_FB_ACK_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_FB_ACK_TIMEOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_0_FB_ACK_EXTRA 6:6 /* RWIVF */
#define NV_PBUS_INTR_EN_0_FB_ACK_EXTRA_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_FB_ACK_EXTRA_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_0_FB_RDATA_TIMEOUT 7:7 /* RWIVF */
#define NV_PBUS_INTR_EN_0_FB_RDATA_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_FB_RDATA_TIMEOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_0_FB_RDATA_EXTRA 8:8 /* RWIVF */
#define NV_PBUS_INTR_EN_0_FB_RDATA_EXTRA_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_FB_RDATA_EXTRA_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_0_SW 26:26 /* RWIVF */
#define NV_PBUS_INTR_EN_0_SW_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_SW_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_0_POSTED_DEADLOCK_TIMEOUT 27:27 /* RWIVF */
#define NV_PBUS_INTR_EN_0_POSTED_DEADLOCK_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_POSTED_DEADLOCK_TIMEOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_0_ACCESS_TIMEOUT 31:31 /* RWIVF */
#define NV_PBUS_INTR_EN_0_ACCESS_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_0_ACCESS_TIMEOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_1 0x00001144 /* RW-4R */
#define NV_PBUS_INTR_EN_1_PRI_FECSERR 2:2 /* RWIVF */
#define NV_PBUS_INTR_EN_1_PRI_FECSERR_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_1_PRI_FECSERR_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_1_PRI_TIMEOUT 3:3 /* RWIVF */
#define NV_PBUS_INTR_EN_1_PRI_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_1_PRI_TIMEOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_1_FB_REQ_TIMEOUT 4:4 /* RWIVF */
#define NV_PBUS_INTR_EN_1_FB_REQ_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_1_FB_REQ_TIMEOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_1_FB_ACK_TIMEOUT 5:5 /* RWIVF */
#define NV_PBUS_INTR_EN_1_FB_ACK_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_1_FB_ACK_TIMEOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_1_FB_ACK_EXTRA 6:6 /* RWIVF */
#define NV_PBUS_INTR_EN_1_FB_ACK_EXTRA_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_1_FB_ACK_EXTRA_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_1_FB_RDATA_TIMEOUT 7:7 /* RWIVF */
#define NV_PBUS_INTR_EN_1_FB_RDATA_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_1_FB_RDATA_TIMEOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_1_FB_RDATA_EXTRA 8:8 /* RWIVF */
#define NV_PBUS_INTR_EN_1_FB_RDATA_EXTRA_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_1_FB_RDATA_EXTRA_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_1_SW 26:26 /* RWIVF */
#define NV_PBUS_INTR_EN_1_SW_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_1_SW_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_1_POSTED_DEADLOCK_TIMEOUT 27:27 /* RWIVF */
#define NV_PBUS_INTR_EN_1_POSTED_DEADLOCK_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_1_POSTED_DEADLOCK_TIMEOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_INTR_EN_1_ACCESS_TIMEOUT 31:31 /* RWIVF */
#define NV_PBUS_INTR_EN_1_ACCESS_TIMEOUT_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_INTR_EN_1_ACCESS_TIMEOUT_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_SW_INTR_0 0x00001150 /* -W-4R */
#define NV_PBUS_SW_INTR_0_SET 0:0 /* -W-VF */
#define NV_PBUS_SW_INTR_0_SET_PENDING 0x00000001 /* -W--V */
#define NV_PBUS_SW_INTR_1 0x00001154 /* RW-4R */
#define NV_PBUS_SW_INTR_1_SCRATCH 31:0 /* RWIVF */
#define NV_PBUS_SW_INTR_1_SCRATCH_DATA 0x00000000 /* RWI-V */
#define NV_PBUS_SW_INTR_2 0x00001158 /* RW-4R */
#define NV_PBUS_SW_INTR_2_SCRATCH 31:0 /* RWIVF */
#define NV_PBUS_SW_INTR_2_SCRATCH_DATA 0x00000000 /* RWI-V */
#define NV_PBUS_SW_INTR_3 0x0000115C /* RW-4R */
#define NV_PBUS_SW_INTR_3_SCRATCH 31:0 /* RWIVF */
#define NV_PBUS_SW_INTR_3_SCRATCH_FLAG 0x00000000 /* RWI-V */
#define NV_PBUS_SW_INTR_4 0x00001160 /* RW-4R */
#define NV_PBUS_SW_INTR_4_SCRATCH 31:0 /* RWIVF */
#define NV_PBUS_SW_INTR_4_SCRATCH_FLAG 0x00000000 /* RWI-V */
#define NV_PBUS_BAR0_WINDOW 0x00001700 /* RW-4R */
#define NV_PBUS_BAR0_WINDOW_BASE 23:0 /* RWIUF */
#define NV_PBUS_BAR0_WINDOW_BASE_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR0_WINDOW_TARGET 25:24 /* RWIUF */
#define NV_PBUS_BAR0_WINDOW_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR0_WINDOW_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR0_WINDOW_BASE_SHIFT 16 /* */
#define NV_PBUS_BAR1_BLOCK 0x00001704 /* RW-4R */
#define NV_PBUS_BAR1_BLOCK__FMOD_NO_STORAGE 1 /* */
#define NV_PBUS_BAR1_BLOCK_MAP 29:0 /* */
#define NV_PBUS_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR1_BLOCK_PTR_SHIFT 12 /* */
#define NV_PBUS_BIND_STATUS 0x00001710 /* R--4R */
#define NV_PBUS_BIND_STATUS__FMOD_NO_STORAGE 1 /* */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_PBUS_BAR2_BLOCK 0x00001714 /* RW-4R */
#define NV_PBUS_BAR2_BLOCK__FMOD_NO_STORAGE 1 /* */
#define NV_PBUS_BAR2_BLOCK_MAP 29:0 /* */
#define NV_PBUS_BAR2_BLOCK_PTR 27:0 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_MODE 31:31 /* RWIUF */
#define NV_PBUS_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_PBUS_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_PBUS_BAR2_BLOCK_PTR_SHIFT 12 /* */
#define NV_PBUS_BAR2_BLOCK_RESERVED 30:30 /* */
#define NV_PBUS_BAR2_BLOCK_RESERVED_DEFAULT 0x00000001 /* */
#define NV_PBUS_EXT_CG 0x00001C00 /* RW-4R */
#define NV_PBUS_EXT_CG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
#define NV_PBUS_EXT_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
#define NV_PBUS_EXT_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */
#define NV_PBUS_EXT_CG_IDLE_CG_EN 6:6 /* RWIVF */
#define NV_PBUS_EXT_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_EXT_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_EXT_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_PBUS_EXT_CG_STALL_CG_EN 14:14 /* RWIVF */
#define NV_PBUS_EXT_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_EXT_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_EXT_CG_STALL_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
#define NV_PBUS_EXT_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWI-V */
#define NV_PBUS_EXT_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1 0x00001C04 /* RW-4R */
#define NV_PBUS_EXT_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_PBUS_EXT_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PBUS_EXT_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_PBUS_EXT_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG 9:1 /* */
#define NV_PBUS_EXT_CG1_SLCG_ENABLED 0x00000000 /* */
#define NV_PBUS_EXT_CG1_SLCG_DISABLED 0x000001ff /* */
#define NV_PBUS_EXT_CG1_SLCG__PROD 0x00000000 /* */
#define NV_PBUS_EXT_CG1_SLCG_BL 1:1 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_BL_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_BL_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_BL__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_C11 2:2 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_C11_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_C11_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_C11__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_MAP 3:3 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_MAP_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_MAP_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_MAP__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_PRI 4:4 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_PRI_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_PRI_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_PRI__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_UNROLL 5:5 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_UNROLL_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_UNROLL_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_UNROLL__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_ASMBL 6:6 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_ASMBL_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_ASMBL_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_ASMBL__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_ROLL 7:7 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_ROLL_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_ROLL_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_ROLL__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_IFR 8:8 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_IFR_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_IFR_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_IFR__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_PM 9:9 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_PM_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_PM_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_PM__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_CPUQ_RSP 10:10 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_CPUQ_RSP_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_CPUQ_RSP_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_CPUQ_RSP__PROD 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_PRIV_RING 11:11 /* RWIVF */
#define NV_PBUS_EXT_CG1_SLCG_PRIV_RING_ENABLED 0x00000000 /* RW--V */
#define NV_PBUS_EXT_CG1_SLCG_PRIV_RING_DISABLED 0x00000001 /* RWI-V */
#define NV_PBUS_EXT_CG1_SLCG_PRIV_RING__PROD 0x00000000 /* RW--V */
#define NV_PBUS_IFR_STATUS1 0x00001724 /* R--4R */
#define NV_PBUS_IFR_STATUS1_BAR0ADDR 23:0 /* R-IVF */
#define NV_PBUS_IFR_STATUS1_BAR0ADDR_INIT 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_STATUS1_IFF_DONE 27:27 /* R-IVF */
#define NV_PBUS_IFR_STATUS1_IFF_DONE_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_STATUS1_IFF_DONE_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_STATUS1_IDLE 29:29 /* R-IVF */
#define NV_PBUS_IFR_STATUS1_IDLE_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_STATUS1_IDLE_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_STATUS1_LASTEXEC 30:30 /* R-IVF */
#define NV_PBUS_IFR_STATUS1_LASTEXEC_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_STATUS1_LASTEXEC_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_STATUS1_READINRMW 31:31 /* R-IVF */
#define NV_PBUS_IFR_STATUS1_READINRMW_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_STATUS1_READINRMW_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_ERROR 0x00001728 /* R--4R */
#define NV_PBUS_IFR_ERROR_BADSIG 0:0 /* R-IVF */
#define NV_PBUS_IFR_ERROR_BADSIG_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_ERROR_BADSIG_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_ERROR_FAILSAFE_TIMEOUT 1:1 /* R-IVF */
#define NV_PBUS_IFR_ERROR_FAILSAFE_TIMEOUT_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_ERROR_FAILSAFE_TIMEOUT_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_ERROR_BADPARITY 8:8 /* R-IVF */
#define NV_PBUS_IFR_ERROR_BADPARITY_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_ERROR_BADPARITY_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_ERROR_BADROMLEN 12:12 /* R-IVF */
#define NV_PBUS_IFR_ERROR_BADROMLEN_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_ERROR_BADROMLEN_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_ERROR_BADCHECKSUM 16:16 /* R-IVF */
#define NV_PBUS_IFR_ERROR_BADCHECKSUM_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_ERROR_BADCHECKSUM_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_ERROR_BADFORMAT 20:20 /* R-IVF */
#define NV_PBUS_IFR_ERROR_BADFORMAT_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_ERROR_BADFORMAT_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_ERROR_PRI_ERROR 21:21 /* R-IVF */
#define NV_PBUS_IFR_ERROR_PRI_ERROR_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_ERROR_PRI_ERROR_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_ERROR_IFF_RESENSE_TIMEOUT 23:23 /* R-IVF */
#define NV_PBUS_IFR_ERROR_IFF_RESENSE_TIMEOUT_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_ERROR_IFF_RESENSE_TIMEOUT_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_ERROR_IFF_BADFIELDSPEC 24:24 /* R-IVF */
#define NV_PBUS_IFR_ERROR_IFF_BADFIELDSPEC_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_ERROR_IFF_BADFIELDSPEC_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_ERROR_IFF_BADSPACEID 25:25 /* R-IVF */
#define NV_PBUS_IFR_ERROR_IFF_BADSPACEID_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_ERROR_IFF_BADSPACEID_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_ERROR_IFF_BADFUSELEN 26:26 /* R-IVF */
#define NV_PBUS_IFR_ERROR_IFF_BADFUSELEN_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_ERROR_IFF_BADFUSELEN_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_ERROR_IFF_BADCMDOP 27:27 /* R-IVF */
#define NV_PBUS_IFR_ERROR_IFF_BADCMDOP_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_ERROR_IFF_BADCMDOP_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_IFR_ERROR_IFF_PRI_ERROR 29:29 /* R-IVF */
#define NV_PBUS_IFR_ERROR_IFF_PRI_ERROR_TRUE 0x00000001 /* R---V */
#define NV_PBUS_IFR_ERROR_IFF_PRI_ERROR_FALSE 0x00000000 /* R-I-V */
#define NV_PBUS_LVDS_USER 0x00001800 /* RW-4R */
#define NV_PBUS_LVDS_USER_VALUE 3:0 /* RWIVF */
#define NV_PBUS_LVDS_USER_VALUE_INIT 0x0000000F /* RWI-V */
//
// --------------------------------------------------------------------------------

100
include/ampere/ga100/dev_ctrl.ref.h Normal file
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@@ -0,0 +1,100 @@
// --------------------------------------------------------------------------------
//
#define NV_CTRL 0x00b7ffff:0x00b60000 /* RW--D */
#define NV_CTRL_CPU_INTR_TOP(i) (0x00B73400+(i)*4) /* R--4A */
#define NV_CTRL_CPU_INTR_TOP__SIZE_1 64 /* */
#define NV_CTRL_CPU_INTR_TOP_VALUE 31:0 /* R--VF */
#define NV_CTRL_CPU_INTR_TOP_EN_SET(i) (0x00B73800+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_TOP_EN_SET__SIZE_1 64 /* */
#define NV_CTRL_CPU_INTR_TOP_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_TOP_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR(i) (0x00B73C00+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR__SIZE_1 64 /* */
#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_TOP_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_CPU_INTR_LEAF(i) (0x00B74000+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_LEAF__SIZE_1 1024 /* */
#define NV_CTRL_CPU_INTR_LEAF_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_CPU_INTR_LEAF_ARRAY_SIZE_PER_FN 16 /* */
#define NV_CTRL_CPU_INTR_LEAF_EN_SET(i) (0x00B78000+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_LEAF_EN_SET__SIZE_1 1024 /* */
#define NV_CTRL_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR(i) (0x00B7C000+(i)*4) /* RW-4A */
#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 1024 /* */
#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_CTRL_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_CTRL_LEGACY_ENGINE_STALL_INTR_BASE_VECTORID 0xB66880 /* C--4R */
#define NV_CTRL_LEGACY_ENGINE_STALL_INTR_BASE_VECTORID_VECTOR 11:0 /* C--UF */
#define NV_CTRL_LEGACY_ENGINE_STALL_INTR_BASE_VECTORID_VECTOR_INIT 192 /* C---V */
#define NV_CTRL_LEGACY_ENGINE_NONSTALL_INTR_BASE_VECTORID 0xB66884 /* C--4R */
#define NV_CTRL_LEGACY_ENGINE_NONSTALL_INTR_BASE_VECTORID_VECTOR 11:0 /* C--UF */
#define NV_CTRL_LEGACY_ENGINE_NONSTALL_INTR_BASE_VECTORID_VECTOR_INIT 0 /* C---V */
#define NV_CTRL_USERMODE_CFG0 0xB668A8 /* C--4R */
#define NV_CTRL_USERMODE_CFG0_USERMODE_CLASS_ID 15:0 /* C--UF */
#define NV_CTRL_USERMODE_CFG0_USERMODE_CLASS_ID_VALUE 50529 /* C---V */
#define NV_CTRL_MAILBOX_SCRATCH(i) (0x00B60000+(i)*4) /* RW-4A */
#define NV_CTRL_MAILBOX_SCRATCH__SIZE_1 1024 /* */
#define NV_CTRL_MAILBOX_SCRATCH_DATA 31:0 /* RWXVF */
#define NV_CTRL_DOORBELL(i) (0x00B64000+(i)*8) /* */
#define NV_CTRL_DOORBELL__SIZE_1 64 /* */
#define NV_CTRL_DOORBELL_HANDLE 31:0 /* */
#define NV_CTRL_DOORBELL_VECTOR 11:0 /* */
#define NV_CTRL_DOORBELL_RSVD 15:12 /* */
#define NV_CTRL_DOORBELL_RUNLIST_ID 22:16 /* */
#define NV_CTRL_DOORBELL_RUNLIST_ID_INVALID_RUNLIST 0x7F /* */
#define NV_CTRL_DOORBELL_RUNLIST_DOORBELL 22:22 /* */
#define NV_CTRL_DOORBELL_RUNLIST_DOORBELL_DISABLE 0x1 /* */
#define NV_CTRL_DOORBELL_RUNLIST_DOORBELL_ENABLE 0x0 /* */
#define NV_CTRL_DOORBELL_RSVD2 31:23 /* */
#define NV_CTRL_DOORBELL_GSP_DOORBELL 31:31 /* */
#define NV_CTRL_DOORBELL_GSP_DOORBELL_DISABLE 0x1 /* */
#define NV_CTRL_DOORBELL_GSP_DOORBELL_ENABLE 0x0 /* */
#define NV_CTRL_PRIV_DOORBELL(i) (0x00B64800+(i)*8) /* */
#define NV_CTRL_PRIV_DOORBELL__SIZE_1 64 /* */
#define NV_CTRL_PRIV_DOORBELL_HANDLE 31:0 /* */
#define NV_CTRL_PRIV_DOORBELL_VECTOR 11:0 /* */
#define NV_CTRL_PRIV_DOORBELL_RSVD 30:12 /* */
#define NV_CTRL_PRIV_DOORBELL_CPU_NOTIFICATION 31:31 /* */
#define NV_CTRL_PRIV_DOORBELL_CPU_NOTIFICATION_TRUE 1 /* */
#define NV_CTRL_PRIV_DOORBELL_CPU_NOTIFICATION_FALSE 0 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF(i) (0x00B66800+(i)*4) /* RW-4A */
#define NV_CTRL_VIRTUAL_INTR_LEAF__SIZE_1 2 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_PENDING 31:0 /* RWIVF */
#define NV_CTRL_VIRTUAL_INTR_LEAF_PENDING_INIT 0 /* RWI-V */
#define NV_CTRL_VIRTUAL_INTR_LEAF_PENDING_INTR 1 /* R---V */
#define NV_CTRL_VIRTUAL_INTR_LEAF_PENDING_CLEAR 1 /* -W--V */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET(i) (0x00B66820+(i)*4) /* RW-4A */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET__SIZE_1 2 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VALUE_INIT 0 /* RWI-V */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VECTOR(i) (i) /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VECTOR_ENABLE 1 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VECTOR_ENABLED 1 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_SET_VECTOR_DISABLED 0 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR(i) (0x00B66840+(i)*4) /* RW-4A */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR__SIZE_1 2 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR_VALUE_INIT 0 /* RWI-V */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR_VECTOR(i) (i) /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR_VECTOR_DISABLE 1 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR_VECTOR_ENABLED 1 /* */
#define NV_CTRL_VIRTUAL_INTR_LEAF_EN_CLEAR_VECTOR_DISABLED 0 /* */
#define NV_CTRL_VIRTUAL_INTR_RETRIGGER 0x00B66870 /* -W-4R */
#define NV_CTRL_VIRTUAL_INTR_RETRIGGER_FIELD 0:0 /* -WXVF */
#define NV_CTRL_VIRTUAL_INTR_RETRIGGER_FIELD_RETRIGGER 1 /* -W--V */
#define NV_CTRL_VIRTUAL_INTR_VECTORID 0x00B66874 /* C--4R */
#define NV_CTRL_VIRTUAL_INTR_VECTORID_VALUE 11:0 /* C--VF */
#define NV_CTRL_VIRTUAL_INTR_VECTORID_VALUE_CONSTANT 130 /* C---V */
#define NV_CTRL_CPU_INTR_LEAF_TRIGGER(i) (0x00B66C00+(i)*4) /* -W-4A */
#define NV_CTRL_CPU_INTR_LEAF_TRIGGER__SIZE_1 64 /* */
#define NV_CTRL_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -WXVF */
#define NV_CTRL_CPU_DOORBELL_VECTORID 0x00B6687C /* C--4R */
#define NV_CTRL_CPU_DOORBELL_VECTORID_VALUE 11:0 /* C--VF */
#define NV_CTRL_CPU_DOORBELL_VECTORID_VALUE_CONSTANT 129 /* C---V */
#define NV_CTRL_SW_INTR_NOSTALL_VECTORID 0x00B6688C /* C--4R */
#define NV_CTRL_SW_INTR_NOSTALL_VECTORID_VALUE 11:0 /* C--VF */
#define NV_CTRL_SW_INTR_NOSTALL_VECTORID_VALUE_CONSTANT 31 /* C---V */
//
// --------------------------------------------------------------------------------

521
include/ampere/ga100/dev_func.ref.h Normal file
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@@ -0,0 +1,521 @@
// --------------------------------------------------------------------------------
//
#define NV_FUNC_PRIV_JUMBO 0x0042FFFF:0x00400000 /* RW--D */
#define NV_FUNC_PRIV 0x0002FFFF:0x00000000 /* RW--D */
#define NV_FUNC_FULL_PHYS_OFFSET 0x00BBFFFF:0x00B80000 /* RW--D */
#define NV_FUNC 0x0003FFFF:0x00030000 /* RW--D */
#define NV_FUNC_PRIV_L2_SYSMEM_INVALIDATE 0x00000F00 /* RW-4R */
#define NV_FUNC_PRIV_L2_SYSMEM_INVALIDATE_PENDING 0:0 /* RWIUF */
#define NV_FUNC_PRIV_L2_SYSMEM_INVALIDATE_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_L2_SYSMEM_INVALIDATE_PENDING_BUSY 0x00000001 /* R---V */
#define NV_FUNC_PRIV_L2_SYSMEM_INVALIDATE_PENDING_ISSUE 0x00000001 /* -W--T */
#define NV_FUNC_PRIV_L2_SYSMEM_INVALIDATE_OUTSTANDING 1:1 /* R-IUF */
#define NV_FUNC_PRIV_L2_SYSMEM_INVALIDATE_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_L2_SYSMEM_INVALIDATE_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_FUNC_PRIV_L2_PEERMEM_INVALIDATE 0x00000F04 /* RW-4R */
#define NV_FUNC_PRIV_L2_PEERMEM_INVALIDATE_PENDING 0:0 /* RWIUF */
#define NV_FUNC_PRIV_L2_PEERMEM_INVALIDATE_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_L2_PEERMEM_INVALIDATE_PENDING_BUSY 0x00000001 /* R---V */
#define NV_FUNC_PRIV_L2_PEERMEM_INVALIDATE_PENDING_ISSUE 0x00000001 /* -W--T */
#define NV_FUNC_PRIV_L2_PEERMEM_INVALIDATE_OUTSTANDING 1:1 /* R-IUF */
#define NV_FUNC_PRIV_L2_PEERMEM_INVALIDATE_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_L2_PEERMEM_INVALIDATE_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_FUNC_PRIV_BAR1_BLOCK 0x00000F40 /* RW-4R */
#define NV_FUNC_PRIV_BAR1_BLOCK_MAP 29:0 /* */
#define NV_FUNC_PRIV_BAR1_BLOCK_PTR 27:0 /* RWIUF */
#define NV_FUNC_PRIV_BAR1_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_FUNC_PRIV_BAR1_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_FUNC_PRIV_BAR1_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_FUNC_PRIV_BAR1_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_FUNC_PRIV_BAR1_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_FUNC_PRIV_BAR1_BLOCK_MODE 31:31 /* RWIUF */
#define NV_FUNC_PRIV_BAR1_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_FUNC_PRIV_BAR1_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_BAR2_BLOCK 0x00000F48 /* RW-4R */
#define NV_FUNC_PRIV_BAR2_BLOCK_MAP 29:0 /* */
#define NV_FUNC_PRIV_BAR2_BLOCK_PTR 27:0 /* RWIUF */
#define NV_FUNC_PRIV_BAR2_BLOCK_PTR_0 0x00000000 /* RWI-V */
#define NV_FUNC_PRIV_BAR2_BLOCK_TARGET 29:28 /* RWIUF */
#define NV_FUNC_PRIV_BAR2_BLOCK_TARGET_VID_MEM 0x00000000 /* RWI-V */
#define NV_FUNC_PRIV_BAR2_BLOCK_TARGET_SYS_MEM_COHERENT 0x00000002 /* RW--V */
#define NV_FUNC_PRIV_BAR2_BLOCK_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* RW--V */
#define NV_FUNC_PRIV_BAR2_BLOCK_MODE 31:31 /* RWIUF */
#define NV_FUNC_PRIV_BAR2_BLOCK_MODE_PHYSICAL 0x00000000 /* RWI-V */
#define NV_FUNC_PRIV_BAR2_BLOCK_MODE_VIRTUAL 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_BAR2_BLOCK_RESERVED 30:30 /* */
#define NV_FUNC_PRIV_BAR2_BLOCK_RESERVED_DEFAULT 0x00000001 /* */
#define NV_FUNC_PRIV_BIND_STATUS 0x00000F50 /* R--4R */
#define NV_FUNC_PRIV_BIND_STATUS_BAR1_PENDING 0:0 /* R-IUF */
#define NV_FUNC_PRIV_BIND_STATUS_BAR1_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_BIND_STATUS_BAR1_PENDING_BUSY 0x00000001 /* R---V */
#define NV_FUNC_PRIV_BIND_STATUS_BAR1_OUTSTANDING 1:1 /* R-IUF */
#define NV_FUNC_PRIV_BIND_STATUS_BAR1_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_BIND_STATUS_BAR1_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_FUNC_PRIV_BIND_STATUS_BAR2_PENDING 2:2 /* R-IUF */
#define NV_FUNC_PRIV_BIND_STATUS_BAR2_PENDING_EMPTY 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_BIND_STATUS_BAR2_PENDING_BUSY 0x00000001 /* R---V */
#define NV_FUNC_PRIV_BIND_STATUS_BAR2_OUTSTANDING 3:3 /* R-IUF */
#define NV_FUNC_PRIV_BIND_STATUS_BAR2_OUTSTANDING_FALSE 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_BIND_STATUS_BAR2_OUTSTANDING_TRUE 0x00000001 /* R---V */
#define NV_FUNC_PRIV_CPU_INTR_TOP(i) (0x1600+(i)*4) /* R--4A */
#define NV_FUNC_PRIV_CPU_INTR_TOP__SIZE_1 1 /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_VALUE 31:0 /* R--VF */
#define NV_FUNC_PRIV_CPU_INTR_TOP_SUBTREE(i) (i) /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_SUBTREE__SIZE_1 64 /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_SUBTREE_INTR_PENDING 1 /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_SUBTREE_INTR_NOT_PENDING 0 /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_SET(i) (0x1608+(i)*4) /* RW-4A */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_SET__SIZE_1 1 /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE(i) (i) /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE__SIZE_1 64 /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLE 1 /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_ENABLED 1 /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_SET_SUBTREE_DISABLED 0 /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_CLEAR(i) (0x1610+(i)*4) /* RW-4A */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_CLEAR__SIZE_1 1 /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE(i) (i) /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE__SIZE_1 64 /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLE 1 /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_ENABLED 1 /* */
#define NV_FUNC_PRIV_CPU_INTR_TOP_EN_CLEAR_SUBTREE_DISABLED 0 /* */
#define NV_FUNC_PRIV_CPU_INTR_LEAF(i) (0x1000+(i)*4) /* RW-4A */
#define NV_FUNC_PRIV_CPU_INTR_LEAF__SIZE_1 8 /* */
#define NV_FUNC_PRIV_CPU_INTR_LEAF_VALUE 31:0 /* RWXVF */
#define NV_FUNC_PRIV_CPU_INTR_LEAF_VALUE_INIT 0x00000000 /* R---V */
#define NV_FUNC_PRIV_CPU_INTR_LEAF_EN_SET(i) (0x1200+(i)*4) /* RW-4A */
#define NV_FUNC_PRIV_CPU_INTR_LEAF_EN_SET__SIZE_1 8 /* */
#define NV_FUNC_PRIV_CPU_INTR_LEAF_EN_SET_VALUE 31:0 /* RWIVF */
#define NV_FUNC_PRIV_CPU_INTR_LEAF_EN_SET_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_CPU_INTR_LEAF_EN_CLEAR(i) (0x1400+(i)*4) /* RW-4A */
#define NV_FUNC_PRIV_CPU_INTR_LEAF_EN_CLEAR__SIZE_1 8 /* */
#define NV_FUNC_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE 31:0 /* RWIVF */
#define NV_FUNC_PRIV_CPU_INTR_LEAF_EN_CLEAR_VALUE_INIT 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_INTR_COUNT 0x1644 /* R--4R */
#define NV_FUNC_PRIV_INTR_COUNT_SIZE 11:0 /* R--UF */
#define NV_FUNC_PRIV_CPU_INTR_PFIFO_INTR_0_VECTOR 136 /* */
#define NV_FUNC_PRIV_CPU_INTR_PFIFO_INTR_1_VECTOR 137 /* */
#define NV_FUNC_PRIV_CPU_INTR_PFB_VECTOR 141 /* */
#define NV_FUNC_PRIV_CPU_INTR_IOCTRL_INTR_1_VECTOR 144 /* */
#define NV_FUNC_PRIV_CPU_INTR_THERMAL_VECTOR 146 /* */
#define NV_FUNC_PRIV_CPU_INTR_HDACODEC_VECTOR 147 /* */
#define NV_FUNC_PRIV_CPU_INTR_PTIMER_VECTOR 148 /* */
#define NV_FUNC_PRIV_CPU_INTR_PMGR_VECTOR 149 /* */
#define NV_FUNC_PRIV_CPU_INTR_IOCTRL_INTR_0_VECTOR 150 /* */
#define NV_FUNC_PRIV_CPU_INTR_DFD_VECTOR 151 /* */
#define NV_FUNC_PRIV_CPU_INTR_PMU_VECTOR 152 /* */
#define NV_FUNC_PRIV_CPU_INTR_LTC_ALL_VECTOR 153 /* */
#define NV_FUNC_PRIV_CPU_INTR_PDISP_VECTOR 154 /* */
#define NV_FUNC_PRIV_CPU_INTR_GSP_INTR_0_VECTOR 155 /* */
#define NV_FUNC_PRIV_CPU_INTR_PBUS_VECTOR 156 /* */
#define NV_FUNC_PRIV_CPU_INTR_XVE_VECTOR 157 /* */
#define NV_FUNC_PRIV_CPU_INTR_PRIV_RING_VECTOR 158 /* */
#define NV_FUNC_PRIV_CPU_INTR_PTIMER_ALARM_VECTOR 159 /* */
#define NV_FUNC_PRIV_CPU_INTR_LEAF_TRIGGER 0x00001640 /* -W-4R */
#define NV_FUNC_PRIV_CPU_INTR_LEAF_TRIGGER_VECTOR 11:0 /* -W-VF */
#define NV_FUNC_PRIV_MAILBOX_SCRATCH(i) (0x2100+(i)*4) /* RW-4A */
#define NV_FUNC_PRIV_MAILBOX_SCRATCH__SIZE_1 16 /* */
#define NV_FUNC_PRIV_MAILBOX_SCRATCH_DATA 31:0 /* RWXVF */
#define NV_FUNC_PRIV_DOORBELL 0x2200 /* -W-4R */
#define NV_FUNC_PRIV_DOORBELL_HANDLE 31:0 /* -W-VF */
#define NV_FUNC_PRIV_TIMER 0x2300 /* RW-4R */
#define NV_FUNC_PRIV_TIMER_NSEC 31:0 /* */
#define NV_FUNC_PRIV_TIMER_USEC 31:10 /* RWIUF */
#define NV_FUNC_PRIV_TIMER_USEC_INIT 0x0 /* RWI-V */
#define NV_FUNC_PRIV_MMU_NON_REPLAY_FAULT_BUFFER 0 /* */
#define NV_FUNC_PRIV_MMU_REPLAY_FAULT_BUFFER 1 /* */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_LO(i) (0x00003000+(i)*32) /* RW-4A */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_LO__SIZE_1 2 /* */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_LO_ADDR_MODE 0:0 /* RWXVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_LO_ADDR_MODE_VIRTUAL 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_LO_ADDR_MODE_PHYSICAL 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_LO_PHYS_APERTURE 2:1 /* RWXVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_LOCAL 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_SYS_COH 0x00000002 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_LO_PHYS_APERTURE_SYS_NCOH 0x00000003 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_LO_PHYS_VOL 3:3 /* RWXVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_LO_ADDR 31:12 /* RWXVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_HI(i) (0x00003004+(i)*32) /* RW-4A */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_HI__SIZE_1 2 /* */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_HI_ADDR 31:0 /* RWXVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_GET(i) (0x00003008+(i)*32) /* RW-4A */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_GET__SIZE_1 2 /* */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_GET_PTR 19:0 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_GET_PTR_RESET 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED 30:30 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_NO 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_YES 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_GET_GETPTR_CORRUPTED_CLEAR 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_GET_OVERFLOW 31:31 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_GET_OVERFLOW_NO 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_GET_OVERFLOW_YES 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_GET_OVERFLOW_CLEAR 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_PUT(i) (0x0000300C+(i)*32) /* R--4A */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_PUT__SIZE_1 2 /* */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_PUT_PTR 19:0 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_PUT_PTR_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED 30:30 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_NO 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_PUT_GETPTR_CORRUPTED_YES 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_PUT_OVERFLOW 31:31 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_PUT_OVERFLOW_NO 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_PUT_OVERFLOW_YES 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_SIZE(i) (0x00003010+(i)*32) /* RW-4A */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_SIZE__SIZE_1 2 /* */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_SIZE_VAL 19:0 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_SIZE_VAL_RESET 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR 29:29 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_DISABLE 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_SIZE_OVERFLOW_INTR_ENABLE 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT 30:30 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_NO 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_SIZE_SET_DEFAULT_YES 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE 31:31 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_FALSE 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_BUFFER_SIZE_ENABLE_TRUE 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_PAGE_FAULT_CTRL 0x00003070 /* RW-4R */
#define NV_FUNC_PRIV_MMU_PAGE_FAULT_CTRL_PRF_FILTER 1:0 /* RWEVF */
#define NV_FUNC_PRIV_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_ALL 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_PAGE_FAULT_CTRL_PRF_FILTER_SEND_NONE 0x00000003 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_ADDR_LO 0x00003080 /* R--4R */
#define NV_FUNC_PRIV_MMU_FAULT_ADDR_LO_PHYS_APERTURE 1:0 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_ADDR_LO_PHYS_APERTURE_LOCAL 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_ADDR_LO_PHYS_APERTURE_PEER 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_ADDR_LO_PHYS_APERTURE_SYS_COH 0x00000002 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_ADDR_LO_PHYS_APERTURE_SYS_NCOH 0x00000003 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_ADDR_LO_ADDR 31:12 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_ADDR_LO_ADDR_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_ADDR_HI 0x00003084 /* R--4R */
#define NV_FUNC_PRIV_MMU_FAULT_ADDR_HI_ADDR 31:0 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_ADDR_HI_ADDR_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_INST_LO 0x00003088 /* R--4R */
#define NV_FUNC_PRIV_MMU_FAULT_INST_LO_ENGINE_ID 8:0 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_INST_LO_ENGINE_ID_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_INST_LO_APERTURE 11:10 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_INST_LO_APERTURE_VID_MEM 0x00000000 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INST_LO_APERTURE_SYS_MEM_COHERENT 0x00000002 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INST_LO_APERTURE_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INST_LO_APERTURE_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_INST_LO_ADDR 31:12 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_INST_LO_ADDR_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_INST_HI 0x0000308C /* R--4R */
#define NV_FUNC_PRIV_MMU_FAULT_INST_HI_ADDR 31:0 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_INST_HI_ADDR_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO 0x00003090 /* R--4R */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_FAULT_TYPE 4:0 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_FAULT_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_REPLAYABLE_FAULT 7:7 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_REPLAYABLE_FAULT_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_CLIENT 14:8 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_CLIENT_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE 19:16 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_READ 0x00000000 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_WRITE 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_ATOMIC 0x00000002 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_PREFETCH 0x00000003 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_READ 0x00000000 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_WRITE 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC 0x00000002 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_STRONG 0x00000002 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_PREFETCH 0x00000003 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_VIRT_ATOMIC_WEAK 0x00000004 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_READ 0x00000008 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_WRITE 0x00000009 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_ATOMIC 0x0000000a /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_PHYS_PREFETCH 0x0000000b /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_ACCESS_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_CLIENT_TYPE 20:20 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_CLIENT_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_GPC_ID 28:24 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_GPC_ID_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_PROTECTED_MODE 29:29 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_PROTECTED_MODE_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN 30:30 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_REPLAYABLE_FAULT_EN_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_VALID 31:31 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_INFO_VALID_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS 0x00003094 /* RW-4R */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS 0:0 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_RESET 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_CLEAR 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_PHYS_SET 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT 1:1 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_RESET 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_CLEAR 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR1_VIRT_SET 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS 2:2 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_RESET 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_CLEAR 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_PHYS_SET 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT 3:3 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_RESET 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_CLEAR 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_BAR2_VIRT_SET 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_PHYS 4:4 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_RESET 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_CLEAR 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_PHYS_SET 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_VIRT 5:5 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_RESET 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_CLEAR 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_IFB_VIRT_SET 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS 6:6 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_RESET 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_CLEAR 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_PHYS_SET 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT 7:7 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_RESET 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_CLEAR 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_DROPPED_OTHER_VIRT_SET 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_REPLAYABLE 8:8 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_REPLAYABLE_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_REPLAYABLE_SET 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE 9:9 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_SET 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_REPLAYABLE_ERROR 10:10 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_REPLAYABLE_ERROR_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_REPLAYABLE_ERROR_SET 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR 11:11 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_ERROR_SET 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW 12:12 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_REPLAYABLE_OVERFLOW_SET 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW 13:13 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_OVERFLOW_SET 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED 14:14 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_REPLAYABLE_GETPTR_CORRUPTED_SET 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED 15:15 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_NON_REPLAYABLE_GETPTR_CORRUPTED_SET 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_BUSY_TYPE 29:28 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_BUSY_TYPE_RESET 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_BUSY 30:30 /* R-EVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_BUSY_FALSE 0x00000000 /* R-E-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_BUSY_TRUE 0x00000001 /* R---V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_VALID 31:31 /* RWEVF */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_VALID_RESET 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_VALID_CLEAR 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_FAULT_STATUS_VALID_SET 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_PDB 0x000030A0 /* RW-4R */
#define NV_FUNC_PRIV_MMU_INVALIDATE_PDB_APERTURE 1:1 /* RWEVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_PDB_APERTURE_INIT 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_PDB_APERTURE_VID_MEM 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_PDB_APERTURE_SYS_MEM 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_PDB_ADDR 31:4 /* RWEVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_PDB_ADDR_INIT 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_PDB_ADDR_ALIGNMENT 0x0000000c /* */
#define NV_FUNC_PRIV_MMU_INVALIDATE_UPPER_PDB 0x000030A4 /* RW-4R */
#define NV_FUNC_PRIV_MMU_INVALIDATE_UPPER_PDB_ADDR 19:0 /* RWEVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_UPPER_PDB_ADDR_INIT 0x00000000 /* RWE-V */
#define NV_FUNC_PRIV_MMU_INVALIDATE 0x000030B0 /* RW-4R */
#define NV_FUNC_PRIV_MMU_INVALIDATE_ALL_VA 0:0 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_ALL_VA_FALSE 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_ALL_VA_TRUE 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_ALL_PDB 1:1 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_ALL_PDB_FALSE 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_ALL_PDB_TRUE 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_HUBTLB_ONLY 2:2 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_HUBTLB_ONLY_FALSE 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_HUBTLB_ONLY_TRUE 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_REPLAY 5:3 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_REPLAY_NONE 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_REPLAY_START 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_REPLAY_START_ACK_ALL 0x00000002 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_TARGETED 0x00000003 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_GLOBAL 0x00000004 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_REPLAY_CANCEL_VA_GLOBAL 0x00000005 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_SYS_MEMBAR 6:6 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_SYS_MEMBAR_FALSE 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_SYS_MEMBAR_TRUE 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_ACK 8:7 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_ACK_NONE_REQUIRED 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_ACK_INTRANODE 0x00000002 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_ACK_GLOBALLY 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_ID 14:9 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CANCEL_GPC_ID 19:15 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CANCEL_GPC_ID 19:15 /* */
#define NV_FUNC_PRIV_MMU_INVALIDATE_INVAL_SCOPE 16:15 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_INVAL_SCOPE_ALL_TLBS 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_INVAL_SCOPE_LINK_TLBS 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_INVAL_SCOPE_NON_LINK_TLBS 0x00000002 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE 20:20 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_GPC 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CANCEL_CLIENT_TYPE_HUB 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_USE_PASID 21:21 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_USE_PASID_FALSE 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_USE_PASID_TRUE 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_USE_SIZE 22:22 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_USE_SIZE_FALSE 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_USE_SIZE_TRUE 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_PROP_FLUSH 23:23 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_PROP_FLUSH_FALSE 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_PROP_FLUSH_TRUE 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL 26:24 /* RWXVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_ALL 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_PTE_ONLY 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE0 0x00000002 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE1 0x00000003 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE2 0x00000004 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE3 0x00000005 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE4 0x00000006 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_UP_TO_PDE5 0x00000007 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_READ 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_STRONG 0x00000002 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_RSVRVD 0x00000003 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_WEAK 0x00000004 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ATOMIC_ALL 0x00000005 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_WRITE_AND_ATOMIC 0x00000006 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_CACHE_LEVEL_CANCEL_ALL 0x00000007 /* RW--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_TRIGGER 31:31 /* -WEVF */
#define NV_FUNC_PRIV_MMU_INVALIDATE_TRIGGER_FALSE 0x00000000 /* -WE-V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_TRIGGER_TRUE 0x00000001 /* -W--V */
#define NV_FUNC_PRIV_MMU_INVALIDATE_MAX_CACHELINE_SIZE 0x00000010 /* */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG 0x00003100 /* RW-4R */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_THRESHOLD 15:0 /* RWIVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_THRESHOLD_INIT 0x00000080 /* RWI-V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY 17:16 /* RWIVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_INIT 0x00000000 /* RWI-V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_64K 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_2M 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_16M 0x00000002 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_MIMC_GRANULARITY_16G 0x00000003 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY 19:18 /* RWIVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_INIT 0x00000000 /* RWI-V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_64K 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_2M 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_16M 0x00000002 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_MOMC_GRANULARITY_16G 0x00000003 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_GVA_NOTIFY 20:20 /* RWIVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_GVA_NOTIFY_TRUE 0x00000001 /* RWI-V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_GVA_NOTIFY_FALSE 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PD 30:30 /* RWIVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PD_TRUE 0x00000001 /* RWI-V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PD_FALSE 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PCIE 31:31 /* RWIVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PCIE_TRUE 0x00000001 /* RWI-V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_CONFIG_COUNT_PCIE_FALSE 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO 0x00003108 /* RW-4R */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN 0:0 /* RWIVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN_FALSE 0x00000000 /* RWI-V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_EN_TRUE 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE 31:12 /* RWXVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_LO_BASE_RESET 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI 0x0000310C /* RW-4R */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI_BASE 31:0 /* RWXVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_HI_BASE_RESET 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE 0x00003110 /* R--4R */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_FIELD 31:0 /* */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_HW 12:0 /* R-IUF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_SIZE_HW_ENTRIES 4096 /* R-I-V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET 0x00003114 /* RW-4R */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET 31:0 /* */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET_HW 11:0 /* RWIVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_GET_OFFSET_HW_INIT 0x00000000 /* RWI-V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT 0x00003118 /* R--4R */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET 31:0 /* */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET_HW 11:0 /* R-IVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_PUT_OFFSET_HW_INIT 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO 0x0000311C /* R--4R */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL 0:0 /* R-IVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_FALSE 0x0 /* R-I-V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_FULL_TRUE 0x1 /* R---V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED 1:1 /* R-IVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED_FALSE 0x0 /* R---V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_PUSHED_TRUE 0x1 /* R-I-V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK 24:24 /* R-IVF */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK_FALSE 0x0 /* R-I-V */
#define NV_FUNC_PRIV_ACCESS_COUNTER_NOTIFY_BUFFER_INFO_WRITE_NACK_TRUE 0x1 /* R---V */
#define NV_FUNC_PRIV_MSIX_TABLE_ADDR_LO(i) (0x00010000+(i)*16) /* RW-4A */
#define NV_FUNC_PRIV_MSIX_TABLE_ADDR_LO__SIZE_1 6 /* */
#define NV_FUNC_PRIV_MSIX_TABLE_ADDR_LO_RSVD 1:0 /* C--VF */
#define NV_FUNC_PRIV_MSIX_TABLE_ADDR_LO_RSVD_VALUE 0x00000000 /* C---V */
#define NV_FUNC_PRIV_MSIX_TABLE_ADDR_LO_BITS 31:2 /* RWXVF */
#define NV_FUNC_PRIV_MSIX_TABLE_ADDR_HI(i) (0x00010004+(i)*16) /* RW-4A */
#define NV_FUNC_PRIV_MSIX_TABLE_ADDR_HI__SIZE_1 6 /* */
#define NV_FUNC_PRIV_MSIX_TABLE_ADDR_HI_BITS 31:0 /* RWXVF */
#define NV_FUNC_PRIV_MSIX_TABLE_DATA(i) (0x00010008+(i)*16) /* RW-4A */
#define NV_FUNC_PRIV_MSIX_TABLE_DATA__SIZE_1 6 /* */
#define NV_FUNC_PRIV_MSIX_TABLE_DATA_BITS 31:0 /* RWXVF */
#define NV_FUNC_PRIV_MSIX_TABLE_VECTOR_CONTROL(i) (0x0001000C+(i)*16) /* RW-4A */
#define NV_FUNC_PRIV_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 6 /* */
#define NV_FUNC_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT 0:0 /* RWIVF */
#define NV_FUNC_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_UNMASKED 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_MASKED 0x00000001 /* RWI-V */
#define NV_FUNC_PRIV_MSIX_TABLE_VECTOR_CONTROL_RSVD 31:1 /* C--VF */
#define NV_FUNC_PRIV_MSIX_TABLE_VECTOR_CONTROL_RSVD_VALUE 0x00000000 /* C---V */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_ADDR_LO(i) (0x00410000+(i)*16) /* RW-4A */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_ADDR_LO__SIZE_1 6 /* */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_ADDR_LO_RSVD 1:0 /* C--VF */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_ADDR_LO_RSVD_VALUE 0x00000000 /* C---V */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_ADDR_LO_BITS 31:2 /* RWXVF */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_ADDR_HI(i) (0x00410004+(i)*16) /* RW-4A */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_ADDR_HI__SIZE_1 6 /* */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_ADDR_HI_BITS 31:0 /* RWXVF */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_DATA(i) (0x00410008+(i)*16) /* RW-4A */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_DATA__SIZE_1 6 /* */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_DATA_BITS 31:0 /* RWXVF */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL(i) (0x0041000C+(i)*16) /* RW-4A */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL__SIZE_1 6 /* */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT 0:0 /* RWIVF */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_UNMASKED 0x00000000 /* RW--V */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_MASK_BIT_MASKED 0x00000001 /* RWI-V */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_RSVD 31:1 /* C--VF */
#define NV_FUNC_PRIV_JUMBO_MSIX_TABLE_VECTOR_CONTROL_RSVD_VALUE 0x00000000 /* C---V */
#define NV_FUNC_PRIV_MSIX_PBA 0x00020000 /* R--4R */
#define NV_FUNC_PRIV_MSIX_PBA_BITS 31:0 /* R-IVF */
#define NV_FUNC_PRIV_MSIX_PBA_BITS_INIT 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_JUMBO_MSIX_PBA 0x00420000 /* R--4R */
#define NV_FUNC_PRIV_JUMBO_MSIX_PBA_BITS 31:0 /* R-IVF */
#define NV_FUNC_PRIV_JUMBO_MSIX_PBA_BITS_INIT 0x00000000 /* R-I-V */
#define NV_FUNC_PRIV_MSIX_PBA_SHADOW 0x00002400 /* RW-4R */
#define NV_FUNC_PRIV_MSIX_PBA_SHADOW_BITS 7:0 /* RWIVF */
#define NV_FUNC_PRIV_MSIX_PBA_SHADOW_BITS_NOT_ACTIVE 0x00000000 /* RWI-V */
#define NV_FUNC_PRIV_MSIX_PBA_SHADOW_BITS_CLEAR 0x00000001 /* RW--V */
#define NV_FUNC_PRIV_MSIX_PBA_SHADOW_BIT 31:8 /* C--VF */
#define NV_FUNC_PRIV_MSIX_PBA_SHADOW_BIT_NOT_ACTIVE 0x00000000 /* C---V */
#define NV_FUNC_CFG0 0x00030000 /* C--4R */
#define NV_FUNC_CFG0_USERMODE_CLASS_ID 15:0 /* C--UF */
#define NV_FUNC_CFG0_USERMODE_CLASS_ID_VALUE 50529 /* C---V */
#define NV_FUNC_TIME_0 0x30080 /* R--4R */
#define NV_FUNC_TIME_0_NSEC 31:5 /* R-XUF */
#define NV_FUNC_TIME_1 0x30084 /* R--4R */
#define NV_FUNC_TIME_1_NSEC 28:0 /* R-XUF */
#define NV_FUNC_DOORBELL 0x30090 /* -W-4R */
#define NV_FUNC_DOORBELL_HANDLE 31:0 /* -W-VF */
#define NV_FUNC_ERR_CONT 0x30094 /* R--4R */
#define NV_FUNC_ERR_CONT_GRAPHICS 0:0 /* R--VF */
#define NV_FUNC_ERR_CONT_GRAPHICS_NOT_PENDING 0 /* R---V */
#define NV_FUNC_ERR_CONT_GRAPHICS_PENDING 1 /* R---V */
#define NV_FUNC_ERR_CONT_MMU_ECC 1:1 /* R--VF */
#define NV_FUNC_ERR_CONT_MMU_ECC_NOT_PENDING 0 /* R---V */
#define NV_FUNC_ERR_CONT_MMU_ECC_PENDING 1 /* R---V */
#define NV_FUNC_ERR_CONT_NVLINK_0 2:2 /* R--VF */
#define NV_FUNC_ERR_CONT_NVLINK_0_NOT_PENDING 0 /* R---V */
#define NV_FUNC_ERR_CONT_NVLINK_0_PENDING 1 /* R---V */
#define NV_FUNC_ERR_CONT_NVLINK_1 3:3 /* R--VF */
#define NV_FUNC_ERR_CONT_NVLINK_1_NOT_PENDING 0 /* R---V */
#define NV_FUNC_ERR_CONT_NVLINK_1_PENDING 1 /* R---V */
#define NV_FUNC_ERR_CONT_LTC 4:4 /* R--VF */
#define NV_FUNC_ERR_CONT_LTC_NOT_PENDING 0 /* R---V */
#define NV_FUNC_ERR_CONT_LTC_PENDING 1 /* R---V */
#define NV_FUNC_ERR_CONT_PFB 5:5 /* R--VF */
#define NV_FUNC_ERR_CONT_PFB_NOT_PENDING 0 /* R---V */
#define NV_FUNC_ERR_CONT_PFB_PENDING 1 /* R---V */
#define NV_FUNC_ERR_CONT_FBHUB_0 6:6 /* R--VF */
#define NV_FUNC_ERR_CONT_FBHUB_0_NOT_PENDING 0 /* R---V */
#define NV_FUNC_ERR_CONT_FBHUB_0_PENDING 1 /* R---V */
#define NV_FUNC_ERR_CONT_SMC_ENG_HW_IMPL (8+8-1):8 /* R--VF */
#define NV_FUNC_ERR_CONT_SMC_ENG(i) ((i)+8):((i)+8) /* */
#define NV_FUNC_ERR_CONT_SMC_ENG__SIZE_1 8 /* */
#define NV_FUNC_ERR_CONT_SMC_ENG_NOT_PENDING 0 /* */
#define NV_FUNC_ERR_CONT_SMC_ENG_PENDING 1 /* */
//
// --------------------------------------------------------------------------------

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// --------------------------------------------------------------------------------
//
#define NV_RUNLIST_CONFIG 0x000 /* RW-4R */
#define NV_RUNLIST_CONFIG_SEM_ACQ_STRENGTH 0:0 /* RWIVF */
#define NV_RUNLIST_CONFIG_SEM_ACQ_STRENGTH_WEAK 0x00000000 /* RWI-V */
#define NV_RUNLIST_CONFIG_SEM_ACQ_STRENGTH_STRONG 0x00000001 /* RW--V */
#define NV_RUNLIST_CONFIG_SEM_REL_STRENGTH 4:4 /* RWIVF */
#define NV_RUNLIST_CONFIG_SEM_REL_STRENGTH_WEAK 0x00000000 /* RW--V */
#define NV_RUNLIST_CONFIG_SEM_REL_STRENGTH_STRONG 0x00000001 /* RWI-V */
#define NV_RUNLIST_CONFIG_L2_EVICT 9:8 /* RWIVF */
#define NV_RUNLIST_CONFIG_L2_EVICT_FIRST 0x00000000 /* RWI-V */
#define NV_RUNLIST_CONFIG_L2_EVICT_NORMAL 0x00000001 /* RW--V */
#define NV_RUNLIST_CONFIG_L2_EVICT_LAST 0x00000002 /* RW--V */
#define NV_RUNLIST_CONFIG_SUBCH4 10:10 /* RWXVF */
#define NV_RUNLIST_CONFIG_SUBCH4_INACTIVE 0x00000000 /* RW--V */
#define NV_RUNLIST_CONFIG_SUBCH4_ACTIVE 0x00000001 /* RW--V */
#define NV_RUNLIST_CHANNEL_CONFIG 0x004 /* R--4R */
#define NV_RUNLIST_CHANNEL_CONFIG_NUM_CHANNELS_LOG2 3:0 /* C--UF */
#define NV_RUNLIST_CHANNEL_CONFIG_NUM_CHANNELS_LOG2_2K 11 /* C---V */
#define NV_RUNLIST_CHANNEL_CONFIG_CHRAM_BAR0_OFFSET 31:4 /* R-XVF */
#define NV_RUNLIST_DOORBELL_CONFIG 0x008 /* R--4R */
#define NV_RUNLIST_DOORBELL_CONFIG_ID 31:16 /* R-XVF */
#define NV_RUNLIST_FB_CONFIG 0x00C /* R--4R */
#define NV_RUNLIST_FB_CONFIG_FB_THREAD_ID 7:0 /* R-XVF */
#define NV_RUNLIST_FB_CONFIG_ESC_ID 15:8 /* R-XVF */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG(i) (0x300+(i)*4) /* RW-4A */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG__SIZE_1 64 /* */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_MASK 11:0 /* */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_MASK_HW 10:0 /* RWIVF */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_MASK_HW_INIT 2047 /* RWI-V */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_SET 27:16 /* */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_SET_HW 26:16 /* RWIVF */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_SET_HW_INIT 0x0 /* RWI-V */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_PENDING_ENABLE 31:31 /* RWIVF */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_PENDING_ENABLE_TRUE 1 /* RW--V */
#define NV_RUNLIST_VIRTUAL_CHANNEL_CFG_PENDING_ENABLE_FALSE 0 /* RWI-V */
#define NV_RUNLIST_PBDMA_CONFIG(i) (0x010+(i)*4) /* R--4A */
#define NV_RUNLIST_PBDMA_CONFIG__SIZE_1 2 /* */
#define NV_RUNLIST_PBDMA_CONFIG_PBDMA_BAR0_OFFSET 25:10 /* R-XUF */
#define NV_RUNLIST_PBDMA_CONFIG_VALID 31:31 /* R-XUF */
#define NV_RUNLIST_PBDMA_CONFIG_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PBDMA_CONFIG_VALID_FALSE 0x00000000 /* R---V */
#define NV_RUNLIST_ACQ_PRETEST 0x020 /* RW-4R */
#define NV_RUNLIST_ACQ_PRETEST_TIMEOUT 7:0 /* RWIUF */
#define NV_RUNLIST_ACQ_PRETEST_TIMEOUT_8 0x00000008 /* RWI-V */
#define NV_RUNLIST_ACQ_PRETEST_TIMESCALE 15:12 /* RWIUF */
#define NV_RUNLIST_ACQ_PRETEST_TIMESCALE_0 0x00000000 /* RWI-V */
#define NV_RUNLIST_ACQ_PRETEST_TIMESCALE_10 0x0000000a /* RW--V */
#define NV_RUNLIST_IDLE_FILTER 0x024 /* RW-4R */
#define NV_RUNLIST_IDLE_FILTER_PERIOD 7:0 /* RWIUF */
#define NV_RUNLIST_IDLE_FILTER_PERIOD_INIT 0x00000050 /* RWI-V */
#define NV_RUNLIST_IDLE_FILTER_PERIOD__PROD 0x00000064 /* RW--V */
#define NV_RUNLIST_IDLE_FILTER_PERIOD_8 0x00000008 /* RW--V */
#define NV_RUNLIST_IDLE_FILTER_PERIOD_32 0x00000020 /* RW--V */
#define NV_CHRAM_CHANNEL(i) (0x000+(i)*4) /* RW-4A */
#define NV_CHRAM_CHANNEL__SIZE_1 2048 /* */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL 0:0 /* -WIVF */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_SET_BITS 0x00000000 /* -WI-V */
#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_CLEAR_BITS 0x00000001 /* -W--V */
#define NV_CHRAM_CHANNEL_ENABLE 1:1 /* RWIVF */
#define NV_CHRAM_CHANNEL_ENABLE_NOT_IN_USE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ENABLE_IN_USE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_NEXT 2:2 /* RWIVF */
#define NV_CHRAM_CHANNEL_NEXT_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_NEXT_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_BUSY 3:3 /* R-IVF */
#define NV_CHRAM_CHANNEL_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED 4:4 /* RWIVF */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_ENG_FAULTED 5:5 /* RWIVF */
#define NV_CHRAM_CHANNEL_ENG_FAULTED_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ENG_FAULTED_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_ON_PBDMA 6:6 /* R-IVF */
#define NV_CHRAM_CHANNEL_ON_PBDMA_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ON_PBDMA_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ON_ENG 7:7 /* R-IVF */
#define NV_CHRAM_CHANNEL_ON_ENG_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ON_ENG_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_PENDING 8:8 /* RWIVF */
#define NV_CHRAM_CHANNEL_PENDING_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_PENDING_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_CTX_RELOAD 9:9 /* RWIVF */
#define NV_CHRAM_CHANNEL_CTX_RELOAD_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_CTX_RELOAD_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY 10:10 /* R-IVF */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_PBDMA_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ENG_BUSY 11:11 /* R-IVF */
#define NV_CHRAM_CHANNEL_ENG_BUSY_FALSE 0x00000000 /* R-I-V */
#define NV_CHRAM_CHANNEL_ENG_BUSY_TRUE 0x00000001 /* R---V */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL 12:12 /* RWIVF */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_FALSE 0x00000000 /* RWI-V */
#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_TRUE 0x00000001 /* RW--V */
#define NV_CHRAM_CHANNEL_UPDATE 31:0 /* */
#define NV_CHRAM_CHANNEL_UPDATE_ENABLE_CHANNEL 0x00000002 /* */
#define NV_CHRAM_CHANNEL_UPDATE_DISABLE_CHANNEL 0x00000003 /* */
#define NV_CHRAM_CHANNEL_UPDATE_FORCE_CTX_RELOAD 0x00000200 /* */
#define NV_CHRAM_CHANNEL_UPDATE_RESET_PBDMA_FAULTED 0x00000011 /* */
#define NV_CHRAM_CHANNEL_UPDATE_RESET_ENG_FAULTED 0x00000021 /* */
#define NV_CHRAM_CHANNEL_UPDATE_CLEAR_CHANNEL 0xFFFFFFFF /* */
#define NV_RUNLIST_SUBMIT_BASE_LO 0x080 /* RW-4R */
#define NV_RUNLIST_SUBMIT_BASE_LO_PTR_LO 31:12 /* RWIUF */
#define NV_RUNLIST_SUBMIT_BASE_LO_PTR_LO_NULL 0x00000000 /* RWI-V */
#define NV_RUNLIST_SUBMIT_BASE_LO_TARGET 1:0 /* RWIVF */
#define NV_RUNLIST_SUBMIT_BASE_LO_TARGET_VID_MEM 0x0 /* RWI-V */
#define NV_RUNLIST_SUBMIT_BASE_LO_TARGET_SYS_MEM_COHERENT 0x2 /* RW--V */
#define NV_RUNLIST_SUBMIT_BASE_LO_TARGET_SYS_MEM_NONCOHERENT 0x3 /* RW--V */
#define NV_RUNLIST_SUBMIT_BASE_LO_PTR_ALIGN_SHIFT 12 /* */
#define NV_RUNLIST_SUBMIT_BASE_HI 0x084 /* RW-4R */
#define NV_RUNLIST_SUBMIT_BASE_HI_PTR_HI 7:0 /* RWIUF */
#define NV_RUNLIST_SUBMIT_BASE_HI_PTR_HI_NULL 0x00000000 /* RWI-V */
#define NV_RUNLIST_SUBMIT 0x088 /* RW-4R */
#define NV_RUNLIST_SUBMIT_LENGTH 15:0 /* RWIUF */
#define NV_RUNLIST_SUBMIT_LENGTH_ZERO 0x00000000 /* RWI-V */
#define NV_RUNLIST_SUBMIT_LENGTH_MAX 0x0000ffff /* RW--V */
#define NV_RUNLIST_SUBMIT_OFFSET 31:16 /* RWIVF */
#define NV_RUNLIST_SUBMIT_OFFSET_ZERO 0x00000000 /* RWI-V */
#define NV_RUNLIST_SUBMIT_INFO 0x08C /* R--4R */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID 13:0 /* */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_HW 10:0 /* R-IUF */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_HW_DEFAULT 0x00000000 /* R-I-V */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_VALID 14:14 /* R-IUF */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_TSGID_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_SUBMIT_INFO_PENDING 15:15 /* R-IVF */
#define NV_RUNLIST_SUBMIT_INFO_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_SUBMIT_INFO_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_OFFSET 31:16 /* R-IVF */
#define NV_RUNLIST_SUBMIT_INFO_PREEMPTED_OFFSET_ZERO 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_VECTORID(i) (0x160+(i)*4) /* RW-4A */
#define NV_RUNLIST_INTR_VECTORID__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_VECTORID__PRIV_LEVEL_MASK "NV_RUNLIST_INTR_PRIV_LEVEL_MASK" /* */
#define NV_RUNLIST_INTR_VECTORID_VECTOR 11:0 /* RWXUF */
#define NV_RUNLIST_INTR_VECTORID_GSP 30:30 /* RWIUF */
#define NV_RUNLIST_INTR_VECTORID_GSP_DISABLE 0 /* RW--V */
#define NV_RUNLIST_INTR_VECTORID_GSP_ENABLE 1 /* RWI-V */
#define NV_RUNLIST_INTR_VECTORID_CPU 31:31 /* RWIUF */
#define NV_RUNLIST_INTR_VECTORID_CPU_DISABLE 0 /* RW--V */
#define NV_RUNLIST_INTR_VECTORID_CPU_ENABLE 1 /* RWI-V */
#define NV_RUNLIST_INTR_RETRIGGER(i) (0x180+(i)*4) /* -W-4A */
#define NV_RUNLIST_INTR_RETRIGGER__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_RETRIGGER__PRIV_LEVEL_MASK "NV_RUNLIST_INTR_PRIV_LEVEL_MASK" /* */
#define NV_RUNLIST_INTR_RETRIGGER_TRIGGER 0:0 /* -W-VF */
#define NV_RUNLIST_INTR_RETRIGGER_TRIGGER_TRUE 1 /* -W--V */
#define NV_RUNLIST_INTR_0 0x100 /* RW-4R */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG0 0:0 /* RWIVF */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG0_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG0_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG0_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG1 1:1 /* RWIVF */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG1_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG1_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG1_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG2 2:2 /* RWIVF */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG2_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG2_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG2_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG(i) (i):(i) /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG__SIZE_1 3 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG_NOT_PENDING 0x00000000 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG_PENDING 0x00000001 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_ENG_RESET 0x00000001 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE(i) ((i)+1):((i)+1) /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE_NOT_PENDING 0x00000000 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE_PENDING 0x00000001 /* */
#define NV_RUNLIST_INTR_0_CTXSW_TIMEOUT_GRCE_RESET 0x00000001 /* */
#define NV_RUNLIST_INTR_0_RUNLIST_IDLE 4:4 /* RWIVF */
#define NV_RUNLIST_INTR_0_RUNLIST_IDLE_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_RUNLIST_IDLE_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_IDLE_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE 5:5 /* RWXVF */
#define NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_AND_ENG_IDLE_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE 6:6 /* RWXVF */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE 7:7 /* RWXVF */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_ACQUIRE_AND_ENG_IDLE_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_BAD_TSG 12:12 /* RWIVF */
#define NV_RUNLIST_INTR_0_BAD_TSG_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_BAD_TSG_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_BAD_TSG_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */
#define NV_RUNLIST_INTR_0_TSG_PREEMPT_COMPLETE_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_TSG_PREEMPT_COMPLETE_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_TSG_PREEMPT_COMPLETE_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_0 16:16 /* R-XVF */
#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_0_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_0_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_0 17:17 /* R-XVF */
#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_0_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_0_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_1 18:18 /* R-XVF */
#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_1_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA0_INTR_TREE_1_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_1 19:19 /* R-XVF */
#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_1_NOT_PENDING 0x00000000 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMA1_INTR_TREE_1_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j(i,j) (16+(i)+(j)*2):(16+(i)+(j)*2) /* */
#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j__SIZE_2 2 /* */
#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j_NOT_PENDING 0x00000000 /* */
#define NV_RUNLIST_INTR_0_PBDMAi_INTR_TREE_j_PENDING 0x00000001 /* */
#define NV_RUNLIST_INTR_0_RUNLIST_PREEMPT_COMPLETE 9:9 /* RWIVF */
#define NV_RUNLIST_INTR_0_RUNLIST_PREEMPT_COMPLETE_NOT_PENDING 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_0_RUNLIST_PREEMPT_COMPLETE_PENDING 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_0_RUNLIST_PREEMPT_COMPLETE_RESET 0x00000001 /* -W--V */
#define NV_RUNLIST_INTR_0_RUNLIST_EVENT 9:9 /* */
#define NV_RUNLIST_INTR_0_MASK_SET 0x110 /* RW-4R */
#define NV_RUNLIST_INTR_0_MASK_SET_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */
#define NV_RUNLIST_INTR_0_MASK_SET_TSG_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_MASK_SET_TSG_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_MASK_CLEAR 0x118 /* RW-4R */
#define NV_RUNLIST_INTR_0_MASK_CLEAR_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */
#define NV_RUNLIST_INTR_0_MASK_CLEAR_TSG_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_MASK_CLEAR_TSG_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE(i) (0x120+(i)*8) /* RW-4A */
#define NV_RUNLIST_INTR_0_EN_SET_TREE__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE__PRIV_LEVEL_MASK "NV_RUNLIST_INTR_PRIV_LEVEL_MASK" /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG0 0:0 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG0_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG0_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG1 1:1 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG1_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG1_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG2 2:2 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG2_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG2_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG(i) (i):(i) /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG__SIZE_1 3 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG_DISABLED 0x00000000 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_ENG_ENABLED 0x00000001 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_GRCE(i) ((i)+1):((i)+1) /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_GRCE__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_GRCE_DISABLED 0x00000000 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_CTXSW_TIMEOUT_GRCE_ENABLED 0x00000001 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_IDLE 4:4 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_IDLE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_AND_ENG_IDLE 5:5 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_AND_ENG_IDLE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_AND_ENG_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE 6:6 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE 7:7 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_TSG_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_TSG_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_PREEMPT_COMPLETE 9:9 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_RUNLIST_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_BAD_TSG 12:12 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_BAD_TSG_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_BAD_TSG_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_0 16:16 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_0_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_0_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_0 17:17 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_0_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_0_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_1 18:18 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_1_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA0_INTR_TREE_1_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_1 19:19 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_1_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMA1_INTR_TREE_1_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j(i,j) (16+(i)+(j)*2):(16+(i)+(j)*2) /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j__SIZE_2 2 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j_DISABLED 0x00000000 /* */
#define NV_RUNLIST_INTR_0_EN_SET_TREE_PBDMAi_INTR_TREE_j_ENABLED 0x00000001 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE(i) (0x140+(i)*8) /* RW-4A */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE__PRIV_LEVEL_MASK "NV_RUNLIST_INTR_PRIV_LEVEL_MASK" /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG0 0:0 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG0_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG0_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG1 1:1 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG1_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG1_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG2 2:2 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG2_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG2_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG(i) (i):(i) /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG__SIZE_1 3 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG_DISABLED 0x00000000 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_ENG_ENABLED 0x00000001 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_GRCE(i) ((i)+1):((i)+1) /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_GRCE__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_GRCE_DISABLED 0x00000000 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_CTXSW_TIMEOUT_GRCE_ENABLED 0x00000001 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_IDLE 4:4 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_IDLE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_AND_ENG_IDLE 5:5 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_AND_ENG_IDLE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_AND_ENG_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE 6:6 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE 7:7 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_ACQUIRE_AND_ENG_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_TSG_PREEMPT_COMPLETE 8:8 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_TSG_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_TSG_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_PREEMPT_COMPLETE 9:9 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_PREEMPT_COMPLETE_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_RUNLIST_PREEMPT_COMPLETE_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_BAD_TSG 12:12 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_BAD_TSG_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_BAD_TSG_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_0 16:16 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_0_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_0_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_0 17:17 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_0_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_0_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_1 18:18 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_1_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA0_INTR_TREE_1_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_1 19:19 /* RWIVF */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_1_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMA1_INTR_TREE_1_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j(i,j) (16+(i)+(j)*2):(16+(i)+(j)*2) /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j__SIZE_1 2 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j__SIZE_2 2 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j_DISABLED 0x00000000 /* */
#define NV_RUNLIST_INTR_0_EN_CLEAR_TREE_PBDMAi_INTR_TREE_j_ENABLED 0x00000001 /* */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO(i) (0x224+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_PREV_TSGID 13:0 /* R-IUF */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_PREV_TSGID_DEFAULT 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_CTXSW_STATE 15:14 /* R-IUF */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_CTXSW_STATE_LOAD 0x00000001 /* R-I-V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_CTXSW_STATE_SAVE 0x00000002 /* R---V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_CTXSW_STATE_SWITCH 0x00000003 /* R---V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_NEXT_TSGID 29:16 /* R-IUF */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_NEXT_TSGID_DEFAULT 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS 31:30 /* R-IUF */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS_AWAITING_ACK 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS_ENG_WAS_RESET 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS_ACK_RECEIVED 0x00000002 /* R---V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_INFO_STATUS_DROPPED_TIMEOUT 0x00000003 /* R---V */
#define NV_RUNLIST_INFO 0x108 /* R--4R */
#define NV_RUNLIST_INFO_RUNLIST_IDLE_INTR_ARM 0:0 /* R-IUF */
#define NV_RUNLIST_INFO_RUNLIST_IDLE_INTR_ARM_UNARMED 0x00000000 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_IDLE_INTR_ARM_ARMED 0x00000001 /* R---V */
#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_INTR_ARM 1:1 /* R-IUF */
#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_INTR_ARM_UNARMED 0x00000000 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_INTR_ARM_ARMED 0x00000001 /* R---V */
#define NV_RUNLIST_INFO_RUNLIST_AND_ENG_IDLE_INTR_ARM 4:4 /* R-IUF */
#define NV_RUNLIST_INFO_RUNLIST_AND_ENG_IDLE_INTR_ARM_UNARMED 0x00000000 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_AND_ENG_IDLE_INTR_ARM_ARMED 0x00000001 /* R---V */
#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_AND_ENG_IDLE_INTR_ARM 5:5 /* R-IUF */
#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_AND_ENG_IDLE_INTR_ARM_UNARMED 0x00000000 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_ACQUIRE_AND_ENG_IDLE_INTR_ARM_ARMED 0x00000001 /* R---V */
#define NV_RUNLIST_INFO_ENG_IDLE 8:8 /* R-IUF */
#define NV_RUNLIST_INFO_ENG_IDLE_FALSE 0x00000000 /* R---V */
#define NV_RUNLIST_INFO_ENG_IDLE_TRUE 0x00000001 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_IDLE 9:9 /* R-IUF */
#define NV_RUNLIST_INFO_RUNLIST_IDLE_FALSE 0x00000000 /* R---V */
#define NV_RUNLIST_INFO_RUNLIST_IDLE_TRUE 0x00000001 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_FETCH_STATUS 10:10 /* R-IVF */
#define NV_RUNLIST_INFO_RUNLIST_FETCH_STATUS_IDLE 0x00000000 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_FETCH_STATUS_BUSY 0x00000001 /* R---V */
#define NV_RUNLIST_INFO_ACQUIRE_STILL_PENDING 12:12 /* R-IUF */
#define NV_RUNLIST_INFO_ACQUIRE_STILL_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_INFO_ACQUIRE_STILL_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_INFO_RUNLIST_FETCH_NACKED 13:13 /* R-IUF */
#define NV_RUNLIST_INFO_RUNLIST_FETCH_NACKED_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_INFO_RUNLIST_FETCH_NACKED_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_BAD_TSG 0x174 /* R--4R */
#define NV_RUNLIST_INTR_BAD_TSG_CODE 3:0 /* R-IVF */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_NO_ERROR 0x00000000 /* R-I-V */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_ZERO_LENGTH_TSG 0x00000001 /* R---V */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_MAX_LENGTH_EXCEEDED 0x00000002 /* R---V */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_RUNLIST_OVERFLOW 0x00000003 /* R---V */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_EXPECTED_A_CHID_ENTRY 0x00000004 /* R---V */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_EXPECTED_A_TSG_HEADER 0x00000005 /* R---V */
#define NV_RUNLIST_INTR_BAD_TSG_CODE_INVALID_RUNQUEUE 0x00000006 /* R---V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG(i) (0x220+(i)*64) /* RW-4A */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_PERIOD 30:0 /* RWIVF */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_PERIOD_INIT 0x003fffff /* RWI-V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_PERIOD_MAX 0x7fffffff /* RW--V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_DETECTION 31:31 /* RWIVF */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_DETECTION_DISABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_ENGINE_CTXSW_TIMEOUT_CONFIG_DETECTION_ENABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_BLKCG 0x050 /* RW-4R */
#define NV_RUNLIST_BLKCG_IDLE_CG_DLY_CNT 5:0 /* RWIVF */
#define NV_RUNLIST_BLKCG_IDLE_CG_DLY_CNT_INIT 0x00000000 /* RWI-V */
#define NV_RUNLIST_BLKCG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */
#define NV_RUNLIST_BLKCG_IDLE_CG_EN 6:6 /* RWIVF */
#define NV_RUNLIST_BLKCG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_BLKCG_IDLE_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_BLKCG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_RUNLIST_BLKCG_STATE_CG_EN 7:7 /* */
#define NV_RUNLIST_BLKCG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_RUNLIST_BLKCG_STALL_CG_DLY_CNT_INIT 0x00000000 /* */
#define NV_RUNLIST_BLKCG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */
#define NV_RUNLIST_BLKCG_STALL_CG_EN 14:14 /* RWIVF */
#define NV_RUNLIST_BLKCG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_BLKCG_STALL_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_BLKCG_STALL_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_RUNLIST_BLKCG_QUIESCENT_CG_EN 15:15 /* */
#define NV_RUNLIST_BLKCG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG_QUIESCENT_CG_EN__PROD 0x00000001 /* */
#define NV_RUNLIST_BLKCG_WAKEUP_DLY_CNT 19:16 /* RWIVF */
#define NV_RUNLIST_BLKCG_WAKEUP_DLY_CNT_INIT 0x00000000 /* RWI-V */
#define NV_RUNLIST_BLKCG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG_THROT_CLK_CNT 23:20 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_CNT_INIT 0x0000000f /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_RUNLIST_BLKCG_DI_DT_SKEW_VAL_INIT 0x00000000 /* */
#define NV_RUNLIST_BLKCG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_EN 28:28 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_RUNLIST_BLKCG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG_PAUSE_CG_EN 30:30 /* */
#define NV_RUNLIST_BLKCG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG_HALT_CG_EN 31:31 /* */
#define NV_RUNLIST_BLKCG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_RUNLIST_BLKCG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG_HALT_CG_EN__PROD 0x00000000 /* */
#define NV_RUNLIST_BLKCG1 0x054 /* RW-4R */
#define NV_RUNLIST_BLKCG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_RUNLIST_BLKCG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_BLKCG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_BLKCG1_SLCG 16:1 /* */
#define NV_RUNLIST_BLKCG1_SLCG_ENABLED 0x00000000 /* */
#define NV_RUNLIST_BLKCG1_SLCG_DISABLED 0x0000FFFF /* */
#define NV_RUNLIST_BLKCG1_SLCG__PROD 0x00000001 /* */
#define NV_RUNLIST_BLKCG1_SLCG_RLP 1:1 /* RWIVF */
#define NV_RUNLIST_BLKCG1_SLCG_RLP_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_RLP_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_BLKCG1_SLCG_RLP__PROD 0x00000001 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_EVH 3:3 /* RWIVF */
#define NV_RUNLIST_BLKCG1_SLCG_EVH_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_EVH_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_BLKCG1_SLCG_EVH__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_EISM 7:7 /* RWIVF */
#define NV_RUNLIST_BLKCG1_SLCG_EISM_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_EISM_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_BLKCG1_SLCG_EISM__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_LB 8:8 /* RWIVF */
#define NV_RUNLIST_BLKCG1_SLCG_LB_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_LB_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_BLKCG1_SLCG_LB__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_CTL 9:9 /* RWIVF */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_CTL_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_CTL_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_CTL__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_GP 10:10 /* RWIVF */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_GP_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_GP_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_GP__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_PB 11:11 /* RWIVF */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_PB_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_PB_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_BLKCG1_SLCG_PBDMA_PB__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_PRI 13:13 /* RWIVF */
#define NV_RUNLIST_BLKCG1_SLCG_PRI_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_PRI_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_BLKCG1_SLCG_PRI__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_CHSW 14:14 /* RWIVF */
#define NV_RUNLIST_BLKCG1_SLCG_CHSW_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_CHSW_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_BLKCG1_SLCG_CHSW__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_XBAR 15:15 /* RWIVF */
#define NV_RUNLIST_BLKCG1_SLCG_XBAR_ENABLED 0x00000000 /* RW--V */
#define NV_RUNLIST_BLKCG1_SLCG_XBAR_DISABLED 0x00000001 /* RWI-V */
#define NV_RUNLIST_BLKCG1_SLCG_XBAR__PROD 0x00000000 /* RW--V */
#define NV_RUNLIST_INTERNAL_DOORBELL 0x090 /* -W-4R */
#define NV_RUNLIST_INTERNAL_DOORBELL_CHID 11:0 /* */
#define NV_RUNLIST_INTERNAL_DOORBELL_CHID_HW 10:0 /* -WXUF */
#define NV_RUNLIST_INTERNAL_DOORBELL_GFID 21:16 /* -WXUF */
#define NV_RUNLIST_SCHED_DISABLE 0x094 /* RW-4R */
#define NV_RUNLIST_SCHED_DISABLE_RUNLIST 0:0 /* RWIVF */
#define NV_RUNLIST_SCHED_DISABLE_RUNLIST_ENABLED 0x00000000 /* RWI-V */
#define NV_RUNLIST_SCHED_DISABLE_RUNLIST_DISABLED 0x00000001 /* RW--V */
#define NV_RUNLIST_SCHED_DISABLE_RUNLIST_FALSE 0x00000000 /* */
#define NV_RUNLIST_SCHED_DISABLE_RUNLIST_TRUE 0x00000001 /* */
#define NV_RUNLIST_PREEMPT 0x098 /* RW-4R */
#define NV_RUNLIST_PREEMPT_ID 11:0 /* */
#define NV_RUNLIST_PREEMPT_ID_HW 10:0 /* RWIUF */
#define NV_RUNLIST_PREEMPT_ID_HW_NULL 0x00000000 /* RWI-V */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING 20:20 /* R-IVF */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING 21:21 /* R-IVF */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_PREEMPT_TYPE 25:24 /* RWIVF */
#define NV_RUNLIST_PREEMPT_TYPE_RUNLIST 0x00000000 /* RWI-V */
#define NV_RUNLIST_PREEMPT_TYPE_TSG 0x00000001 /* RW--V */
#define NV_RUNLIST_ENGINE_STATUS0(i) (0x200+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS0__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS0_TSGID 11:0 /* */
#define NV_RUNLIST_ENGINE_STATUS0_TSGID_HW 10:0 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS 15:13 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_INVALID 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_VALID 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_CTXSW_SAVE 0x00000005 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_CTXSW_LOAD 0x00000006 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_STATUS_CTXSW_SWITCH 0x00000007 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS0_CTX 13:13 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_INVALID 0x00000000 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTX_VALID 0x00000001 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTXLOAD 14:14 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTXLOAD_NOT_IN_PROGRESS 0x00000000 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTXLOAD_IN_PROGRESS 0x00000001 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTXSW 15:15 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTXSW_NOT_IN_PROGRESS 0x00000000 /* */
#define NV_RUNLIST_ENGINE_STATUS0_CTXSW_IN_PROGRESS 0x00000001 /* */
#define NV_RUNLIST_ENGINE_STATUS0_NEXT_TSGID 27:16 /* */
#define NV_RUNLIST_ENGINE_STATUS0_NEXT_TSGID_HW 26:16 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS0_ENG_RELOAD 29:29 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS0_ENG_RELOAD_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS0_ENG_RELOAD_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS0_FAULTED 30:30 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS0_FAULTED_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS0_FAULTED_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS0_ENGINE 31:31 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS0_ENGINE_IDLE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS0_ENGINE_BUSY 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS1(i) (0x204+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS1__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS1_GFID 5:0 /* R-XVF */
#define NV_RUNLIST_ENGINE_STATUS1_NEXT_GFID 13:8 /* R-XVF */
#define NV_RUNLIST_ENGINE_STATUS1_INTR_ID 20:16 /* R-XVF */
#define NV_RUNLIST_ENGINE_STATUS1_GFID_VALID 30:30 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS1_GFID_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS1_GFID_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS1_NEXT_GFID_VALID 31:31 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS1_NEXT_GFID_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS1_NEXT_GFID_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL(i,j) (0x208+(i)*64+(j)*4) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL__SIZE_2 2 /* */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_CHID 11:0 /* */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_CHID_HW 10:0 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_VALID 15:15 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_CHID 27:16 /* */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_CHID_HW 26:16 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_VALID 31:31 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_CHANNEL_NEXT_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG(i) (0x228+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_IF_EN 0:0 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_IF_EN_DISABLED 0x00000000 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_IF_EN_ENABLED 0x00000001 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_NO_CREDITS 8:8 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_NO_CREDITS_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_NO_CREDITS_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_WFI 12:12 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_WFI_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE0_WFI_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_NO_CREDITS 16:16 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_NO_CREDITS_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_NO_CREDITS_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_WFI 20:20 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_WFI_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_DEBUG_PIPE1_WFI_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_INST(i) (0x210+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS_INST__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS_INST_TARGET 1:0 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_INST_TARGET_VID_MEM 0x00000000 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_INST_VALID 11:11 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_INST_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_INST_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_INST_PTR_LO 31:12 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_INST_HI(i) (0x214+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS_INST_HI__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS_INST_HI_PTR_HI 31:0 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_INST_HI_PTR_HI_ZERO 0x00000000 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST(i) (0x218+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_TARGET 1:0 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_TARGET_VID_MEM 0x00000000 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_TARGET_SYS_MEM_COHERENT 0x00000002 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_TARGET_SYS_MEM_NONCOHERENT 0x00000003 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_VALID 11:11 /* R-IVF */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_VALID_FALSE 0x00000000 /* R-I-V */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_VALID_TRUE 0x00000001 /* R---V */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_PTR_LO 31:12 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_HI(i) (0x21C+(i)*64) /* R--4A */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_HI__SIZE_1 3 /* */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_HI_PTR_HI 31:0 /* R-XUF */
#define NV_RUNLIST_ENGINE_STATUS_NEXT_INST_HI_PTR_HI_ZERO 0x00000000 /* R---V */
//
// --------------------------------------------------------------------------------
// Channel Teardown Sequence
// ===============================================================================
//
// This section describes the sequence software (specifically RM) can use to
// tear down a channel for robust channels (RC) recovery or in the case of a fault.
//
// In the case of a fault, the esched does not guarantee that a PBDMA has
// saved out prior to RM receiving notification of the fault. RM must determine
// which context has faulted by processing the fault buffer as described in the
// NV_PFB_PRI_MMU_FAULT_BUFFER_* register documentation in pri_mmu_hub.ref and in
// the fault buffer NV_MMU_FAULT_BUF_ENTRY documentation in dev_mmu_fault.ref.
// This context can then be torn down using the following procedure.
//
// Note when a PBDMA fault or CE fault occurs, the PBDMA will save out
// automatically. The TSG related to the context in which the fault occurred will
// not be scheduled again until the fault is handled.
//
// In the case of some other issue requiring the engine to be reset, the TSG
// will need to be manually preempted.
//
// In all cases, a PBDMA interrupt may occur prior to the PBDMA being able to
// switch out. SW must handle these interrupts according to the relevant handling
// procedure before the PBDMA preempt can complete.
//
// Context TSG teardown procedure:
//
// 1. Disable scheduling for the engine's runlist via NV_RUNLIST_SCHED_DISABLE.
// This enables SW to determine whether a context has hung later in the
// process: otherwise, ongoing work on the runlist may keep ENGINE_STATUS0
// from reaching a steady state.
//
// 2. Disable all channels in the TSG being torn down or submit a new runlist
// that does not contain the TSG. This is to prevent the TSG from being
// rescheduled once scheduling is reenabled in step 6.
//
// 3. Initiate a preempt of the engine by writing the bit associated with its
// runlist to NV_RUNLIST_PREEMPT with TYPE=RUNLIST. This allows us to begin
// the preempt process prior to doing the slow register reads needed to
// determine whether the context has hit any interrupts or is hung. Do not
// poll NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING for the preempt to
// complete.
//
// 4. Check for interrupts or hangs while waiting for the preempt to complete.
// During the below polling, any stalling interrupts relating to the runlist
// must be detected and handled in order for the preemption to complete. SW
// should follow the following sub-steps to cleanly tear down the context:
//
// a. Wait for PBDMA preempt completion: For each PBDMA which serves the
// runlist, poll NV_PPBDMA_STATUS_SCHED(pbdma_id) to reach CHAN_STATUS
// INVALID, indicating that no further work will run on the PBDMA during the
// teardown sequence. Interleaved with the polling, PBDMA interrupts must
// be serviced as they arise: such an interrupt can prevent the PBDMA from
// completing its channel save.
//
// Note: SW can use the RUNLIST_PREEMPT_COMPLETE notification intr instead
// of polling.
//
// b. Wait for engine context preempt completion: For each engine served by the
// runlist, read NV_RUNLIST_ENGINE_STATUS0(engine_id) to verify the
// channel/TSG has saved off the engine, or tell if the CTXSW is hung, via
// the CTX_STATUS, ID, and NEXT_ID fields. Take action based on the
// following values for the CTX_STATUS field:
//
// i. CTX_STATUS_SWITCH: Engine save hasn't started yet, continue to poll
// (repeat step 4b).
//
// ii. CTX_STATUS_INVALID: The engine context has switched off. The
// preemption step for this engine is complete.
//
// iii. CTX_STATUS_VALID or CTX_STATUS_CTXSW_SAVE: check the ID field:
// * If ID matches the TSG for the context being torn down, the engine
// reset procedure can be performed (see step 5), or SW can continue
// waiting by repeating step 4b.
// * If ID does NOT match, then skip engine reset (skip step 5) for this
// engine. The context isn't running on the engine.
//
// iv. CTX_STATUS_LOAD: check the NEXT_ID field:
// * If NEXT_ID matches the TSG of the context being torn down, the engine
// is loading the context and reset (see step 5) can be performed
// immediately or after a delay to allow the context a chance to load and
// be saved off.
// * If NEXT_ID does not match the TSG ID then the context is no longer on
// the engine. Skip engine reset (skip step 5) for this engine.
//
// SW may alternatively wait for the CTX_STATUS to reach INVALID, but this
// may take longer if an unrelated context is currently on the engine or
// being switched to.
//
// 5. If a reset is needed as determined by step 4:
//
// a. Halt the memory interface for the engine (as per the relevant engine
// procedure).
//
// b. Reset the engine via NV_PMC_ENABLE.
//
// c. Take the engine out of reset and reinit the engine (as per the relevant
// engine procedure)
//
// 6. Re-enable scheduling for the engine's runlist via NV_RUNLIST_SCHED_ENABLE.
//
// 7. Finally, reset the channel RAM state for the channels in the TSG torn down
// by writing NV_CHRAM_CHANNEL_UPDATE_CLEAR_CHANNEL to each channel in the
// TSG.
//
// After this sequence, resources for the channels in the TSG may be reclaimed.
//
// KEY
// ===============================================================================
// Runlist-Specific Resets (3rd Field: [> --I-- <])
// 'I' = Initialized with hot_sysclk_reset_.
//

37
include/ampere/ga100/dev_timer.ref.h Normal file
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// --------------------------------------------------------------------------------
//
#define NV_PTIMER 0x00009FFF:0x00009000 /* RW--D */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_0 0x00009084 /* RW-4R */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_TO 0:0 /* RWXVF */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_TO_ERROR 0x1 /* RW--V */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_TO_CLEAR 0x0 /* -W--V */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_TO_NONE 0x0 /* RW--V */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_WRITE 1:1 /* RWXVF */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_WRITE_TRUE 0x1 /* RW--V */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_WRITE_FALSE 0x0 /* RW--V */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_ADDR 23:2 /* RWXVF */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_FECS_TGT 31:31 /* RWXVF */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_FECS_TGT_TRUE 0x1 /* RW--V */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_0_FECS_TGT_FALSE 0x0 /* RW--V */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_1 0x00009088 /* RW-4R */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_1_DATA 31:0 /* RWXVF */
#define NV_PTIMER_PRI_TIMEOUT_SAVE_1_DATA_WAS_READ 0x0 /* RW--V */
#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE 0x0000908C /* RW-4R */
#define NV_PTIMER_PRI_TIMEOUT_FECS_ERRCODE_DATA 31:0 /* RWXVF */
#define NV_PTIMER_ALARM_0 0x00009420 /* RW-4R */
#define NV_PTIMER_ALARM_0_NSEC 31:5 /* RWIUF */
#define NV_PTIMER_ALARM_0_NSEC_INIT 0x0 /* RWI-V */
#define NV_PTIMER_TIMER_INTR_VECTOR 0x00009440 /* */
#define NV_PTIMER_TIMER_INTR_VECTOR_ID 7:0 /* */
#define NV_PTIMER_TIMER_INTR_VECTOR_ID_VALUE 148 /* */
#define NV_PTIMER_PRI_TMR_CG1 0x00009600 /* RW-4R */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN 0:0 /* RWIVF */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWI-V */
#define NV_PTIMER_PRI_TMR_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG 1:1 /* RWIVF */
#define NV_PTIMER_PRI_TMR_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG_DISABLED 0x00000001 /* RWI-V */
#define NV_PTIMER_PRI_TMR_CG1_SLCG__PROD 0x00000000 /* RW--V */
//
// --------------------------------------------------------------------------------

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// --------------------------------------------------------------------------------
// KEY LEGEND
// --------------------------------------------------------------------------------
//
// Each define in the .ref file has a 5 field code to say what kind of define it is: i.e. [> RW--R <]
// The following legend shows accepted values for each of the 5 fields:
// Read, Write, Internal State, Declaration/Size, and Define Indicator.
//
// Read
// ' ' = Other Information
// '-' = Field is part of a write-only register
// 'C' = Value read is always the same, constant value line follows (C)
// 'R' = Value is read
//
//
// Write
// ' ' = Other Information
// '-' = Must not be written (D), value ignored when written (R,A,F)
// 'W' = Can be written
//
//
// Internal State
// ' ' = Other Information
// '-' = No internal state
// 'X' = Internal state, initial value is unknown
// 'I' = Internal state, initial value is known and follows (I), see "Reset Signal" section for signal.
// 'E' = Internal state, initial value is known and follows (E), see "Reset Signal" section for signal.
// 'B' = Internal state, initial value is known and follows (B), see "Reset Signal" section for signal.
// 'C' = Internal state, initial value is known and follows (C), see "Reset Signal" section for signal.
//
// 'V' = (legacy) Internal state, initialize at volatile reset
// 'D' = (legacy) Internal state, default initial value at object creation (legacy: Only used in dev_ram.h)
// 'C' = (legacy) Internal state, initial value at object creation
// 'C' = (legacy) Internal state, class-based initial value at object creation (legacy: Only used in dev_ram.h)
//
//
// Declaration/Size
// ' ' = Other Information
// '-' = Does Not Apply
// 'V' = Type is void
// 'U' = Type is unsigned integer
// 'S' = Type is signed integer
// 'F' = Type is IEEE floating point
// '1' = Byte size (008)
// '2' = Short size (016)
// '3' = Three byte size (024)
// '4' = Word size (032)
// '8' = Double size (064)
//
//
// Define Indicator
// ' ' = Other Information
// 'C' = Clear value
// 'D' = Device
// 'L' = Logical device.
// 'M' = Memory
// 'R' = Register
// 'A' = Array of Registers
// 'F' = Field
// 'V' = Value
// 'T' = Task
// 'P' = Phantom Register
//
// 'B' = (legacy) Bundle address
// 'G' = (legacy) General purpose configuration register
// 'C' = (legacy) Class
//
// Reset signal defaults for graphics engine registers.
// All graphics engine registers use the following defaults for reset signals:
// 'E' = initialized with engine_reset_
// 'I' = initialized with context_reset_
// 'B' = initialized with reset_IB_dly_
//
// Reset signal
// For units that differ from the graphics engine defaults, the reset signals should be defined here:

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// --------------------------------------------------------------------------------
//
#define NV_PGRAPH_PRI_CWD_FS 0x00405B00 /* RWE4R */
#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS 7:0 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_FS_NUM_GPCS_INIT 0x0 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS 15:8 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_FS_NUM_TPCS_INIT 0x0 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_DELAY_CILP_PREEMPT 0x00405B24 /* RWI4R */
#define NV_PGRAPH_PRI_CWD_DELAY_CILP_PREEMPT_TIMEOUT 31:0 /* RWIVF */
#define NV_PGRAPH_PRI_CWD_DELAY_CILP_PREEMPT_TIMEOUT_INIT 0x00000000 /* RWI-V */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL 0x00405B2c /* RWI4R */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_PARTITIONING_SELECT 1:0 /* RWIVF */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_PARTITIONING_SELECT_NONE 0x0 /* RWI-V */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_PARTITIONING_SELECT_STATIC 0x1 /* RW--V */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_PARTITIONING_SELECT_DYNAMIC 0x2 /* RW--V */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_SEL 3:2 /* RWIVF */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_SEL_NONE 0x0 /* RWI-V */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_SEL_PARTITIONING_ENABLE 0x1 /* RW--V */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_SEL_PARTITIONING_LMEM_BLK 0x2 /* RW--V */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_VEID_OFFSET 21:16 /* RWIVF */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_VEID_OFFSET_ZERO 0x0 /* RWI-V */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_VEID_OFFSET_MAX 0x3f /* RW--V */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_OFFSET 29:24 /* RWIVF */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_OFFSET_ZERO 0x0 /* RWI-V */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_OFFSET_PARTITIONING_ENABLE_MAX 1 /* RW--V */
#define NV_PGRAPH_PRI_CWD_PARTITION_CTL_TBL_OFFSET_PARTITIONING_LMEM_BLK_MAX 15 /* RW--V */
#define NV_PGRAPH_PRI_CWD_PARTITION_DATA 0x00405B30 /* RWI4R */
#define NV_PGRAPH_PRI_CWD_PARTITION_DATA_REG 31:0 /* RWIVF */
#define NV_PGRAPH_PRI_CWD_PARTITION_DATA_REG_INIT 0x0 /* RWI-V */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID(i) (0x00405B60+(i)*4) /* RWE4A */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID__SIZE_1 16 /* */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC0 3:0 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC0_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC0 7:4 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC0_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC1 11:8 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC1_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC1 15:12 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC1_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC2 19:16 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC2_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC2 23:20 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC2_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC3 27:24 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_TPC3_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC3 31:28 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_GPC_TPC_ID_GPC3_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_SM_ID(i) (0x00405Ba0+(i)*4) /* RWE4A */
#define NV_PGRAPH_PRI_CWD_SM_ID__SIZE_1 16 /* */
#define NV_PGRAPH_PRI_CWD_SM_ID_TPC0 7:0 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_SM_ID_TPC0_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_SM_ID_TPC1 15:8 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_SM_ID_TPC1_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_SM_ID_TPC2 23:16 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_SM_ID_TPC2_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_SM_ID_TPC3 31:24 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_SM_ID_TPC3_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_CG 0x00405BF0 /* RWE4R */
#define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_DLY_CNT__PROD 0x00000004 /* RW--V */
#define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_EN 6:6 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_CWD_CG_STATE_CG_EN 7:7 /* */
#define NV_PGRAPH_PRI_CWD_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_CWD_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_PGRAPH_PRI_CWD_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_STALL_CG_DLY_CNT__PROD 0x00000004 /* */
#define NV_PGRAPH_PRI_CWD_CG_STALL_CG_EN 14:14 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_CWD_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_CWD_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_PGRAPH_PRI_CWD_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_CWD_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */
#define NV_PGRAPH_PRI_CWD_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_CNT 23:20 /* */
#define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_PGRAPH_PRI_CWD_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_EN 28:28 /* */
#define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_PAUSE_CG_EN 30:30 /* */
#define NV_PGRAPH_PRI_CWD_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_CWD_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_HALT_CG_EN 31:31 /* */
#define NV_PGRAPH_PRI_CWD_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_CWD_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG_HALT_CG_EN__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_CWD_CG1 0x00405BF4 /* RWE4R */
#define NV_PGRAPH_PRI_CWD_CG1_MONITOR_CG_EN 0:0 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_CWD_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_CWD_CG1_SLCG 1:1 /* RWEVF */
#define NV_PGRAPH_PRI_CWD_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_CWD_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_CWD_CG1_SLCG__PROD 0x00000000 /* RW--V */
//
// --------------------------------------------------------------------------------

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// --------------------------------------------------------------------------------
//
#define NV_PGRAPH_DEBUG_0 0x00400080 /* RWE4R */
#define NV_PGRAPH_DEBUG_0_BROADCAST_ALL_BUNDLES 0:0 /* RWEVF */
#define NV_PGRAPH_DEBUG_0_BROADCAST_ALL_BUNDLES_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_DEBUG_0_BROADCAST_ALL_BUNDLES_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_0_DATAHIGH 1:1 /* RWEVF */
#define NV_PGRAPH_DEBUG_0_DATAHIGH_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_0_DATAHIGH_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_0_ILLEGAL_METHOD_CHECKS 4:4 /* RWEVF */
#define NV_PGRAPH_DEBUG_0_ILLEGAL_METHOD_CHECKS_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_0_ILLEGAL_METHOD_CHECKS_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_0_LAUNCH_CHECKS 6:6 /* RWEVF */
#define NV_PGRAPH_DEBUG_0_LAUNCH_CHECKS_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_0_LAUNCH_CHECKS_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_0_METHOD_CHECKS 7:7 /* RWEVF */
#define NV_PGRAPH_DEBUG_0_METHOD_CHECKS_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_0_METHOD_CHECKS_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_0_ZEROBIT_CHECKS 8:8 /* RWEVF */
#define NV_PGRAPH_DEBUG_0_ZEROBIT_CHECKS_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_0_ZEROBIT_CHECKS_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_0_FE_EMITTER 9:9 /* RWEVF */
#define NV_PGRAPH_DEBUG_0_FE_EMITTER_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_DEBUG_0_FE_EMITTER_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_0_FE_EMITTER__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_0_SCG_FORCE_SLOW_DRAIN_TPC 11:11 /* RWEVF */
#define NV_PGRAPH_DEBUG_0_SCG_FORCE_SLOW_DRAIN_TPC_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_DEBUG_0_SCG_FORCE_SLOW_DRAIN_TPC_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_0_SCG_SCHEDULING_MODE_ALWAYS_MIXED 12:12 /* RWEVF */
#define NV_PGRAPH_DEBUG_0_SCG_SCHEDULING_MODE_ALWAYS_MIXED_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_DEBUG_0_SCG_SCHEDULING_MODE_ALWAYS_MIXED_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_0_ZERO_TIMESTAMPS 14:14 /* RWEVF */
#define NV_PGRAPH_DEBUG_0_ZERO_TIMESTAMPS_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_DEBUG_0_ZERO_TIMESTAMPS_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_0_SCG_STALL_CWD_WHEN_DRAIN_FIFO_FULL 15:15 /* RWEVF */
#define NV_PGRAPH_DEBUG_0_SCG_STALL_CWD_WHEN_DRAIN_FIFO_FULL_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_DEBUG_0_SCG_STALL_CWD_WHEN_DRAIN_FIFO_FULL_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_0_STATUS_SETTLE 31:16 /* RWEVF */
#define NV_PGRAPH_DEBUG_0_STATUS_SETTLE_INIT 0x00000018 /* RWE-V */
#define NV_PGRAPH_DEBUG_0_STATUS_SETTLE__PROD 0x00000030 /* RW--V */
#define NV_PGRAPH_DEBUG_0_STATUS_SETTLE_MIN 0x00000010 /* RW--V */
#define NV_PGRAPH_DEBUG_2 0x00400088 /* RWE4R */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_WRITE 0:0 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_WRITE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_WRITE_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_WRITE_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_AWAKEN 1:1 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_AWAKEN_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_AWAKEN_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_NOTIFY_AWAKEN_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_BROADCAST_GO_IDLE 2:2 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_BROADCAST_GO_IDLE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_BROADCAST_GO_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_BROADCAST_GO_IDLE_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_BROADCAST_COMPUTE_GO_IDLE 3:3 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_BROADCAST_COMPUTE_GO_IDLE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_BROADCAST_COMPUTE_GO_IDLE_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_BROADCAST_COMPUTE_GO_IDLE_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_HOLD_STATUS_UNTIL_PIPE_ACTIVE 4:4 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_HOLD_STATUS_UNTIL_PIPE_ACTIVE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_HOLD_STATUS_UNTIL_PIPE_ACTIVE_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_HOLD_STATUS_UNTIL_PIPE_ACTIVE_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_SEMAPHORE_AWAKEN 5:5 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_SEMAPHORE_AWAKEN_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_SEMAPHORE_AWAKEN_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_SEMAPHORE_AWAKEN_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_MEMFMT_AWAKEN 6:6 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_MEMFMT_AWAKEN_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_MEMFMT_AWAKEN_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_BEFORE_MEMFMT_AWAKEN_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_NO_RMW_REQUIRED 7:7 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_NO_RMW_REQUIRED_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_NO_RMW_REQUIRED_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_NO_RMW_REQUIRED_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_WFI_CONDITIONAL 8:8 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_WFI_CONDITIONAL_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_WFI_CONDITIONAL_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_WFI_CONDITIONAL_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_FLUSH_DISABLE_FLAG 9:9 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_FLUSH_DISABLE_FLAG_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_DISABLE_FLAG_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_DISABLE_FLAG_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_THREED_SUBCHANNEL 10:10 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_THREED_SUBCHANNEL_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_THREED_SUBCHANNEL_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_THREED_SUBCHANNEL_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_TWOD_SUBCHANNEL 11:11 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_TWOD_SUBCHANNEL_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_TWOD_SUBCHANNEL_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_TWOD_SUBCHANNEL_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_M2M_SUBCHANNEL 12:12 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_M2M_SUBCHANNEL_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_M2M_SUBCHANNEL_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_M2M_SUBCHANNEL_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_COMPUTE_SUBCHANNEL 13:13 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_COMPUTE_SUBCHANNEL_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_COMPUTE_SUBCHANNEL_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_COMPUTE_SUBCHANNEL_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_HOST_SUBCHANNEL 15:15 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_HOST_SUBCHANNEL_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_HOST_SUBCHANNEL_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_FLUSH_AFTER_HOST_SUBCHANNEL_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_GRAPHICS_AUTO_GO_IDLE 17:17 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_GRAPHICS_AUTO_GO_IDLE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_GRAPHICS_AUTO_GO_IDLE_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_COMPUTE_AUTO_GO_IDLE 18:18 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_COMPUTE_AUTO_GO_IDLE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_COMPUTE_AUTO_GO_IDLE_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_AUTO_GO_IDLE_HWW 19:19 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_AUTO_GO_IDLE_HWW_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_AUTO_GO_IDLE_HWW_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_AUTO_GO_IDLE_HWW_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_NO_WFI_AFTER_ILLEGAL_METHOD_INTERRUPT 22:22 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_NO_WFI_AFTER_ILLEGAL_METHOD_INTERRUPT_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_NO_WFI_AFTER_ILLEGAL_METHOD_INTERRUPT_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_NO_WFI_AFTER_ILLEGAL_METHOD_INTERRUPT_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_GFXP_WFI_ALWAYS_INJECTS_WFI 23:23 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_GFXP_WFI_ALWAYS_INJECTS_WFI_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_GFXP_WFI_ALWAYS_INJECTS_WFI_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_GFXP_WFI_ALWAYS_INJECTS_WFI_INIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_GO_IDLE 25:24 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_GO_IDLE_NONE 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_GO_IDLE_ASYNC 0x00000002 /* RW--V */
#define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_GO_IDLE_BOTH 0x00000003 /* RW--V */
#define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_GO_IDLE_INIT 0x00000002 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_PREEMPT 26:26 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_PREEMPT_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_PREEMPT_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_INJECT_CWD_HYSTERESIS_CONTROL_PREEMPT_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_GFXP_WFI_TIMEOUT_UNIT 27:27 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_GFXP_WFI_TIMEOUT_UNIT_USEC 0x00000000 /* RW--V */
#define NV_PGRAPH_DEBUG_2_GFXP_WFI_TIMEOUT_UNIT_SYSCLK 0x00000001 /* RW--V */
#define NV_PGRAPH_DEBUG_2_GFXP_WFI_TIMEOUT_UNIT_INIT 0x00000001 /* RWE-V */
#define NV_PGRAPH_DEBUG_2_CYA_SPARE 31:28 /* RWEVF */
#define NV_PGRAPH_DEBUG_2_CYA_SPARE_INIT 0xF /* RWE-V */
#define NV_PGRAPH_INTR 0x00400100 /* RWE4R */
#define NV_PGRAPH_INTR_NOTIFY 0:0 /* RWEVF */
#define NV_PGRAPH_INTR_NOTIFY_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_INTR_NOTIFY_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_NOTIFY_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_INTR_SEMAPHORE 1:1 /* RWEVF */
#define NV_PGRAPH_INTR_SEMAPHORE_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_INTR_SEMAPHORE_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_SEMAPHORE_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_INTR_ILLEGAL_METHOD 4:4 /* RWEVF */
#define NV_PGRAPH_INTR_ILLEGAL_METHOD_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_INTR_ILLEGAL_METHOD_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_ILLEGAL_METHOD_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_INTR_ILLEGAL_CLASS 5:5 /* RWEVF */
#define NV_PGRAPH_INTR_ILLEGAL_CLASS_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_INTR_ILLEGAL_CLASS_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_ILLEGAL_CLASS_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY 6:6 /* RWEVF */
#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_ILLEGAL_NOTIFY_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_INTR_DEBUG_METHOD 7:7 /* RWEVF */
#define NV_PGRAPH_INTR_DEBUG_METHOD_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_INTR_DEBUG_METHOD_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_DEBUG_METHOD_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_INTR_FIRMWARE_METHOD 8:8 /* RWEVF */
#define NV_PGRAPH_INTR_FIRMWARE_METHOD_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_INTR_FIRMWARE_METHOD_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_FIRMWARE_METHOD_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_INTR_BUFFER_NOTIFY 16:16 /* RWEVF */
#define NV_PGRAPH_INTR_BUFFER_NOTIFY_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_INTR_BUFFER_NOTIFY_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_BUFFER_NOTIFY_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_INTR_FECS_ERROR 19:19 /* RWEVF */
#define NV_PGRAPH_INTR_FECS_ERROR_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_INTR_FECS_ERROR_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_FECS_ERROR_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_INTR_CLASS_ERROR 20:20 /* RWEVF */
#define NV_PGRAPH_INTR_CLASS_ERROR_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_INTR_CLASS_ERROR_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_CLASS_ERROR_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_INTR_EXCEPTION 21:21 /* RWEVF */
#define NV_PGRAPH_INTR_EXCEPTION_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_INTR_EXCEPTION_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_EXCEPTION_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_INTR_FE_DEBUG_INTR 22:22 /* RWEVF */
#define NV_PGRAPH_INTR_FE_DEBUG_INTR_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_INTR_FE_DEBUG_INTR_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_INTR_FE_DEBUG_INTR_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_INTR_EN 0x0040013C /* RWE4R */
#define NV_PGRAPH_INTR_EN_NOTIFY 0:0 /* RWEVF */
#define NV_PGRAPH_INTR_EN_NOTIFY_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_INTR_EN_NOTIFY_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_NOTIFY__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_SEMAPHORE 1:1 /* RWEVF */
#define NV_PGRAPH_INTR_EN_SEMAPHORE_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_INTR_EN_SEMAPHORE_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_SEMAPHORE__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_ILLEGAL_METHOD 4:4 /* RWEVF */
#define NV_PGRAPH_INTR_EN_ILLEGAL_METHOD_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_INTR_EN_ILLEGAL_METHOD_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_ILLEGAL_METHOD__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_ILLEGAL_CLASS 5:5 /* RWEVF */
#define NV_PGRAPH_INTR_EN_ILLEGAL_CLASS_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_INTR_EN_ILLEGAL_CLASS_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_ILLEGAL_CLASS__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_ILLEGAL_NOTIFY 6:6 /* RWEVF */
#define NV_PGRAPH_INTR_EN_ILLEGAL_NOTIFY_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_INTR_EN_ILLEGAL_NOTIFY_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_ILLEGAL_NOTIFY__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_DEBUG_METHOD 7:7 /* RWEVF */
#define NV_PGRAPH_INTR_EN_DEBUG_METHOD_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_INTR_EN_DEBUG_METHOD_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_DEBUG_METHOD__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_FIRMWARE_METHOD 8:8 /* RWEVF */
#define NV_PGRAPH_INTR_EN_FIRMWARE_METHOD_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_INTR_EN_FIRMWARE_METHOD_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_FIRMWARE_METHOD__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY 16:16 /* RWEVF */
#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_BUFFER_NOTIFY__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_FECS_ERROR 19:19 /* RWEVF */
#define NV_PGRAPH_INTR_EN_FECS_ERROR_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_INTR_EN_FECS_ERROR_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_FECS_ERROR__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_CLASS_ERROR 20:20 /* RWEVF */
#define NV_PGRAPH_INTR_EN_CLASS_ERROR_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_INTR_EN_CLASS_ERROR_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_CLASS_ERROR__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_EXCEPTION 21:21 /* RWEVF */
#define NV_PGRAPH_INTR_EN_EXCEPTION_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_INTR_EN_EXCEPTION_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_EXCEPTION__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_FE_DEBUG_INTR 22:22 /* RWEVF */
#define NV_PGRAPH_INTR_EN_FE_DEBUG_INTR_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_INTR_EN_FE_DEBUG_INTR_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_EN_FE_DEBUG_INTR__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_ROUTE 0x00400140 /* RWE4R */
#define NV_PGRAPH_INTR_ROUTE_ILLEGAL_METHOD 4:4 /* RWEVF */
#define NV_PGRAPH_INTR_ROUTE_ILLEGAL_METHOD_HOST 0x00000000 /* RWE-V */
#define NV_PGRAPH_INTR_ROUTE_ILLEGAL_METHOD_FECS 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_ROUTE_FIRMWARE_METHOD 8:8 /* RWEVF */
#define NV_PGRAPH_INTR_ROUTE_FIRMWARE_METHOD_HOST 0x00000000 /* RW--V */
#define NV_PGRAPH_INTR_ROUTE_FIRMWARE_METHOD_FECS 0x00000001 /* RWE-V */
#define NV_PGRAPH_FECS_INTR 0x00400144 /* RWE4R */
#define NV_PGRAPH_FECS_INTR_ILLEGAL_METHOD 4:4 /* RWEVF */
#define NV_PGRAPH_FECS_INTR_ILLEGAL_METHOD_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_FECS_INTR_ILLEGAL_METHOD_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_FECS_INTR_ILLEGAL_METHOD_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_FECS_INTR_FIRMWARE_METHOD 8:8 /* RWEVF */
#define NV_PGRAPH_FECS_INTR_FIRMWARE_METHOD_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_FECS_INTR_FIRMWARE_METHOD_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_FECS_INTR_FIRMWARE_METHOD_RESET 0x00000001 /* -W--T */
#define NV_PGRAPH_FECS_INTR_EN 0x00400148 /* RWE4R */
#define NV_PGRAPH_FECS_INTR_EN_ILLEGAL_METHOD 4:4 /* RWEVF */
#define NV_PGRAPH_FECS_INTR_EN_ILLEGAL_METHOD_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_FECS_INTR_EN_ILLEGAL_METHOD_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_FECS_INTR_EN_ILLEGAL_METHOD__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_FECS_INTR_EN_FIRMWARE_METHOD 8:8 /* RWEVF */
#define NV_PGRAPH_FECS_INTR_EN_FIRMWARE_METHOD_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_FECS_INTR_EN_FIRMWARE_METHOD_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_FECS_INTR_EN_FIRMWARE_METHOD__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_INTR_CTRL 0x00400154 /* RW-4R */
#define NV_PGRAPH_INTR_CTRL__PRIV_LEVEL_MASK 0x0040014C /* */
#define NV_PGRAPH_INTR_CTRL_VECTOR 11:0 /* RWXUF */
#define NV_PGRAPH_INTR_CTRL_GFID 6+20-1:20 /* RWXUF */
#define NV_PGRAPH_INTR_CTRL_GSP 30:30 /* RWXUF */
#define NV_PGRAPH_INTR_CTRL_GSP_ENABLE 1 /* ----V */
#define NV_PGRAPH_INTR_CTRL_GSP_DISABLE 0 /* ----V */
#define NV_PGRAPH_INTR_CTRL_CPU 31:31 /* RWXUF */
#define NV_PGRAPH_INTR_CTRL_CPU_ENABLE 1 /* ----V */
#define NV_PGRAPH_INTR_CTRL_CPU_DISABLE 0 /* ----V */
#define NV_PGRAPH_INTR_RETRIGGER 0x00400158 /* -W-4R */
#define NV_PGRAPH_INTR_RETRIGGER__PRIV_LEVEL_MASK 0x00400150 /* */
#define NV_PGRAPH_INTR_RETRIGGER_TRIGGER 0:0 /* -WXUF */
#define NV_PGRAPH_INTR_RETRIGGER_TRIGGER_TRUE 1 /* ----V */
#define NV_PGRAPH_INTR_NOTIFY_CTRL 0x00400160 /* RW-4R */
#define NV_PGRAPH_INTR_NOTIFY_CTRL__PRIV_LEVEL_MASK 0x0040015C /* */
#define NV_PGRAPH_INTR_NOTIFY_CTRL_VECTOR 11:0 /* RWXUF */
#define NV_PGRAPH_INTR_NOTIFY_CTRL_GFID 6+20-1:20 /* RWXUF */
#define NV_PGRAPH_INTR_NOTIFY_CTRL_GSP 30:30 /* RWXUF */
#define NV_PGRAPH_INTR_NOTIFY_CTRL_GSP_ENABLE 1 /* ----V */
#define NV_PGRAPH_INTR_NOTIFY_CTRL_GSP_DISABLE 0 /* ----V */
#define NV_PGRAPH_INTR_NOTIFY_CTRL_CPU 31:31 /* RWXUF */
#define NV_PGRAPH_INTR_NOTIFY_CTRL_CPU_ENABLE 1 /* ----V */
#define NV_PGRAPH_INTR_NOTIFY_CTRL_CPU_DISABLE 0 /* ----V */
#define NV_PGRAPH_EXCEPTION 0x00400108 /* R--4R */
#define NV_PGRAPH_EXCEPTION_FE 0:0 /* R-EVF */
#define NV_PGRAPH_EXCEPTION_FE_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_EXCEPTION_FE_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_EXCEPTION_MEMFMT 1:1 /* R-EVF */
#define NV_PGRAPH_EXCEPTION_MEMFMT_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_EXCEPTION_MEMFMT_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_EXCEPTION_PD 2:2 /* R-EVF */
#define NV_PGRAPH_EXCEPTION_PD_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_EXCEPTION_PD_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_EXCEPTION_SCC 3:3 /* R-EVF */
#define NV_PGRAPH_EXCEPTION_SCC_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_EXCEPTION_SCC_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_EXCEPTION_DS 4:4 /* R-EVF */
#define NV_PGRAPH_EXCEPTION_DS_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_EXCEPTION_DS_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_EXCEPTION_SSYNC 5:5 /* R-EVF */
#define NV_PGRAPH_EXCEPTION_SSYNC_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_EXCEPTION_SSYNC_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_EXCEPTION_MME 7:7 /* R-EVF */
#define NV_PGRAPH_EXCEPTION_MME_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_EXCEPTION_MME_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_EXCEPTION_SKED 8:8 /* R-EVF */
#define NV_PGRAPH_EXCEPTION_SKED_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_EXCEPTION_SKED_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_EXCEPTION_GPC 24:24 /* R-EVF */
#define NV_PGRAPH_EXCEPTION_GPC_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_EXCEPTION_GPC_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_EXCEPTION_BE 25:25 /* R-EVF */
#define NV_PGRAPH_EXCEPTION_BE_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_EXCEPTION_BE_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_EXCEPTION1 0x00400118 /* R--4R */
#define NV_PGRAPH_EXCEPTION1_GPC 32-1:0 /* R-EVF */
#define NV_PGRAPH_EXCEPTION1_GPC_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_EXCEPTION1_GPC_0_NOT_PENDING 0x00000000 /* R---V */
#define NV_PGRAPH_EXCEPTION1_GPC_0_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_EXCEPTION2 0x0040011C /* R--4R */
#define NV_PGRAPH_EXCEPTION2_BE 32-1:0 /* R-EVF */
#define NV_PGRAPH_EXCEPTION2_BE_NOT_PENDING 0x00000000 /* R-E-V */
#define NV_PGRAPH_EXCEPTION2_BE_0_NOT_PENDING 0x00000000 /* R---V */
#define NV_PGRAPH_EXCEPTION2_BE_0_PENDING 0x00000001 /* R---V */
#define NV_PGRAPH_EXCEPTION_EN 0x00400138 /* RWE4R */
#define NV_PGRAPH_EXCEPTION_EN_FE 0:0 /* RWEVF */
#define NV_PGRAPH_EXCEPTION_EN_FE_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_EXCEPTION_EN_FE_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_EXCEPTION_EN_MEMFMT 1:1 /* RWEVF */
#define NV_PGRAPH_EXCEPTION_EN_MEMFMT_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_EXCEPTION_EN_MEMFMT_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_EXCEPTION_EN_PD 2:2 /* RWEVF */
#define NV_PGRAPH_EXCEPTION_EN_PD_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_EXCEPTION_EN_PD_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_EXCEPTION_EN_SCC 3:3 /* RWEVF */
#define NV_PGRAPH_EXCEPTION_EN_SCC_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_EXCEPTION_EN_SCC_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_EXCEPTION_EN_DS 4:4 /* RWEVF */
#define NV_PGRAPH_EXCEPTION_EN_DS_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_EXCEPTION_EN_DS_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_EXCEPTION_EN_SSYNC 5:5 /* RWEVF */
#define NV_PGRAPH_EXCEPTION_EN_SSYNC_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_EXCEPTION_EN_SSYNC_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_EXCEPTION_EN_MME 7:7 /* RWEVF */
#define NV_PGRAPH_EXCEPTION_EN_MME_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_EXCEPTION_EN_MME_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_EXCEPTION_EN_SKED 8:8 /* RWEVF */
#define NV_PGRAPH_EXCEPTION_EN_SKED_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_EXCEPTION_EN_SKED_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_EXCEPTION_EN_GPC 24:24 /* RWEVF */
#define NV_PGRAPH_EXCEPTION_EN_GPC_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_EXCEPTION_EN_GPC_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_EXCEPTION_EN_BE 25:25 /* RWEVF */
#define NV_PGRAPH_EXCEPTION_EN_BE_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_EXCEPTION_EN_BE_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_EXCEPTION1_EN 0x00400130 /* RWE4R */
#define NV_PGRAPH_EXCEPTION1_EN_GPC 32-1:0 /* RWEVF */
#define NV_PGRAPH_EXCEPTION1_EN_GPC_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_EXCEPTION1_EN_GPC_0_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_EXCEPTION1_EN_GPC_0_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_EXCEPTION2_EN 0x00400134 /* RWE4R */
#define NV_PGRAPH_EXCEPTION2_EN_BE 32-1:0 /* RWEVF */
#define NV_PGRAPH_EXCEPTION2_EN_BE_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_EXCEPTION2_EN_BE_0_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_EXCEPTION2_EN_BE_0_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_CLASS_ERROR 0x00400110 /* R--4R */
#define NV_PGRAPH_CLASS_ERROR_CODE 15:0 /* R-EVF */
#define NV_PGRAPH_CLASS_ERROR_CODE_NOERROR 0x00000000 /* R-E-V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_OPERATION 0x00000003 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_VALUE 0x00000004 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_ENUM 0x00000005 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_METHOD 0x00000006 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_ARGUMENT 0x00000007 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_OBJECT_CLASS 0x00000008 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_ACCESS_TYPE 0x00000009 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_REGION_TYPE 0x0000000a /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_ALIGNMENT 0x0000000b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_UNUSED_FIELD 0x0000000c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_METHOD_IN_BEGIN_END 0x0000000d /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZCULL_SUBREGION_LIMBO 0x0000000e /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_WIDTH 0x0000000f /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_HEIGHT 0x00000010 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_TARGET_FORMAT 0x00000013 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_VCAA_SETTING 0x00000016 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_ALIGNMENT 0x0000001a /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SAMPLER_SLOT 0x0000001b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_HEADER_SLOT 0x0000001c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_CONSTANT_OFFSET 0x0000001d /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_OUTPUT_COUNT_TOO_SMALL 0x00000020 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_LAYER_EXCEEDS_DEPTH 0x00000021 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHARED_MEMORY_SIZE32_K_B 0x00000022 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_I2M_RECT_OUT_OF_BOUNDS 0x00000023 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_MEM2_MEM_RECT_OUT_OF_BOUNDS 0x00000023 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_VS_INPUT_COUNT 0x00000024 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_CLEAR_REQIRES_BLOCK_LINEAR 0x00000025 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_GRF_SIZE_GRID_RASTER_DISABLED 0x00000026 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_GRF_SIZE_GRID_RASTER_SIMPLE 0x00000027 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_REGISTER_ALLOCATION 0x00000028 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_GRID_WIDTH_ZERO 0x0000002a /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_THREAD_COUNT_EXCEEDS_DIMENSIONS 0x0000002b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_CTA_MEMORY_THROTTLE_EXCEEDED 0x0000002c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_CTA_STACK_THROTTLE_EXCEEDED 0x0000002d /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_COMPUTE_MISSING_INITIALIZE 0x0000002e /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_SRC_FORMAT 0x0000002f /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_SRC_FORMAT_WITH_COLOR_KEY 0x00000030 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_DST_FORMAT 0x00000031 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_DST_FORMAT_WITH_COLOR_KEY 0x00000032 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_DST_FORMAT_WITH_OPERATION 0x00000033 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_MISMATCHED_DST_FORMAT 0x00000034 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_MISMATCHED_FORMAT_WITH_COLOR_KEY 0x00000035 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_Y1_8_X8_REQUIRES_BLOCKLINEAR 0x00000036 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_Y1_8_X8_REQUIRES_POINT_SAMPLING 0x00000037 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_MONO_PATTERN_COLOR_FORMAT_WITH_DST_FORMAT 0x00000038 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LRF_BALANCE_SM0_PS 0x00000039 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LRF_BALANCE_SM0_VS 0x0000003a /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LRF_BALANCE_SM1_PS 0x0000003b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LRF_BALANCE_SM1_VS 0x0000003c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LRF_BALANCE_SM1_GS 0x0000003d /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_OBSOLETE_PS_INPUT_VIEWPORT_INDEX_ENABLE_FIELD 0x0000003e /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PRIMITIVE_ID_SLOT 0x0000003f /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PS_REGISTER_ALLOCATION 0x00000040 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_WINDOW_OFFSET_Y 0x00000041 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_GRF_ALLOCATION 0x00000042 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LINE_WIDTH 0x00000043 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_VIEWPORT_INDEX_SLOT 0x00000044 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_SLOT 0x00000045 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_GS_SELECTS_LAYER 0x00000046 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_USER_CLIP_SLOT 0x00000047 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_POINT_SIZE_SLOT 0x00000048 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHARED_MEMORY_SIZE_PER_SM 0x00000049 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_SRGB_DST_FORMAT_FOR_SOLID_PRIM 0x0000004a /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_FP_DST_FORMAT_FOR_SOLID_PRIM 0x0000004b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_DST_FORMAT_FOR_SOLID_PRIM 0x0000004c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR2D_ILLEGAL_DST_FORMAT_FOR_PIXELS_FROM_CPU 0x0000004d /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_LINE_TOO_LONG 0x0000004e /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_SRC_LINE_TOO_LONG 0x0000004f /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DST_LINE_TOO_LONG 0x00000050 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_SRC_LINE_EXCEEDS_PITCH 0x00000051 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_SRC_LINE_EXCEEDS_NEG_PITCH 0x00000052 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DST_LINE_EXCEEDS_PITCH 0x00000053 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DST_LINE_EXCEEDS_NEG_PITCH 0x00000054 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_SRC_INLINE_NOT_PITCH 0x00000055 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_GA_TO_VA_MAPPING_UPDATE_WHILE_ENABLED 0x00000056 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PITCH_SURFACE_HEIGHT_GREATER_THAN_ONE 0x00000057 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_BAD_SRC_PIXEL_COMPONENT_REFERENCE 0x00000058 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_TARGET_COUNT 0x00000059 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_TARGET0_NOT0 0x0000005b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_WITHOUT_SEPERATE_ALPHA 0x0000005c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_WITH_PER_TARGET_BLEND 0x0000005d /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_WITH_DUAL_SOURCE 0x0000005e /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_R_TO_A_WITHOUT_ITERATED_ALPHA 0x0000005f /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_ALPHA_ILLEGAL_R_TO_A 0x00000060 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ITERATED_BLEND_WRONG_PROGRAM_SIZE 0x00000061 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS01 0x00000064 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS02 0x00000065 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS12 0x00000066 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS03 0x00000067 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS13 0x00000068 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS23 0x00000069 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS04 0x0000006a /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS14 0x0000006b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS24 0x0000006c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS34 0x0000006d /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS05 0x0000006e /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS15 0x0000006f /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS25 0x00000070 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS35 0x00000071 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS45 0x00000072 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS06 0x00000073 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS16 0x00000074 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS26 0x00000075 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS36 0x00000076 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS46 0x00000077 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS56 0x00000078 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS07 0x00000079 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS17 0x0000007a /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS27 0x0000007b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS37 0x0000007c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS47 0x0000007d /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS57 0x0000007e /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_DUPLICATE_COLOR_TARGETS67 0x0000007f /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT01 0x00000080 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT02 0x00000081 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT03 0x00000082 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT04 0x00000083 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT05 0x00000084 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT06 0x00000085 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT07 0x00000086 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT12 0x00000087 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT13 0x00000088 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT14 0x00000089 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT15 0x0000008a /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT16 0x0000008b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT17 0x0000008c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT23 0x0000008d /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT24 0x0000008e /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT25 0x0000008f /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT26 0x00000090 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT27 0x00000091 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT34 0x00000092 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT35 0x00000093 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT36 0x00000094 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT37 0x00000095 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT45 0x00000096 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT46 0x00000097 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT47 0x00000098 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT56 0x00000099 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT57 0x0000009a /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONFLICTING_MEMORY_LAYOUT67 0x0000009b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR0 0x0000009c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR1 0x0000009d /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR2 0x0000009e /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR3 0x0000009f /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR4 0x000000a0 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR5 0x000000a1 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR6 0x000000a2 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ZETA_REQUIRES_BLOCK_LINEAR7 0x000000a3 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH0 0x000000a4 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH1 0x000000a5 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH2 0x000000a6 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH3 0x000000a7 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH4 0x000000a8 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH5 0x000000a9 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH6 0x000000aa /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_PITCH7 0x000000ab /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR0 0x000000ac /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR1 0x000000ad /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR2 0x000000ae /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR3 0x000000af /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR4 0x000000b0 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR5 0x000000b1 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR6 0x000000b2 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_BLOCKLINEAR7 0x000000b3 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_REGISTER_COUNT0 0x000000b4 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_REGISTER_COUNT1 0x000000b5 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_REGISTER_COUNT2 0x000000b6 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_REGISTER_COUNT3 0x000000b7 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_REGISTER_COUNT4 0x000000b8 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_REGISTER_COUNT5 0x000000b9 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_LOCAL_MEMORY0 0x000000ba /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_LOCAL_MEMORY1 0x000000bb /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_LOCAL_MEMORY2 0x000000bc /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_ENABLES0 0x000000bd /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHADER_ENABLES1 0x000000be /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_RESTART_TOPOLOGY 0x000000bf /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_STREAM_STRIDE0 0x000000c0 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_STREAM_STRIDE1 0x000000c1 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_STREAM_STRIDE2 0x000000c2 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_STREAM_STRIDE3 0x000000c3 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHARED_LOCAL_OVERLAP 0x000000cc /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHARED_MEMORY_SIZE16_K_B 0x000000cd /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_SHARED_MEMORY_SIZE48_K_B 0x000000ce /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TWO_SIDED_LIGHTING_ILLEGAL_WITH_SM3_REORDER 0x000000cf /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_STREAM_OUTPUT_ILLEGAL_WITH_SM3_REORDER 0x000000d0 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_SM3_REORDER_WITHOUT_PIXEL_SHADER 0x000000d1 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET0_LAYER_OFFSET_VS_THIRD_DIMENSION 0x000000d2 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET1_LAYER_OFFSET_VS_THIRD_DIMENSION 0x000000d3 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET2_LAYER_OFFSET_VS_THIRD_DIMENSION 0x000000d4 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET3_LAYER_OFFSET_VS_THIRD_DIMENSION 0x000000d5 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET4_LAYER_OFFSET_VS_THIRD_DIMENSION 0x000000d6 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET5_LAYER_OFFSET_VS_THIRD_DIMENSION 0x000000d7 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET6_LAYER_OFFSET_VS_THIRD_DIMENSION 0x000000d8 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_COLOR_TARGET7_LAYER_OFFSET_VS_THIRD_DIMENSION 0x000000d9 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_ZT_LAYER_OFFSET_VS_THIRD_DIMENSION 0x000000da /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_ILLEGAL_ZT_LAYER_OFFSET_VS_DEPTH_IS_ONE 0x000000db /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR1 0x000000f4 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR2 0x000000f5 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR3 0x000000f6 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR4 0x000000f7 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR5 0x000000f8 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR6 0x000000f9 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR0_COLOR7 0x000000fa /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR1_COLOR2 0x000000fb /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR1_COLOR3 0x000000fc /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR1_COLOR4 0x000000fd /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR1_COLOR5 0x000000fe /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR1_COLOR6 0x000000ff /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR1_COLOR7 0x00000100 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR2_COLOR3 0x00000101 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR2_COLOR4 0x00000102 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR2_COLOR5 0x00000103 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR2_COLOR6 0x00000104 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR2_COLOR7 0x00000105 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR3_COLOR4 0x00000106 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR3_COLOR5 0x00000107 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR3_COLOR6 0x00000108 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR3_COLOR7 0x00000109 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR4_COLOR5 0x0000010a /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR4_COLOR6 0x0000010b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR4_COLOR7 0x0000010c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR5_COLOR6 0x0000010d /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR5_COLOR7 0x0000010e /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_COLOR6_COLOR7 0x0000010f /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR0 0x00000110 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR1 0x00000111 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR2 0x00000112 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR3 0x00000113 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR4 0x00000114 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR5 0x00000115 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR6 0x00000116 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_TARGET_DEPTH_MISMATCH_ZETA_COLOR7 0x00000117 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_MAX_PIXEL_WARP_REGISTERS 0x00000118 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_DEPTH_TEST 0x00000119 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_STENCIL_TEST 0x0000011a /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_DEPTH_BOUNDS_TEST 0x0000011b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_BLEND_WITH_DUAL_SOURCE 0x0000011c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_TARGET_COUNT 0x0000011d /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_TARGET0_NOT0 0x0000011e /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_TIR 0x0000011f /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM16X_A_A 0x00000120 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_RASTER_SAMPLES_MODE 0x00000121 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_SAMPLES 0x00000122 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION01 0x00000123 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION02 0x00000124 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION03 0x00000125 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION04 0x00000126 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION05 0x00000127 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION06 0x00000128 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION07 0x00000129 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION08 0x0000012a /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION09 0x0000012b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION10 0x0000012c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION11 0x0000012d /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION12 0x0000012e /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION13 0x0000012f /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION14 0x00000130 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_TIR_COMBINATION15 0x00000131 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_A_A_COMBINATION01 0x00000132 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_A_A_COMBINATION02 0x00000133 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_A_A_COMBINATION03 0x00000134 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_CLIPPING_COMBINATION01 0x00000135 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_CLIPPING_COMBINATION02 0x00000136 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_EARLY_Z_COMBINATION01 0x00000137 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_A_A_COMBINATION04 0x00000138 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_A_A_COMBINATION05 0x00000139 /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_A_A_COMBINATION06 0x0000013a /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_PFM_C2_C 0x0000013b /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_CONSTANT_COLOR_RENDERING_WITHOUT_PRE_PS_COVERAGE 0x0000013c /* R---V */
#define NV_PGRAPH_CLASS_ERROR_CODE_ERROR_INVALID_VPRS_COMBINATION 0x0000013d /* R---V */
#define NV_PGRAPH_NONSTALL_INTR_EN 0x00400124 /* RWE4R */
#define NV_PGRAPH_NONSTALL_INTR_EN_TRAP 1:1 /* RWEVF */
#define NV_PGRAPH_NONSTALL_INTR_EN_TRAP_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_NONSTALL_INTR_EN_TRAP_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_NONSTALL_INTR_EN_TRAP__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_NONSTALL_INTR_EN_FE_DEBUG_INTR 2:2 /* RWEVF */
#define NV_PGRAPH_NONSTALL_INTR_EN_FE_DEBUG_INTR_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_NONSTALL_INTR_EN_FE_DEBUG_INTR_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_NONSTALL_INTR_EN_FE_DEBUG_INTR__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_GRFIFO_CONTROL 0x00400500 /* RWE4R */
#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS 0:0 /* RWEVF */
#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_GRFIFO_CONTROL_ACCESS__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS 16:16 /* RWEVF */
#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_GRFIFO_CONTROL_SEMAPHORE_ACCESS__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_GRFIFO_STATUS 0x00400504 /* R--4R */
#define NV_PGRAPH_GRFIFO_STATUS_EMPTY 0:0 /* R-IVF */
#define NV_PGRAPH_GRFIFO_STATUS_EMPTY_FALSE 0x0 /* R---V */
#define NV_PGRAPH_GRFIFO_STATUS_EMPTY_TRUE 0x1 /* R-I-V */
#define NV_PGRAPH_GRFIFO_STATUS_FULL 1:1 /* R-IVF */
#define NV_PGRAPH_GRFIFO_STATUS_FULL_FALSE 0x0 /* R-I-V */
#define NV_PGRAPH_GRFIFO_STATUS_FULL_TRUE 0x1 /* R---V */
#define NV_PGRAPH_GRFIFO_STATUS_COUNT 13:8 /* R-IVF */
#define NV_PGRAPH_GRFIFO_STATUS_COUNT_0 0x0 /* R-I-V */
#define NV_PGRAPH_GRFIFO_STATUS_READ_PTR 20:16 /* R-IVF */
#define NV_PGRAPH_GRFIFO_STATUS_READ_PTR_0 0x0 /* R-I-V */
#define NV_PGRAPH_GRFIFO_STATUS_WRITE_PTR 28:24 /* R-IVF */
#define NV_PGRAPH_GRFIFO_STATUS_WRITE_PTR_0 0x0 /* R-I-V */
#define NV_PGRAPH_TRAPPED_ADDR 0x00400704 /* R--4R */
#define NV_PGRAPH_TRAPPED_ADDR_MTHD 13:2 /* R-XVF */
#define NV_PGRAPH_TRAPPED_ADDR_SUBCH 18:16 /* R-XVF */
#define NV_PGRAPH_TRAPPED_ADDR_MME_GENERATED 20:20 /* R-XVF */
#define NV_PGRAPH_TRAPPED_ADDR_MME_GENERATED_FALSE 0x0 /* R---V */
#define NV_PGRAPH_TRAPPED_ADDR_MME_GENERATED_TRUE 0x1 /* R---V */
#define NV_PGRAPH_TRAPPED_ADDR_FEPIPE 22:22 /* R-XVF */
#define NV_PGRAPH_TRAPPED_ADDR_FEPIPE_FE0 0x0 /* R---V */
#define NV_PGRAPH_TRAPPED_ADDR_FEPIPE_FE1 0x1 /* R---V */
#define NV_PGRAPH_TRAPPED_ADDR_DATAHIGH 24:24 /* R-XVF */
#define NV_PGRAPH_TRAPPED_ADDR_DATAHIGH_INVALID 0x00000000 /* R---V */
#define NV_PGRAPH_TRAPPED_ADDR_DATAHIGH_VALID 0x00000001 /* R---V */
#define NV_PGRAPH_TRAPPED_ADDR_PRIV 28:28 /* R-XUF */
#define NV_PGRAPH_TRAPPED_ADDR_PRIV_DISABLED 0x00000000 /* R---V */
#define NV_PGRAPH_TRAPPED_ADDR_PRIV_ENABLED 0x00000001 /* R---V */
#define NV_PGRAPH_TRAPPED_ADDR_STATUS 31:31 /* R-XVF */
#define NV_PGRAPH_TRAPPED_ADDR_STATUS_INVALID 0x00000001 /* R---V */
#define NV_PGRAPH_TRAPPED_ADDR_STATUS_VALID 0x00000000 /* R---V */
#define NV_PGRAPH_TRAPPED_DATA_LOW 0x00400708 /* R--4R */
#define NV_PGRAPH_TRAPPED_DATA_LOW_VALUE 31:0 /* R-XVF */
#define NV_PGRAPH_TRAPPED_DATA_HIGH 0x0040070C /* R--4R */
#define NV_PGRAPH_TRAPPED_DATA_HIGH_VALUE 31:0 /* R-XVF */
#define NV_PGRAPH_TRAPPED_DATA_MME 0x00400710 /* R--4R */
#define NV_PGRAPH_TRAPPED_DATA_MME_PC 11:0 /* R-XVF */
#define NV_PGRAPH_TRAPPED_DATA_MME_MACRO_ADDRESS 19:12 /* R-XVF */
#define NV_PGRAPH_TRAPPED_ADDR_EX 0x00400714 /* R--4R */
#define NV_PGRAPH_TRAPPED_ADDR_EX_VEID 6+23:24 /* R-XVF */
#define NV_PGRAPH_TRAPPED_ADDR_EX_VEID_INIT 0x00000000 /* R---V */
#define NV_PGRAPH_STATUS 0x00400700 /* R--4R */
#define NV_PGRAPH_STATUS_STATE 0:0 /* R-IVF */
#define NV_PGRAPH_STATUS_STATE_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_STATE_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_FE_METHOD_UPPER 1:1 /* R-IVF */
#define NV_PGRAPH_STATUS_FE_METHOD_UPPER_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_FE_METHOD_UPPER_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_FE_METHOD_LOWER 2:2 /* R-IVF */
#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_FE_METHOD_LOWER_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_FE_FUNNEL 3:3 /* R-IVF */
#define NV_PGRAPH_STATUS_FE_FUNNEL_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_FE_FUNNEL_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_FE_NOTIFY 4:4 /* R-IVF */
#define NV_PGRAPH_STATUS_FE_NOTIFY_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_FE_NOTIFY_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_SEMAPHORE 5:5 /* R-IVF */
#define NV_PGRAPH_STATUS_SEMAPHORE_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_SEMAPHORE_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_MEMFMT 6:6 /* R-IVF */
#define NV_PGRAPH_STATUS_MEMFMT_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_MEMFMT_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_CONTEXT_SWITCH 7:7 /* R-IVF */
#define NV_PGRAPH_STATUS_CONTEXT_SWITCH_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_CONTEXT_SWITCH_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_PD 8:8 /* R-IVF */
#define NV_PGRAPH_STATUS_PD_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_PD_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_PDB 9:9 /* R-IVF */
#define NV_PGRAPH_STATUS_PDB_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_PDB_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_SCC 11:11 /* R-IVF */
#define NV_PGRAPH_STATUS_SCC_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_SCC_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_SSYNC 12:12 /* R-IVF */
#define NV_PGRAPH_STATUS_SSYNC_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_SSYNC_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_CWD 13:13 /* R-IVF */
#define NV_PGRAPH_STATUS_CWD_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_CWD_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_RASTWOD 14:14 /* R-IVF */
#define NV_PGRAPH_STATUS_RASTWOD_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_RASTWOD_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_SMCARB 15:15 /* R-IVF */
#define NV_PGRAPH_STATUS_SMCARB_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_SMCARB_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_FB 17:17 /* R-IVF */
#define NV_PGRAPH_STATUS_FB_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_FB_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_SKED 18:18 /* R-IVF */
#define NV_PGRAPH_STATUS_SKED_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_SKED_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_FE_CONST 19:19 /* R-IVF */
#define NV_PGRAPH_STATUS_FE_CONST_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_FE_CONST_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_FE_GI 21:21 /* R-IVF */
#define NV_PGRAPH_STATUS_FE_GI_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_FE_GI_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_TPC_MGR 22:22 /* R-IVF */
#define NV_PGRAPH_STATUS_TPC_MGR_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_TPC_MGR_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_GPC 24:24 /* R-IVF */
#define NV_PGRAPH_STATUS_GPC_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_GPC_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_BE 25:25 /* R-IVF */
#define NV_PGRAPH_STATUS_BE_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_BE_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_FE_METHOD_UPPER_FE1 26:26 /* R-IVF */
#define NV_PGRAPH_STATUS_FE_METHOD_UPPER_FE1_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_FE_METHOD_UPPER_FE1_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_FE_NOTIFY_FE1 27:27 /* R-IVF */
#define NV_PGRAPH_STATUS_FE_NOTIFY_FE1_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS_FE_NOTIFY_FE1_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS_MASK 0x00400610 /* RWE4R */
#define NV_PGRAPH_STATUS_MASK_PD 8:8 /* RWEVF */
#define NV_PGRAPH_STATUS_MASK_PD_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_STATUS_MASK_PD_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_STATUS_MASK_PDB 9:9 /* RWEVF */
#define NV_PGRAPH_STATUS_MASK_PDB_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_STATUS_MASK_PDB_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_STATUS_MASK_SCC 11:11 /* RWEVF */
#define NV_PGRAPH_STATUS_MASK_SCC_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_STATUS_MASK_SCC_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_STATUS_MASK_SSYNC 12:12 /* RWEVF */
#define NV_PGRAPH_STATUS_MASK_SSYNC_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_STATUS_MASK_SSYNC_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_STATUS_MASK_RASTWOD 14:14 /* RWEVF */
#define NV_PGRAPH_STATUS_MASK_RASTWOD_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_STATUS_MASK_RASTWOD_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_STATUS_MASK_SMCARB 15:15 /* RWEVF */
#define NV_PGRAPH_STATUS_MASK_SMCARB_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_STATUS_MASK_SMCARB_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_STATUS_MASK_FB 17:17 /* RWEVF */
#define NV_PGRAPH_STATUS_MASK_FB_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_STATUS_MASK_FB_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_STATUS_MASK_BE 25:25 /* RWEVF */
#define NV_PGRAPH_STATUS_MASK_BE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_STATUS_MASK_BE_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_ENGINE_CONFIG 0x00400614 /* RW-4R */
#define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_3D 0:0 /* RWXUF */
#define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_3D_FALSE 0 /* ----V */
#define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_3D_TRUE 1 /* ----V */
#define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_COMPUTE 1:1 /* RWXUF */
#define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_COMPUTE_FALSE 0 /* ----V */
#define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_COMPUTE_TRUE 1 /* ----V */
#define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_I2M 2:2 /* RWXUF */
#define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_I2M_FALSE 0 /* ----V */
#define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_I2M_TRUE 1 /* ----V */
#define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_2D 3:3 /* RWXUF */
#define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_2D_FALSE 0 /* ----V */
#define NV_PGRAPH_ENGINE_CONFIG_ENGINE_SUPPORTED_2D_TRUE 1 /* ----V */
#define NV_PGRAPH_STATUS1 0x00400604 /* R--4R */
#define NV_PGRAPH_STATUS1_GPC 32-1:0 /* R-IVF */
#define NV_PGRAPH_STATUS1_GPC_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS1_GPC_0_IDLE 0x00000000 /* R---V */
#define NV_PGRAPH_STATUS1_GPC_0_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_STATUS2 0x00400608 /* R--4R */
#define NV_PGRAPH_STATUS2_BE 32-1:0 /* R-IVF */
#define NV_PGRAPH_STATUS2_BE_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_STATUS2_BE_0_IDLE 0x00000000 /* R---V */
#define NV_PGRAPH_STATUS2_BE_0_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_ENGINE_STATUS 0x0040060C /* R--4R */
#define NV_PGRAPH_ENGINE_STATUS_VALUE 0:0 /* R-IVF */
#define NV_PGRAPH_ENGINE_STATUS_VALUE_IDLE 0x00000000 /* R-I-V */
#define NV_PGRAPH_ENGINE_STATUS_VALUE_BUSY 0x00000001 /* R---V */
#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS 0x00400200 /* RW-4R */
#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS__PRIV_LEVEL_MASK 0x004001FC /* */
#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE 15:0 /* RWIVF */
#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VALUE_INIT 0x0000 /* RWI-V */
#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_BROADCAST 16:16 /* RWIVF */
#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_BROADCAST_INIT 0x0 /* RWI-V */
#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VEID 6+19:20 /* RWIVF */
#define NV_PGRAPH_PIPE_BUNDLE_ADDRESS_VEID_INIT 0x0 /* RWI-V */
#define NV_PGRAPH_PIPE_BUNDLE_DATA 0x00400204 /* RWI4R */
#define NV_PGRAPH_PIPE_BUNDLE_DATA__PRIV_LEVEL_MASK 0x004001FC /* */
#define NV_PGRAPH_PIPE_BUNDLE_DATA_VALUE 31:0 /* RWIVF */
#define NV_PGRAPH_PIPE_BUNDLE_DATA_VALUE_INIT 0x00000000 /* RWI-V */
#define NV_PGRAPH_PIPE_BUNDLE_DATA_HI 0x0040020C /* RWI4R */
#define NV_PGRAPH_PIPE_BUNDLE_DATA_HI__PRIV_LEVEL_MASK 0x004001FC /* */
#define NV_PGRAPH_PIPE_BUNDLE_DATA_HI_VALUE 31:0 /* RWIVF */
#define NV_PGRAPH_PIPE_BUNDLE_DATA_HI_VALUE_INIT 0x00000000 /* RWI-V */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG 0x00400208 /* RWI4R */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG__PRIV_LEVEL_MASK 0x004001FC /* */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_MAJOR_MODE 3:0 /* RWIVF */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_MAJOR_MODE_NONE 0x0 /* RWI-V */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_MAJOR_MODE_MEM_TO_MEMFMT 0x1 /* RW--V */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_MAJOR_MODE_TWOD 0x2 /* RW--V */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_MAJOR_MODE_THREED 0x4 /* RW--V */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_MAJOR_MODE_COMPUTE 0x8 /* RW--V */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_CURRENT_OBJECT_MAJOR_MODE 7:4 /* R-IVF */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_CURRENT_OBJECT_MAJOR_MODE_NONE 0x0 /* R-I-V */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_CURRENT_OBJECT_MAJOR_MODE_MEM_TO_MEMFMT 0x1 /* R---V */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_CURRENT_OBJECT_MAJOR_MODE_TWOD 0x2 /* R---V */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_CURRENT_OBJECT_MAJOR_MODE_THREED 0x4 /* R---V */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_CURRENT_OBJECT_MAJOR_MODE_COMPUTE 0x8 /* R---V */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE 31:31 /* RWIVF */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE_DISABLED 0x0 /* RWI-V */
#define NV_PGRAPH_PIPE_BUNDLE_CONFIG_OVERRIDE_PIPE_MODE_ENABLED 0x1 /* RW--V */
//
// --------------------------------------------------------------------------------

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// --------------------------------------------------------------------------------
//
#define NV_PGRAPH_PRI_FE_HWW_ESR 0x00404000 /* RWE4R */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INJECTED_BUNDLE_ERROR 0:0 /* R-EVF */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INJECTED_BUNDLE_ERROR_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INJECTED_BUNDLE_ERROR_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_CLASS_SUBCH_MISMATCH 1:1 /* R-EVF */
#define NV_PGRAPH_PRI_FE_HWW_ESR_CLASS_SUBCH_MISMATCH_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_CLASS_SUBCH_MISMATCH_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_SPECULATIVE_GO_IDLE 3:3 /* R-EVF */
#define NV_PGRAPH_PRI_FE_HWW_ESR_SPECULATIVE_GO_IDLE_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_SPECULATIVE_GO_IDLE_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_ILLEGAL_FE_ATOMIC_SEQ 4:4 /* R-EVF */
#define NV_PGRAPH_PRI_FE_HWW_ESR_ILLEGAL_FE_ATOMIC_SEQ_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_ILLEGAL_FE_ATOMIC_SEQ_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_ILLEGAL_SMC_MEM_PARTITIONING 5:5 /* R-EVF */
#define NV_PGRAPH_PRI_FE_HWW_ESR_ILLEGAL_SMC_MEM_PARTITIONING_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_ILLEGAL_SMC_MEM_PARTITIONING_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET 30:30 /* -WEVF */
#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_V_0 0x0 /* -WE-V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */
#define NV_PGRAPH_PRI_FE_HWW_ESR_EN 31:31 /* RWEVF */
#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_DISABLE 0x0 /* RW--V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO 0x004041B0 /* R--4R */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_CLASS 15:0 /* R-EVF */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_CLASS_0 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_SUBCH 18:16 /* R-EVF */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_SUBCH_0 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_SUBCH_1 0x1 /* R---V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_FEPIPE 19:19 /* R-EVF */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_FEPIPE_FE0 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_CLASS_SUBCH_MISMATCH_FEPIPE_FE1 0x1 /* R---V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_ILLEGAL_FE_ATOMIC_SEQ_FEPIPE 21:21 /* R-EVF */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_ILLEGAL_FE_ATOMIC_SEQ_FEPIPE_FE0 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_ILLEGAL_FE_ATOMIC_SEQ_FEPIPE_FE1 0x1 /* R---V */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_VEID 6+23:24 /* R-EVF */
#define NV_PGRAPH_PRI_FE_HWW_ESR_INFO_VEID_INIT 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_FE_CHIP_DEF_INFO 0x00404030 /* C--4R */
#define NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT 11:0 /* C--UF */
#define NV_PGRAPH_PRI_FE_CHIP_DEF_INFO_MAX_VEID_COUNT_INIT 64 /* C--UV */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_A 0x0040413C /* R--4R */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_A_OFFSET_UPPER 7:0 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_B 0x00404140 /* R--4R */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_B_OFFSET_LOWER 31:0 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_C 0x00404144 /* R--4R */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_C_PAYLOAD 31:0 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D 0x00404148 /* R--4R */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_OPERATION 3:0 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_OPERATION_RELEASE 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_OPERATION_REPORT_ONLY 0x00000002 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_OPERATION_TRAP 0x00000003 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_OPERATION_FLUSH_PENDING_WRITES 0x00000004 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION 7:4 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_WORLD 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_WORLD_ALPHA 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_WORLD_BETA 0x00000002 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_CWD 0x00000003 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_SCREEN 0x00000004 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_FE 0x00000005 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_PIPELINE_LOCATION_SCREEN_CROP 0x00000006 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_COMPARISON 8:8 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_COMPARISON_EQ 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_COMPARISON_GE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_AWAKEN_ENABLE 9:9 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_AWAKEN_ENABLE_FALSE 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_AWAKEN_ENABLE_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT 14:10 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_NONE 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_DA_VERTICES_GENERATED 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ZPASS_PIXEL_CNT 0x00000002 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_DA_PRIMITIVES_GENERATED 0x00000003 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ALPHA_BETA_CLOCKS 0x00000004 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_VS_INVOCATIONS 0x00000005 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_STREAMING_PRIMITIVES_NEEDED_MIN_SUCC 0x00000006 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_GS_INVOCATIONS 0x00000007 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_GS_PRIMITIVES_GENERATED 0x00000009 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ZCULL_STATS0 0x0000000A /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_STREAMING_PRIMITIVES_SUCCEEDED 0x0000000B /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ZCULL_STATS1 0x0000000C /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_STREAMING_PRIMITIVES_NEEDED 0x0000000D /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ZCULL_STATS2 0x0000000E /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_CLIPPER_INVOCATIONS 0x0000000F /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ZCULL_STATS3 0x00000010 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_CLIPPER_PRIMITIVES_GENERATED 0x00000011 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_VTG_PRIMITIVES_OUT 0x00000012 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_PS_INVOCATIONS 0x00000013 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_ZPASS_PIXEL_CNT64 0x00000015 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_IEEE_CLEAN_COLOR_TARGET 0x00000018 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_IEEE_CLEAN_ZETA_TARGET 0x00000019 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_STREAMING_BYTE_COUNT 0x0000001A /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_TI_INVOCATIONS 0x0000001B /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_TS_INVOCATIONS 0x0000001D /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_TOTAL_STREAMING_PRIMS_NEEDED_MIN_SUCC 0x0000001E /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_TS_PRIMITIVES_GENERATED 0x0000001F /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_STRUCTURE_SIZE 15:15 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_STRUCTURE_SIZE_FOUR_WORDS 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_STRUCTURE_SIZE_ONE_WORD 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_SUB_REPORT 18:16 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_FLUSH_DISABLE 19:19 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_FLUSH_DISABLE_FALSE 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_FLUSH_DISABLE_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_SIZE 20:20 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_SIZE_FOUR_BYTES 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_SIZE_EIGHT_BYTES 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_DWORD_NUM 21:21 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_DWORD_NUM_LOWER 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_REPORT_DWORD_NUM_UPPER 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_VEID 6+23:24 /* R-XVF */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_D_VEID_0 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_REPORT 0x0040414C /* R--4R */
#define NV_PGRAPH_PRI_FE_SEMAPHORE_STATE_REPORT_V 31:0 /* R-XVF */
#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT 0x00404154 /* RWI4R */
#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT 31:0 /* RWIVF */
#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT_INIT 0x7FFFFFFF /* RWI-V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT__PROD 0x00001800 /* RW--V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_TIMEOUT_COUNT_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_FE_PWR_MODE 0x00404170 /* RWE4R */
#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE 1:0 /* RWEVF */
#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_AUTO 0x0 /* RWE-V */
#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_SLOW 0x1 /* RW--V */
#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_ON 0x2 /* RW--V */
#define NV_PGRAPH_PRI_FE_PWR_MODE_MODE_FORCE_POWER 0x3 /* RW--V */
#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ 4:4 /* RWEVF */
#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_DONE 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_FE_PWR_MODE_REQ_SEND 0x1 /* -W--T */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO 0x00404194 /* RWI4R */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_GPM_CNT 3:0 /* RWIVF */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_GPM_CNT_INIT 0x0 /* RWI-V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_ROP_CNT 7:4 /* RWIVF */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_ROP_CNT_INIT 0x0 /* RWI-V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_MAX_GPM_ROP_CNT 11:8 /* RWIVF */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_MAX_GPM_ROP_CNT_INIT 0x7 /* RWI-V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_OUTSTANDING_GO_IDLE 13:12 /* R-IVF */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_OUTSTANDING_GO_IDLE_IS_NONE 0x0 /* R-I-V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_OUTSTANDING_GO_IDLE_IS_SINGLE 0x1 /* R---V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_OUTSTANDING_GO_IDLE_IS_ALL 0x2 /* R---V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_CNT 16:16 /* R-IVF */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_CNT_MAX 0x1 /* R---V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_SKED_CNT_INIT 0x0 /* R-I-V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_I2M_CNT 20:20 /* R-IVF */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_I2M_CNT_MAX 0x1 /* R---V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_I2M_CNT_INIT 0x0 /* R-I-V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_GFX_LAST_EMITTER_IS_GO_IDLE 24:24 /* RWIVF */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_GFX_LAST_EMITTER_IS_GO_IDLE_TRUE 0x1 /* R-I-V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_GFX_LAST_EMITTER_IS_GO_IDLE_FALSE 0x0 /* R---V */
#define NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT 0x004041C0 /* RWI4R */
#define NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT_COUNT 31:0 /* RWIVF */
#define NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT_COUNT_INIT 0x00000800 /* RWI-V */
#define NV_PGRAPH_PRI_FE_GFXP_WFI_TIMEOUT_COUNT_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_FE_CG 0x004041F0 /* RWE4R */
#define NV_PGRAPH_PRI_FE_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */
#define NV_PGRAPH_PRI_FE_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_FE_CG_IDLE_CG_DLY_CNT__PROD 0x00000006 /* RW--V */
#define NV_PGRAPH_PRI_FE_CG_IDLE_CG_EN 6:6 /* RWEVF */
#define NV_PGRAPH_PRI_FE_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_FE_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_FE_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_FE_CG_STATE_CG_EN 7:7 /* */
#define NV_PGRAPH_PRI_FE_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_FE_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_PGRAPH_PRI_FE_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_STALL_CG_DLY_CNT__PROD 0x00000006 /* */
#define NV_PGRAPH_PRI_FE_CG_STALL_CG_EN 14:14 /* RWEVF */
#define NV_PGRAPH_PRI_FE_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_FE_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_FE_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_FE_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_PGRAPH_PRI_FE_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_FE_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */
#define NV_PGRAPH_PRI_FE_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */
#define NV_PGRAPH_PRI_FE_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_FE_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_FE_CG_THROT_CLK_CNT 23:20 /* */
#define NV_PGRAPH_PRI_FE_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_PGRAPH_PRI_FE_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_PGRAPH_PRI_FE_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_THROT_CLK_EN 28:28 /* */
#define NV_PGRAPH_PRI_FE_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_FE_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_PGRAPH_PRI_FE_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_PGRAPH_PRI_FE_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_PAUSE_CG_EN 30:30 /* */
#define NV_PGRAPH_PRI_FE_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_FE_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_PAUSE_CG_EN__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_HALT_CG_EN 31:31 /* */
#define NV_PGRAPH_PRI_FE_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_FE_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG_HALT_CG_EN__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_FE_CG1 0x004041F4 /* RWE4R */
#define NV_PGRAPH_PRI_FE_CG1_MONITOR_CG_EN 0:0 /* RWEVF */
#define NV_PGRAPH_PRI_FE_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_FE_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_FE_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_FE_CG1_SLCG 27:1 /* RWEVF */
#define NV_PGRAPH_PRI_FE_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_FE_CG1_SLCG_DISABLED 0x07FFFFFF /* RWE-V */
#define NV_PGRAPH_PRI_FE_CG1_SLCG__PROD 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_FE_OBJECT_TABLE(i) (0x00404200+(i)*4) /* R--4A */
#define NV_PGRAPH_PRI_FE_OBJECT_TABLE__SIZE_1 4 /* */
#define NV_PGRAPH_PRI_FE_OBJECT_TABLE_NVCLASS 15:0 /* R--VF */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_COMPUTE(i) (0x00404210+(i)*4) /* RWI4A */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_COMPUTE__SIZE_1 2 /* */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_COMPUTE_LAST_EMITTER_IS_GO_IDLE 31:0 /* RWIVF */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_COMPUTE_LAST_EMITTER_IS_GO_IDLE_INIT 0xffffffff /* R-I-V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_COMPUTE_LAST_EMITTER_IS_GO_IDLE_TRUE 0x1 /* R---V */
#define NV_PGRAPH_PRI_FE_GO_IDLE_INFO_COMPUTE_LAST_EMITTER_IS_GO_IDLE_FALSE 0x0 /* R---V */
#define NV_PGRAPH_PRI_FE_TPC_FS(i) (0x0040A200+(i)*4) /* R--4A */
#define NV_PGRAPH_PRI_FE_TPC_FS__SIZE_1 8 /* */
#define NV_PGRAPH_PRI_FE_TPC_FS_MASK 31:0 /* R-IVF */
#define NV_PGRAPH_PRI_FE_TPC_FS_MASK_TPC_DISABLED 0x00000000 /* R-I-V */
#define NV_PGRAPH_PRI_FE_TPC_FS_MASK_TPC_ENABLED 0x00000001 /* R---V */
//
// --------------------------------------------------------------------------------

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include/ampere/ga100/pri_memfmt.ref.h Normal file
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// --------------------------------------------------------------------------------
//
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR 0x00404600 /* RWE4R */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EXTRA_INLINE_DATA 0:0 /* R-EVF */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EXTRA_INLINE_DATA_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EXTRA_INLINE_DATA_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_MISSING_INLINE_DATA 1:1 /* R-EVF */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_MISSING_INLINE_DATA_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_MISSING_INLINE_DATA_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_FEPIPE 19:19 /* R-EVF */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_FEPIPE_FE0 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_FEPIPE_FE1 0x1 /* R---V */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_VEID 6+19:20 /* R-EVF */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_VEID_INIT 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET 30:30 /* -WEVF */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_V_0 0x0 /* -WE-V */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN 31:31 /* RWEVF */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_DISABLE 0x0 /* RW--V */
#define NV_PGRAPH_PRI_MEMFMT_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */
//
// --------------------------------------------------------------------------------

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include/ampere/ga100/pri_mme.ref.h Normal file
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// --------------------------------------------------------------------------------
//
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX 0x00404488 /* RWE4R */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_NVCLASS 15:0 /* RWEVF */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_NVCLASS_INIT 0x0000 /* RWE-V */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_METHOD_ADDR 27:16 /* RWEVF */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_METHOD_ADDR_INIT 0x000 /* RWE-V */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_FEPIPE 29:29 /* RWEVF */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_FEPIPE_FE0 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_FEPIPE_FE1 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_READ 30:30 /* RWEVF */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_READ_DONE 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_READ_TRIGGER 0x1 /* -W--T */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE 31:31 /* RWEVF */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_DONE 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_INDEX_WRITE_TRIGGER 0x1 /* -W--T */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA 0x0040448C /* RWE4R */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA_V 31:0 /* RWEVF */
#define NV_PGRAPH_PRI_MME_SHADOW_RAM_DATA_V_INIT 0x0 /* RWE-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR 0x00404490 /* RWE4R */
#define NV_PGRAPH_PRI_MME_HWW_ESR_MISSING_MACRO_DATA 0:0 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_MISSING_MACRO_DATA_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_MISSING_MACRO_DATA_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_EXTRA_MACRO_DATA 1:1 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_EXTRA_MACRO_DATA_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_EXTRA_MACRO_DATA_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_OPCODE 2:2 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_OPCODE_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_OPCODE_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_BRANCH_IN_DELAY_SLOT 3:3 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_BRANCH_IN_DELAY_SLOT_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_BRANCH_IN_DELAY_SLOT_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_MAX_INSTR_LIMIT 4:4 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_MAX_INSTR_LIMIT_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_MAX_INSTR_LIMIT_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS 5:5 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INSTR_RAM_ACCESS_OUT_OF_BOUNDS_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DATA_RAM_ACCESS_OUT_OF_BOUNDS 6:6 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DATA_RAM_ACCESS_OUT_OF_BOUNDS_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DATA_RAM_ACCESS_OUT_OF_BOUNDS_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_MME_METHOD 7:7 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_MME_METHOD_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_ILLEGAL_MME_METHOD_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_DRAM_ACCESS_OUT_OF_BOUNDS 16:16 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_DRAM_ACCESS_OUT_OF_BOUNDS_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_DRAM_ACCESS_OUT_OF_BOUNDS_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_FROM_PB 17:17 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_FROM_PB_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_FROM_PB_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_ILLEGAL_FIFO_CONFIG 18:18 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_ILLEGAL_FIFO_CONFIG_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_ILLEGAL_FIFO_CONFIG_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_OVERFLOW 19:19 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_OVERFLOW_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_READ_FIFOED_OVERFLOW_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_FIFO_RESIZED_WHEN_NONIDLE 20:20 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_FIFO_RESIZED_WHEN_NONIDLE_NOT_PENDING 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_DMA_FIFO_RESIZED_WHEN_NONIDLE_PENDING 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_STOP_ON_TRAP 29:29 /* RWEVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_STOP_ON_TRAP_DISABLED 0x0 /* RWE-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_STOP_ON_TRAP_ENABLED 0x1 /* RW--V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET 30:30 /* -WEVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_V_0 0x0 /* -WE-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */
#define NV_PGRAPH_PRI_MME_HWW_ESR_EN 31:31 /* RWEVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_DISABLE 0x0 /* RW--V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_EN_ENABLE 0x1 /* RWE-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO 0x00404494 /* R--4R */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC 11:0 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC_INIT 0x000 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MACRO_ADDRESS 19:12 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_MACRO_ADDRESS_INIT 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_VEID 27:28-6 /* C--VF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_VEID_0 0x00000000 /* C---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC_VALID 28:28 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_PC_VALID_INIT 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX 0x004044A4 /* R--4R */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_DATA_FIFO_SIZE 7:0 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_DATA_FIFO_SIZE_INIT 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_LOADSOURCE 8:8 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_LOADSOURCE_MTHD 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO_EX_LOADSOURCE_DMA 0x1 /* R---V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO2 0x0040449c /* R--4R */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO2_IR 31:0 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO2_IR_INIT 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO3 0x004044A8 /* R--4R */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO3_IR 31:0 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO3_IR_INIT 0x0 /* R-E-V */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO4 0x004044AC /* R--4R */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO4_IR 31:0 /* R-EVF */
#define NV_PGRAPH_PRI_MME_HWW_ESR_INFO4_IR_INIT 0x0 /* R-E-V */
//
// --------------------------------------------------------------------------------

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include/ampere/ga100/pri_sked.ref.h Normal file
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// --------------------------------------------------------------------------------
//
#define NV_PGRAPH_PRI_SKED_CG 0x00407000 /* RWE4R */
#define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_DLY_CNT 5:0 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_DLY_CNT__PROD 0x00000002 /* RW--V */
#define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_EN 6:6 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_CG_IDLE_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_SKED_CG_STATE_CG_EN 7:7 /* */
#define NV_PGRAPH_PRI_SKED_CG_STATE_CG_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_SKED_CG_STATE_CG_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG_STATE_CG_EN__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG_STALL_CG_DLY_CNT 13:8 /* */
#define NV_PGRAPH_PRI_SKED_CG_STALL_CG_DLY_CNT_HWINIT 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG_STALL_CG_DLY_CNT__PROD 0x00000002 /* */
#define NV_PGRAPH_PRI_SKED_CG_STALL_CG_EN 14:14 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_CG_STALL_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_SKED_CG_STALL_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_CG_STALL_CG_EN__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_SKED_CG_QUIESCENT_CG_EN 15:15 /* */
#define NV_PGRAPH_PRI_SKED_CG_QUIESCENT_CG_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_SKED_CG_QUIESCENT_CG_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG_QUIESCENT_CG_EN__PROD 0x00000001 /* */
#define NV_PGRAPH_PRI_SKED_CG_WAKEUP_DLY_CNT 19:16 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_CG_WAKEUP_DLY_CNT_HWINIT 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_CG_WAKEUP_DLY_CNT__PROD 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_CNT 23:20 /* */
#define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_CNT_FULLSPEED 0x0000000f /* */
#define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_CNT__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG_DI_DT_SKEW_VAL 27:24 /* */
#define NV_PGRAPH_PRI_SKED_CG_DI_DT_SKEW_VAL_HWINIT 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG_DI_DT_SKEW_VAL__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_EN 28:28 /* */
#define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_EN__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_SW_OVER 29:29 /* */
#define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_SW_OVER_EN 0x00000001 /* */
#define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_SW_OVER_DIS 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG_THROT_CLK_SW_OVER__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG_PAUSE_CG_EN 30:30 /* */
#define NV_PGRAPH_PRI_SKED_CG_PAUSE_CG_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_SKED_CG_PAUSE_CG_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG_PAUSE_CG_EN__PROD 0x00000001 /* */
#define NV_PGRAPH_PRI_SKED_CG_HALT_CG_EN 31:31 /* */
#define NV_PGRAPH_PRI_SKED_CG_HALT_CG_EN_ENABLED 0x00000001 /* */
#define NV_PGRAPH_PRI_SKED_CG_HALT_CG_EN_DISABLED 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG_HALT_CG_EN__PROD 0x00000000 /* */
#define NV_PGRAPH_PRI_SKED_CG1 0x00407004 /* RWE4R */
#define NV_PGRAPH_PRI_SKED_CG1_MONITOR_CG_EN 0:0 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_CG1_MONITOR_CG_EN_ENABLED 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_SKED_CG1_MONITOR_CG_EN_DISABLED 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_CG1_MONITOR_CG_EN__PROD 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_CG1_SLCG 8:1 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_CG1_SLCG_DISABLED 0x000000FF /* RWE-V */
#define NV_PGRAPH_PRI_SKED_CG1_SLCG__PROD 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR 0x00407020 /* RWE4R */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK33_SCG_TYPE_GO_IDLE_RESTRICTION 0:0 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK33_SCG_TYPE_GO_IDLE_RESTRICTION_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK33_SCG_TYPE_GO_IDLE_RESTRICTION_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK34_CTA_STEER_REG_WARP 1:1 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK34_CTA_STEER_REG_WARP_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK34_CTA_STEER_REG_WARP_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK28_PCAS_WITH_SEM 2:2 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK28_PCAS_WITH_SEM_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK28_PCAS_WITH_SEM_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK27_VSPAN_OVERFLOW 3:3 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK27_VSPAN_OVERFLOW_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK27_VSPAN_OVERFLOW_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK32_VSPAN_NONEMPTY_PREEMPT 4:4 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK32_VSPAN_NONEMPTY_PREEMPT_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK32_VSPAN_NONEMPTY_PREEMPT_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK25_THROTTLED_IS_RESTRICTED 5:5 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK25_THROTTLED_IS_RESTRICTED_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK25_THROTTLED_IS_RESTRICTED_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK24_CTA_RESUME 6:6 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK24_CTA_RESUME_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK24_CTA_RESUME_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK23_CONSTANT_BUFFER_SIZE 7:7 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK23_CONSTANT_BUFFER_SIZE_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK23_CONSTANT_BUFFER_SIZE_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK36_DEPENDENCE_COUNTER_UNDERFLOW 8:8 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK36_DEPENDENCE_COUNTER_UNDERFLOW_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK36_DEPENDENCE_COUNTER_UNDERFLOW_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK02_LOCAL_MEMORY_LOW_SIZE 9:9 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK02_LOCAL_MEMORY_LOW_SIZE_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK02_LOCAL_MEMORY_LOW_SIZE_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK03_LOCAL_MEMORY_HIGH_SIZE 10:10 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK03_LOCAL_MEMORY_HIGH_SIZE_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK03_LOCAL_MEMORY_HIGH_SIZE_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK04_LOCAL_MEMORY_CRS_SIZE 11:11 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK04_LOCAL_MEMORY_CRS_SIZE_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK04_LOCAL_MEMORY_CRS_SIZE_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK05_LOCAL_MEMORY_TOTAL_SIZE 12:12 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK05_LOCAL_MEMORY_TOTAL_SIZE_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK05_LOCAL_MEMORY_TOTAL_SIZE_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK06_REGISTER_COUNT 13:13 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK06_REGISTER_COUNT_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK06_REGISTER_COUNT_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK07_OUTER_PUT 14:14 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK07_OUTER_PUT_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK07_OUTER_PUT_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK08_INNER_PUT 15:15 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK08_INNER_PUT_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK08_INNER_PUT_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK09_INNER_GET 16:16 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK09_INNER_GET_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK09_INNER_GET_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK10_OUTER_GET 17:17 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK10_OUTER_GET_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK10_OUTER_GET_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK11_TOTAL_THREADS 18:18 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK11_TOTAL_THREADS_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK11_TOTAL_THREADS_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK35_IGNORE_VEID_CACHE_LINE 19:19 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK35_IGNORE_VEID_CACHE_LINE_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK35_IGNORE_VEID_CACHE_LINE_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK13_PROGRAM_OFFSET 20:20 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK13_PROGRAM_OFFSET_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK13_PROGRAM_OFFSET_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK14_SHARED_MEMORY_SIZE 21:21 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK14_SHARED_MEMORY_SIZE_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK14_SHARED_MEMORY_SIZE_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK15_UNUSED 22:22 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK15_UNUSED_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK15_UNUSED_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK16_CTA_THREAD_DIMENSION_ZERO 23:23 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK16_CTA_THREAD_DIMENSION_ZERO_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK16_CTA_THREAD_DIMENSION_ZERO_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK17_MEMORY_WINDOW_OVERLAP 24:24 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK17_MEMORY_WINDOW_OVERLAP_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK17_MEMORY_WINDOW_OVERLAP_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK18_L1_CONFIG_TOO_SMALL 25:25 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK18_L1_CONFIG_TOO_SMALL_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK18_L1_CONFIG_TOO_SMALL_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION 26:26 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK20_GET_PUT_TOO_LARGE 27:27 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK20_GET_PUT_TOO_LARGE_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK20_GET_PUT_TOO_LARGE_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK21_CIRCULAR_QUEUE_SIZE 28:28 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK21_CIRCULAR_QUEUE_SIZE_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK21_CIRCULAR_QUEUE_SIZE_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK22_INVALIDATE_ACTIVE_QMD 29:29 /* R-EVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK22_INVALIDATE_ACTIVE_QMD_FALSE 0x00000000 /* R-E-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_SKEDCHECK22_INVALIDATE_ACTIVE_QMD_TRUE 0x00000001 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET 30:30 /* -WEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_NONACTIVE 0x0 /* -WE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_RESET_ACTIVE 0x1 /* -W--T */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN 0x00407024 /* RWE4R */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK33_SCG_TYPE_GO_IDLE_RESTRICTION 0:0 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK33_SCG_TYPE_GO_IDLE_RESTRICTION_FALSE 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK33_SCG_TYPE_GO_IDLE_RESTRICTION_TRUE 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK34_CTA_STEER_REG_WARP 1:1 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK34_CTA_STEER_REG_WARP_FALSE 0x00000000 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK34_CTA_STEER_REG_WARP_TRUE 0x00000001 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK28_PCAS_WITH_SEM 2:2 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK28_PCAS_WITH_SEM_FALSE 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK28_PCAS_WITH_SEM_TRUE 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK27_VSPAN_OVERFLOW 3:3 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK27_VSPAN_OVERFLOW_FALSE 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK27_VSPAN_OVERFLOW_TRUE 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK32_VSPAN_NONEMPTY_PREEMPT 4:4 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK32_VSPAN_NONEMPTY_PREEMPT_FALSE 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK32_VSPAN_NONEMPTY_PREEMPT_TRUE 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK25_THROTTLED_IS_RESTRICTED 5:5 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK25_THROTTLED_IS_RESTRICTED_FALSE 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK25_THROTTLED_IS_RESTRICTED_TRUE 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK24_CTA_RESUME 6:6 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK24_CTA_RESUME_FALSE 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK24_CTA_RESUME_TRUE 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK23_CONSTANT_BUFFER_SIZE 7:7 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK23_CONSTANT_BUFFER_SIZE_FALSE 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK23_CONSTANT_BUFFER_SIZE_TRUE 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK36_DEPENDENCE_COUNTER_UNDERFLOW 8:8 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK36_DEPENDENCE_COUNTER_UNDERFLOW_FALSE 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK36_DEPENDENCE_COUNTER_UNDERFLOW_TRUE 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK02_LOCAL_MEMORY_LOW_SIZE 9:9 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK02_LOCAL_MEMORY_LOW_SIZE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK02_LOCAL_MEMORY_LOW_SIZE_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK03_LOCAL_MEMORY_HIGH_SIZE 10:10 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK03_LOCAL_MEMORY_HIGH_SIZE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK03_LOCAL_MEMORY_HIGH_SIZE_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK04_LOCAL_MEMORY_CRS_SIZE 11:11 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK04_LOCAL_MEMORY_CRS_SIZE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK04_LOCAL_MEMORY_CRS_SIZE_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK05_LOCAL_MEMORY_TOTAL_SIZE 12:12 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK05_LOCAL_MEMORY_TOTAL_SIZE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK05_LOCAL_MEMORY_TOTAL_SIZE_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK06_REGISTER_COUNT 13:13 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK06_REGISTER_COUNT_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK06_REGISTER_COUNT_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK07_OUTER_PUT 14:14 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK07_OUTER_PUT_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK07_OUTER_PUT_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK08_INNER_PUT 15:15 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK08_INNER_PUT_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK08_INNER_PUT_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK09_INNER_GET 16:16 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK09_INNER_GET_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK09_INNER_GET_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK10_OUTER_GET 17:17 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK10_OUTER_GET_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK10_OUTER_GET_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK11_TOTAL_THREADS 18:18 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK11_TOTAL_THREADS_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK11_TOTAL_THREADS_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK35_IGNORE_VEID_CACHE_LINE 19:19 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK35_IGNORE_VEID_CACHE_LINE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK35_IGNORE_VEID_CACHE_LINE_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK13_PROGRAM_OFFSET 20:20 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK13_PROGRAM_OFFSET_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK13_PROGRAM_OFFSET_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK14_SHARED_MEMORY_SIZE 21:21 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK14_SHARED_MEMORY_SIZE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK14_SHARED_MEMORY_SIZE_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK15_UNUSED 22:22 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK15_UNUSED_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK15_UNUSED_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK16_CTA_THREAD_DIMENSION_ZERO 23:23 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK16_CTA_THREAD_DIMENSION_ZERO_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK16_CTA_THREAD_DIMENSION_ZERO_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK17_MEMORY_WINDOW_OVERLAP 24:24 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK17_MEMORY_WINDOW_OVERLAP_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK17_MEMORY_WINDOW_OVERLAP_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK18_L1_CONFIG_TOO_SMALL 25:25 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK18_L1_CONFIG_TOO_SMALL_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK18_L1_CONFIG_TOO_SMALL_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK19_CTA_REGISTER_CONSUMPTION 26:26 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK19_CTA_REGISTER_CONSUMPTION_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK20_GET_PUT_TOO_LARGE 27:27 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK20_GET_PUT_TOO_LARGE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK20_GET_PUT_TOO_LARGE_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK21_CIRCULAR_QUEUE_SIZE 28:28 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK21_CIRCULAR_QUEUE_SIZE_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK21_CIRCULAR_QUEUE_SIZE_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK22_INVALIDATE_ACTIVE_QMD 29:29 /* RWEVF */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK22_INVALIDATE_ACTIVE_QMD_DISABLED 0x00000000 /* RW--V */
#define NV_PGRAPH_PRI_SKED_HWW_ESR_EN_SKEDCHECK22_INVALIDATE_ACTIVE_QMD_ENABLED 0x00000001 /* RWE-V */
#define NV_PGRAPH_PRI_SKED_HWW_INFO_1 0x00407028 /* R--4R */
#define NV_PGRAPH_PRI_SKED_HWW_INFO_1_VEID 7:0 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_HWW_INFO_1_VEID_0 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_INFO_1_CWD_SLOT 15:8 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_HWW_INFO_1_CWD_SLOT_0 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_INFO_2 0x0040702c /* R--4R */
#define NV_PGRAPH_PRI_SKED_HWW_INFO_2_QMD_ID 31:0 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_HWW_INFO_2_QMD_ID_0 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_INFO_3 0x00407030 /* R--4R */
#define NV_PGRAPH_PRI_SKED_HWW_INFO_3_FROM 23:0 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_HWW_INFO_3_FROM_0 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_SKED_HWW_INFO_3_DELTA 31:24 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_HWW_INFO_3_DELTA_0 0x00000000 /* R---V */
#define NV_PGRAPH_PRI_SKED_ACTIVITY 0x00407054 /* R--4R */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_SFE 2:0 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_SFE_IDLE 0x0 /* R---V */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_PP 5:3 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_PP_IDLE 0x0 /* R---V */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_TM 8:6 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_TM_IDLE 0x0 /* R---V */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_TFL 11:9 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_TFL_IDLE 0x0 /* R---V */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_CACHE 14:12 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_CACHE_IDLE 0x0 /* R---V */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_FBI_IF 17:15 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_FBI_IF_IDLE 0x0 /* R---V */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_FBI_CORE 20:18 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_FBI_CORE_IDLE 0x0 /* R---V */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_IQ 23:21 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_IQ_IDLE 0x0 /* R---V */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_SKED_FE 31:29 /* R-XVF */
#define NV_PGRAPH_PRI_SKED_ACTIVITY_SKED_FE_IDLE 0x0 /* R---V */
#define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK(i) (0x004070a0+(i)*4) /* RWI4A */
#define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK__SIZE_1 16 /* */
#define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX0 7:0 /* RWIVF */
#define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX0_INIT 0x00000001 /* RWI-V */
#define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX1 15:8 /* RWIVF */
#define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX1_INIT 0x00000001 /* RWI-V */
#define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX2 23:16 /* RWIVF */
#define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX2_INIT 0x00000001 /* RWI-V */
#define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX3 31:24 /* RWIVF */
#define NV_PGRAPH_PRI_SKED_SUBCTX_WATERMARK_SUBCTX3_INIT 0x00000001 /* RWI-V */
//
// --------------------------------------------------------------------------------