255 lines
11 KiB
C++
255 lines
11 KiB
C++
#include <cstdint>
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#include <cstddef>
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#include <cstring>
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#include <cstdio>
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#include "../common/uarch.hpp"
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#include "../common/global.hpp"
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#include "../common/gpu.hpp"
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#include "chips.hpp"
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#include "pci.hpp"
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#include "cpuid.hpp"
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// Data not available
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#define NA -1
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// Unknown manufacturing process
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#define UNK -1
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/*
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* Mapping between iGPU and CPU uarchs
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* -----------------------------------
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* Gen6: Sandy Bridge (2th Gen)
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* Gen7: Ivy Brdige (3th Gen)
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* Gen7.5: Haswell (4th Gen)
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* Gen8: Broadwell (5th Gen)
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* Gen9: Skylake (6th Gen)
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* Gen9.5: Kaby Lake
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* Gen11: Ice Lake (10th Gen)
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* Gen12: Rocket/Tiger Lake (11th Gen)
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*/
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enum {
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UARCH_UNKNOWN,
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UARCH_GEN6,
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UARCH_GEN7,
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UARCH_GEN7_5,
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UARCH_GEN8,
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UARCH_GEN9,
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UARCH_GEN9_5,
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UARCH_GEN11,
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UARCH_GEN12_RKL,
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UARCH_GEN12_TGL,
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};
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static const char *uarch_str[] = {
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/*[ARCH_UNKNOWN = */ STRING_UNKNOWN,
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/*[ARCH_GEN6] = */ "Gen6",
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/*[ARCH_GEN7] = */ "Gen7",
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/*[ARCH_GEN7_5] = */ "Gen7.5",
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/*[ARCH_GEN8] = */ "Gen8",
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/*[ARCH_GEN9] = */ "Gen9",
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/*[ARCH_GEN9_5] = */ "Gen9.5",
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/*[ARCH_GEN11] = */ "Gen11",
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/*[ARCH_GEN12_RKL] = */ "Gen12",
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/*[ARCH_GEN12_TGL] = */ "Gen12"
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};
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// Graphic Tiers (GT)
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enum {
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GT_UNKNOWN,
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GT1,
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GT1_4, // GT1 with 4 EUs
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GT1_5,
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GT2,
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GT3,
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GT3e,
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GT4e
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};
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static const char *gt_str[] = {
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/*[GT_UNKNOWN] = */ STRING_UNKNOWN,
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/*[GT1] = */ "GT1",
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/*[GT1_4] = */ "GT1",
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/*[GT1_5] = */ "GT1.5",
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/*[GT2] = */ "GT2",
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/*[GT3] = */ "GT3",
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/*[GT3e] = */ "GT3e",
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/*[GT4e] = */ "GT4e",
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};
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#define CHECK_UARCH_START if (false) {}
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#define CHECK_UARCH(arch, chip_, str, uarch, gt, process) \
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else if (arch->chip == chip_) fill_uarch(arch, str, uarch, gt, process);
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#define CHECK_UARCH_END else { printBug("map_chip_to_uarch_intel: Unknown chip id: %d", arch->chip); fill_uarch(arch, STRING_UNKNOWN, UARCH_UNKNOWN, GT_UNKNOWN, 0); }
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#define CHECK_TOPO_START if (false) {}
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#define CHECK_TOPO(topo, arch, uarch_, gt_, eu_sub, sub, sli) \
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else if(arch->uarch == uarch_ && arch->gt == gt_) fill_topo(topo, eu_sub, sub, sli);
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#define CHECK_TOPO_END else { printBug("get_topology_info: Invalid uarch and gt combination: '%s' and '%s'", arch->chip_str, get_str_gt(arch)); fill_topo(topo, UNK, UNK, UNK); }
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void fill_topo(struct topology_i* topo_i, int32_t eu_sub, int32_t sub, int32_t sli) {
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topo_i->slices = sli;
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topo_i->subslices = sub;
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topo_i->eu_subslice = eu_sub;
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}
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void fill_uarch(struct uarch* arch, char const *str, MICROARCH u, int32_t gt, uint32_t process) {
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arch->chip_str = (char *) emalloc(sizeof(char) * (strlen(str)+1));
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strcpy(arch->chip_str, str);
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arch->uarch = u;
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arch->process = process;
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arch->gt = gt;
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}
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void map_chip_to_uarch_intel(struct uarch* arch) {
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CHECK_UARCH_START
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// Gen6
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CHECK_UARCH(arch, CHIP_HD_SANDY, "HD Graphics (Sandy Bridge)", UARCH_GEN6, GT1, 32)
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CHECK_UARCH(arch, CHIP_HD_2000, "HD Graphics 2000", UARCH_GEN6, GT1, 32)
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CHECK_UARCH(arch, CHIP_HD_3000, "HD Graphics 3000", UARCH_GEN6, GT2, 32)
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// Gen7
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CHECK_UARCH(arch, CHIP_HD_IVY, "HD Graphics (Ivy Bridge)", UARCH_GEN7, GT1, 22)
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CHECK_UARCH(arch, CHIP_HD_SILVER, "HD Graphics (Silvermont)", UARCH_GEN7, GT1_4, 22)
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CHECK_UARCH(arch, CHIP_HD_2500, "HD Graphics 2500", UARCH_GEN7, GT1, 22)
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CHECK_UARCH(arch, CHIP_HD_4000, "HD Graphics 4000", UARCH_GEN7, GT2, 22)
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CHECK_UARCH(arch, CHIP_HD_P4000, "HD Graphics P4000", UARCH_GEN7, GT2, 22)
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// Gen7.5
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CHECK_UARCH(arch, CHIP_HD_HASWELL, "HD Graphics (Haswell)", UARCH_GEN7_5, GT1, 22)
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CHECK_UARCH(arch, CHIP_HD_4200, "HD Graphics 4200", UARCH_GEN7_5, GT2, 22)
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CHECK_UARCH(arch, CHIP_HD_4400, "HD Graphics 4400", UARCH_GEN7_5, GT2, 22)
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CHECK_UARCH(arch, CHIP_HD_4600, "HD Graphics 4600", UARCH_GEN7_5, GT2, 22)
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CHECK_UARCH(arch, CHIP_HD_P4600, "HD Graphics P4600", UARCH_GEN7_5, GT2, 22)
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CHECK_UARCH(arch, CHIP_IRIS_5100, "HD Iris 5100", UARCH_GEN7_5, GT3, 22)
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CHECK_UARCH(arch, CHIP_IRISP_5200, "HD Iris Pro 5200", UARCH_GEN7_5, GT3, 22)
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CHECK_UARCH(arch, CHIP_IRISP_P5200, "HD Iris Pro P5200", UARCH_GEN7_5, GT3, 22)
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// Gen8
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CHECK_UARCH(arch, CHIP_HD_BROADWELL, "HD Graphics (Broadwell)", UARCH_GEN8, GT1, 14)
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CHECK_UARCH(arch, CHIP_HD_5300, "HD Graphics 5300", UARCH_GEN8, GT2, 14)
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CHECK_UARCH(arch, CHIP_HD_5500, "HD Graphics 5500", UARCH_GEN8, GT2, 14)
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CHECK_UARCH(arch, CHIP_HD_5600, "HD Graphics 5600", UARCH_GEN8, GT2, 14)
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CHECK_UARCH(arch, CHIP_HD_P5700, "HD Graphics P5700", UARCH_GEN8, GT2, 14)
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CHECK_UARCH(arch, CHIP_HD_6000, "HD Graphics 6000", UARCH_GEN8, GT3, 14)
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CHECK_UARCH(arch, CHIP_IRIS_6100, "Iris Graphics 6100", UARCH_GEN8, GT3, 14)
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CHECK_UARCH(arch, CHIP_IRISP_6200, "Iris Pro Graphics 6200", UARCH_GEN8, GT3, 14)
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CHECK_UARCH(arch, CHIP_IRISP_P6300, "Iris Pro Graphics P6300", UARCH_GEN8, GT3, 14)
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// Gen9
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CHECK_UARCH(arch, CHIP_HD_510, "HD Graphics 510", UARCH_GEN9, GT1, 14)
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CHECK_UARCH(arch, CHIP_HD_515, "HD Graphics 515", UARCH_GEN9, GT2, 14)
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CHECK_UARCH(arch, CHIP_HD_520, "HD Graphics 520", UARCH_GEN9, GT2, 14)
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CHECK_UARCH(arch, CHIP_HD_530, "HD Graphics 530", UARCH_GEN9, GT2, 14)
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CHECK_UARCH(arch, CHIP_HD_P530, "HD Graphics P530", UARCH_GEN9, GT2, 14)
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// Gen9.5
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CHECK_UARCH(arch, CHIP_UHD_600, "UHD Graphics 600", UARCH_GEN9_5, GT1, 14)
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CHECK_UARCH(arch, CHIP_UHD_605, "UHD Graphics 605", UARCH_GEN9_5, GT1_5, 14)
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CHECK_UARCH(arch, CHIP_UHD_620, "UHD Graphics 620", UARCH_GEN9_5, GT2, 14)
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CHECK_UARCH(arch, CHIP_UHD_630, "UHD Graphics 630", UARCH_GEN9_5, GT2, 14)
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CHECK_UARCH(arch, CHIP_HD_610, "HD Graphics 610", UARCH_GEN9_5, GT1, 14)
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CHECK_UARCH(arch, CHIP_HD_615, "HD Graphics 615", UARCH_GEN9_5, GT2, 14)
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CHECK_UARCH(arch, CHIP_HD_630, "HD Graphics 630", UARCH_GEN9_5, GT2, 14)
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CHECK_UARCH(arch, CHIP_HD_P630, "HD Graphics P630", UARCH_GEN9_5, GT2, 14)
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CHECK_UARCH(arch, CHIP_IRISP_640, "Iris Plus Graphics 640", UARCH_GEN9_5, GT3e, 14)
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CHECK_UARCH(arch, CHIP_IRISP_640, "Iris Plus Graphics 650", UARCH_GEN9_5, GT3e, 14)
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// Gen11
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CHECK_UARCH(arch, CHIP_UHD_G1, "UHD Graphics G1", UARCH_GEN11, GT1, 10)
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CHECK_UARCH(arch, CHIP_IRISP_G4, "Iris Plus Graphics G4", UARCH_GEN11, GT1_5, 10)
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CHECK_UARCH(arch, CHIP_IRISP_G7, "Iris Plus Graphics G7", UARCH_GEN11, GT2, 10)
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// Gen12
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CHECK_UARCH(arch, CHIP_UHD_730, "UHD Graphics 730", UARCH_GEN12_RKL, GT1, 14)
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CHECK_UARCH(arch, CHIP_UHD_750, "UHD Graphics 750", UARCH_GEN12_RKL, GT1, 14)
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CHECK_UARCH(arch, CHIP_XE_G4, "Iris Xe G4", UARCH_GEN12_TGL, GT2, 10)
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CHECK_UARCH(arch, CHIP_XE_G7, "Iris Xe G7", UARCH_GEN12_TGL, GT2, 10)
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CHECK_UARCH_END
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}
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const char* get_str_uarch_intel(struct uarch* arch) {
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return uarch_str[arch->uarch];
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}
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const char* get_str_gt(struct uarch* arch) {
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return gt_str[arch->gt];
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}
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struct uarch* get_uarch_from_pci(struct pci* pci) {
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struct uarch* arch = (struct uarch*) emalloc(sizeof(struct uarch));
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arch->chip_str = NULL;
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arch->chip = get_chip_from_pci_intel(pci);
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if(arch->chip == CHIP_UNKNOWN_INTEL) {
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return NULL;
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}
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else {
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map_chip_to_uarch_intel(arch);
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return arch;
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}
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}
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char* get_name_from_uarch(struct uarch* arch) {
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char* name = (char *) emalloc(sizeof(char) * (strlen(arch->chip_str) + 6 + 1));
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sprintf(name, "%s", arch->chip_str);
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return name;
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}
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/*
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* Refs:
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* Gen6: https://en.wikipedia.org/wiki/List_of_Intel_graphics_processing_units#Gen6
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* Gen7/7.5: https://en.wikipedia.org/wiki/List_of_Intel_graphics_processing_units#Gen7
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"The Compute Architecture of Intel Processor Graphics Gen7.5, v1.0"
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* Gen8: https://en.wikipedia.org/wiki/List_of_Intel_graphics_processing_units#Gen8
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"The Compute Architecture of Intel Processor Graphics Gen8, v1.1"
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* Gen9: https://en.wikichip.org/wiki/intel/microarchitectures/gen9#Configuration
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"The Compute Architecture of Intel Processor Graphics Gen9, v1.0"
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* Gen9.5: https://en.wikichip.org/wiki/intel/microarchitectures/gen9.5#Configuration
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* Also: https://www.techpowerup.com/gpu-specs/intel-rocket-lake-gt1.g993
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*/
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struct topology_i* get_topology_info(struct uarch* arch) {
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struct topology_i* topo = (struct topology_i*) emalloc(sizeof(struct topology_i));
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// Syntax: (EU per subslice, Subslices, Slices)
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CHECK_TOPO_START
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// Gen6
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CHECK_TOPO(topo, arch, UARCH_GEN6, GT1, 6, 1, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN6, GT2, 6, 2, 1)
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// Gen7
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CHECK_TOPO(topo, arch, UARCH_GEN7, GT1_4, 4, 1, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN7, GT1, 6, 1, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN7, GT2, 8, 2, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN7, GT3, 6, 1, 1)
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// Gen7.5
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CHECK_TOPO(topo, arch, UARCH_GEN7_5, GT1, 10, 1, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN7_5, GT2, 10, 2, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN7_5, GT3, 10, 4, 1)
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// Gen8
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CHECK_TOPO(topo, arch, UARCH_GEN8, GT1, 6, 2, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN8, GT2, 8, 3, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN8, GT3, 8, 6, 2)
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// Gen9
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CHECK_TOPO(topo, arch, UARCH_GEN9, GT1, 6, 2, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN9, GT2, 8, 3, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN9, GT3, 8, 6, 2)
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CHECK_TOPO(topo, arch, UARCH_GEN9, GT4e, 8, 9, 3)
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// Gen9.5
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CHECK_TOPO(topo, arch, UARCH_GEN9_5, GT1, 6, 2, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN9_5, GT1_5, 6, 3, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN9_5, GT2, 8, 3, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN9_5, GT3, 8, 6, 2)
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CHECK_TOPO(topo, arch, UARCH_GEN9_5, GT3e, 8, 6, 2) // Same as GT3, but has eDRAM cache
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// Gen11
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CHECK_TOPO(topo, arch, UARCH_GEN11, GT1, 8, 4, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN11, GT1_5, 8, 6, 1)
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CHECK_TOPO(topo, arch, UARCH_GEN11, GT2, 8, 8, 1)
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// Gen12
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CHECK_TOPO(topo, arch, UARCH_GEN12_RKL, GT1, 16, 2, 1)
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else if(arch->uarch == UARCH_GEN12_TGL && arch->gt == GT2) {
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// Special case: TigerLake GT2 needs to check if is i5/i7 to know the exact topology
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if(is_corei5()) {
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fill_topo(topo, 10, 8, 1); // Should be 80 EUs, but not sure about the organization
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}
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else {
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fill_topo(topo, 16, 6, 1);
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}
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}
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CHECK_TOPO_END
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return topo;
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}
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