[v0.25] Add missing Ampere GPU chips and new uarchs: ada and hopper

.gitignore

@@ -1 +1,2 @@
 gpufetch
+build/

CMakeLists.txt

@@ -45,6 +45,8 @@ if(NOT ${PCIUTILS_FOUND})
 else()
   include_directories(${PCIUTILS_INCLUDE_DIR})
   link_libraries(${PCIUTILS_LIBRARIES})
+  # Needed for linking libpci in FreeBSD
+  link_directories(/usr/local/lib/)
 endif()
 
 add_executable(gpufetch ${COMMON_DIR}/main.cpp ${COMMON_DIR}/args.cpp ${COMMON_DIR}/gpu.cpp ${COMMON_DIR}/pci.cpp ${COMMON_DIR}/sort.cpp ${COMMON_DIR}/global.cpp ${COMMON_DIR}/printer.cpp ${COMMON_DIR}/master.cpp ${COMMON_DIR}/uarch.cpp)

build.sh

@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/bin/sh
 
 # gpufetch build script
 set -e
@@ -27,6 +27,13 @@ fi
 # cmake -DCMAKE_BUILD_TYPE=$BUILD_TYPE -DENABLE_INTEL_BACKEND=OFF ..
 
 cmake -DCMAKE_BUILD_TYPE=$BUILD_TYPE ..
+
+os=$(uname)
+if [ "$os" == 'Linux' ]; then
   make -j$(nproc)
+elif [ "$os" == 'FreeBSD' ]; then
+  gmake -j4
+fi
+
 cd -
 ln -s build/gpufetch .

src/common/args.hpp

@@ -1,6 +1,8 @@
 #ifndef __ARGS__
 #define __ARGS__
 
+#include <cstdint>
+
 struct color {
   int32_t R;
   int32_t G;

src/common/main.cpp

@@ -8,7 +8,7 @@
 #include "../cuda/cuda.hpp"
 #include "../cuda/uarch.hpp"
 
-static const char* VERSION = "0.24";
+static const char* VERSION = "0.25";
 
 void print_help(char *argv[]) {
   const char **t = args_str;
@@ -71,6 +71,11 @@ int main(int argc, char* argv[]) {
 
   set_log_level(verbose_enabled());
 
+  int idx = get_gpu_idx();
+  if(!gpu_idx_valid(idx)) {
+    return EXIT_FAILURE;
+  }
+
   struct gpu_list* list = get_gpu_list();
   if(list_gpus()) {
     return print_gpus_list(list);
@@ -86,7 +91,7 @@ int main(int argc, char* argv[]) {
     return EXIT_FAILURE;
   }
 
-  struct gpu_info* gpu = get_gpu_info(list, get_gpu_idx());
+  struct gpu_info* gpu = get_gpu_info(list, idx);
   if(gpu == NULL)
     return EXIT_FAILURE;
 

src/common/master.cpp

@@ -5,6 +5,7 @@
 #include "global.hpp"
 #include "colors.hpp"
 #include "master.hpp"
+#include "args.hpp"
 #include "../cuda/cuda.hpp"
 #include "../intel/intel.hpp"
 
@@ -80,9 +81,19 @@ int get_num_gpus_available(struct gpu_list* list) {
   return list->num_gpus;
 }
 
+bool gpu_idx_valid(int idx) {
+  if(idx < 0) {
+    printErr("Specified GPU index is out of range: %d. ", idx);
+    printf("Run gpufetch with the --%s option to check out valid GPU indexes\n", args_str[ARG_LIST]);
+    return false;
+  }
+  return true;
+}
+
 struct gpu_info* get_gpu_info(struct gpu_list* list, int idx) {
   if(idx >= list->num_gpus || idx < 0) {
     printErr("Specified GPU index is out of range: %d", idx);
+    printf("Run gpufetch with the --%s option to check out valid GPU indexes\n", args_str[ARG_LIST]);
     return NULL;
   }
   return list->gpus[idx];

src/common/master.hpp

@@ -9,6 +9,7 @@ struct gpu_list* get_gpu_list();
 bool print_gpus_list(struct gpu_list* list);
 int get_num_gpus_available(struct gpu_list* list);
 void print_enabled_backends();
+bool gpu_idx_valid(int idx);
 struct gpu_info* get_gpu_info(struct gpu_list* list, int idx);
 
 #endif

src/common/pci.cpp

@@ -100,7 +100,8 @@ void print_gpus_list_pci() {
 
   for(struct pci_dev *dev=devices; dev != NULL; dev=dev->next) {
     if(dev->device_class == CLASS_VGA_CONTROLLER) {
-      printf("- GPU %d: ", i);
+      printf("- GPU %d:\n", i);
+      printf("  * Vendor: ");
       if(dev->vendor_id == PCI_VENDOR_ID_NVIDIA) {
         printf("NVIDIA");
       }
@@ -110,7 +111,11 @@ void print_gpus_list_pci() {
       else if(dev->vendor_id == PCI_VENDOR_ID_AMD) {
         printf("AMD");
       }
-      printf("%.4x:%.4x\n", dev->vendor_id, dev->device_id);
+      else {
+        printf("Unknown");
+      }
+      printf("\n  * PCI id: %.4x:%.4x\n", dev->vendor_id, dev->device_id);
+      i++;
     }
   }
 }

src/cuda/chips.hpp

@@ -5,6 +5,10 @@ typedef uint32_t GPUCHIP;
 
 enum {
   CHIP_UNKNOWN_CUDA,
+  CHIP_AD102,
+  CHIP_AD102GL,
+  CHIP_AD104,
+  CHIP_AD104GL,
   CHIP_G80,
   CHIP_G80GL,
   CHIP_G84,
@@ -37,6 +41,9 @@ enum {
   CHIP_GA100GL,
   CHIP_GA102,
   CHIP_GA102GL,
+  CHIP_GA103,
+  CHIP_GA103GLM,
+  CHIP_GA103M,
   CHIP_GA104,
   CHIP_GA104GL,
   CHIP_GA104GLM,
@@ -45,6 +52,7 @@ enum {
   CHIP_GA106M,
   CHIP_GA107,
   CHIP_GA107BM,
+  CHIP_GA107GL,
   CHIP_GA107GLM,
   CHIP_GA107M,
   CHIP_GF100,
@@ -71,6 +79,7 @@ enum {
   CHIP_GF117M,
   CHIP_GF119,
   CHIP_GF119M,
+  CHIP_GH100,
   CHIP_GK104,
   CHIP_GK104GL,
   CHIP_GK104GLM,
@@ -166,7 +175,7 @@ enum {
   CHIP_TU117BM,
   CHIP_TU117GL,
   CHIP_TU117GLM,
-  CHIP_TU117M,
+  CHIP_TU117M
 };
 
 #endif

src/cuda/cuda.cpp

@@ -118,16 +118,18 @@ struct gpu_info* get_gpu_info_cuda(struct pci_dev *devices, int gpu_idx) {
 
   int num_gpus = -1;
   cudaError_t err = cudaSuccess;
-  if ((err = cudaGetDeviceCount(&num_gpus)) != cudaSuccess) {
+  err = cudaGetDeviceCount(&num_gpus);
-    printErr("%s: %s", cudaGetErrorName(err), cudaGetErrorString(err));
-    return NULL;
-  }
 
   if(gpu_idx == 0) {
-    printf("\r");
+    printf("\r%*c\r", (int) strlen(CUDA_DRIVER_START_WARNING), ' ');
     fflush(stdout);
   }
 
+  if(err != cudaSuccess) {
+    printErr("%s: %s", cudaGetErrorName(err), cudaGetErrorString(err));
+    return NULL;
+  }
+
   if(num_gpus <= 0) {
     printErr("No CUDA capable devices found!");
     return NULL;

src/cuda/pci.cpp

@@ -8,7 +8,7 @@
 #define CHECK_PCI_START if (false) {}
 #define CHECK_PCI(pci, id, chip) \
    else if (pci->device_id == id) return chip;
-#define CHECK_PCI_END else { printBug("Unkown CUDA device id: 0x%.4X", pci->device_id); return CHIP_UNKNOWN_CUDA; }
+#define CHECK_PCI_END else { printBug("Unknown CUDA device id: 0x%.4X", pci->device_id); return CHIP_UNKNOWN_CUDA; }
 
 /*
  * pci ids were retrieved using https://github.com/pciutils/pciids
@@ -21,61 +21,110 @@
 
 GPUCHIP get_chip_from_pci_cuda(struct pci* pci) {
   CHECK_PCI_START
+  CHECK_PCI(pci, 0x27b8, CHIP_AD104GL)
+  CHECK_PCI(pci, 0x2785, CHIP_AD104)
+  CHECK_PCI(pci, 0x26b8, CHIP_AD102GL)
+  CHECK_PCI(pci, 0x26b5, CHIP_AD102GL)
+  CHECK_PCI(pci, 0x26b1, CHIP_AD102GL)
+  CHECK_PCI(pci, 0x2684, CHIP_AD102)
+  CHECK_PCI(pci, 0x25fa, CHIP_GA107)
+  CHECK_PCI(pci, 0x25f9, CHIP_GA107)
   CHECK_PCI(pci, 0x25e5, CHIP_GA107BM)
   CHECK_PCI(pci, 0x25e2, CHIP_GA107BM)
   CHECK_PCI(pci, 0x25e0, CHIP_GA107BM)
+  CHECK_PCI(pci, 0x25bb, CHIP_GA107GLM)
+  CHECK_PCI(pci, 0x25ba, CHIP_GA107GLM)
+  CHECK_PCI(pci, 0x25b9, CHIP_GA107GLM)
   CHECK_PCI(pci, 0x25b8, CHIP_GA107GLM)
+  CHECK_PCI(pci, 0x25b6, CHIP_GA107GL)
   CHECK_PCI(pci, 0x25b5, CHIP_GA107GLM)
   CHECK_PCI(pci, 0x25af, CHIP_GA107)
+  CHECK_PCI(pci, 0x25aa, CHIP_GA107M)
+  CHECK_PCI(pci, 0x25a9, CHIP_GA107M)
+  CHECK_PCI(pci, 0x25a7, CHIP_GA107M)
+  CHECK_PCI(pci, 0x25a6, CHIP_GA107M)
   CHECK_PCI(pci, 0x25a5, CHIP_GA107M)
   CHECK_PCI(pci, 0x25a4, CHIP_GA107)
+  CHECK_PCI(pci, 0x25a3, CHIP_GA107)
   CHECK_PCI(pci, 0x25a2, CHIP_GA107M)
   CHECK_PCI(pci, 0x25a0, CHIP_GA107M)
   CHECK_PCI(pci, 0x2583, CHIP_GA107)
+  CHECK_PCI(pci, 0x2571, CHIP_GA106)
   CHECK_PCI(pci, 0x2563, CHIP_GA106M)
+  CHECK_PCI(pci, 0x2561, CHIP_GA106M)
   CHECK_PCI(pci, 0x2560, CHIP_GA106M)
+  CHECK_PCI(pci, 0x2544, CHIP_GA106)
+  CHECK_PCI(pci, 0x2531, CHIP_GA106)
   CHECK_PCI(pci, 0x252f, CHIP_GA106)
   CHECK_PCI(pci, 0x2523, CHIP_GA106M)
+  CHECK_PCI(pci, 0x2521, CHIP_GA106M)
   CHECK_PCI(pci, 0x2520, CHIP_GA106M)
+  CHECK_PCI(pci, 0x2508, CHIP_GA106)
+  CHECK_PCI(pci, 0x2507, CHIP_GA106)
   CHECK_PCI(pci, 0x2505, CHIP_GA106)
   CHECK_PCI(pci, 0x2504, CHIP_GA106)
   CHECK_PCI(pci, 0x2503, CHIP_GA106)
   CHECK_PCI(pci, 0x2501, CHIP_GA106)
+  CHECK_PCI(pci, 0x24fa, CHIP_GA104)
+  CHECK_PCI(pci, 0x24e0, CHIP_GA104M)
+  CHECK_PCI(pci, 0x24df, CHIP_GA104M)
   CHECK_PCI(pci, 0x24dd, CHIP_GA104M)
   CHECK_PCI(pci, 0x24dc, CHIP_GA104M)
+  CHECK_PCI(pci, 0x24c9, CHIP_GA104)
   CHECK_PCI(pci, 0x24bf, CHIP_GA104)
+  CHECK_PCI(pci, 0x24bb, CHIP_GA104GLM)
+  CHECK_PCI(pci, 0x24ba, CHIP_GA104GLM)
+  CHECK_PCI(pci, 0x24b9, CHIP_GA104GLM)
   CHECK_PCI(pci, 0x24b8, CHIP_GA104GLM)
   CHECK_PCI(pci, 0x24b7, CHIP_GA104GLM)
   CHECK_PCI(pci, 0x24b6, CHIP_GA104GLM)
+  CHECK_PCI(pci, 0x24b1, CHIP_GA104GL)
   CHECK_PCI(pci, 0x24b0, CHIP_GA104GL)
   CHECK_PCI(pci, 0x24af, CHIP_GA104)
   CHECK_PCI(pci, 0x24ad, CHIP_GA104)
   CHECK_PCI(pci, 0x24ac, CHIP_GA104)
+  CHECK_PCI(pci, 0x24a0, CHIP_GA104)
   CHECK_PCI(pci, 0x249f, CHIP_GA104M)
   CHECK_PCI(pci, 0x249d, CHIP_GA104M)
   CHECK_PCI(pci, 0x249c, CHIP_GA104M)
   CHECK_PCI(pci, 0x248a, CHIP_GA104)
   CHECK_PCI(pci, 0x2489, CHIP_GA104)
   CHECK_PCI(pci, 0x2488, CHIP_GA104)
+  CHECK_PCI(pci, 0x2487, CHIP_GA104)
   CHECK_PCI(pci, 0x2486, CHIP_GA104)
   CHECK_PCI(pci, 0x2484, CHIP_GA104)
   CHECK_PCI(pci, 0x2483, CHIP_GA104)
   CHECK_PCI(pci, 0x2482, CHIP_GA104)
+  CHECK_PCI(pci, 0x2460, CHIP_GA103M)
+  CHECK_PCI(pci, 0x2438, CHIP_GA103GLM)
+  CHECK_PCI(pci, 0x2420, CHIP_GA103M)
+  CHECK_PCI(pci, 0x2414, CHIP_GA103)
+  CHECK_PCI(pci, 0x2336, CHIP_GH100)
+  CHECK_PCI(pci, 0x2331, CHIP_GH100)
+  CHECK_PCI(pci, 0x2321, CHIP_GH100)
+  CHECK_PCI(pci, 0x2302, CHIP_GH100)
+  CHECK_PCI(pci, 0x228e, CHIP_GA106)
   CHECK_PCI(pci, 0x228b, CHIP_GA104)
   CHECK_PCI(pci, 0x223f, CHIP_GA102GL)
+  CHECK_PCI(pci, 0x2238, CHIP_GA102GL)
   CHECK_PCI(pci, 0x2237, CHIP_GA102GL)
   CHECK_PCI(pci, 0x2236, CHIP_GA102GL)
   CHECK_PCI(pci, 0x2235, CHIP_GA102GL)
+  CHECK_PCI(pci, 0x2233, CHIP_GA102GL)
+  CHECK_PCI(pci, 0x2232, CHIP_GA102GL)
   CHECK_PCI(pci, 0x2231, CHIP_GA102GL)
   CHECK_PCI(pci, 0x2230, CHIP_GA102GL)
   CHECK_PCI(pci, 0x222f, CHIP_GA102)
   CHECK_PCI(pci, 0x222b, CHIP_GA102)
   CHECK_PCI(pci, 0x2216, CHIP_GA102)
   CHECK_PCI(pci, 0x220d, CHIP_GA102)
+  CHECK_PCI(pci, 0x220a, CHIP_GA102)
   CHECK_PCI(pci, 0x2208, CHIP_GA102)
+  CHECK_PCI(pci, 0x2207, CHIP_GA102)
   CHECK_PCI(pci, 0x2206, CHIP_GA102)
   CHECK_PCI(pci, 0x2205, CHIP_GA102)
   CHECK_PCI(pci, 0x2204, CHIP_GA102)
+  CHECK_PCI(pci, 0x2203, CHIP_GA102)
   CHECK_PCI(pci, 0x2200, CHIP_GA102)
   CHECK_PCI(pci, 0x21d1, CHIP_TU116BM)
   CHECK_PCI(pci, 0x21c4, CHIP_TU116)
@@ -90,27 +139,45 @@ GPUCHIP get_chip_from_pci_cuda(struct pci* pci) {
   CHECK_PCI(pci, 0x2184, CHIP_TU116)
   CHECK_PCI(pci, 0x2183, CHIP_TU116)
   CHECK_PCI(pci, 0x2182, CHIP_TU116)
+  CHECK_PCI(pci, 0x20f6, CHIP_GA100)
+  CHECK_PCI(pci, 0x20f5, CHIP_GA100)
+  CHECK_PCI(pci, 0x20f2, CHIP_GA100)
   CHECK_PCI(pci, 0x20f1, CHIP_GA100)
+  CHECK_PCI(pci, 0x20f0, CHIP_GA100)
+  CHECK_PCI(pci, 0x20c2, CHIP_GA100)
   CHECK_PCI(pci, 0x20bf, CHIP_GA100)
   CHECK_PCI(pci, 0x20be, CHIP_GA100)
+  CHECK_PCI(pci, 0x20bb, CHIP_GA100)
+  CHECK_PCI(pci, 0x20b9, CHIP_GA100)
+  CHECK_PCI(pci, 0x20b8, CHIP_GA100)
   CHECK_PCI(pci, 0x20b7, CHIP_GA100GL)
   CHECK_PCI(pci, 0x20b6, CHIP_GA100GL)
   CHECK_PCI(pci, 0x20b5, CHIP_GA100)
+  CHECK_PCI(pci, 0x20b3, CHIP_GA100)
   CHECK_PCI(pci, 0x20b2, CHIP_GA100)
   CHECK_PCI(pci, 0x20b1, CHIP_GA100)
   CHECK_PCI(pci, 0x20b0, CHIP_GA100)
+  CHECK_PCI(pci, 0x2082, CHIP_GA100)
   CHECK_PCI(pci, 0x1ff9, CHIP_TU117GLM)
+  CHECK_PCI(pci, 0x1ff2, CHIP_TU117GL)
+  CHECK_PCI(pci, 0x1ff0, CHIP_TU117GL)
   CHECK_PCI(pci, 0x1fdd, CHIP_TU117BM)
   CHECK_PCI(pci, 0x1fd9, CHIP_TU117BM)
   CHECK_PCI(pci, 0x1fbf, CHIP_TU117GL)
+  CHECK_PCI(pci, 0x1fbc, CHIP_TU117GLM)
   CHECK_PCI(pci, 0x1fbb, CHIP_TU117GLM)
   CHECK_PCI(pci, 0x1fba, CHIP_TU117GLM)
   CHECK_PCI(pci, 0x1fb9, CHIP_TU117GLM)
   CHECK_PCI(pci, 0x1fb8, CHIP_TU117GLM)
+  CHECK_PCI(pci, 0x1fb7, CHIP_TU117GLM)
+  CHECK_PCI(pci, 0x1fb6, CHIP_TU117GLM)
   CHECK_PCI(pci, 0x1fb2, CHIP_TU117GLM)
   CHECK_PCI(pci, 0x1fb1, CHIP_TU117GL)
   CHECK_PCI(pci, 0x1fb0, CHIP_TU117GLM)
   CHECK_PCI(pci, 0x1fae, CHIP_TU117GL)
+  CHECK_PCI(pci, 0x1fa1, CHIP_TU117M)
+  CHECK_PCI(pci, 0x1fa0, CHIP_TU117M)
+  CHECK_PCI(pci, 0x1f9f, CHIP_TU117M)
   CHECK_PCI(pci, 0x1f9d, CHIP_TU117M)
   CHECK_PCI(pci, 0x1f9c, CHIP_TU117M)
   CHECK_PCI(pci, 0x1f99, CHIP_TU117M)
@@ -121,6 +188,7 @@ GPUCHIP get_chip_from_pci_cuda(struct pci* pci) {
   CHECK_PCI(pci, 0x1f94, CHIP_TU117M)
   CHECK_PCI(pci, 0x1f92, CHIP_TU117M)
   CHECK_PCI(pci, 0x1f91, CHIP_TU117M)
+  CHECK_PCI(pci, 0x1f83, CHIP_TU117)
   CHECK_PCI(pci, 0x1f82, CHIP_TU117)
   CHECK_PCI(pci, 0x1f81, CHIP_TU117)
   CHECK_PCI(pci, 0x1f76, CHIP_TU106GLM)
@@ -144,6 +212,7 @@ GPUCHIP get_chip_from_pci_cuda(struct pci* pci) {
   CHECK_PCI(pci, 0x1f07, CHIP_TU106)
   CHECK_PCI(pci, 0x1f06, CHIP_TU106)
   CHECK_PCI(pci, 0x1f04, CHIP_TU106)
+  CHECK_PCI(pci, 0x1f03, CHIP_TU106)
   CHECK_PCI(pci, 0x1f02, CHIP_TU106)
   CHECK_PCI(pci, 0x1ef5, CHIP_TU104GLM)
   CHECK_PCI(pci, 0x1ed3, CHIP_TU104BM)
@@ -156,6 +225,7 @@ GPUCHIP get_chip_from_pci_cuda(struct pci* pci) {
   CHECK_PCI(pci, 0x1eb8, CHIP_TU104GL)
   CHECK_PCI(pci, 0x1eb6, CHIP_TU104GLM)
   CHECK_PCI(pci, 0x1eb5, CHIP_TU104GLM)
+  CHECK_PCI(pci, 0x1eb4, CHIP_TU104GL)
   CHECK_PCI(pci, 0x1eb1, CHIP_TU104GL)
   CHECK_PCI(pci, 0x1eb0, CHIP_TU104GL)
   CHECK_PCI(pci, 0x1eae, CHIP_TU104M)
@@ -186,6 +256,7 @@ GPUCHIP get_chip_from_pci_cuda(struct pci* pci) {
   CHECK_PCI(pci, 0x1df5, CHIP_GV100GL)
   CHECK_PCI(pci, 0x1df2, CHIP_GV100GL)
   CHECK_PCI(pci, 0x1df0, CHIP_GV100GL)
+  CHECK_PCI(pci, 0x1dbe, CHIP_GV100)
   CHECK_PCI(pci, 0x1dba, CHIP_GV100GL)
   CHECK_PCI(pci, 0x1db8, CHIP_GV100GL)
   CHECK_PCI(pci, 0x1db7, CHIP_GV100GL)
@@ -205,6 +276,7 @@ GPUCHIP get_chip_from_pci_cuda(struct pci* pci) {
   CHECK_PCI(pci, 0x1d12, CHIP_GP108M)
   CHECK_PCI(pci, 0x1d11, CHIP_GP108M)
   CHECK_PCI(pci, 0x1d10, CHIP_GP108M)
+  CHECK_PCI(pci, 0x1d02, CHIP_GP108)
   CHECK_PCI(pci, 0x1d01, CHIP_GP108)
   CHECK_PCI(pci, 0x1cfb, CHIP_GP107GL)
   CHECK_PCI(pci, 0x1cfa, CHIP_GP107GL)
@@ -290,6 +362,7 @@ GPUCHIP get_chip_from_pci_cuda(struct pci* pci) {
   CHECK_PCI(pci, 0x1b02, CHIP_GP102)
   CHECK_PCI(pci, 0x1b01, CHIP_GP102)
   CHECK_PCI(pci, 0x1b00, CHIP_GP102)
+  CHECK_PCI(pci, 0x1af1, CHIP_GA100)
   CHECK_PCI(pci, 0x1aef, CHIP_GA102)
   CHECK_PCI(pci, 0x1aed, CHIP_TU116)
   CHECK_PCI(pci, 0x1aec, CHIP_TU116)

src/cuda/uarch.cpp

@@ -24,6 +24,8 @@ enum {
   UARCH_VOLTA,
   UARCH_TURING,
   UARCH_AMPERE,
+  UARCH_ADA,
+  UARCH_HOPPER
 };
 
 static const char *uarch_str[] = {
@@ -36,6 +38,8 @@ static const char *uarch_str[] = {
   /*[ARCH_VOLTA]      = */ "Volta",
   /*[ARCH_TURING]     = */ "Turing",
   /*[ARCH_AMPERE]     = */ "Ampere",
+  /*[ARCH_ADA]        = */ "Ada Lovelace",
+  /*[ARCH_HOPPER]     = */ "Hopper"
 };
 
 #define CHECK_UARCH_START if (false) {}
@@ -218,6 +222,9 @@ void map_chip_to_uarch_cuda(struct uarch* arch) {
   CHECK_UARCH(arch, CHIP_GA100GL,  "GA100",    UARCH_AMPERE,   7)
   CHECK_UARCH(arch, CHIP_GA102,    "GA102",    UARCH_AMPERE,   8)
   CHECK_UARCH(arch, CHIP_GA102GL,  "GA102",    UARCH_AMPERE,   8)
+  CHECK_UARCH(arch, CHIP_GA103,    "GA103",    UARCH_AMPERE,   8)
+  CHECK_UARCH(arch, CHIP_GA103GLM, "GA103",    UARCH_AMPERE,   8)
+  CHECK_UARCH(arch, CHIP_GA103M,   "GA103",    UARCH_AMPERE,   8)
   CHECK_UARCH(arch, CHIP_GA104,    "GA104",    UARCH_AMPERE,   8)
   CHECK_UARCH(arch, CHIP_GA104GL,  "GA104",    UARCH_AMPERE,   8)
   CHECK_UARCH(arch, CHIP_GA104GLM, "GA104",    UARCH_AMPERE,   8)
@@ -228,6 +235,13 @@ void map_chip_to_uarch_cuda(struct uarch* arch) {
   CHECK_UARCH(arch, CHIP_GA107BM,  "GA107",    UARCH_AMPERE,   8)
   CHECK_UARCH(arch, CHIP_GA107GLM, "GA107",    UARCH_AMPERE,   8)
   CHECK_UARCH(arch, CHIP_GA107M,   "GA107",    UARCH_AMPERE,   8)
+  // ADA LOVELACE (8.9)
+  CHECK_UARCH(arch, CHIP_AD102,    "AD102",    UARCH_ADA,      4)
+  CHECK_UARCH(arch, CHIP_AD102GL,  "AD102",    UARCH_ADA,      4)
+  CHECK_UARCH(arch, CHIP_AD104,    "AD104",    UARCH_ADA,      4)
+  CHECK_UARCH(arch, CHIP_AD104GL,  "AD104",    UARCH_ADA,      4)
+  // HOPPER (9.0)
+  CHECK_UARCH(arch, CHIP_GH100,    "GH100",    UARCH_HOPPER,   4)
   CHECK_UARCH_END
 }
 
@@ -266,6 +280,8 @@ bool clkm_possible_for_uarch(int clkm, struct uarch* arch) {
     case UARCH_VOLTA:   return clkm == 1;
     case UARCH_TURING:  return clkm == 2 || clkm == 4;
     case UARCH_AMPERE:  return clkm == 1 || clkm == 4 || clkm == 8;
+    case UARCH_ADA:     return clkm == 8;
+    case UARCH_HOPPER:  return clkm == 1;
   }
   return false;
 }
@@ -317,6 +333,10 @@ MEMTYPE guess_memtype_from_cmul_and_uarch(int clkm, struct uarch* arch) {
   CHECK_MEMTYPE(arch, clkm, UARCH_AMPERE,     1, MEMTYPE_HBM2)
   CHECK_MEMTYPE(arch, clkm, UARCH_AMPERE,     4, MEMTYPE_GDDR6)
   CHECK_MEMTYPE(arch, clkm, UARCH_AMPERE,     8, MEMTYPE_GDDR6X)
+  // ADA
+  CHECK_MEMTYPE(arch, clkm, UARCH_ADA,        8, MEMTYPE_GDDR6X)
+  // HOPPER
+  CHECK_MEMTYPE(arch, clkm, UARCH_HOPPER,     1, MEMTYPE_HBM2)
   CHECK_MEMTYPE_END
 }
 

src/intel/chips.hpp

@@ -59,13 +59,18 @@ enum {
   CHIP_HD_P630,
   CHIP_IRISP_640,
   CHIP_IRISP_650,
+  CHIP_UHD_KBL_GT1,
+  CHIP_UHD_KBL_GT2,
   // Gen11
   CHIP_UHD_G1,
   CHIP_IRISP_G4,
   CHIP_IRISP_G7,
   // Gen12
-  CHIP_UHD_730,
+  CHIP_UHD_710,
+  CHIP_UHD_730_ALD,
+  CHIP_UHD_730_RKL,
   CHIP_UHD_750,
+  CHIP_UHD_770,
   CHIP_XE_G4,
   CHIP_XE_G7
 };

src/intel/intel.cpp

@@ -9,7 +9,13 @@
 #include "../common/global.hpp"
 
 int64_t get_peak_performance_intel(struct gpu_info* gpu) {
-  if(gpu->topo_i->eu_subslice < 0 || gpu->topo_i->subslices < 0) return -1;
+  // Check that we have valid data
+  if(gpu->topo_i->eu_subslice < 0 ||
+     gpu->topo_i->subslices < 0   ||
+     gpu->freq <= 0)
+  {
+    return -1;
+  }
   return gpu->freq * 1000000 * gpu->topo_i->eu_subslice * gpu->topo_i->subslices * 8 * 2;
 }
 

src/intel/pci.cpp

@@ -8,12 +8,13 @@
 #define CHECK_PCI_START if (false) {}
 #define CHECK_PCI(pci, id, chip) \
    else if (pci->device_id == id) return chip;
-#define CHECK_PCI_END else { printBug("Unkown Intel device id: 0x%.4X", pci->device_id); return CHIP_UNKNOWN_INTEL; }
+#define CHECK_PCI_END else { printBug("Unknown Intel device id: 0x%.4X", pci->device_id); return CHIP_UNKNOWN_INTEL; }
 
 // TODO: Review wikipedia link to improve the LUT
 /*
  * https://en.wikipedia.org/wiki/List_of_Intel_graphics_processing_units
  * https://github.com/mesa3d/mesa/blob/main/include/pci_ids/iris_pci_ids.h
+ * https://raw.githubusercontent.com/smxi/inxi/master/inxi
  */
 GPUCHIP get_chip_from_pci_intel(struct pci* pci) {
   CHECK_PCI_START
@@ -112,11 +113,16 @@ GPUCHIP get_chip_from_pci_intel(struct pci* pci) {
   CHECK_PCI(pci, 0x8A51, CHIP_IRISP_G7)
   CHECK_PCI(pci, 0x8A52, CHIP_IRISP_G7)
   CHECK_PCI(pci, 0x8A53, CHIP_IRISP_G7)
-  // Gen12
+  // Xe (Gen12)
-  CHECK_PCI(pci, 0x4C8B, CHIP_UHD_730)
+  CHECK_PCI(pci, 0x4693, CHIP_UHD_710)
-  CHECK_PCI(pci, 0x4C8B, CHIP_UHD_750)
+  CHECK_PCI(pci, 0x4692, CHIP_UHD_730_ALD)
+  CHECK_PCI(pci, 0x4C8B, CHIP_UHD_730_RKL)
+  CHECK_PCI(pci, 0x4C8A, CHIP_UHD_750)
+  CHECK_PCI(pci, 0x4690, CHIP_UHD_770)
+  CHECK_PCI(pci, 0x4680, CHIP_UHD_770)
   CHECK_PCI(pci, 0x9A78, CHIP_XE_G4)
   CHECK_PCI(pci, 0x9A40, CHIP_XE_G7) // G7 may have 80 or 96 EUs
   CHECK_PCI(pci, 0x9A49, CHIP_XE_G7) // Same for this G7
+  // TODO: Add generic generic UHD Graphics and Iris Xe Graphics from Mobile
   CHECK_PCI_END
 }

src/intel/uarch.cpp

@@ -27,6 +27,7 @@
  * Gen9.5: Kaby Lake
  * Gen11:  Ice Lake          (10th Gen)
  * Gen12:  Rocket/Tiger Lake (11th Gen)
+ * Gen12:  Alder Lake        (12th Gen)
  */
 enum {
   UARCH_UNKNOWN,
@@ -39,6 +40,7 @@ enum {
   UARCH_GEN11,
   UARCH_GEN12_RKL,
   UARCH_GEN12_TGL,
+  UARCH_GEN12_ALD,
 };
 
 static const char *uarch_str[] = {
@@ -50,13 +52,15 @@ static const char *uarch_str[] = {
   /*[ARCH_GEN9]      = */ "Gen9",
   /*[ARCH_GEN9_5]    = */ "Gen9.5",
   /*[ARCH_GEN11]     = */ "Gen11",
-  /*[ARCH_GEN12_RKL] = */ "Gen12",
+  /*[ARCH_GEN12_RKL] = */ "Xe",
-  /*[ARCH_GEN12_TGL] = */ "Gen12"
+  /*[ARCH_GEN12_TGL] = */ "Xe",
+  /*[ARCH_GEN12_ALD] = */ "Xe",
 };
 
 // Graphic Tiers (GT)
 enum {
   GT_UNKNOWN,
+  GT0_5, // Saw that 0.5 thing in iris_pci_ids.h
   GT1,
   GT1_4, // GT1 with 4 EUs
   GT1_5,
@@ -68,6 +72,7 @@ enum {
 
 static const char *gt_str[] = {
   /*[GT_UNKNOWN] = */ STRING_UNKNOWN,
+  /*[GT0_5]      = */ "GT0.5",
   /*[GT1]        = */ "GT1",
   /*[GT1_4]      = */ "GT1",
   /*[GT1_5]      = */ "GT1.5",
@@ -85,6 +90,8 @@ static const char *gt_str[] = {
 #define CHECK_TOPO_START if (false) {}
 #define CHECK_TOPO(topo, arch, uarch_, gt_, eu_sub, sub, sli) \
   else if(arch->uarch == uarch_ && arch->gt == gt_) fill_topo(topo, eu_sub, sub, sli);
+#define CHECK_TOPO_CHIP(topo, arch, uarch_, chip_, eu_sub, sub, sli) \
+  else if(arch->uarch == uarch_ && arch->chip == chip_) fill_topo(topo, eu_sub, sub, sli);
 #define CHECK_TOPO_END else { printBug("get_topology_info: Invalid uarch and gt combination: '%s' and '%s'", arch->chip_str, get_str_gt(arch)); fill_topo(topo, UNK, UNK, UNK); }
 
 void fill_topo(struct topology_i* topo_i, int32_t eu_sub, int32_t sub, int32_t sli) {
@@ -143,6 +150,8 @@ void map_chip_to_uarch_intel(struct uarch* arch) {
   CHECK_UARCH(arch, CHIP_UHD_605,      "UHD Graphics 605",           UARCH_GEN9_5, GT1_5, 14)
   CHECK_UARCH(arch, CHIP_UHD_620,      "UHD Graphics 620",           UARCH_GEN9_5, GT2,   14)
   CHECK_UARCH(arch, CHIP_UHD_630,      "UHD Graphics 630",           UARCH_GEN9_5, GT2,   14)
+  CHECK_UARCH(arch, CHIP_UHD_KBL_GT1,  "UHD Graphics",               UARCH_GEN9_5, GT1,   14)
+  CHECK_UARCH(arch, CHIP_UHD_KBL_GT2,  "UHD Graphics",               UARCH_GEN9_5, GT2,   14)
   CHECK_UARCH(arch, CHIP_HD_610,       "HD Graphics 610",            UARCH_GEN9_5, GT1,   14)
   CHECK_UARCH(arch, CHIP_HD_615,       "HD Graphics 615",            UARCH_GEN9_5, GT2,   14)
   CHECK_UARCH(arch, CHIP_HD_630,       "HD Graphics 630",            UARCH_GEN9_5, GT2,   14)
@@ -153,8 +162,11 @@ void map_chip_to_uarch_intel(struct uarch* arch) {
   CHECK_UARCH(arch, CHIP_UHD_G1,       "UHD Graphics G1",            UARCH_GEN11,  GT1,   10)
   CHECK_UARCH(arch, CHIP_IRISP_G4,     "Iris Plus Graphics G4",      UARCH_GEN11,  GT1_5, 10)
   CHECK_UARCH(arch, CHIP_IRISP_G7,     "Iris Plus Graphics G7",      UARCH_GEN11,  GT2,   10)
-  // Gen12
+  // Xe (Gen12)
-  CHECK_UARCH(arch, CHIP_UHD_730,      "UHD Graphics 730",           UARCH_GEN12_RKL, GT1,   14)
+  CHECK_UARCH(arch, CHIP_UHD_710,      "UHD Graphics 710",           UARCH_GEN12_ALD, GT1,   10)
+  CHECK_UARCH(arch, CHIP_UHD_730_ALD,  "UHD Graphics 730",           UARCH_GEN12_ALD, GT1,   10)
+  CHECK_UARCH(arch, CHIP_UHD_770,      "UHD Graphics 770",           UARCH_GEN12_ALD, GT1,   10)
+  CHECK_UARCH(arch, CHIP_UHD_730_RKL,  "UHD Graphics 730",           UARCH_GEN12_RKL, GT1,   14)
   CHECK_UARCH(arch, CHIP_UHD_750,      "UHD Graphics 750",           UARCH_GEN12_RKL, GT1,   14)
   CHECK_UARCH(arch, CHIP_XE_G4,        "Iris Xe G4",                 UARCH_GEN12_TGL, GT2,   10)
   CHECK_UARCH(arch, CHIP_XE_G7,        "Iris Xe G7",                 UARCH_GEN12_TGL, GT2,   10)
@@ -201,6 +213,8 @@ char* get_name_from_uarch(struct uarch* arch) {
  * Gen9.5:   https://en.wikichip.org/wiki/intel/microarchitectures/gen9.5#Configuration
 
  * Also:     https://www.techpowerup.com/gpu-specs/intel-rocket-lake-gt1.g993
+             https://www.techpowerup.com/gpu-specs/?architecture=Generation%2012.1
+             https://elixir.bootlin.com/linux/latest/source/include/drm/i915_pciids.h
  */
 struct topology_i* get_topology_info(struct uarch* arch) {
   struct topology_i* topo = (struct topology_i*) emalloc(sizeof(struct topology_i));
@@ -238,9 +252,13 @@ struct topology_i* get_topology_info(struct uarch* arch) {
   CHECK_TOPO(topo, arch, UARCH_GEN11,  GT1,   8, 4, 1)
   CHECK_TOPO(topo, arch, UARCH_GEN11,  GT1_5, 8, 6, 1)
   CHECK_TOPO(topo, arch, UARCH_GEN11,  GT2,   8, 8, 1)
-  // Gen12
+  // Xe (Gen12)
-  CHECK_TOPO(topo, arch, UARCH_GEN12_RKL, GT1, 16, 2, 1)
+  // NOTE: Instead of checking for uarch + graphics tier,
-  else if(arch->uarch == UARCH_GEN12_TGL && arch->gt == GT2) {
+  // we have to check for uarch + exact chip
+  CHECK_TOPO_CHIP(topo, arch, UARCH_GEN12_RKL, CHIP_UHD_730_RKL, 8, 3, 1)
+  CHECK_TOPO_CHIP(topo, arch, UARCH_GEN12_RKL, CHIP_UHD_750,     8, 4, 1)
+  CHECK_TOPO_CHIP(topo, arch, UARCH_GEN12_TGL, CHIP_XE_G4,       8, 6, 1)
+  else if(arch->uarch == UARCH_GEN12_TGL && arch->chip == CHIP_XE_G7) {
     // Special case: TigerLake GT2 needs to check if is i5/i7 to know the exact topology
     if(is_corei5()) {
       fill_topo(topo, 10, 8, 1); // Should be 80 EUs, but not sure about the organization
@@ -249,6 +267,10 @@ struct topology_i* get_topology_info(struct uarch* arch) {
       fill_topo(topo, 16, 6, 1);
     }
   }
+  CHECK_TOPO_CHIP(topo, arch, UARCH_GEN12_ALD, CHIP_UHD_710,     8, 2, 1)
+  CHECK_TOPO_CHIP(topo, arch, UARCH_GEN12_ALD, CHIP_UHD_730_ALD, 8, 3, 1)
+  CHECK_TOPO_CHIP(topo, arch, UARCH_GEN12_ALD, CHIP_UHD_770,     8, 4, 1)
+  // TODO: Add ALD UHD Graphics/Xe Graphics
   CHECK_TOPO_END
   return topo;
 }