From e7c4d5bf91ea3c411794c190e16fdf10a3d85a31 Mon Sep 17 00:00:00 2001 From: Dr-Noob Date: Sat, 27 Nov 2021 12:23:41 +0100 Subject: [PATCH] [v0.11] Adding Gen6, 7, 7.5 and 8 to database --- src/intel/chips.hpp | 24 +++++++++++++++++ src/intel/pci.cpp | 34 ++++++++++++++++++++++++ src/intel/uarch.cpp | 64 +++++++++++++++++++++++++++++++++------------ 3 files changed, 106 insertions(+), 16 deletions(-) diff --git a/src/intel/chips.hpp b/src/intel/chips.hpp index 1a4a924..c4efb35 100644 --- a/src/intel/chips.hpp +++ b/src/intel/chips.hpp @@ -7,6 +7,30 @@ typedef uint32_t GPUCHIP; enum { CHIP_UNKNOWN_INTEL, + // Gen6 + CHIP_HD_2000, + CHIP_HD_3000, + // Gen7 + CHIP_HD_2500, + CHIP_HD_4000, + CHIP_HD_P4000, + // Gen7.5 + CHIP_HD_4200, + CHIP_HD_4400, + CHIP_HD_4600, + CHIP_HD_P4600, + CHIP_IRIS_5100, + CHIP_IRISP_5200, + CHIP_IRISP_P5200, + // Gen8 + CHIP_HD_5300, + CHIP_HD_5500, + CHIP_HD_5600, + CHIP_HD_P5700, + CHIP_HD_6000, + CHIP_IRIS_6100, + CHIP_IRISP_6200, + CHIP_IRISP_P6300, // Gen9 CHIP_HD_510, CHIP_HD_515, diff --git a/src/intel/pci.cpp b/src/intel/pci.cpp index ea4ab63..cfb77a9 100644 --- a/src/intel/pci.cpp +++ b/src/intel/pci.cpp @@ -15,6 +15,40 @@ */ GPUCHIP get_chip_from_pci(struct pci* pci) { CHECK_PCI_START + // Gen6 + CHECK_PCI(pci, 0x0102, CHIP_HD_2000) + CHECK_PCI(pci, 0x0106, CHIP_HD_2000) + CHECK_PCI(pci, 0x010A, CHIP_HD_2000) + CHECK_PCI(pci, 0x0112, CHIP_HD_3000) + CHECK_PCI(pci, 0x0122, CHIP_HD_3000) + CHECK_PCI(pci, 0x0116, CHIP_HD_3000) + CHECK_PCI(pci, 0x0126, CHIP_HD_3000) + // Gen7 + CHECK_PCI(pci, 0x0152, CHIP_HD_2500) + CHECK_PCI(pci, 0x0156, CHIP_HD_2500) + CHECK_PCI(pci, 0x0162, CHIP_HD_4000) + CHECK_PCI(pci, 0x0166, CHIP_HD_4000) + CHECK_PCI(pci, 0x016a, CHIP_HD_P4000) + // Gen7.5 + CHECK_PCI(pci, 0x0A1E, CHIP_HD_4200) + CHECK_PCI(pci, 0x041E, CHIP_HD_4400) + CHECK_PCI(pci, 0x0A16, CHIP_HD_4400) + CHECK_PCI(pci, 0x0412, CHIP_HD_4600) + CHECK_PCI(pci, 0x0416, CHIP_HD_4600) + CHECK_PCI(pci, 0x0D12, CHIP_HD_4600) + CHECK_PCI(pci, 0x041A, CHIP_HD_P4600) + CHECK_PCI(pci, 0x0A2E, CHIP_IRIS_5100) + CHECK_PCI(pci, 0x0D22, CHIP_IRISP_5200) + CHECK_PCI(pci, 0x0D26, CHIP_IRISP_P5200) + // Gen8 + CHECK_PCI(pci, 0x161E, CHIP_HD_5300) + CHECK_PCI(pci, 0x1616, CHIP_HD_5500) + CHECK_PCI(pci, 0x1612, CHIP_HD_5600) + CHECK_PCI(pci, 0x161A, CHIP_HD_P5700) + CHECK_PCI(pci, 0x1626, CHIP_HD_6000) + CHECK_PCI(pci, 0x162B, CHIP_IRIS_6100) + CHECK_PCI(pci, 0x1622, CHIP_IRISP_6200) + CHECK_PCI(pci, 0x162A, CHIP_IRISP_P6300) // Gen9 CHECK_PCI(pci, 0x1902, CHIP_HD_510) CHECK_PCI(pci, 0x1906, CHIP_HD_510) diff --git a/src/intel/uarch.cpp b/src/intel/uarch.cpp index 7f5512c..778b27e 100644 --- a/src/intel/uarch.cpp +++ b/src/intel/uarch.cpp @@ -17,14 +17,22 @@ // MICROARCH values enum { UARCH_UNKNOWN, + UARCH_GEN6, + UARCH_GEN7, + UARCH_GEN7_5, + UARCH_GEN8, UARCH_GEN9, UARCH_GEN9_5, }; static const char *uarch_str[] = { /*[ARCH_UNKNOWN = */ STRING_UNKNOWN, + /*[ARCH_GEN6] = */ "Gen6", + /*[ARCH_GEN7] = */ "Gen7", + /*[ARCH_GEN7_5] = */ "Gen7.5", + /*[ARCH_GEN8] = */ "Gen8", /*[ARCH_GEN9] = */ "Gen9", - /*[ARCH_GEN9.5] = */ "Gen9.5", + /*[ARCH_GEN9_5] = */ "Gen9.5", }; #define CHECK_UARCH_START if (false) {} @@ -41,23 +49,47 @@ void fill_uarch(struct uarch* arch, char const *str, MICROARCH u, uint32_t proce void map_chip_to_uarch(struct uarch* arch) { CHECK_UARCH_START + // Gen6 + CHECK_UARCH(arch, CHIP_HD_2000, "HD Graphics 2000", UARCH_GEN6, 32) + CHECK_UARCH(arch, CHIP_HD_3000, "HD Graphics 3000", UARCH_GEN6, 32) + // Gen7 + CHECK_UARCH(arch, CHIP_HD_2500, "HD Graphics 2500", UARCH_GEN7, 22) + CHECK_UARCH(arch, CHIP_HD_4000, "HD Graphics 4000", UARCH_GEN7, 22) + CHECK_UARCH(arch, CHIP_HD_P4000, "HD Graphics P4000", UARCH_GEN7, 22) + // Gen7.5 + CHECK_UARCH(arch, CHIP_HD_4200, "HD Graphics 4200", UARCH_GEN7_5, 22) + CHECK_UARCH(arch, CHIP_HD_4400, "HD Graphics 4400", UARCH_GEN7_5, 22) + CHECK_UARCH(arch, CHIP_HD_4600, "HD Graphics 4600", UARCH_GEN7_5, 22) + CHECK_UARCH(arch, CHIP_HD_P4600, "HD Graphics P4600", UARCH_GEN7_5, 22) + CHECK_UARCH(arch, CHIP_IRIS_5100, "HD Iris 5100", UARCH_GEN7_5, 22) + CHECK_UARCH(arch, CHIP_IRISP_5200, "HD Iris Pro 5200", UARCH_GEN7_5, 22) + CHECK_UARCH(arch, CHIP_IRISP_P5200, "HD Iris Pro P5200", UARCH_GEN7_5, 22) + // Gen8 + CHECK_UARCH(arch, CHIP_HD_5300, "HD Graphics 5300", UARCH_GEN8, 14) + CHECK_UARCH(arch, CHIP_HD_5500, "HD Graphics 5500", UARCH_GEN8, 14) + CHECK_UARCH(arch, CHIP_HD_5600, "HD Graphics 5600", UARCH_GEN8, 14) + CHECK_UARCH(arch, CHIP_HD_P5700, "HD Graphics P5700", UARCH_GEN8, 14) + CHECK_UARCH(arch, CHIP_HD_6000, "HD Graphics 6000", UARCH_GEN8, 14) + CHECK_UARCH(arch, CHIP_IRIS_6100, "Iris Graphics 6100", UARCH_GEN8, 14) + CHECK_UARCH(arch, CHIP_IRISP_6200, "Iris Pro Graphics 6200", UARCH_GEN8, 14) + CHECK_UARCH(arch, CHIP_IRISP_P6300, "Iris Pro Graphics P6300", UARCH_GEN8, 14) // Gen9 - CHECK_UARCH(arch, CHIP_HD_510, "HD Graphics 510", UARCH_GEN9, 14) - CHECK_UARCH(arch, CHIP_HD_515, "HD Graphics 515", UARCH_GEN9, 14) - CHECK_UARCH(arch, CHIP_HD_520, "HD Graphics 520", UARCH_GEN9, 14) - CHECK_UARCH(arch, CHIP_HD_530, "HD Graphics 530", UARCH_GEN9, 14) - CHECK_UARCH(arch, CHIP_HD_P530, "HD Graphics P530", UARCH_GEN9, 14) + CHECK_UARCH(arch, CHIP_HD_510, "HD Graphics 510", UARCH_GEN9, 14) + CHECK_UARCH(arch, CHIP_HD_515, "HD Graphics 515", UARCH_GEN9, 14) + CHECK_UARCH(arch, CHIP_HD_520, "HD Graphics 520", UARCH_GEN9, 14) + CHECK_UARCH(arch, CHIP_HD_530, "HD Graphics 530", UARCH_GEN9, 14) + CHECK_UARCH(arch, CHIP_HD_P530, "HD Graphics P530", UARCH_GEN9, 14) // Gen9.5 - CHECK_UARCH(arch, CHIP_UHD_600, "UHD Graphics 600", UARCH_GEN9_5, 14) - CHECK_UARCH(arch, CHIP_UHD_605, "UHD Graphics 605", UARCH_GEN9_5, 14) - CHECK_UARCH(arch, CHIP_UHD_620, "UHD Graphics 620", UARCH_GEN9_5, 14) - CHECK_UARCH(arch, CHIP_UHD_630, "UHD Graphics 630", UARCH_GEN9_5, 14) - CHECK_UARCH(arch, CHIP_HD_610, "HD Graphics 610", UARCH_GEN9_5, 14) - CHECK_UARCH(arch, CHIP_HD_615, "HD Graphics 615", UARCH_GEN9_5, 14) - CHECK_UARCH(arch, CHIP_HD_630, "HD Graphics 630", UARCH_GEN9_5, 14) - CHECK_UARCH(arch, CHIP_HD_P630, "HD Graphics P630", UARCH_GEN9_5, 14) - CHECK_UARCH(arch, CHIP_IRISP_640, "Iris(R) Plus Graphics 640", UARCH_GEN9_5, 14) - CHECK_UARCH(arch, CHIP_IRISP_640, "Iris(R) Plus Graphics 650", UARCH_GEN9_5, 14) + CHECK_UARCH(arch, CHIP_UHD_600, "UHD Graphics 600", UARCH_GEN9_5, 14) + CHECK_UARCH(arch, CHIP_UHD_605, "UHD Graphics 605", UARCH_GEN9_5, 14) + CHECK_UARCH(arch, CHIP_UHD_620, "UHD Graphics 620", UARCH_GEN9_5, 14) + CHECK_UARCH(arch, CHIP_UHD_630, "UHD Graphics 630", UARCH_GEN9_5, 14) + CHECK_UARCH(arch, CHIP_HD_610, "HD Graphics 610", UARCH_GEN9_5, 14) + CHECK_UARCH(arch, CHIP_HD_615, "HD Graphics 615", UARCH_GEN9_5, 14) + CHECK_UARCH(arch, CHIP_HD_630, "HD Graphics 630", UARCH_GEN9_5, 14) + CHECK_UARCH(arch, CHIP_HD_P630, "HD Graphics P630", UARCH_GEN9_5, 14) + CHECK_UARCH(arch, CHIP_IRISP_640, "Iris Plus Graphics 640", UARCH_GEN9_5, 14) + CHECK_UARCH(arch, CHIP_IRISP_640, "Iris Plus Graphics 650", UARCH_GEN9_5, 14) CHECK_UARCH_END }