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[v0.21] Add unamed HD graphics (thanks #7 for reporting)

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Dr-Noob
2021-12-27 18:48:24 +01:00
parent e73f301eef
commit 118d9c0b67
4 changed files with 69 additions and 37 deletions
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2
src/common/main.cpp
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@@ -8,7 +8,7 @@
#include "../cuda/cuda.hpp" #include "../cuda/cuda.hpp"
#include "../cuda/uarch.hpp" #include "../cuda/uarch.hpp"
static const char* VERSION = "0.20"; static const char* VERSION = "0.21";
void print_help(char *argv[]) { void print_help(char *argv[]) {
const char **t = args_str; const char **t = args_str;

5
src/intel/chips.hpp
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@@ -8,13 +8,17 @@ typedef uint32_t GPUCHIP;
enum { enum {
CHIP_UNKNOWN_INTEL, CHIP_UNKNOWN_INTEL,
// Gen6 // Gen6
CHIP_HD_SANDY,
CHIP_HD_2000, CHIP_HD_2000,
CHIP_HD_3000, CHIP_HD_3000,
// Gen7 // Gen7
CHIP_HD_SILVER,
CHIP_HD_IVY,
CHIP_HD_2500, CHIP_HD_2500,
CHIP_HD_4000, CHIP_HD_4000,
CHIP_HD_P4000, CHIP_HD_P4000,
// Gen7.5 // Gen7.5
CHIP_HD_HASWELL,
CHIP_HD_4200, CHIP_HD_4200,
CHIP_HD_4400, CHIP_HD_4400,
CHIP_HD_4600, CHIP_HD_4600,
@@ -23,6 +27,7 @@ enum {
CHIP_IRISP_5200, CHIP_IRISP_5200,
CHIP_IRISP_P5200, CHIP_IRISP_P5200,
// Gen8 // Gen8
CHIP_HD_BROADWELL,
CHIP_HD_5300, CHIP_HD_5300,
CHIP_HD_5500, CHIP_HD_5500,
CHIP_HD_5600, CHIP_HD_5600,

22
src/intel/pci.cpp
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@@ -10,26 +10,45 @@
else if (pci->device_id == id) return chip; else if (pci->device_id == id) return chip;
#define CHECK_PCI_END else { printBug("Unkown Intel device id: 0x%.4X", pci->device_id); return CHIP_UNKNOWN_INTEL; } #define CHECK_PCI_END else { printBug("Unkown Intel device id: 0x%.4X", pci->device_id); return CHIP_UNKNOWN_INTEL; }
// TODO: Review wikipedia link to improve the LUT
/* /*
* https://en.wikipedia.org/wiki/List_of_Intel_graphics_processing_units
* https://github.com/mesa3d/mesa/blob/main/include/pci_ids/i965_pci_ids.h * https://github.com/mesa3d/mesa/blob/main/include/pci_ids/i965_pci_ids.h
*/ */
GPUCHIP get_chip_from_pci_intel(struct pci* pci) { GPUCHIP get_chip_from_pci_intel(struct pci* pci) {
CHECK_PCI_START CHECK_PCI_START
// Gen6 // Gen6
CHECK_PCI(pci, 0x010A, CHIP_HD_SANDY)
CHECK_PCI(pci, 0x0102, CHIP_HD_2000) CHECK_PCI(pci, 0x0102, CHIP_HD_2000)
CHECK_PCI(pci, 0x0106, CHIP_HD_2000) CHECK_PCI(pci, 0x0106, CHIP_HD_2000)
CHECK_PCI(pci, 0x010A, CHIP_HD_2000)
CHECK_PCI(pci, 0x0112, CHIP_HD_3000) CHECK_PCI(pci, 0x0112, CHIP_HD_3000)
CHECK_PCI(pci, 0x0122, CHIP_HD_3000) CHECK_PCI(pci, 0x0122, CHIP_HD_3000)
CHECK_PCI(pci, 0x0116, CHIP_HD_3000) CHECK_PCI(pci, 0x0116, CHIP_HD_3000)
CHECK_PCI(pci, 0x0126, CHIP_HD_3000) CHECK_PCI(pci, 0x0126, CHIP_HD_3000)
// Gen7 // Gen7
CHECK_PCI(pci, 0x015A, CHIP_HD_IVY)
CHECK_PCI(pci, 0x0F30, CHIP_HD_SILVER)
CHECK_PCI(pci, 0x0F31, CHIP_HD_SILVER)
CHECK_PCI(pci, 0x0F32, CHIP_HD_SILVER)
CHECK_PCI(pci, 0x0F33, CHIP_HD_SILVER)
CHECK_PCI(pci, 0x0155, CHIP_HD_SILVER)
CHECK_PCI(pci, 0x0157, CHIP_HD_SILVER)
CHECK_PCI(pci, 0x0152, CHIP_HD_2500) CHECK_PCI(pci, 0x0152, CHIP_HD_2500)
CHECK_PCI(pci, 0x0156, CHIP_HD_2500) CHECK_PCI(pci, 0x0156, CHIP_HD_2500)
CHECK_PCI(pci, 0x0162, CHIP_HD_4000) CHECK_PCI(pci, 0x0162, CHIP_HD_4000)
CHECK_PCI(pci, 0x0166, CHIP_HD_4000) CHECK_PCI(pci, 0x0166, CHIP_HD_4000)
CHECK_PCI(pci, 0x016a, CHIP_HD_P4000) CHECK_PCI(pci, 0x016a, CHIP_HD_P4000)
// Gen7.5 // Gen7.5
CHECK_PCI(pci, 0x0402, CHIP_HD_HASWELL)
CHECK_PCI(pci, 0x0406, CHIP_HD_HASWELL)
CHECK_PCI(pci, 0x040A, CHIP_HD_HASWELL)
CHECK_PCI(pci, 0x040B, CHIP_HD_HASWELL)
CHECK_PCI(pci, 0x040E, CHIP_HD_HASWELL)
CHECK_PCI(pci, 0x0A02, CHIP_HD_HASWELL)
CHECK_PCI(pci, 0x0A06, CHIP_HD_HASWELL)
CHECK_PCI(pci, 0x0A0A, CHIP_HD_HASWELL)
CHECK_PCI(pci, 0x0A0B, CHIP_HD_HASWELL)
CHECK_PCI(pci, 0x0A0E, CHIP_HD_HASWELL)
CHECK_PCI(pci, 0x0A1E, CHIP_HD_4200) CHECK_PCI(pci, 0x0A1E, CHIP_HD_4200)
CHECK_PCI(pci, 0x041E, CHIP_HD_4400) CHECK_PCI(pci, 0x041E, CHIP_HD_4400)
CHECK_PCI(pci, 0x0A16, CHIP_HD_4400) CHECK_PCI(pci, 0x0A16, CHIP_HD_4400)
@@ -41,6 +60,7 @@ GPUCHIP get_chip_from_pci_intel(struct pci* pci) {
CHECK_PCI(pci, 0x0D22, CHIP_IRISP_5200) CHECK_PCI(pci, 0x0D22, CHIP_IRISP_5200)
CHECK_PCI(pci, 0x0D26, CHIP_IRISP_P5200) CHECK_PCI(pci, 0x0D26, CHIP_IRISP_P5200)
// Gen8 // Gen8
CHECK_PCI(pci, 0x1606, CHIP_HD_BROADWELL)
CHECK_PCI(pci, 0x161E, CHIP_HD_5300) CHECK_PCI(pci, 0x161E, CHIP_HD_5300)
CHECK_PCI(pci, 0x1616, CHIP_HD_5500) CHECK_PCI(pci, 0x1616, CHIP_HD_5500)
CHECK_PCI(pci, 0x1612, CHIP_HD_5600) CHECK_PCI(pci, 0x1612, CHIP_HD_5600)

77
src/intel/uarch.cpp
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@@ -49,6 +49,7 @@ static const char *uarch_str[] = {
enum { enum {
GT_UNKNOWN, GT_UNKNOWN,
GT1, GT1,
GT1_4, // GT1 with 4 EUs
GT1_5, GT1_5,
GT2, GT2,
GT3, GT3,
@@ -93,46 +94,51 @@ void fill_uarch(struct uarch* arch, char const *str, MICROARCH u, int32_t gt, ui
void map_chip_to_uarch_intel(struct uarch* arch) { void map_chip_to_uarch_intel(struct uarch* arch) {
CHECK_UARCH_START CHECK_UARCH_START
// Gen6 // Gen6
CHECK_UARCH(arch, CHIP_HD_2000, "HD Graphics 2000", UARCH_GEN6, GT1, 32) CHECK_UARCH(arch, CHIP_HD_SANDY, "HD Graphics (Sandy Bridge)", UARCH_GEN6, GT1, 32)
CHECK_UARCH(arch, CHIP_HD_3000, "HD Graphics 3000", UARCH_GEN6, GT2, 32) CHECK_UARCH(arch, CHIP_HD_2000, "HD Graphics 2000", UARCH_GEN6, GT1, 32)
CHECK_UARCH(arch, CHIP_HD_3000, "HD Graphics 3000", UARCH_GEN6, GT2, 32)
// Gen7 // Gen7
CHECK_UARCH(arch, CHIP_HD_2500, "HD Graphics 2500", UARCH_GEN7, GT1, 22) CHECK_UARCH(arch, CHIP_HD_IVY, "HD Graphics (Ivy Bridge)", UARCH_GEN7, GT1, 22)
CHECK_UARCH(arch, CHIP_HD_4000, "HD Graphics 4000", UARCH_GEN7, GT2, 22) CHECK_UARCH(arch, CHIP_HD_SILVER, "HD Graphics (Silvermont)", UARCH_GEN7, GT1_4, 22)
CHECK_UARCH(arch, CHIP_HD_P4000, "HD Graphics P4000", UARCH_GEN7, GT2, 22) CHECK_UARCH(arch, CHIP_HD_2500, "HD Graphics 2500", UARCH_GEN7, GT1, 22)
CHECK_UARCH(arch, CHIP_HD_4000, "HD Graphics 4000", UARCH_GEN7, GT2, 22)
CHECK_UARCH(arch, CHIP_HD_P4000, "HD Graphics P4000", UARCH_GEN7, GT2, 22)
// Gen7.5 // Gen7.5
CHECK_UARCH(arch, CHIP_HD_4200, "HD Graphics 4200", UARCH_GEN7_5, GT2, 22) CHECK_UARCH(arch, CHIP_HD_HASWELL, "HD Graphics (Haswell)", UARCH_GEN7_5, GT1, 22)
CHECK_UARCH(arch, CHIP_HD_4400, "HD Graphics 4400", UARCH_GEN7_5, GT2, 22) CHECK_UARCH(arch, CHIP_HD_4200, "HD Graphics 4200", UARCH_GEN7_5, GT2, 22)
CHECK_UARCH(arch, CHIP_HD_4600, "HD Graphics 4600", UARCH_GEN7_5, GT2, 22) CHECK_UARCH(arch, CHIP_HD_4400, "HD Graphics 4400", UARCH_GEN7_5, GT2, 22)
CHECK_UARCH(arch, CHIP_HD_P4600, "HD Graphics P4600", UARCH_GEN7_5, GT2, 22) CHECK_UARCH(arch, CHIP_HD_4600, "HD Graphics 4600", UARCH_GEN7_5, GT2, 22)
CHECK_UARCH(arch, CHIP_IRIS_5100, "HD Iris 5100", UARCH_GEN7_5, GT3, 22) CHECK_UARCH(arch, CHIP_HD_P4600, "HD Graphics P4600", UARCH_GEN7_5, GT2, 22)
CHECK_UARCH(arch, CHIP_IRISP_5200, "HD Iris Pro 5200", UARCH_GEN7_5, GT3, 22) CHECK_UARCH(arch, CHIP_IRIS_5100, "HD Iris 5100", UARCH_GEN7_5, GT3, 22)
CHECK_UARCH(arch, CHIP_IRISP_P5200, "HD Iris Pro P5200", UARCH_GEN7_5, GT3, 22) CHECK_UARCH(arch, CHIP_IRISP_5200, "HD Iris Pro 5200", UARCH_GEN7_5, GT3, 22)
CHECK_UARCH(arch, CHIP_IRISP_P5200, "HD Iris Pro P5200", UARCH_GEN7_5, GT3, 22)
// Gen8 // Gen8
CHECK_UARCH(arch, CHIP_HD_5300, "HD Graphics 5300", UARCH_GEN8, GT2, 14) CHECK_UARCH(arch, CHIP_HD_BROADWELL, "HD Graphics (Broadwell)", UARCH_GEN8, GT1, 14)
CHECK_UARCH(arch, CHIP_HD_5500, "HD Graphics 5500", UARCH_GEN8, GT2, 14) CHECK_UARCH(arch, CHIP_HD_5300, "HD Graphics 5300", UARCH_GEN8, GT2, 14)
CHECK_UARCH(arch, CHIP_HD_5600, "HD Graphics 5600", UARCH_GEN8, GT2, 14) CHECK_UARCH(arch, CHIP_HD_5500, "HD Graphics 5500", UARCH_GEN8, GT2, 14)
CHECK_UARCH(arch, CHIP_HD_P5700, "HD Graphics P5700", UARCH_GEN8, GT2, 14) CHECK_UARCH(arch, CHIP_HD_5600, "HD Graphics 5600", UARCH_GEN8, GT2, 14)
CHECK_UARCH(arch, CHIP_HD_6000, "HD Graphics 6000", UARCH_GEN8, GT3, 14) CHECK_UARCH(arch, CHIP_HD_P5700, "HD Graphics P5700", UARCH_GEN8, GT2, 14)
CHECK_UARCH(arch, CHIP_IRIS_6100, "Iris Graphics 6100", UARCH_GEN8, GT3, 14) CHECK_UARCH(arch, CHIP_HD_6000, "HD Graphics 6000", UARCH_GEN8, GT3, 14)
CHECK_UARCH(arch, CHIP_IRISP_6200, "Iris Pro Graphics 6200", UARCH_GEN8, GT3, 14) CHECK_UARCH(arch, CHIP_IRIS_6100, "Iris Graphics 6100", UARCH_GEN8, GT3, 14)
CHECK_UARCH(arch, CHIP_IRISP_P6300, "Iris Pro Graphics P6300", UARCH_GEN8, GT3, 14) CHECK_UARCH(arch, CHIP_IRISP_6200, "Iris Pro Graphics 6200", UARCH_GEN8, GT3, 14)
CHECK_UARCH(arch, CHIP_IRISP_P6300, "Iris Pro Graphics P6300", UARCH_GEN8, GT3, 14)
// Gen9 // Gen9
CHECK_UARCH(arch, CHIP_HD_510, "HD Graphics 510", UARCH_GEN9, GT1, 14) CHECK_UARCH(arch, CHIP_HD_510, "HD Graphics 510", UARCH_GEN9, GT1, 14)
CHECK_UARCH(arch, CHIP_HD_515, "HD Graphics 515", UARCH_GEN9, GT2, 14) CHECK_UARCH(arch, CHIP_HD_515, "HD Graphics 515", UARCH_GEN9, GT2, 14)
CHECK_UARCH(arch, CHIP_HD_520, "HD Graphics 520", UARCH_GEN9, GT2, 14) CHECK_UARCH(arch, CHIP_HD_520, "HD Graphics 520", UARCH_GEN9, GT2, 14)
CHECK_UARCH(arch, CHIP_HD_530, "HD Graphics 530", UARCH_GEN9, GT2, 14) CHECK_UARCH(arch, CHIP_HD_530, "HD Graphics 530", UARCH_GEN9, GT2, 14)
CHECK_UARCH(arch, CHIP_HD_P530, "HD Graphics P530", UARCH_GEN9, GT2, 14) CHECK_UARCH(arch, CHIP_HD_P530, "HD Graphics P530", UARCH_GEN9, GT2, 14)
// Gen9.5 // Gen9.5
CHECK_UARCH(arch, CHIP_UHD_600, "UHD Graphics 600", UARCH_GEN9_5, GT1, 14) CHECK_UARCH(arch, CHIP_UHD_600, "UHD Graphics 600", UARCH_GEN9_5, GT1, 14)
CHECK_UARCH(arch, CHIP_UHD_605, "UHD Graphics 605", UARCH_GEN9_5, GT1_5, 14) CHECK_UARCH(arch, CHIP_UHD_605, "UHD Graphics 605", UARCH_GEN9_5, GT1_5, 14)
CHECK_UARCH(arch, CHIP_UHD_620, "UHD Graphics 620", UARCH_GEN9_5, GT2, 14) CHECK_UARCH(arch, CHIP_UHD_620, "UHD Graphics 620", UARCH_GEN9_5, GT2, 14)
CHECK_UARCH(arch, CHIP_UHD_630, "UHD Graphics 630", UARCH_GEN9_5, GT2, 14) CHECK_UARCH(arch, CHIP_UHD_630, "UHD Graphics 630", UARCH_GEN9_5, GT2, 14)
CHECK_UARCH(arch, CHIP_HD_610, "HD Graphics 610", UARCH_GEN9_5, GT1, 14) CHECK_UARCH(arch, CHIP_HD_610, "HD Graphics 610", UARCH_GEN9_5, GT1, 14)
CHECK_UARCH(arch, CHIP_HD_615, "HD Graphics 615", UARCH_GEN9_5, GT2, 14) CHECK_UARCH(arch, CHIP_HD_615, "HD Graphics 615", UARCH_GEN9_5, GT2, 14)
CHECK_UARCH(arch, CHIP_HD_630, "HD Graphics 630", UARCH_GEN9_5, GT2, 14) CHECK_UARCH(arch, CHIP_HD_630, "HD Graphics 630", UARCH_GEN9_5, GT2, 14)
CHECK_UARCH(arch, CHIP_HD_P630, "HD Graphics P630", UARCH_GEN9_5, GT2, 14) CHECK_UARCH(arch, CHIP_HD_P630, "HD Graphics P630", UARCH_GEN9_5, GT2, 14)
CHECK_UARCH(arch, CHIP_IRISP_640, "Iris Plus Graphics 640", UARCH_GEN9_5, GT3e, 14) CHECK_UARCH(arch, CHIP_IRISP_640, "Iris Plus Graphics 640", UARCH_GEN9_5, GT3e, 14)
CHECK_UARCH(arch, CHIP_IRISP_640, "Iris Plus Graphics 650", UARCH_GEN9_5, GT3e, 14) CHECK_UARCH(arch, CHIP_IRISP_640, "Iris Plus Graphics 650", UARCH_GEN9_5, GT3e, 14)
CHECK_UARCH_END CHECK_UARCH_END
} }
@@ -184,6 +190,7 @@ struct topology_i* get_topology_info(struct uarch* arch) {
CHECK_TOPO(topo, arch, UARCH_GEN6, GT1, 6, 1, 1) CHECK_TOPO(topo, arch, UARCH_GEN6, GT1, 6, 1, 1)
CHECK_TOPO(topo, arch, UARCH_GEN6, GT2, 6, 2, 1) CHECK_TOPO(topo, arch, UARCH_GEN6, GT2, 6, 2, 1)
// Gen7 // Gen7
CHECK_TOPO(topo, arch, UARCH_GEN7, GT1_4, 4, 1, 1)
CHECK_TOPO(topo, arch, UARCH_GEN7, GT1, 6, 1, 1) CHECK_TOPO(topo, arch, UARCH_GEN7, GT1, 6, 1, 1)
CHECK_TOPO(topo, arch, UARCH_GEN7, GT2, 8, 2, 1) CHECK_TOPO(topo, arch, UARCH_GEN7, GT2, 8, 2, 1)
CHECK_TOPO(topo, arch, UARCH_GEN7, GT3, 6, 1, 1) CHECK_TOPO(topo, arch, UARCH_GEN7, GT3, 6, 1, 1)