146 lines
8.1 KiB
C
146 lines
8.1 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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/* This file is autogenerated by ref2h.pl. Do not edit */
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#define NV_EGPC_IN_GR_BASE 1572864
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#define NV_EGPC_IN_GR_SHARED_BASE 524288
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#define NV_EGPC_PRI_SHARED_INDEX -32
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#define NV_EGPC_PRI_STRIDE 32768
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#define NV_FBPA_PRI_STRIDE 16384
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#define NV_FBP_PRIV_BASE 1212416
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#define NV_FBP_PRIV_BC_BASE 1183744
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#define NV_FBP_PRIV_STRIDE 2048
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#define NV_GPC_IN_GR_BASE 1048576
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#define NV_GPC_IN_GR_SHARED_BASE 98304
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#define NV_GPC_PRIV_BASE 1196032
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#define NV_GPC_PRIV_BC_BASE 1181696
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#define NV_GPC_PRIV_STRIDE 2048
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#define NV_GPC_PRI_BASE 5242880
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#define NV_GPC_PRI_SHARED_BASE 4292608
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#define NV_GPC_PRI_SHARED_INDEX -29
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#define NV_GPC_PRI_STRIDE 32768
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#define NV_LTC_PRI_BASE 1310720
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#define NV_LTC_PRI_STRIDE 8192
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#define NV_LTS_PRI_STRIDE 512
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#define NV_CHIP_EXTENDED_PHYSICAL_ADDRESS_BITS 47
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#define NV_CHIP_EXTENDED_SYSTEM_PHYSICAL_ADDRESS_BITS 47
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#define NV_CHIP_EXTENDED_VIRTUAL_ADDRESS_BITS 49
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#define NV_CHIP_ISBE_SIZE 49152
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#define NV_CHIP_LOCAL_PHYSICAL_ADDRESS_BITS 37
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#define NV_CHIP_LTC_LTS_BYTES_PER_LINE 128
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#define NV_CHIP_LTC_LTS_CBC_USE_HUB_BASE 1
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#define NV_CHIP_LTC_LTS_ISO_RDAT_FIFO_DEPTH 192
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#define NV_CHIP_LTC_LTS_NUM_SETS 64
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#define NV_CHIP_PES_ENABLED 1
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#define NV_CHIP_PHYSICAL_ADDRESS_BITS 40
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#define NV_CHIP_SYSTEM_PHYSICAL_ADDRESS_BITS 40
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#define NV_CHIP_TEX_PER_TPC 2
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#define NV_CHIP_VIRTUAL_ADDRESS_BITS 40
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#define NV_GR_FECS_FALCON_IMEM_SIZE 128
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#define NV_GR_GPCCS_FALCON_IMEM_SIZE 64
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#define NV_HOST_MAX_NUM_GRCE_PER_RUNLIST 2
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#define NV_HOST_MAX_NUM_PBDMA 16
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#define NV_HOST_NEW_MEMOP 1
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#define NV_HOST_NUM_ENGINES 11
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#define NV_HOST_NUM_PBDMA 10
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#define NV_LITTER_SUPPORTS_PLC 1
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#define NV_MMU_FAULT_BUFFER_COUNT 2
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#define NV_MMU_NON_REPLAY_FAULT_BUFFER 0
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#define NV_MMU_PROTECTION_REGIONS 1
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#define NV_MMU_PROTECTION_REGION_ADDR_ALIGN 20
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#define NV_MMU_PROTECTION_REGION_ADDR_WIDTH 17
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#define NV_MMU_PROTECTION_REGION_CYA_WIDTH 48
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#define NV_MMU_REPLAY_FAULT_BUFFER 1
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#define NV_MMU_WRITE_PROTECTION_REGIONS 2
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#define NV_MMU_WRITE_PROTECTION_REGION_ADDR_ALIGN 17
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#define NV_MMU_WRITE_PROTECTION_REGION_ADDR_WIDTH 20
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#define NV_MMU_WRITE_PROTECTION_REGION_SECURE_LEVELS 4
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#define NV_NVL_NVLIPT_NUM_LINKS 4
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#define NV_PGRAPH_ZCULL_ALIQUOTS_COVERED 5120
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#define NV_PGRAPH_ZCULL_BYTES_PER_ALIQUOT_PER_GPC 32
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#define NV_PGRAPH_ZCULL_NUM_ZFAR 4
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#define NV_PGRAPH_ZCULL_NUM_ZNEAR 4
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#define NV_PGRAPH_ZCULL_PIXELS_COVERED 36700160
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#define NV_PGRAPH_ZCULL_SAVE_RESTORE_HEADER_BYTES_PER_GPC 32
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#define NV_PGRAPH_ZCULL_SAVE_RESTORE_SUBREGION_HEADER_BYTES_PER_GPC 192
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#define NV_PGRAPH_ZCULL_SUBREGION_QTY 16
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#define NV_RAMRL_ENTRY_EXPANDED 1
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#define NV_SCAL_FAMILY_MAX_FBPS 16
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#define NV_SCAL_FAMILY_MAX_GPCS 32
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#define NV_SCAL_FAMILY_MAX_SYSS 1
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#define NV_SCAL_FAMILY_MAX_TPC_PER_GPC 8
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#define NV_SCAL_FAMILY_MAX_ZCULL_BANKS 8
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#define NV_SCAL_LITTER_MAX_NUM_COMP_SMC_ENGINES 0
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#define NV_SCAL_LITTER_MAX_NUM_GFXC_SMC_ENGINES 1
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#define NV_SCAL_LITTER_MAX_NUM_SMC_ENGINES 1
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#define NV_SCAL_LITTER_NUM_FBHUB_PORTS 2
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#define NV_SCAL_LITTER_NUM_FBPAS 6
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#define NV_SCAL_LITTER_NUM_FBPA_PER_FBP 1
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#define NV_SCAL_LITTER_NUM_FBPS 6
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#define NV_SCAL_LITTER_NUM_GPCMMU_PER_GPC 1
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#define NV_SCAL_LITTER_NUM_GPCS 7
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#define NV_SCAL_LITTER_NUM_IOCTRL 1
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#define NV_SCAL_LITTER_NUM_LTCS 12
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#define NV_SCAL_LITTER_NUM_LTC_LTS_SETS 64
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#define NV_SCAL_LITTER_NUM_LTC_LTS_WAYS 16
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#define NV_SCAL_LITTER_NUM_LTC_PER_FBP 2
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#define NV_SCAL_LITTER_NUM_LTC_SLICES 8
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#define NV_SCAL_LITTER_NUM_MIN_FBPS 1
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#define NV_SCAL_LITTER_NUM_MXBAR_FBP_PORTS 8
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#define NV_SCAL_LITTER_NUM_MXBAR_HUB_PORTS 8
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#define NV_SCAL_LITTER_NUM_NVLINK 4
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#define NV_SCAL_LITTER_NUM_PES_PER_GPC 3
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#define NV_SCAL_LITTER_NUM_ROP_PER_GPC 2
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#define NV_SCAL_LITTER_NUM_SLICES_PER_LTC 4
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#define NV_SCAL_LITTER_NUM_SM_PER_TPC 2
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#define NV_SCAL_LITTER_NUM_SYSB 0
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#define NV_SCAL_LITTER_NUM_SYSC 1
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#define NV_SCAL_LITTER_NUM_SYSS 1
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#define NV_SCAL_LITTER_NUM_TPCS_PER_PES 2
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#define NV_SCAL_LITTER_NUM_TPC_PER_GPC 6
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#define NV_SCAL_LITTER_NUM_ZCULL_BANKS 4
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#define NV_SCAL_LITTER_SM_FMA32_PER_SM 128
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#define NV_UPPER_MEMORY_BIT 36
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#define NV_PGRAPH_BASE 4194304
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#define NV_PPC_IN_GPC_BASE 12288
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#define NV_PPC_IN_GPC_PRI_SHARED_INDEX 7
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#define NV_PPC_IN_GPC_SHARED_BASE 15872
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#define NV_PPC_IN_GPC_STRIDE 512
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#define NV_PRI_GPC_ADDR_WIDTH 15
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#define NV_PRI_TPC_ADDR_WIDTH 11
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#define NV_ROP_IN_GPC_BASE 14336
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#define NV_ROP_IN_GPC_PRI_SHARED_INDEX 2
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#define NV_ROP_IN_GPC_SHARED_BASE 15360
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#define NV_ROP_IN_GPC_STRIDE 512
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#define NV_ROP_PRI_BASE 4259840
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#define NV_ROP_PRI_SHARED_BASE 4229120
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#define NV_ROP_PRI_SHARED_INDEX -30
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#define NV_ROP_PRI_STRIDE 1024
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#define NV_SMC_PRIV_BASE 16777216
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#define NV_SMC_PRIV_STRIDE 2097152
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#define NV_SMPC_PRI_BASE 512
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#define NV_SMPC_PRI_SHARED_BASE 768
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#define NV_SMPC_PRI_STRIDE 256
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#define NV_SMPC_PRI_UNIQUE_BASE 1536
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#define NV_SM_PRI_SHARED_BASE 1664
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#define NV_SM_PRI_STRIDE 128
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#define NV_SM_PRI_UNIQUE_BASE 1792
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#define NV_SYSB_PRIV_BASE 1189888
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#define NV_SYSB_PRIV_STRIDE 2048
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#define NV_SYSC_PRIV_BASE 1191936
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#define NV_SYSC_PRIV_STRIDE 2048
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#define NV_SYS_PRIV_BASE 1187840
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#define NV_SYS_PRIV_BC_BASE 1185792
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#define NV_SYS_PRIV_STRIDE 2048
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#define NV_TPC_IN_GPC_BASE 16384
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#define NV_TPC_IN_GPC_PRI_SHARED_INDEX -5
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#define NV_TPC_IN_GPC_SHARED_BASE 6144
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#define NV_TPC_IN_GPC_STRIDE 2048
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