274 lines
11 KiB
C
274 lines
11 KiB
C
// gddr6.c
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#define _FILE_OFFSET_BITS 64
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#define _GNU_SOURCE
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#include "gddr6.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <unistd.h>
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#include <string.h>
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#include <errno.h>
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#include <fcntl.h>
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#include <sys/mman.h>
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#include <pci/pci.h>
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#define PG_SZ sysconf(_SC_PAGE_SIZE)
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#define PRINT_ERROR() \
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do { \
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fprintf(stderr, "Error at line %d, file %s (%d) [%s]\n", \
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__LINE__, __FILE__, errno, strerror(errno)); exit(1); \
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} while(0)
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#define MAX_DEVICES 32
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struct gddr6_ctx ctx = {0};
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// Ada/Ampere GPUs: temperature field is bits [11:0], Celsius = field / 32.
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struct device dev_table[] =
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{
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{ .offset = 0x0000E2A8, .dev_id = 0x2684, .vram = "GDDR6X", .arch = "AD102", .name = "RTX 4090" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2685, .vram = "GDDR6X", .arch = "AD102", .name = "RTX 4090 D" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2702, .vram = "GDDR6X", .arch = "AD103", .name = "RTX 4080 Super" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2704, .vram = "GDDR6X", .arch = "AD103", .name = "RTX 4080" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2705, .vram = "GDDR6X", .arch = "AD103", .name = "RTX 4070 Ti Super" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2782, .vram = "GDDR6X", .arch = "AD104", .name = "RTX 4070 Ti" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2783, .vram = "GDDR6X", .arch = "AD104", .name = "RTX 4070 Super" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2786, .vram = "GDDR6X", .arch = "AD104", .name = "RTX 4070" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2860, .vram = "GDDR6", .arch = "AD106", .name = "RTX 4070 Max-Q / Mobile" },
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{ .offset = 0x0000E2A8, .dev_id = 0x28e0, .vram = "GDDR6", .arch = "AD107", .name = "RTX 4060 Max-Q / Mobile" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2203, .vram = "GDDR6X", .arch = "GA102", .name = "RTX 3090 Ti" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2204, .vram = "GDDR6X", .arch = "GA102", .name = "RTX 3090" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2208, .vram = "GDDR6X", .arch = "GA102", .name = "RTX 3080 Ti" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2206, .vram = "GDDR6X", .arch = "GA102", .name = "RTX 3080" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2216, .vram = "GDDR6X", .arch = "GA102", .name = "RTX 3080 LHR" },
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{ .offset = 0x0000EE50, .dev_id = 0x2484, .vram = "GDDR6", .arch = "GA104", .name = "RTX 3070" },
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{ .offset = 0x0000EE50, .dev_id = 0x2488, .vram = "GDDR6", .arch = "GA104", .name = "RTX 3070 LHR" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2531, .vram = "GDDR6", .arch = "GA106", .name = "RTX A2000" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2571, .vram = "GDDR6", .arch = "GA106", .name = "RTX A2000" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2232, .vram = "GDDR6", .arch = "GA102", .name = "RTX A4500" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2231, .vram = "GDDR6", .arch = "GA102", .name = "RTX A5000" },
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{ .offset = 0x0000E2A8, .dev_id = 0x26B1, .vram = "GDDR6", .arch = "AD102", .name = "RTX 6000 Ada Generation" },
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{ .offset = 0x0000E2A8, .dev_id = 0x27b8, .vram = "GDDR6", .arch = "AD104", .name = "L4" },
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{ .offset = 0x0000E2A8, .dev_id = 0x26b9, .vram = "GDDR6", .arch = "AD102", .name = "L40S" },
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{ .offset = 0x0000E2A8, .dev_id = 0x2236, .vram = "GDDR6", .arch = "GA102", .name = "A10" },
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// Blackwell GDDR7 memory temperature: the raw FBPA DRAM sensor at
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// NV_PFB_FBPA_DQR_STATUS_DQ_IC0_SUBP0 (0x9A24C0) - the register the FBFALCON
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// firmware reads. NOT PLM-locked; reads valid data from userspace (validity
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// bit 24 of 0x9A24D0). The value is a per-device GDDR temp MR-code in bits
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// 23:16; DECODE_GDDR_MRCODE converts it to Celsius. (The documented mem-temp
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// reg 0x9A44B0 is PLM-locked and its 0xE2A8 scratch mirror is unpopulated on
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// this card, so we read the raw sensor directly.)
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{ .offset = 0x009A24C0, .decode = DECODE_GDDR_MRCODE, .dev_id = 0x2b85, .vram = "GDDR7", .arch = "GB202", .name = "RTX 5090" },
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};
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void gddr6_init(void)
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{
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ctx.fd = open("/dev/mem", O_RDONLY);
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if (ctx.fd == -1) {
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PRINT_ERROR();
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}
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}
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int gddr6_detect_compatible_gpus(void)
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{
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ctx.devices = NULL;
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ctx.num_devices = 0;
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struct pci_access *pacc = NULL;
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struct pci_dev *pci_dev = NULL;
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ssize_t dev_table_size = (sizeof(dev_table)/sizeof(struct device));
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pacc = pci_alloc();
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pci_init(pacc);
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pci_scan_bus(pacc);
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for (pci_dev = pacc->devices; pci_dev != NULL; pci_dev = pci_dev->next)
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{
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pci_fill_info(pci_dev, PCI_FILL_IDENT | PCI_FILL_BASES | PCI_FILL_CLASS);
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for (uint32_t i = 0; i < dev_table_size; ++i)
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{
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if (pci_dev->device_id == dev_table[i].dev_id)
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{
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struct device *new_devices = realloc(ctx.devices, (ctx.num_devices + 1) * sizeof(struct device));
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if (new_devices == NULL)
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{
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fprintf(stderr, "Memory allocation failed\n");
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pci_cleanup(pacc);
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free(ctx.devices);
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ctx.devices = NULL;
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return 0;
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}
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ctx.devices = new_devices;
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ctx.devices[ctx.num_devices] = dev_table[i];
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ctx.devices[ctx.num_devices].bar0 =
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(uint64_t)(pci_dev->base_addr[0] & PCI_ADDR_MEM_MASK);
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ctx.devices[ctx.num_devices].bus = pci_dev->bus;
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ctx.devices[ctx.num_devices].dev = pci_dev->dev;
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ctx.devices[ctx.num_devices].func = pci_dev->func;
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ctx.num_devices++;
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}
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}
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}
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pci_cleanup(pacc);
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return ctx.num_devices;
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}
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void gddr6_memory_map(void)
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{
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for (uint32_t i = 0; i < ctx.num_devices; i++)
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{
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ctx.devices[i].phys_addr = (ctx.devices[i].bar0 + ctx.devices[i].offset);
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ctx.devices[i].base_offset =
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ctx.devices[i].phys_addr & ~((uint64_t)PG_SZ - 1);
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ctx.devices[i].mapped_addr = mmap(0, PG_SZ, PROT_READ, MAP_SHARED,
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ctx.fd, (off_t)ctx.devices[i].base_offset);
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if (ctx.devices[i].mapped_addr == MAP_FAILED)
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{
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ctx.devices[i].mapped_addr = NULL;
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fprintf(stderr, "Memory mapping failed for pci=%x:%x:%x\n", ctx.devices[i].bus, ctx.devices[i].dev, ctx.devices[i].func);
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fprintf(stderr, "Did you enable iomem=relaxed? Are you r00t?\n");
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exit(EXIT_FAILURE);
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} else {
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printf("Device: %s %s (%s / 0x%04x) pci=%x:%x:%x\n", ctx.devices[i].name, ctx.devices[i].vram,
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ctx.devices[i].arch, ctx.devices[i].dev_id, ctx.devices[i].bus, ctx.devices[i].dev, ctx.devices[i].func);
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}
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}
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}
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// Convert a raw register value to degrees Celsius per the device's decode.
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static int decode_temp(enum temp_decode decode, uint32_t raw)
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{
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switch (decode)
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{
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case DECODE_GDDR_MRCODE:
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{
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// GDDR temp MR-code in bits 23:16 (see NV_PFB_FBPA_DQR_STATUS_DQ).
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// code 20 = 0 C, +2 C per unit above 20; below 20 is negative.
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int code = (raw >> 16) & 0xFF;
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if (code > 80) code = 80;
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return (code > 19) ? (code - 20) * 2 : -(40 - code * 2);
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}
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case DECODE_ADA:
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default:
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return (raw & 0x00000fff) / 0x20;
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}
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}
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// Blackwell GDDR7 per-memory-partition (module) DQR sensors. Module p lives at
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// BAR0 + DQR_MODULE0 + p*DQR_STRIDE; validity nibble (all 4 IC/subp valid = 0xF)
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// is at +DQR_VLD_OFF. Unlike the single pre-mapped register, these span several
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// pages, so they are read on demand with a fresh page-aligned mmap.
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#define DQR_MODULE0 0x009024C0u
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#define DQR_VLD_OFF (0x009024D0u - 0x009024C0u) // +0x10
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#define DQR_STRIDE 0x00004000u
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#define DQR_MAX_MODULES 16
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// Read one 32-bit MMIO register at BAR0+off via a fresh read-only page mmap.
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// Returns 0 on success. Used only for the on-demand per-module GDDR7 reads.
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static int read_bar0_reg(uint64_t bar0, uint32_t off, uint32_t *out)
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{
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long pg = PG_SZ;
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uint64_t phys = (uint64_t)bar0 + off;
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uint64_t base = phys & ~((uint64_t)pg - 1);
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volatile void *map = mmap(0, pg, PROT_READ, MAP_SHARED, ctx.fd, (off_t)base);
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if (map == MAP_FAILED) return -1;
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*out = *(volatile uint32_t *)((const uint8_t *)map + (phys - base));
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munmap((void *)map, pg);
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return 0;
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}
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// Read the GDDR7 modules for a Blackwell device. Fills temps[]/present[] for up
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// to DQR_MAX_MODULES, returns the module count found and the hottest temp in
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// *hottest. A module counts as present only if all 4 DQR valid bits are set and
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// the data word is not the 0xBADF.... poison sentinel.
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static int gddr7_read_modules(uint64_t bar0, int temps[], int *hottest)
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{
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int count = 0, hot = -128;
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for (int p = 0; p < DQR_MAX_MODULES; p++)
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{
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uint32_t off = DQR_MODULE0 + (uint32_t)p * DQR_STRIDE;
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uint32_t vld = 0, dq = 0;
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if (read_bar0_reg(bar0, off + DQR_VLD_OFF, &vld) != 0) continue;
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if (read_bar0_reg(bar0, off, &dq) != 0) continue;
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int all_valid = (((vld >> 24) & 0xF) == 0xF);
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int poison = ((dq & 0xFFFF0000u) == 0xBADF0000u);
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if (!all_valid || poison) continue;
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int c = decode_temp(DECODE_GDDR_MRCODE, dq);
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temps[count++] = c;
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if (c > hot) hot = c;
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}
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*hottest = hot;
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return count;
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}
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void gddr6_monitor_temperatures(int per_module)
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{
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int temps[DQR_MAX_MODULES];
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while (1) {
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printf("\rVRAM Temps: |");
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for (uint32_t i = 0; i < ctx.num_devices; i++)
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{
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if (ctx.devices[i].mapped_addr == NULL || ctx.devices[i].mapped_addr == MAP_FAILED)
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{
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continue;
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}
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// Blackwell GDDR7: per-module DQR sensors. Default shows the hotspot
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// (max across modules); --per-module lists each module.
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if (ctx.devices[i].decode == DECODE_GDDR_MRCODE)
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{
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int hottest = 0;
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int n = gddr7_read_modules(ctx.devices[i].bar0, temps, &hottest);
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if (n == 0) { printf(" n/a |"); continue; }
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if (per_module)
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{
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for (int m = 0; m < n; m++)
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printf(" m%d=%3d°C |", m, temps[m]);
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}
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else
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{
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printf(" %3d°C (hotspot) |", hottest);
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}
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continue;
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}
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// Ada/Ampere: single pre-mapped VRAM register.
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void *virt_addr = (uint8_t *) ctx.devices[i].mapped_addr + (ctx.devices[i].phys_addr - ctx.devices[i].base_offset);
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uint32_t read_result = *((uint32_t *)virt_addr);
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int temp = decode_temp(ctx.devices[i].decode, read_result);
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printf(" %3d°C |", temp);
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}
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fflush(stdout);
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sleep(1);
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}
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}
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void gddr6_cleanup(int signal)
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{
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for (uint32_t i = 0; i < ctx.num_devices; i++)
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{
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if (ctx.devices[i].mapped_addr != NULL && ctx.devices[i].mapped_addr != MAP_FAILED)
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{
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munmap(ctx.devices[i].mapped_addr, PG_SZ);
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ctx.devices[i].mapped_addr = NULL;
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}
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}
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if (ctx.fd != -1)
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{
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close(ctx.fd);
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ctx.fd = -1;
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}
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if (ctx.devices)
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{
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free(ctx.devices);
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ctx.devices = NULL;
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}
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exit(signal);
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}
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