1760 lines
220 KiB
C
1760 lines
220 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_pmu_riscv_csr_64_h__
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#define __ga102_dev_pmu_riscv_csr_64_h__
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/* This file is autogenerated. Do not edit */
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#define NV_RISCV_CSR 0x007fff:0x000000 /* RW--D */
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#define NV_RISCV_CSR_MISA 0x00000301 /* R-I4R */
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#define NV_RISCV_CSR_MISA_MXL 64-1:64-2 /* R-IVF */
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#define NV_RISCV_CSR_MISA_MXL_32 0x00000001 /* R---V */
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#define NV_RISCV_CSR_MISA_MXL_64 0x00000002 /* R-I-V */
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#define NV_RISCV_CSR_MISA_MXL_128 0x00000003 /* R---V */
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#define NV_RISCV_CSR_MISA_WPRI 64-3:26 /* R-IVF */
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#define NV_RISCV_CSR_MISA_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MISA_EXT2 25:3 /* R-IVF */
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#define NV_RISCV_CSR_MISA_EXT2_RST 0x00128224 /* R-I-V */
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#define NV_RISCV_CSR_MISA_EXT_C 2:2 /* R-IVF */
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#define NV_RISCV_CSR_MISA_EXT_C_RST 0x00000001 /* R-I-V */
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#define NV_RISCV_CSR_MISA_EXT1 1:0 /* R-IVF */
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#define NV_RISCV_CSR_MISA_EXT1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MVENDORID 0x00000f11 /* R-I4R */
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#define NV_RISCV_CSR_MVENDORID_VENDORH 63:32 /* R-IVF */
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#define NV_RISCV_CSR_MVENDORID_VENDORH_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MVENDORID_VENDORL 31:0 /* R-IVF */
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#define NV_RISCV_CSR_MVENDORID_VENDORL_RST 0x000001eb /* R-I-V */
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#define NV_RISCV_CSR_MARCHID 0x00000f12 /* R-I4R */
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#define NV_RISCV_CSR_MARCHID_MSB 64-1:64-1 /* R-IVF */
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#define NV_RISCV_CSR_MARCHID_MSB_RST 0x00000001 /* R-I-V */
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#define NV_RISCV_CSR_MARCHID_RS1 64-2:16 /* R-IVF */
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#define NV_RISCV_CSR_MARCHID_RS1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MARCHID_CORE_MAJOR 15:12 /* R-IVF */
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#define NV_RISCV_CSR_MARCHID_CORE_MAJOR_RST 0x00000002 /* R-I-V */
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#define NV_RISCV_CSR_MARCHID_CORE_MINOR 11:8 /* R-IVF */
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#define NV_RISCV_CSR_MARCHID_CORE_MINOR_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MARCHID_DCACHE_SIZE 7:4 /* R--VF */
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#define NV_RISCV_CSR_MARCHID_DCACHE_SIZE_128KB 8 /* */
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#define NV_RISCV_CSR_MARCHID_DCACHE_SIZE_64KB 7 /* */
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#define NV_RISCV_CSR_MARCHID_DCACHE_SIZE_32KB 6 /* */
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#define NV_RISCV_CSR_MARCHID_DCACHE_SIZE_16KB 5 /* */
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#define NV_RISCV_CSR_MARCHID_DCACHE_SIZE_0KB 0 /* */
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#define NV_RISCV_CSR_MARCHID_ICACHE_SIZE 3:0 /* R--VF */
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#define NV_RISCV_CSR_MARCHID_ICACHE_SIZE_128KB 8 /* */
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#define NV_RISCV_CSR_MARCHID_ICACHE_SIZE_64KB 7 /* */
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#define NV_RISCV_CSR_MARCHID_ICACHE_SIZE_32KB 6 /* */
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#define NV_RISCV_CSR_MARCHID_ICACHE_SIZE_16KB 5 /* */
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#define NV_RISCV_CSR_MARCHID_ICACHE_SIZE_0KB 0 /* */
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#define NV_RISCV_CSR_MIMPID 0x00000f13 /* R-I4R */
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#define NV_RISCV_CSR_MIMPID_IMPID 64-1:0 /* R-IVF */
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#define NV_RISCV_CSR_MIMPID_IMPID_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MHARTID 0x00000f14 /* R-I4R */
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#define NV_RISCV_CSR_MHARTID_HART 64-1:0 /* R-IVF */
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#define NV_RISCV_CSR_MHARTID_HART_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSTATUS 0x00000300 /* RWI4R */
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#define NV_RISCV_CSR_MSTATUS_SD 63:63 /* R--VF */
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#define NV_RISCV_CSR_MSTATUS_WPRI4 62:36 /* R-IVF */
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#define NV_RISCV_CSR_MSTATUS_WPRI4_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSTATUS_SXL 35:34 /* R-IVF */
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#define NV_RISCV_CSR_MSTATUS_SXL_RST 0x00000002 /* R-I-V */
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#define NV_RISCV_CSR_MSTATUS_UXL 33:32 /* R-IVF */
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#define NV_RISCV_CSR_MSTATUS_UXL_RST 0x00000002 /* R-I-V */
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#define NV_RISCV_CSR_MSTATUS_WPRI3 31:24 /* R-IVF */
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#define NV_RISCV_CSR_MSTATUS_WPRI3_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSTATUS_MMI 23:23 /* RWIVF */
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#define NV_RISCV_CSR_MSTATUS_MMI_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSTATUS_MMI_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_TSR 22:22 /* RWIVF */
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#define NV_RISCV_CSR_MSTATUS_TSR_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSTATUS_TSR_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_TW 21:21 /* RWIVF */
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#define NV_RISCV_CSR_MSTATUS_TW_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSTATUS_TW_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_TVM 20:20 /* RWIVF */
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#define NV_RISCV_CSR_MSTATUS_TVM_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSTATUS_TVM_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_MXR 19:19 /* RWIVF */
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#define NV_RISCV_CSR_MSTATUS_MXR_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSTATUS_MXR_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_SUM 18:18 /* R-IVF */
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#define NV_RISCV_CSR_MSTATUS_SUM_DISABLE 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSTATUS_MPRV 17:17 /* RWIVF */
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#define NV_RISCV_CSR_MSTATUS_MPRV_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSTATUS_MPRV_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_XS 16:15 /* R-IVF */
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#define NV_RISCV_CSR_MSTATUS_XS_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSTATUS_FS 14:13 /* RWIVF */
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#define NV_RISCV_CSR_MSTATUS_FS_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSTATUS_FS_INITIAL 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_FS_CLEAN 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_FS_DIRTY 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_MPP 12:11 /* RWIVF */
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#define NV_RISCV_CSR_MSTATUS_MPP_USER 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSTATUS_MPP_SUPERVISOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_MPP_MACHINE 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_WPRI2 10:9 /* R-IVF */
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#define NV_RISCV_CSR_MSTATUS_WPRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSTATUS_SPP 8:8 /* RWIVF */
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#define NV_RISCV_CSR_MSTATUS_SPP_USER 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSTATUS_SPP_SUPERVISOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_MPIE 7:7 /* RWIVF */
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#define NV_RISCV_CSR_MSTATUS_MPIE_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSTATUS_MPIE_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_WPRI1 6:6 /* R-IVF */
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#define NV_RISCV_CSR_MSTATUS_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSTATUS_SPIE 5:5 /* RWIVF */
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#define NV_RISCV_CSR_MSTATUS_SPIE_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSTATUS_SPIE_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_UPIE 4:4 /* R-IVF */
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#define NV_RISCV_CSR_MSTATUS_UPIE_DISABLE 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSTATUS_MIE 3:3 /* RWIVF */
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#define NV_RISCV_CSR_MSTATUS_MIE_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSTATUS_MIE_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_WPRI0 2:2 /* R-IVF */
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#define NV_RISCV_CSR_MSTATUS_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSTATUS_SIE 1:1 /* RWIVF */
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#define NV_RISCV_CSR_MSTATUS_SIE_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSTATUS_SIE_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSTATUS_UIE 0:0 /* R-IVF */
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#define NV_RISCV_CSR_MSTATUS_UIE_DISABLE 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MTVEC 0x00000305 /* RWI4R */
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#define NV_RISCV_CSR_MTVEC_BASE 64-1:2 /* RWIVF */
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#define NV_RISCV_CSR_MTVEC_BASE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MTVEC_MODE 1:0 /* RWIVF */
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#define NV_RISCV_CSR_MTVEC_MODE_DIRECT 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MTVEC_MODE_VECTORED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEDELEG 0x00000302 /* RWI4R */
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#define NV_RISCV_CSR_MEDELEG_WPRI3 64-1:29 /* R-IVF */
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#define NV_RISCV_CSR_MEDELEG_WPRI3_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEDELEG_USS 28:28 /* RWIVF */
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#define NV_RISCV_CSR_MEDELEG_USS_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEDELEG_USS_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEDELEG_WPRI2 27:16 /* R-IVF */
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#define NV_RISCV_CSR_MEDELEG_WPRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEDELEG_STORE_PAGE_FAULT 15:15 /* RWIVF */
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#define NV_RISCV_CSR_MEDELEG_STORE_PAGE_FAULT_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEDELEG_STORE_PAGE_FAULT_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEDELEG_WPRI1 14:14 /* R-IVF */
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#define NV_RISCV_CSR_MEDELEG_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEDELEG_LOAD_PAGE_FAULT 13:13 /* RWIVF */
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#define NV_RISCV_CSR_MEDELEG_LOAD_PAGE_FAULT_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEDELEG_LOAD_PAGE_FAULT_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEDELEG_FETCH_PAGE_FAULT 12:12 /* RWIVF */
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#define NV_RISCV_CSR_MEDELEG_FETCH_PAGE_FAULT_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEDELEG_FETCH_PAGE_FAULT_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEDELEG_WPRI0 11:9 /* R-IVF */
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#define NV_RISCV_CSR_MEDELEG_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEDELEG_USER_ECALL 8:8 /* RWIVF */
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#define NV_RISCV_CSR_MEDELEG_USER_ECALL_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEDELEG_USER_ECALL_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEDELEG_FAULT_STORE 7:7 /* RWIVF */
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#define NV_RISCV_CSR_MEDELEG_FAULT_STORE_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEDELEG_FAULT_STORE_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEDELEG_MISALIGNED_STORE 6:6 /* RWIVF */
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#define NV_RISCV_CSR_MEDELEG_MISALIGNED_STORE_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEDELEG_MISALIGNED_STORE_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEDELEG_FAULT_LOAD 5:5 /* RWIVF */
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#define NV_RISCV_CSR_MEDELEG_FAULT_LOAD_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEDELEG_FAULT_LOAD_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEDELEG_MISALIGNED_LOAD 4:4 /* RWIVF */
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#define NV_RISCV_CSR_MEDELEG_MISALIGNED_LOAD_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEDELEG_MISALIGNED_LOAD_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEDELEG_BREAKPOINT 3:3 /* RWIVF */
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#define NV_RISCV_CSR_MEDELEG_BREAKPOINT_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEDELEG_BREAKPOINT_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEDELEG_ILLEGAL_INSTRUCTION 2:2 /* RWIVF */
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#define NV_RISCV_CSR_MEDELEG_ILLEGAL_INSTRUCTION_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEDELEG_ILLEGAL_INSTRUCTION_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEDELEG_FAULT_FETCH 1:1 /* RWIVF */
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#define NV_RISCV_CSR_MEDELEG_FAULT_FETCH_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEDELEG_FAULT_FETCH_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEDELEG_MISALIGNED_FETCH 0:0 /* RWIVF */
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#define NV_RISCV_CSR_MEDELEG_MISALIGNED_FETCH_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEDELEG_MISALIGNED_FETCH_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MIDELEG 0x00000303 /* RWI4R */
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#define NV_RISCV_CSR_MIDELEG_WPRI2 64-1:10 /* R-IVF */
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#define NV_RISCV_CSR_MIDELEG_WPRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIDELEG_SEID 9:9 /* RWIVF */
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#define NV_RISCV_CSR_MIDELEG_SEID_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MIDELEG_SEID_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MIDELEG_UEID 8:8 /* R-IVF */
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#define NV_RISCV_CSR_MIDELEG_UEID_NODELEG 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIDELEG_UEID_DELEG 0x00000001 /* R---V */
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#define NV_RISCV_CSR_MIDELEG_WPRI1 7:6 /* R-IVF */
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#define NV_RISCV_CSR_MIDELEG_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIDELEG_STID 5:5 /* RWIVF */
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#define NV_RISCV_CSR_MIDELEG_STID_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MIDELEG_STID_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MIDELEG_UTID 4:4 /* R-IVF */
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#define NV_RISCV_CSR_MIDELEG_UTID_NODELEG 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIDELEG_UTID_DELEG 0x00000001 /* R---V */
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#define NV_RISCV_CSR_MIDELEG_WPRI0 3:2 /* R-IVF */
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#define NV_RISCV_CSR_MIDELEG_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIDELEG_SSID 1:1 /* RWIVF */
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#define NV_RISCV_CSR_MIDELEG_SSID_NODELEG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MIDELEG_SSID_DELEG 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MIDELEG_USID 0:0 /* R-IVF */
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#define NV_RISCV_CSR_MIDELEG_USID_NODELEG 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIDELEG_USID_DELEG 0x00000001 /* R---V */
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#define NV_RISCV_CSR_MIP 0x00000344 /* RWI4R */
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#define NV_RISCV_CSR_MIP_WIRI3 64-1:12 /* R-IVF */
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#define NV_RISCV_CSR_MIP_WIRI3_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIP_MEIP 11:11 /* R-IVF */
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#define NV_RISCV_CSR_MIP_MEIP_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIP_WIRI2 10:10 /* R-IVF */
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#define NV_RISCV_CSR_MIP_WIRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIP_SEIP 9:9 /* RWIVF */
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#define NV_RISCV_CSR_MIP_SEIP_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MIP_UEIP 8:8 /* R-IVF */
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#define NV_RISCV_CSR_MIP_UEIP_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIP_MTIP 7:7 /* R-IVF */
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#define NV_RISCV_CSR_MIP_MTIP_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIP_WIRI1 6:6 /* R-IVF */
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#define NV_RISCV_CSR_MIP_WIRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIP_STIP 5:5 /* RWIVF */
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#define NV_RISCV_CSR_MIP_STIP_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MIP_UTIP 4:4 /* R-IVF */
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#define NV_RISCV_CSR_MIP_UTIP_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIP_MSIP 3:3 /* R-IVF */
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#define NV_RISCV_CSR_MIP_MSIP_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIP_WIRI0 2:2 /* R-IVF */
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#define NV_RISCV_CSR_MIP_WIRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIP_SSIP 1:1 /* RWIVF */
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#define NV_RISCV_CSR_MIP_SSIP_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MIP_USIP 0:0 /* R-IVF */
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#define NV_RISCV_CSR_MIP_USIP_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIE 0x00000304 /* RWI4R */
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#define NV_RISCV_CSR_MIE_WPRI3 64-1:12 /* R-IVF */
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#define NV_RISCV_CSR_MIE_WPRI3_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIE_MEIE 11:11 /* RWIVF */
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#define NV_RISCV_CSR_MIE_MEIE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MIE_WPRI2 10:10 /* R-IVF */
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#define NV_RISCV_CSR_MIE_WPRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIE_SEIE 9:9 /* RWIVF */
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#define NV_RISCV_CSR_MIE_SEIE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MIE_UEIE 8:8 /* R-IVF */
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#define NV_RISCV_CSR_MIE_UEIE_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIE_MTIE 7:7 /* RWIVF */
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#define NV_RISCV_CSR_MIE_MTIE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MIE_WPRI1 6:6 /* R-IVF */
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#define NV_RISCV_CSR_MIE_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIE_STIE 5:5 /* RWIVF */
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#define NV_RISCV_CSR_MIE_STIE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MIE_UTIE 4:4 /* R-IVF */
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#define NV_RISCV_CSR_MIE_UTIE_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIE_MSIE 3:3 /* RWIVF */
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#define NV_RISCV_CSR_MIE_MSIE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MIE_WPRI0 2:2 /* R-IVF */
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#define NV_RISCV_CSR_MIE_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MIE_SSIE 1:1 /* RWIVF */
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#define NV_RISCV_CSR_MIE_SSIE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MIE_USIE 0:0 /* R-IVF */
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#define NV_RISCV_CSR_MIE_USIE_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MHPMCOUNTER(i) (0x00000b00+(i)) /* RWI4A */
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#define NV_RISCV_CSR_MHPMCOUNTER__SIZE_1 32 /* */
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#define NV_RISCV_CSR_MHPMCOUNTER_VALUE 64-1:0 /* RWIVF */
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#define NV_RISCV_CSR_MHPMCOUNTER_VALUE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MHPMCOUNTER_MCYCLE 0x00000b00 /* */
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#define NV_RISCV_CSR_MHPMCOUNTER_MINSTRET 0x00000b02 /* */
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#define NV_RISCV_CSR_MCOUNTEREN 0x00000306 /* RWI4R */
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#define NV_RISCV_CSR_MCOUNTEREN_RS0 63:32 /* R-IVF */
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#define NV_RISCV_CSR_MCOUNTEREN_RS0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MCOUNTEREN_HPM 31:3 /* RWIVF */
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#define NV_RISCV_CSR_MCOUNTEREN_HPM_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCOUNTEREN_IR 2:2 /* RWIVF */
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#define NV_RISCV_CSR_MCOUNTEREN_IR_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCOUNTEREN_IR_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCOUNTEREN_TM 1:1 /* RWIVF */
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#define NV_RISCV_CSR_MCOUNTEREN_TM_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCOUNTEREN_TM_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCOUNTEREN_CY 0:0 /* RWIVF */
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#define NV_RISCV_CSR_MCOUNTEREN_CY_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCOUNTEREN_CY_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MHPMEVENT(i) (0x00000320+(i)) /* RWI4A */
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#define NV_RISCV_CSR_MHPMEVENT__SIZE_1 32 /* */
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#define NV_RISCV_CSR_MHPMEVENT_VALUE 63:0 /* RWIVF */
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#define NV_RISCV_CSR_MHPMEVENT_VALUE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSCRATCH 0x00000340 /* RWI4R */
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#define NV_RISCV_CSR_MSCRATCH_SCRATCH 64-1:0 /* RWIVF */
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#define NV_RISCV_CSR_MSCRATCH_SCRATCH_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEPC 0x00000341 /* RWI4R */
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#define NV_RISCV_CSR_MEPC_EPC 64-1:0 /* RWIVF */
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#define NV_RISCV_CSR_MEPC_EPC_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCAUSE 0x00000342 /* RWI4R */
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#define NV_RISCV_CSR_MCAUSE_INT 64-1:64-1 /* RWIVF */
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#define NV_RISCV_CSR_MCAUSE_INT_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCAUSE_WLRL 64-2:5 /* R-IVF */
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#define NV_RISCV_CSR_MCAUSE_WLRL_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE 4:0 /* RWIVF */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_IAMA 0x00000000 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_IACC_FAULT 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_ILL 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_BKPT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_LAMA 0x00000004 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_LACC_FAULT 0x00000005 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_SAMA 0x00000006 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_SACC_FAULT 0x00000007 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_UCALL 0x00000008 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_SCALL 0x00000009 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_MCALL 0x0000000b /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_IPAGE_FAULT 0x0000000c /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_LPAGE_FAULT 0x0000000d /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_SPAGE_FAULT 0x0000000f /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_USS 0x0000001c /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_SSS 0x0000001d /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_U_SWINT 0x00000000 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_S_SWINT 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_M_SWINT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_U_TINT 0x00000004 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_S_TINT 0x00000005 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_M_TINT 0x00000007 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_U_EINT 0x00000008 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_S_EINT 0x00000009 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE_EXCODE_M_EINT 0x0000000b /* RW--V */
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#define NV_RISCV_CSR_MCAUSE2 0x000007d4 /* RWI4R */
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#define NV_RISCV_CSR_MCAUSE2_WPRI 64-1:24 /* R-IVF */
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#define NV_RISCV_CSR_MCAUSE2_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MCAUSE2_CAUSE 23:16 /* RWIVF */
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#define NV_RISCV_CSR_MCAUSE2_CAUSE_NO 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCAUSE2_CAUSE_EBREAK 0x00000017 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE2_CAUSE_HW_TRIGGER 0x00000018 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE2_CAUSE_U_SINGLE_STEP 0x00000019 /* RW--V */
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#define NV_RISCV_CSR_MCAUSE2_ERROR 15:0 /* RWIVF */
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#define NV_RISCV_CSR_MCAUSE2_ERROR_NO 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCAUSE2_TRIGGER_INDEX 5:0 /* */
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#define NV_RISCV_CSR_MTVAL 0x00000343 /* RWI4R */
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#define NV_RISCV_CSR_MTVAL_VALUE 64-1:0 /* RWIVF */
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#define NV_RISCV_CSR_MTVAL_VALUE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0 0x000003a0 /* RWI4R */
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#define NV_RISCV_CSR_PMPCFG0_PMP7L 63:63 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP7L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP7L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP7S 62:61 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP7S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP7A 60:59 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP7A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP7A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP7A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP7A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP7X 58:58 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP7X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP7X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP7W 57:57 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP7W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP7W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP7R 56:56 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP7R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP7R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP6L 55:55 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP6L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP6L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP6S 54:53 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP6S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP6A 52:51 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP6A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP6A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP6A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP6A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP6X 50:50 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP6X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP6X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP6W 49:49 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP6W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP6W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP6R 48:48 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP6R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP6R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP5L 47:47 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP5L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP5L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP5S 46:45 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP5S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP5A 44:43 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP5A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP5A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP5A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP5A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP5X 42:42 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP5X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP5X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP5W 41:41 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP5W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP5W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP5R 40:40 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP5R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP5R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP4L 39:39 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP4L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP4L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP4S 38:37 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP4S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP4A 36:35 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP4A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP4A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP4A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP4A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP4X 34:34 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP4X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP4X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP4W 33:33 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP4W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP4W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP4R 32:32 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP4R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP4R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP3L 31:31 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP3L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP3L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP3S 30:29 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP3S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP3A 28:27 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP3A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP3A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP3A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP3A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP3X 26:26 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP3X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP3X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP3W 25:25 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP3W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP3W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP3R 24:24 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP3R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP3R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP2L 23:23 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP2L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP2L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP2S 22:21 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP2S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP2A 20:19 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP2A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP2A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP2A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP2A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP2X 18:18 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP2X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP2X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP2W 17:17 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP2W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP2W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP2R 16:16 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP2R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP2R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP1L 15:15 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP1L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP1L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP1S 14:13 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP1S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP1A 12:11 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP1A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP1A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP1A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP1A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP1X 10:10 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP1X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP1X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP1W 9:9 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP1W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP1W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP1R 8:8 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP1R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP1R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP0L 7:7 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP0L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP0L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP0S 6:5 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP0S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP0A 4:3 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP0A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP0A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP0A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP0A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP0X 2:2 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP0X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP0X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP0W 1:1 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP0W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP0W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG0_PMP0R 0:0 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG0_PMP0R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG0_PMP0R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2 0x000003a2 /* RWI4R */
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#define NV_RISCV_CSR_PMPCFG2_PMP15L 63:63 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP15L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP15L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP15S 62:61 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP15S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP15A 60:59 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP15A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP15A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP15A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP15A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP15X 58:58 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP15X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP15X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP15W 57:57 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP15W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP15W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP15R 56:56 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP15R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP15R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP14L 55:55 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP14L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP14L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP14S 54:53 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP14S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP14A 52:51 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP14A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP14A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP14A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP14A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP14X 50:50 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP14X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP14X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP14W 49:49 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP14W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP14W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP14R 48:48 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP14R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP14R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP13L 47:47 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP13L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP13L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP13S 46:45 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP13S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP13A 44:43 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP13A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP13A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP13A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP13A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP13X 42:42 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP13X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP13X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP13W 41:41 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP13W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP13W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP13R 40:40 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP13R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP13R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP12L 39:39 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP12L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP12L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP12S 38:37 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP12S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP12A 36:35 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP12A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP12A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP12A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP12A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP12X 34:34 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP12X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP12X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP12W 33:33 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP12W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP12W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP12R 32:32 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP12R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP12R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP11L 31:31 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP11L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP11L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP11S 30:29 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP11S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP11A 28:27 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP11A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP11A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP11A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP11A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP11X 26:26 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP11X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP11X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP11W 25:25 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP11W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP11W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP11R 24:24 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP11R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP11R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP10L 23:23 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP10L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP10L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP10S 22:21 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP10S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP10A 20:19 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP10A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP10A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP10A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP10A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP10X 18:18 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP10X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP10X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP10W 17:17 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP10W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP10W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP10R 16:16 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP10R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP10R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP9L 15:15 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP9L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP9L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP9S 14:13 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP9S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP9A 12:11 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP9A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP9A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP9A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP9A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP9X 10:10 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP9X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP9X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP9W 9:9 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP9W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP9W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP9R 8:8 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP9R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP9R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP8L 7:7 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP8L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP8L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP8S 6:5 /* R-IVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP8S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP8A 4:3 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP8A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP8A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP8A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP8A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP8X 2:2 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP8X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP8X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP8W 1:1 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP8W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP8W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPCFG2_PMP8R 0:0 /* RWIVF */
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#define NV_RISCV_CSR_PMPCFG2_PMP8R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_PMPCFG2_PMP8R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_PMPADDR(i) (0x000003b0+(i)) /* RWI4A */
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#define NV_RISCV_CSR_PMPADDR__SIZE_1 16 /* */
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#define NV_RISCV_CSR_PMPADDR_WIRI 64-1:64-2 /* R-IVF */
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#define NV_RISCV_CSR_PMPADDR_WIRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_PMPADDR_ADDR 64-3:0 /* RWIVF */
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#define NV_RISCV_CSR_PMPADDR_ADDR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0 0x000007f0 /* RWI4R */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23L 63:63 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23S 62:61 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23A 60:59 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23X 58:58 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23W 57:57 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23R 56:56 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP23R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22L 55:55 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22S 54:53 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22A 52:51 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22X 50:50 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22W 49:49 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22R 48:48 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP22R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21L 47:47 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21S 46:45 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21A 44:43 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21X 42:42 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21W 41:41 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21R 40:40 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP21R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20L 39:39 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20S 38:37 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20A 36:35 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20X 34:34 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20W 33:33 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20R 32:32 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP20R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19L 31:31 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19S 30:29 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19A 28:27 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19X 26:26 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19W 25:25 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19R 24:24 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP19R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18L 23:23 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18S 22:21 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18A 20:19 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18X 18:18 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18W 17:17 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18R 16:16 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP18R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17L 15:15 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17S 14:13 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17A 12:11 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17X 10:10 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17W 9:9 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17R 8:8 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP17R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16L 7:7 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16S 6:5 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16A 4:3 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16X 2:2 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16W 1:1 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16R 0:0 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG0_PMP16R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2 0x000007f2 /* RWI4R */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31L 63:63 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31S 62:61 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31A 60:59 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31X 58:58 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31W 57:57 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31R 56:56 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP31R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30L 55:55 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30S 54:53 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30A 52:51 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30X 50:50 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30W 49:49 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30R 48:48 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP30R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29L 47:47 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29S 46:45 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29A 44:43 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29X 42:42 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29W 41:41 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29R 40:40 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP29R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28L 39:39 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28S 38:37 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28A 36:35 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28X 34:34 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28W 33:33 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28R 32:32 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP28R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27L 31:31 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27S 30:29 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27A 28:27 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27X 26:26 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27W 25:25 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27R 24:24 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP27R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26L 23:23 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26S 22:21 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26A 20:19 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26X 18:18 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26W 17:17 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26R 16:16 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP26R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25L 15:15 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25S 14:13 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25A 12:11 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25X 10:10 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25W 9:9 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25R 8:8 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP25R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24L 7:7 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24L_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24L_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24S 6:5 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24S_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24A 4:3 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24A_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24A_TOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24A_NA4 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24A_NAPOT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24X 2:2 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24X_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24X_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24W 1:1 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24W_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24W_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24R 0:0 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24R_DENIED 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MEXTPMPCFG2_PMP24R_PERMITTED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MEXTPMPADDR(i) (0x000007e0+(i)) /* RWI4A */
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#define NV_RISCV_CSR_MEXTPMPADDR__SIZE_1 16 /* */
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#define NV_RISCV_CSR_MEXTPMPADDR_WIRI 64-1:64-2 /* R-IVF */
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#define NV_RISCV_CSR_MEXTPMPADDR_WIRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MEXTPMPADDR_ADDR 64-3:0 /* RWIVF */
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#define NV_RISCV_CSR_MEXTPMPADDR_ADDR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSCRATCH2 0x000007c0 /* RWI4R */
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#define NV_RISCV_CSR_MSCRATCH2_VALUE 64-1:0 /* RWIVF */
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#define NV_RISCV_CSR_MSCRATCH2_VALUE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MTIMECMP 0x000007db /* RWI4R */
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#define NV_RISCV_CSR_MTIMECMP_TIME 63:0 /* RWIVF */
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#define NV_RISCV_CSR_MTIMECMP_TIME_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCFG 0x000007d5 /* RWI4R */
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#define NV_RISCV_CSR_MCFG_WPRI4 64-1:16 /* R-IVF */
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#define NV_RISCV_CSR_MCFG_WPRI4_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MCFG_MPOSTIO 15:15 /* RWIVF */
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#define NV_RISCV_CSR_MCFG_MPOSTIO_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCFG_MPOSTIO_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCFG_WPRI5 14:14 /* R-IVF */
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#define NV_RISCV_CSR_MCFG_WPRI5_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MCFG_SPOSTIO 13:13 /* RWIVF */
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#define NV_RISCV_CSR_MCFG_SPOSTIO_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCFG_SPOSTIO_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCFG_UPOSTIO 12:12 /* RWIVF */
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#define NV_RISCV_CSR_MCFG_UPOSTIO_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCFG_UPOSTIO_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCFG_MSBC 11:11 /* RWIVF */
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#define NV_RISCV_CSR_MCFG_MSBC_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCFG_MSBC_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCFG_WPRI3 10:10 /* R-IVF */
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#define NV_RISCV_CSR_MCFG_WPRI3_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MCFG_SSBC 9:9 /* RWIVF */
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#define NV_RISCV_CSR_MCFG_SSBC_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCFG_SSBC_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCFG_USBC 8:8 /* RWIVF */
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#define NV_RISCV_CSR_MCFG_USBC_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCFG_USBC_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCFG_WPRI2 7:6 /* R-IVF */
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#define NV_RISCV_CSR_MCFG_WPRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MCFG_SSSE 5:5 /* RWIVF */
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#define NV_RISCV_CSR_MCFG_SSSE_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCFG_SSSE_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCFG_USSE 4:4 /* RWIVF */
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#define NV_RISCV_CSR_MCFG_USSE_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCFG_USSE_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCFG_MWFP_DIS 3:3 /* RWIVF */
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#define NV_RISCV_CSR_MCFG_MWFP_DIS_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCFG_MWFP_DIS_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCFG_WPRI1 2:2 /* R-IVF */
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#define NV_RISCV_CSR_MCFG_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MCFG_SWFP_DIS 1:1 /* RWIVF */
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#define NV_RISCV_CSR_MCFG_SWFP_DIS_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCFG_SWFP_DIS_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MCFG_UWFP_DIS 0:0 /* R-IVF */
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#define NV_RISCV_CSR_MCFG_UWFP_DIS_FALSE 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MBPCFG 0x000007dd /* RWI4R */
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#define NV_RISCV_CSR_MBPCFG_WPRI2 64-1:22 /* R-IVF */
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#define NV_RISCV_CSR_MBPCFG_WPRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MBPCFG_RAS_FLUSH 21:21 /* -W-VF */
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#define NV_RISCV_CSR_MBPCFG_RAS_FLUSH_TRUE 0x00000001 /* -W--V */
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#define NV_RISCV_CSR_MBPCFG_BHT_FLUSH 20:20 /* -W-VF */
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#define NV_RISCV_CSR_MBPCFG_BHT_FLUSH_TRUE 0x00000001 /* -W--V */
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#define NV_RISCV_CSR_MBPCFG_BTB_FLUSHM 19:19 /* -W-VF */
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#define NV_RISCV_CSR_MBPCFG_BTB_FLUSHM_TRUE 0x00000001 /* -W--V */
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#define NV_RISCV_CSR_MBPCFG_WPRI1 18:18 /* R-IVF */
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#define NV_RISCV_CSR_MBPCFG_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MBPCFG_BTB_FLUSHS 17:17 /* -W-VF */
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#define NV_RISCV_CSR_MBPCFG_BTB_FLUSHS_TRUE 0x00000001 /* -W--V */
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#define NV_RISCV_CSR_MBPCFG_BTB_FLUSHU 16:16 /* -W-VF */
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#define NV_RISCV_CSR_MBPCFG_BTB_FLUSHU_TRUE 0x00000001 /* -W--V */
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#define NV_RISCV_CSR_MBPCFG_WPRI0 15:3 /* R-IVF */
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#define NV_RISCV_CSR_MBPCFG_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MBPCFG_RAS_EN 2:2 /* RWIVF */
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#define NV_RISCV_CSR_MBPCFG_RAS_EN_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MBPCFG_RAS_EN_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MBPCFG_BHT_EN 1:1 /* RWIVF */
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#define NV_RISCV_CSR_MBPCFG_BHT_EN_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MBPCFG_BHT_EN_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MBPCFG_BTB_EN 0:0 /* RWIVF */
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#define NV_RISCV_CSR_MBPCFG_BTB_EN_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MBPCFG_BTB_EN_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MDCACHEOP 0x00000bd0 /* RWI4R */
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#define NV_RISCV_CSR_MDCACHEOP_ADDR 64-1:6 /* -W-VF */
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#define NV_RISCV_CSR_MDCACHEOP_RS0 5:3 /* R--VF */
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#define NV_RISCV_CSR_MDCACHEOP_ADDR_MODE 2:2 /* -W-VF */
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#define NV_RISCV_CSR_MDCACHEOP_ADDR_MODE_VA 0x00000000 /* -W--V */
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#define NV_RISCV_CSR_MDCACHEOP_ADDR_MODE_PA 0x00000001 /* -W--V */
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#define NV_RISCV_CSR_MDCACHEOP_MODE 1:0 /* -W-VF */
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#define NV_RISCV_CSR_MDCACHEOP_MODE_INV_ALL 0x00000000 /* -W--V */
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#define NV_RISCV_CSR_MDCACHEOP_MODE_INV_LINE 0x00000001 /* -W--V */
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#define NV_RISCV_CSR_MDCACHEOP_MODE_CLR_ALL 0x00000002 /* -W--V */
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#define NV_RISCV_CSR_MDCACHEOP_MODE_CLR_LINE 0x00000003 /* -W--V */
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#define NV_RISCV_CSR_MMPUCTL 0x000007c9 /* RWI4R */
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#define NV_RISCV_CSR_MMPUCTL_WPRI1 64-1:24 /* R-IVF */
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#define NV_RISCV_CSR_MMPUCTL_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MMPUCTL_ENTRY_COUNT 23:16 /* RWIVF */
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#define NV_RISCV_CSR_MMPUCTL_ENTRY_COUNT_RST 0x00000080 /* RWI-V */
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#define NV_RISCV_CSR_MMPUCTL_WPRI0 15:7 /* R-IVF */
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#define NV_RISCV_CSR_MMPUCTL_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MMPUCTL_START_INDEX 6:0 /* RWIVF */
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#define NV_RISCV_CSR_MMPUCTL_START_INDEX_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCURRUID 0x000007d7 /* RWI4R */
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#define NV_RISCV_CSR_MCURRUID_RS0 63:32 /* R-IVF */
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#define NV_RISCV_CSR_MCURRUID_RS0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MCURRUID_MCURRUID 31:24 /* RWIVF */
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#define NV_RISCV_CSR_MCURRUID_MCURRUID_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCURRUID_WPRI0 23:16 /* R-IVF */
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#define NV_RISCV_CSR_MCURRUID_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MCURRUID_SCURRUID 15:8 /* RWIVF */
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#define NV_RISCV_CSR_MCURRUID_SCURRUID_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MCURRUID_UCURRUID 7:0 /* R-IVF */
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#define NV_RISCV_CSR_MCURRUID_UCURRUID_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MOPT 0x000007d8 /* -W-4R */
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#define NV_RISCV_CSR_MOPT_WPRI 64-1:5 /* -W-VF */
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#define NV_RISCV_CSR_MOPT_CMD 4:0 /* -W-VF */
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#define NV_RISCV_CSR_MOPT_CMD_HALT 0x00000000 /* -W--V */
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#define NV_RISCV_CSR_MMISCOPEN 0x000007f9 /* RWI4R */
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#define NV_RISCV_CSR_MMISCOPEN_WPRI 64-1:1 /* R-IVF */
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#define NV_RISCV_CSR_MMISCOPEN_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MMISCOPEN_DCACHEOP 0:0 /* RWIVF */
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#define NV_RISCV_CSR_MMISCOPEN_DCACHEOP_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MMISCOPEN_DCACHEOP_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MLDSTATTR 0x000007c8 /* RWI4R */
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#define NV_RISCV_CSR_MLDSTATTR_RS0 64-1:30 /* R-IVF */
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#define NV_RISCV_CSR_MLDSTATTR_RS0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MLDSTATTR_VPR 29:29 /* RWIVF */
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#define NV_RISCV_CSR_MLDSTATTR_VPR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MLDSTATTR_WPR 28:24 /* RWIVF */
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#define NV_RISCV_CSR_MLDSTATTR_WPR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MLDSTATTR_L2C_RD 23:22 /* RWIVF */
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#define NV_RISCV_CSR_MLDSTATTR_L2C_RD_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MLDSTATTR_L2C_WR 21:20 /* RWIVF */
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#define NV_RISCV_CSR_MLDSTATTR_L2C_WR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MLDSTATTR_COHERENT 19:19 /* RWIVF */
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#define NV_RISCV_CSR_MLDSTATTR_COHERENT_RST 0x00000001 /* RWI-V */
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#define NV_RISCV_CSR_MLDSTATTR_CACHEABLE 18:18 /* RWIVF */
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#define NV_RISCV_CSR_MLDSTATTR_CACHEABLE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MLDSTATTR_RS1 17:0 /* R-IVF */
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#define NV_RISCV_CSR_MLDSTATTR_RS1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MFETCHATTR 0x000007df /* RWI4R */
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#define NV_RISCV_CSR_MFETCHATTR_RS0 64-1:30 /* R-IVF */
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#define NV_RISCV_CSR_MFETCHATTR_RS0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MFETCHATTR_VPR 29:29 /* RWIVF */
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#define NV_RISCV_CSR_MFETCHATTR_VPR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MFETCHATTR_WPR 28:24 /* RWIVF */
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#define NV_RISCV_CSR_MFETCHATTR_WPR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MFETCHATTR_L2C_RD 23:22 /* RWIVF */
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#define NV_RISCV_CSR_MFETCHATTR_L2C_RD_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MFETCHATTR_L2C_WR 21:20 /* RWIVF */
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#define NV_RISCV_CSR_MFETCHATTR_L2C_WR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MFETCHATTR_COHERENT 19:19 /* RWIVF */
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#define NV_RISCV_CSR_MFETCHATTR_COHERENT_RST 0x00000001 /* RWI-V */
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#define NV_RISCV_CSR_MFETCHATTR_CACHEABLE 18:18 /* RWIVF */
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#define NV_RISCV_CSR_MFETCHATTR_CACHEABLE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MFETCHATTR_RS1 17:0 /* R-IVF */
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#define NV_RISCV_CSR_MFETCHATTR_RS1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_FFLAGS 0x00000001 /* RWI4R */
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#define NV_RISCV_CSR_FFLAGS_RS0 63:5 /* R-IVF */
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#define NV_RISCV_CSR_FFLAGS_RS0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_FFLAGS_FFLAGS 4:0 /* RWIVF */
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#define NV_RISCV_CSR_FFLAGS_FFLAGS_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_FRM 0x00000002 /* RWI4R */
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#define NV_RISCV_CSR_FRM_RS0 63:3 /* R-IVF */
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#define NV_RISCV_CSR_FRM_RS0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_FRM_FRM 2:0 /* RWIVF */
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#define NV_RISCV_CSR_FRM_FRM_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_FCSR 0x00000003 /* RWI4R */
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#define NV_RISCV_CSR_FCSR_RS0 63:8 /* R-IVF */
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#define NV_RISCV_CSR_FCSR_RS0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_FCSR_FRM 7:5 /* RWIVF */
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#define NV_RISCV_CSR_FCSR_FRM_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_FCSR_FFLAGS 4:0 /* RWIVF */
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#define NV_RISCV_CSR_FCSR_FFLAGS_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_HPMCOUNTER(i) (0x00000c00+(i)) /* R-I4A */
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#define NV_RISCV_CSR_HPMCOUNTER__SIZE_1 32 /* */
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#define NV_RISCV_CSR_HPMCOUNTER_VALUE 64-1:0 /* R-IVF */
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#define NV_RISCV_CSR_HPMCOUNTER_VALUE_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_HPMCOUNTER_CYCLE 0x00000c00 /* */
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#define NV_RISCV_CSR_HPMCOUNTER_TIME 0x00000c01 /* */
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#define NV_RISCV_CSR_HPMCOUNTER_INSTRET 0x00000c02 /* */
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#define NV_RISCV_CSR_MSPM 0x000007d9 /* RWI4R */
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#define NV_RISCV_CSR_MSPM_WPRI3 64-1:32 /* R-IVF */
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#define NV_RISCV_CSR_MSPM_WPRI3_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSPM_MMLOCK 31:31 /* RWIVF */
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#define NV_RISCV_CSR_MSPM_MMLOCK_UNLOCK 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSPM_MMLOCK_LOCK 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSPM_WPRI2 30:20 /* R-IVF */
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#define NV_RISCV_CSR_MSPM_WPRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSPM_MSECM 19:19 /* RWIVF */
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#define NV_RISCV_CSR_MSPM_MSECM_INSEC 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSPM_MSECM_SEC 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSPM_WPRI1 18:18 /* R-IVF */
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#define NV_RISCV_CSR_MSPM_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSPM_SSECM 17:17 /* RWIVF */
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#define NV_RISCV_CSR_MSPM_SSECM_INSEC 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSPM_SSECM_SEC 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSPM_USECM 16:16 /* RWIVF */
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#define NV_RISCV_CSR_MSPM_USECM_INSEC 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSPM_USECM_SEC 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSPM_MPLM 15:12 /* R-IVF */
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#define NV_RISCV_CSR_MSPM_MPLM_LEVEL0 0x00000001 /* R-I-V */
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#define NV_RISCV_CSR_MSPM_MPLM_LEVEL1 0x00000003 /* R---V */
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#define NV_RISCV_CSR_MSPM_MPLM_LEVEL2 0x00000005 /* R---V */
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#define NV_RISCV_CSR_MSPM_MPLM_LEVEL3 0x0000000f /* R---V */
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#define NV_RISCV_CSR_MSPM_WPRI0 11:8 /* R-IVF */
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#define NV_RISCV_CSR_MSPM_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSPM_SPLM 7:4 /* RWIVF */
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#define NV_RISCV_CSR_MSPM_SPLM_LEVEL0 0x00000001 /* RWI-V */
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#define NV_RISCV_CSR_MSPM_SPLM_LEVEL1 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MSPM_SPLM_LEVEL2 0x00000005 /* RW--V */
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#define NV_RISCV_CSR_MSPM_SPLM_LEVEL3 0x0000000f /* RW--V */
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#define NV_RISCV_CSR_MSPM_UPLM 3:0 /* RWIVF */
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#define NV_RISCV_CSR_MSPM_UPLM_LEVEL0 0x00000001 /* RWI-V */
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#define NV_RISCV_CSR_MSPM_UPLM_LEVEL1 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MSPM_UPLM_LEVEL2 0x00000005 /* RW--V */
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#define NV_RISCV_CSR_MSPM_UPLM_LEVEL3 0x0000000f /* RW--V */
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#define NV_RISCV_CSR_MDBGCTL 0x000007de /* RWI4R */
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#define NV_RISCV_CSR_MDBGCTL_WIRI 64-1:6 /* R-IVF */
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#define NV_RISCV_CSR_MDBGCTL_WIRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MDBGCTL_MICD_DIS 5:5 /* RWIVF */
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#define NV_RISCV_CSR_MDBGCTL_MICD_DIS_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MDBGCTL_MICD_DIS_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MDBGCTL_ICDCSRPRV_S_OVERRIDE 4:4 /* RWIVF */
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#define NV_RISCV_CSR_MDBGCTL_ICDCSRPRV_S_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MDBGCTL_ICDCSRPRV_S_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MDBGCTL_ICDMEMPRV 3:2 /* RWIVF */
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#define NV_RISCV_CSR_MDBGCTL_ICDMEMPRV_U 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MDBGCTL_ICDMEMPRV_S 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MDBGCTL_ICDMEMPRV_M 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MDBGCTL_ICDMEMPRV_OVERRIDE 1:1 /* RWIVF */
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#define NV_RISCV_CSR_MDBGCTL_ICDMEMPRV_OVERRIDE_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MDBGCTL_ICDMEMPRV_OVERRIDE_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MDBGCTL_ICDPL 0:0 /* RWIVF */
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#define NV_RISCV_CSR_MDBGCTL_ICDPL_USE_PL0 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MDBGCTL_ICDPL_USE_CUR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MRSP 0x000007da /* RWI4R */
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#define NV_RISCV_CSR_MRSP_WPRI2 64-1:12 /* R-IVF */
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#define NV_RISCV_CSR_MRSP_WPRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MRSP_MRSEC 11:11 /* RWIVF */
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#define NV_RISCV_CSR_MRSP_MRSEC_INSEC 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MRSP_MRSEC_SEC 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MRSP_WPRI1 10:10 /* R-IVF */
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#define NV_RISCV_CSR_MRSP_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MRSP_SRSEC 9:9 /* RWIVF */
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#define NV_RISCV_CSR_MRSP_SRSEC_INSEC 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MRSP_SRSEC_SEC 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MRSP_URSEC 8:8 /* RWIVF */
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#define NV_RISCV_CSR_MRSP_URSEC_INSEC 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MRSP_URSEC_SEC 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MRSP_MRPL 7:6 /* RWIVF */
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#define NV_RISCV_CSR_MRSP_MRPL_LEVEL0 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MRSP_MRPL_LEVEL1 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MRSP_MRPL_LEVEL2 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MRSP_MRPL_LEVEL3 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MRSP_WPRI0 5:4 /* R-IVF */
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#define NV_RISCV_CSR_MRSP_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MRSP_SRPL 3:2 /* RWIVF */
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#define NV_RISCV_CSR_MRSP_SRPL_LEVEL0 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MRSP_SRPL_LEVEL1 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MRSP_SRPL_LEVEL2 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MRSP_SRPL_LEVEL3 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_MRSP_URPL 1:0 /* RWIVF */
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#define NV_RISCV_CSR_MRSP_URPL_LEVEL0 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MRSP_URPL_LEVEL1 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MRSP_URPL_LEVEL2 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_MRSP_URPL_LEVEL3 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_SPM 0x00000899 /* R-I4R */
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#define NV_RISCV_CSR_SPM_WIRI1 64-1:17 /* R-IVF */
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#define NV_RISCV_CSR_SPM_WIRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SPM_USECM 16:16 /* R-IVF */
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#define NV_RISCV_CSR_SPM_USECM_INSEC 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SPM_USECM_SEC 0x00000001 /* R---V */
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#define NV_RISCV_CSR_SPM_WIRI0 15:4 /* R-IVF */
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#define NV_RISCV_CSR_SPM_WIRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SPM_UPLM 3:0 /* R-IVF */
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#define NV_RISCV_CSR_SPM_UPLM_LEVEL0 0x00000001 /* R-I-V */
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#define NV_RISCV_CSR_SPM_UPLM_LEVEL1 0x00000003 /* R---V */
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#define NV_RISCV_CSR_SPM_UPLM_LEVEL2 0x00000005 /* R---V */
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#define NV_RISCV_CSR_SPM_UPLM_LEVEL3 0x0000000f /* R---V */
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#define NV_RISCV_CSR_RSP 0x0000089a /* RWI4R */
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#define NV_RISCV_CSR_RSP_WPRI1 64-1:9 /* R-IVF */
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#define NV_RISCV_CSR_RSP_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_RSP_URSEC 8:8 /* RWIVF */
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#define NV_RISCV_CSR_RSP_URSEC_INSEC 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_RSP_URSEC_SEC 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_RSP_WPRI0 7:2 /* R-IVF */
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#define NV_RISCV_CSR_RSP_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_RSP_URPL 1:0 /* RWIVF */
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#define NV_RISCV_CSR_RSP_URPL_LEVEL0 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_RSP_URPL_LEVEL1 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_RSP_URPL_LEVEL2 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_RSP_URPL_LEVEL3 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_TSELECT 0x000007a0 /* RWI4R */
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#define NV_RISCV_CSR_TSELECT_RS0 64-1:6 /* R-IVF */
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#define NV_RISCV_CSR_TSELECT_RS0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_TSELECT_INDEX 5:0 /* RWIVF */
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#define NV_RISCV_CSR_TSELECT_INDEX_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_TDATA1 0x000007a1 /* RWI4R */
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#define NV_RISCV_CSR_TDATA1_TYPE 63:60 /* R-IVF */
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#define NV_RISCV_CSR_TDATA1_TYPE_ADDR_DATA 0x00000002 /* R-I-V */
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#define NV_RISCV_CSR_TDATA1_DMODE 59:59 /* R-IVF */
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#define NV_RISCV_CSR_TDATA1_DMODE_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_TDATA1_MASKMAX 58:53 /* R-IVF */
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#define NV_RISCV_CSR_TDATA1_MASKMAX_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_TDATA1_RS0 52:20 /* R-IVF */
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#define NV_RISCV_CSR_TDATA1_RS0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_TDATA1_SELECT 19:19 /* R-IVF */
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#define NV_RISCV_CSR_TDATA1_SELECT_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_TDATA1_TIMING 18:18 /* R-IVF */
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#define NV_RISCV_CSR_TDATA1_TIMING_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_TDATA1_ACTION 17:12 /* RWIVF */
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#define NV_RISCV_CSR_TDATA1_ACTION_DBG 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_TDATA1_ACTION_ICD 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_TDATA1_CHAIN 11:11 /* R-IVF */
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#define NV_RISCV_CSR_TDATA1_CHAIN_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_TDATA1_MATCH 10:7 /* R-IVF */
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#define NV_RISCV_CSR_TDATA1_MATCH_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_TDATA1_M 6:6 /* RWIVF */
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#define NV_RISCV_CSR_TDATA1_M_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_TDATA1_M_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_TDATA1_RS1 5:5 /* R-IVF */
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#define NV_RISCV_CSR_TDATA1_RS1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_TDATA1_S 4:4 /* RWIVF */
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#define NV_RISCV_CSR_TDATA1_S_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_TDATA1_S_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_TDATA1_U 3:3 /* RWIVF */
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#define NV_RISCV_CSR_TDATA1_U_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_TDATA1_U_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_TDATA1_EXECUTE 2:2 /* RWIVF */
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#define NV_RISCV_CSR_TDATA1_EXECUTE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_TDATA1_STORE 1:1 /* RWIVF */
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#define NV_RISCV_CSR_TDATA1_STORE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_TDATA1_LOAD 0:0 /* RWIVF */
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#define NV_RISCV_CSR_TDATA1_LOAD_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_TDATA2 0x000007a2 /* RWI4R */
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#define NV_RISCV_CSR_TDATA2_VALUE 64-1:0 /* RWIVF */
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#define NV_RISCV_CSR_TDATA2_VALUE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_DCSR 0x000007b0 /* R-I4R */
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#define NV_RISCV_CSR_DCSR_RS0 64-1:2 /* R--VF */
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#define NV_RISCV_CSR_DCSR_PRV 1:0 /* R--VF */
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#define NV_RISCV_CSR_MBIND 0x00000bc0 /* -W-4R */
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#define NV_RISCV_CSR_MBIND_GFID 59:54 /* -W-VF */
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#define NV_RISCV_CSR_MBIND_INST_BLK_PTR_APERTURE 53:52 /* -W-VF */
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#define NV_RISCV_CSR_MBIND_INST_BLK_PTR_ADR 27:0 /* -W-VF */
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#define NV_RISCV_CSR_MTLBINVDATA1 0x00000bc1 /* -W-4R */
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#define NV_RISCV_CSR_MTLBINVDATA1_ACK_TYPE 58:57 /* -W-VF */
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#define NV_RISCV_CSR_MTLBINVDATA1_SYS_MEMBAR 56:56 /* -W-VF */
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#define NV_RISCV_CSR_MTLBINVDATA1_CANCEL_TARGET_GPC_ID 55:53 /* -W-VF */
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#define NV_RISCV_CSR_MTLBINVDATA1_CANCEL_TARGET_CLIENT_UNIT_ID 52:46 /* -W-VF */
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#define NV_RISCV_CSR_MTLBINVDATA1_MMU_REPLAY 45:43 /* -W-VF */
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#define NV_RISCV_CSR_MTLBINVDATA1_TARGET_AVA 42:42 /* -W-VF */
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#define NV_RISCV_CSR_MTLBINVDATA1_PAGE_TABLE_LEVEL 41:39 /* -W-VF */
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#define NV_RISCV_CSR_MTLBINVDATA1_PDB_ADR 38:4 /* -W-VF */
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#define NV_RISCV_CSR_MTLBINVDATA1_TARGET 3:2 /* -W-VF */
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#define NV_RISCV_CSR_MTLBINVDATA1_PDB 1:1 /* -W-VF */
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#define NV_RISCV_CSR_MTLBINVDATA1_GPC 0:0 /* -W-VF */
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#define NV_RISCV_CSR_MTLBINVOP 0x00000bc2 /* -W-4R */
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#define NV_RISCV_CSR_MTLBINVOP_TARGET_ADR 36:0 /* -W-VF */
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#define NV_RISCV_CSR_MFLUSH 0x00000bc3 /* -W-4R */
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#define NV_RISCV_CSR_MFLUSH_RS0 64-1:1 /* -W-VF */
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#define NV_RISCV_CSR_MFLUSH_HOST2FB_MEMBAR_TYPE_T 0:0 /* -W-VF */
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#define NV_RISCV_CSR_ML2SYSINV 0x00000bc4 /* -W-4R */
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#define NV_RISCV_CSR_ML2SYSINV_VALUE 64-1:0 /* -W-VF */
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#define NV_RISCV_CSR_ML2PEERINV 0x00000bc5 /* -W-4R */
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#define NV_RISCV_CSR_ML2PEERINV_VALUE 64-1:0 /* -W-VF */
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#define NV_RISCV_CSR_ML2CLNCOMP 0x00000bc6 /* -W-4R */
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#define NV_RISCV_CSR_ML2CLNCOMP_VALUE 64-1:0 /* -W-VF */
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#define NV_RISCV_CSR_ML2FLHDTY 0x00000bc7 /* -W-4R */
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#define NV_RISCV_CSR_ML2FLHDTY_VALUE 64-1:0 /* -W-VF */
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#define NV_RISCV_CSR_MSYSOPEN 0x000007f8 /* RWI4R */
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#define NV_RISCV_CSR_MSYSOPEN_WPRI 64-1:8 /* R-IVF */
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#define NV_RISCV_CSR_MSYSOPEN_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_MSYSOPEN_L2FLHDTY 7:7 /* RWIVF */
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#define NV_RISCV_CSR_MSYSOPEN_L2FLHDTY_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSYSOPEN_L2FLHDTY_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSYSOPEN_L2CLNCOMP 6:6 /* RWIVF */
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#define NV_RISCV_CSR_MSYSOPEN_L2CLNCOMP_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSYSOPEN_L2CLNCOMP_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSYSOPEN_L2PEERINV 5:5 /* RWIVF */
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#define NV_RISCV_CSR_MSYSOPEN_L2PEERINV_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSYSOPEN_L2PEERINV_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSYSOPEN_L2SYSINV 4:4 /* RWIVF */
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#define NV_RISCV_CSR_MSYSOPEN_L2SYSINV_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSYSOPEN_L2SYSINV_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSYSOPEN_FLUSH 3:3 /* RWIVF */
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#define NV_RISCV_CSR_MSYSOPEN_FLUSH_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSYSOPEN_FLUSH_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSYSOPEN_TLBINVOP 2:2 /* RWIVF */
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#define NV_RISCV_CSR_MSYSOPEN_TLBINVOP_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSYSOPEN_TLBINVOP_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSYSOPEN_TLBINVDATA1 1:1 /* RWIVF */
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#define NV_RISCV_CSR_MSYSOPEN_TLBINVDATA1_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSYSOPEN_TLBINVDATA1_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MSYSOPEN_BIND 0:0 /* RWIVF */
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#define NV_RISCV_CSR_MSYSOPEN_BIND_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_MSYSOPEN_BIND_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_MROMPROT 0x000007c4 /* RW-4R */
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#define NV_RISCV_CSR_MROMPROT_ROM_PROT 64-1:0 /* RW-VF */
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#define NV_RISCV_CSR_BIND 0x000008c0 /* -W-4R */
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#define NV_RISCV_CSR_BIND_GFID 59:54 /* -W-VF */
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#define NV_RISCV_CSR_BIND_INST_BLK_PTR_APERTURE 53:52 /* -W-VF */
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#define NV_RISCV_CSR_BIND_INST_BLK_PTR_ADR 27:0 /* -W-VF */
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#define NV_RISCV_CSR_TLBINVDATA1 0x000008c1 /* -W-4R */
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#define NV_RISCV_CSR_TLBINVDATA1_ACK_TYPE 58:57 /* -W-VF */
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#define NV_RISCV_CSR_TLBINVDATA1_SYS_MEMBAR 56:56 /* -W-VF */
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#define NV_RISCV_CSR_TLBINVDATA1_CANCEL_TARGET_GPC_ID 55:53 /* -W-VF */
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#define NV_RISCV_CSR_TLBINVDATA1_CANCEL_TARGET_CLIENT_UNIT_ID 52:46 /* -W-VF */
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#define NV_RISCV_CSR_TLBINVDATA1_MMU_REPLAY 45:43 /* -W-VF */
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#define NV_RISCV_CSR_TLBINVDATA1_TARGET_AVA 42:42 /* -W-VF */
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#define NV_RISCV_CSR_TLBINVDATA1_PAGE_TABLE_LEVEL 41:39 /* -W-VF */
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#define NV_RISCV_CSR_TLBINVDATA1_PDB_ADR 38:4 /* -W-VF */
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#define NV_RISCV_CSR_TLBINVDATA1_TARGET 3:2 /* -W-VF */
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#define NV_RISCV_CSR_TLBINVDATA1_PDB 1:1 /* -W-VF */
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#define NV_RISCV_CSR_TLBINVDATA1_GPC 0:0 /* -W-VF */
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#define NV_RISCV_CSR_TLBINVOP 0x000008c2 /* -W-4R */
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#define NV_RISCV_CSR_TLBINVOP_TARGET_ADR 36:0 /* -W-VF */
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#define NV_RISCV_CSR_FLUSH 0x000008c3 /* -W-4R */
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#define NV_RISCV_CSR_FLUSH_RS0 64-1:1 /* -W-VF */
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#define NV_RISCV_CSR_FLUSH_HOST2FB_MEMBAR_TYPE_T 0:0 /* -W-VF */
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#define NV_RISCV_CSR_L2SYSINV 0x000008c4 /* -W-4R */
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#define NV_RISCV_CSR_L2SYSINV_VALUE 64-1:0 /* -W-VF */
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#define NV_RISCV_CSR_L2PEERINV 0x000008c5 /* -W-4R */
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#define NV_RISCV_CSR_L2PEERINV_VALUE 64-1:0 /* -W-VF */
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#define NV_RISCV_CSR_L2CLNCOMP 0x000008c6 /* -W-4R */
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#define NV_RISCV_CSR_L2CLNCOMP_VALUE 64-1:0 /* -W-VF */
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#define NV_RISCV_CSR_L2FLHDTY 0x000008c7 /* -W-4R */
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#define NV_RISCV_CSR_L2FLHDTY_VALUE 64-1:0 /* -W-VF */
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#define NV_RISCV_CSR_LWFENCEIO 0x00000800 /* -W-4R */
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#define NV_RISCV_CSR_LWFENCEIO_VALUE 64-1:0 /* -W-VF */
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#define NV_RISCV_CSR_LWFENCEMEM 0x00000801 /* -W-4R */
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#define NV_RISCV_CSR_LWFENCEMEM_VALUE 64-1:0 /* -W-VF */
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#define NV_RISCV_CSR_LWFENCEALL 0x00000802 /* -W-4R */
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#define NV_RISCV_CSR_LWFENCEALL_VALUE 64-1:0 /* -W-VF */
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#define NV_RISCV_CSR_SSTATUS 0x00000100 /* RWI4R */
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#define NV_RISCV_CSR_SSTATUS_SD 63:63 /* R--VF */
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#define NV_RISCV_CSR_SSTATUS_WPRI5 62:34 /* R-IVF */
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#define NV_RISCV_CSR_SSTATUS_WPRI5_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SSTATUS_UXL 33:32 /* R-IVF */
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#define NV_RISCV_CSR_SSTATUS_UXL_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SSTATUS_WPRI4 31:20 /* R-IVF */
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#define NV_RISCV_CSR_SSTATUS_WPRI4_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SSTATUS_MXR 19:19 /* RWIVF */
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#define NV_RISCV_CSR_SSTATUS_MXR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSTATUS_SUM 18:18 /* RWIVF */
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#define NV_RISCV_CSR_SSTATUS_SUM_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSTATUS_SUM_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SSTATUS_WPRI3 17:17 /* R-IVF */
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#define NV_RISCV_CSR_SSTATUS_WPRI3_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SSTATUS_XS 16:15 /* R-IVF */
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#define NV_RISCV_CSR_SSTATUS_XS_OFF 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SSTATUS_FS 14:13 /* RWIVF */
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#define NV_RISCV_CSR_SSTATUS_FS_OFF 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSTATUS_FS_INITIAL 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SSTATUS_FS_CLEAN 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_SSTATUS_FS_DIRTY 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_SSTATUS_WPRI2 12:9 /* R-IVF */
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#define NV_RISCV_CSR_SSTATUS_WPRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SSTATUS_SPP 8:8 /* RWIVF */
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#define NV_RISCV_CSR_SSTATUS_SPP_USER 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSTATUS_SPP_SUPERVISOR 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SSTATUS_WPRI1 7:6 /* R-IVF */
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#define NV_RISCV_CSR_SSTATUS_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SSTATUS_SPIE 5:5 /* RWIVF */
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#define NV_RISCV_CSR_SSTATUS_SPIE_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSTATUS_SPIE_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SSTATUS_UPIE 4:4 /* R-IVF */
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#define NV_RISCV_CSR_SSTATUS_UPIE_DISABLE 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SSTATUS_WPRI0 3:2 /* R-IVF */
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#define NV_RISCV_CSR_SSTATUS_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SSTATUS_SIE 1:1 /* RWIVF */
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#define NV_RISCV_CSR_SSTATUS_SIE_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSTATUS_SIE_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SSTATUS_UIE 0:0 /* R-IVF */
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#define NV_RISCV_CSR_SSTATUS_UIE_DISABLE 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_STVEC 0x00000105 /* RWI4R */
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#define NV_RISCV_CSR_STVEC_BASE 64-1:2 /* RWIVF */
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#define NV_RISCV_CSR_STVEC_BASE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_STVEC_MODE 1:0 /* RWIVF */
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#define NV_RISCV_CSR_STVEC_MODE_DIRECT 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_STVEC_MODE_VECTORED 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SSCRATCH 0x00000140 /* RWI4R */
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#define NV_RISCV_CSR_SSCRATCH_SCRATCH 64-1:0 /* RWIVF */
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#define NV_RISCV_CSR_SSCRATCH_SCRATCH_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SIP 0x00000144 /* RWI4R */
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#define NV_RISCV_CSR_SIP_WIRI2 64-1:10 /* R-IVF */
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#define NV_RISCV_CSR_SIP_WIRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SIP_SEIP 9:9 /* R-IVF */
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#define NV_RISCV_CSR_SIP_SEIP_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SIP_UEIP 8:8 /* R-IVF */
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#define NV_RISCV_CSR_SIP_UEIP_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SIP_WIRI1 7:6 /* R-IVF */
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#define NV_RISCV_CSR_SIP_WIRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SIP_STIP 5:5 /* R-IVF */
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#define NV_RISCV_CSR_SIP_STIP_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SIP_UTIP 4:4 /* R-IVF */
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#define NV_RISCV_CSR_SIP_UTIP_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SIP_WIRI0 3:2 /* R-IVF */
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#define NV_RISCV_CSR_SIP_WIRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SIP_SSIP 1:1 /* RWIVF */
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#define NV_RISCV_CSR_SIP_SSIP_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SIP_USIP 0:0 /* R-IVF */
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#define NV_RISCV_CSR_SIP_USIP_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SIE 0x00000104 /* RWI4R */
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#define NV_RISCV_CSR_SIE_WPRI2 64-1:10 /* R-IVF */
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#define NV_RISCV_CSR_SIE_WPRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SIE_SEIE 9:9 /* RWIVF */
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#define NV_RISCV_CSR_SIE_SEIE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SIE_UEIE 8:8 /* R-IVF */
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#define NV_RISCV_CSR_SIE_UEIE_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SIE_WPRI1 7:6 /* R-IVF */
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#define NV_RISCV_CSR_SIE_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SIE_STIE 5:5 /* RWIVF */
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#define NV_RISCV_CSR_SIE_STIE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SIE_UTIE 4:4 /* R-IVF */
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#define NV_RISCV_CSR_SIE_UTIE_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SIE_WPRI0 3:2 /* R-IVF */
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#define NV_RISCV_CSR_SIE_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SIE_SSIE 1:1 /* RWIVF */
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#define NV_RISCV_CSR_SIE_SSIE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SIE_USIE 0:0 /* R-IVF */
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#define NV_RISCV_CSR_SIE_USIE_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_STVAL 0x00000143 /* RWI4R */
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#define NV_RISCV_CSR_STVAL_VALUE 64-1:0 /* RWIVF */
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#define NV_RISCV_CSR_STVAL_VALUE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SEPC 0x00000141 /* RWI4R */
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#define NV_RISCV_CSR_SEPC_EPC 64-1:0 /* RWIVF */
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#define NV_RISCV_CSR_SEPC_EPC_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCAUSE 0x00000142 /* RWI4R */
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#define NV_RISCV_CSR_SCAUSE_INT 64-1:64-1 /* RWIVF */
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#define NV_RISCV_CSR_SCAUSE_INT_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCAUSE_WLRL 64-2:5 /* R-IVF */
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#define NV_RISCV_CSR_SCAUSE_WLRL_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE 4:0 /* RWIVF */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_IAMA 0x00000000 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_IACC_FAULT 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_ILL 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_BKPT 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_LAMA 0x00000004 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_LACC_FAULT 0x00000005 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_SAMA 0x00000006 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_SACC_FAULT 0x00000007 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_UCALL 0x00000008 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_SCALL 0x00000009 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_IPAGE_FAULT 0x0000000c /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_LPAGE_FAULT 0x0000000d /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_SPAGE_FAULT 0x0000000f /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_USS 0x0000001c /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_U_SWINT 0x00000000 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_S_SWINT 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_U_TINT 0x00000004 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_S_TINT 0x00000005 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_U_EINT 0x00000008 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE_EXCODE_S_EINT 0x00000009 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE2 0x000005d4 /* RWI4R */
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#define NV_RISCV_CSR_SCAUSE2_WPRI 64-1:24 /* R-IVF */
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#define NV_RISCV_CSR_SCAUSE2_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SCAUSE2_CAUSE 23:16 /* RWIVF */
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#define NV_RISCV_CSR_SCAUSE2_CAUSE_NO 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCAUSE2_CAUSE_EBREAK 0x00000017 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE2_CAUSE_HW_TRIGGER 0x00000018 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE2_CAUSE_U_SINGLE_STEP 0x00000019 /* RW--V */
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#define NV_RISCV_CSR_SCAUSE2_ERROR 15:0 /* RWIVF */
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#define NV_RISCV_CSR_SCAUSE2_ERROR_NO 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCAUSE2_TRIGGER_INDEX 5:0 /* */
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#define NV_RISCV_CSR_SATP 0x00000180 /* RWI4R */
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#define NV_RISCV_CSR_SATP_MODE 63:60 /* RWIVF */
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#define NV_RISCV_CSR_SATP_MODE_BARE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SATP_MODE_NVMPU 0x0000000f /* RW--V */
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#define NV_RISCV_CSR_SATP_ASID 59:44 /* R-IVF */
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#define NV_RISCV_CSR_SATP_ASID_BARE 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SATP_PPN 43:0 /* R-IVF */
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#define NV_RISCV_CSR_SATP_PPN_BARE 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SCOUNTEREN 0x00000106 /* RWI4R */
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#define NV_RISCV_CSR_SCOUNTEREN_RS0 63:32 /* R-IVF */
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#define NV_RISCV_CSR_SCOUNTEREN_RS0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SCOUNTEREN_HPM 31:3 /* RWIVF */
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#define NV_RISCV_CSR_SCOUNTEREN_HPM_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCOUNTEREN_IR 2:2 /* RWIVF */
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#define NV_RISCV_CSR_SCOUNTEREN_IR_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCOUNTEREN_IR_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SCOUNTEREN_TM 1:1 /* RWIVF */
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#define NV_RISCV_CSR_SCOUNTEREN_TM_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCOUNTEREN_TM_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SCOUNTEREN_CY 0:0 /* RWIVF */
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#define NV_RISCV_CSR_SCOUNTEREN_CY_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCOUNTEREN_CY_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SSPM 0x000005d9 /* RWI4R */
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#define NV_RISCV_CSR_SSPM_WPRI1 64-1:18 /* R-IVF */
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#define NV_RISCV_CSR_SSPM_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SSPM_SSECM 17:17 /* R-IVF */
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#define NV_RISCV_CSR_SSPM_SSECM_INSEC 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SSPM_SSECM_SEC 0x00000001 /* R---V */
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#define NV_RISCV_CSR_SSPM_USECM 16:16 /* RWIVF */
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#define NV_RISCV_CSR_SSPM_USECM_INSEC 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSPM_USECM_SEC 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SSPM_WPRI0 15:8 /* R-IVF */
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#define NV_RISCV_CSR_SSPM_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SSPM_SPLM 7:4 /* R-IVF */
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#define NV_RISCV_CSR_SSPM_SPLM_LEVEL0 0x00000001 /* R-I-V */
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#define NV_RISCV_CSR_SSPM_SPLM_LEVEL1 0x00000003 /* R---V */
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#define NV_RISCV_CSR_SSPM_SPLM_LEVEL2 0x00000005 /* R---V */
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#define NV_RISCV_CSR_SSPM_SPLM_LEVEL3 0x0000000f /* R---V */
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#define NV_RISCV_CSR_SSPM_UPLM 3:0 /* RWIVF */
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#define NV_RISCV_CSR_SSPM_UPLM_LEVEL0 0x00000001 /* RWI-V */
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#define NV_RISCV_CSR_SSPM_UPLM_LEVEL1 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_SSPM_UPLM_LEVEL2 0x00000005 /* RW--V */
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#define NV_RISCV_CSR_SSPM_UPLM_LEVEL3 0x0000000f /* RW--V */
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#define NV_RISCV_CSR_SRSP 0x000005da /* RWI4R */
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#define NV_RISCV_CSR_SRSP_WPRI1 64-1:10 /* R-IVF */
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#define NV_RISCV_CSR_SRSP_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SRSP_SRSEC 9:9 /* RWIVF */
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#define NV_RISCV_CSR_SRSP_SRSEC_INSEC 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SRSP_SRSEC_SEC 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SRSP_URSEC 8:8 /* RWIVF */
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#define NV_RISCV_CSR_SRSP_URSEC_INSEC 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SRSP_URSEC_SEC 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SRSP_WPRI0 7:4 /* R-IVF */
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#define NV_RISCV_CSR_SRSP_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SRSP_SRPL 3:2 /* RWIVF */
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#define NV_RISCV_CSR_SRSP_SRPL_LEVEL0 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SRSP_SRPL_LEVEL1 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SRSP_SRPL_LEVEL2 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_SRSP_SRPL_LEVEL3 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_SRSP_URPL 1:0 /* RWIVF */
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#define NV_RISCV_CSR_SRSP_URPL_LEVEL0 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SRSP_URPL_LEVEL1 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SRSP_URPL_LEVEL2 0x00000002 /* RW--V */
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#define NV_RISCV_CSR_SRSP_URPL_LEVEL3 0x00000003 /* RW--V */
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#define NV_RISCV_CSR_SCURRUID 0x000005d7 /* RWI4R */
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#define NV_RISCV_CSR_SCURRUID_WPRI 64-1:16 /* R-IVF */
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#define NV_RISCV_CSR_SCURRUID_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SCURRUID_SCURRUID 15:8 /* R-IVF */
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#define NV_RISCV_CSR_SCURRUID_SCURRUID_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SCURRUID_UCURRUID 7:0 /* R-IVF */
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#define NV_RISCV_CSR_SCURRUID_UCURRUID_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SCFG 0x000005d5 /* RWI4R */
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#define NV_RISCV_CSR_SCFG_WPRI4 64-1:14 /* R-IVF */
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#define NV_RISCV_CSR_SCFG_WPRI4_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SCFG_SPOSTIO 13:13 /* RWIVF */
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#define NV_RISCV_CSR_SCFG_SPOSTIO_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCFG_SPOSTIO_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SCFG_UPOSTIO 12:12 /* RWIVF */
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#define NV_RISCV_CSR_SCFG_UPOSTIO_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCFG_UPOSTIO_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SCFG_WPRI3 11:10 /* R-IVF */
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#define NV_RISCV_CSR_SCFG_WPRI3_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SCFG_SSBC 9:9 /* RWIVF */
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#define NV_RISCV_CSR_SCFG_SSBC_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCFG_SSBC_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SCFG_USBC 8:8 /* RWIVF */
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#define NV_RISCV_CSR_SCFG_USBC_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCFG_USBC_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SCFG_WPRI2 7:5 /* R-IVF */
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#define NV_RISCV_CSR_SCFG_WPRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SCFG_USSE 4:4 /* RWIVF */
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#define NV_RISCV_CSR_SCFG_USSE_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCFG_USSE_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SCFG_WPRI1 3:2 /* R-IVF */
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#define NV_RISCV_CSR_SCFG_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SCFG_SWFP_DIS 1:1 /* RWIVF */
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#define NV_RISCV_CSR_SCFG_SWFP_DIS_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SCFG_SWFP_DIS_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SCFG_UWFP_DIS 0:0 /* R-IVF */
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#define NV_RISCV_CSR_SCFG_UWFP_DIS_FALSE 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SBPCFG 0x000005dd /* RWI4R */
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#define NV_RISCV_CSR_SBPCFG_WPRI1 64-1:18 /* R-IVF */
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#define NV_RISCV_CSR_SBPCFG_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SBPCFG_BTB_FLUSHS 17:17 /* -W-VF */
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#define NV_RISCV_CSR_SBPCFG_BTB_FLUSHS_TRUE 0x00000001 /* -W--V */
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#define NV_RISCV_CSR_SBPCFG_BTB_FLUSHU 16:16 /* -W-VF */
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#define NV_RISCV_CSR_SBPCFG_BTB_FLUSHU_TRUE 0x00000001 /* -W--V */
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#define NV_RISCV_CSR_SBPCFG_WPRI0 15:0 /* R-IVF */
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#define NV_RISCV_CSR_SBPCFG_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMISCOPEN 0x000005f9 /* RWI4R */
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#define NV_RISCV_CSR_SMISCOPEN_WPRI 64-1:1 /* R-IVF */
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#define NV_RISCV_CSR_SMISCOPEN_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMISCOPEN_DCACHEOP 0:0 /* RWIVF */
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#define NV_RISCV_CSR_SMISCOPEN_DCACHEOP_DISABLE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMISCOPEN_DCACHEOP_ENABLE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_SSCRATCH2 0x000005c0 /* RWI4R */
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#define NV_RISCV_CSR_SSCRATCH2_VALUE 64-1:0 /* RWIVF */
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#define NV_RISCV_CSR_SSCRATCH2_VALUE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUCTL 0x000005c9 /* R-I4R */
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#define NV_RISCV_CSR_SMPUCTL_WPRI1 64-1:24 /* R-IVF */
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#define NV_RISCV_CSR_SMPUCTL_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMPUCTL_ENTRY_COUNT 23:16 /* R-IVF */
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#define NV_RISCV_CSR_SMPUCTL_ENTRY_COUNT_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMPUCTL_WPRI0 15:0 /* R-IVF */
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#define NV_RISCV_CSR_SMPUCTL_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMPUIDX 0x000005ca /* RWI4R */
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#define NV_RISCV_CSR_SMPUIDX_WPRI 64-1:7 /* R-IVF */
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#define NV_RISCV_CSR_SMPUIDX_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMPUIDX_INDEX 6:0 /* RWIVF */
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#define NV_RISCV_CSR_SMPUIDX_INDEX_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUVA 0x000005cb /* RWI4R */
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#define NV_RISCV_CSR_SMPUVA_BASE 64-1:10 /* RWIVF */
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#define NV_RISCV_CSR_SMPUVA_BASE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUVA_WPRI1 9:8 /* R-IVF */
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#define NV_RISCV_CSR_SMPUVA_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMPUVA_D 7:7 /* RWIVF */
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#define NV_RISCV_CSR_SMPUVA_D_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUVA_A 6:6 /* RWIVF */
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#define NV_RISCV_CSR_SMPUVA_A_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUVA_WPRI 5:1 /* R-IVF */
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#define NV_RISCV_CSR_SMPUVA_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMPUVA_VLD 0:0 /* RWIVF */
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#define NV_RISCV_CSR_SMPUVA_VLD_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUPA 0x000005cc /* RWI4R */
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#define NV_RISCV_CSR_SMPUPA_BASE 64-1:10 /* RWIVF */
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#define NV_RISCV_CSR_SMPUPA_BASE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUPA_WPRI 9:0 /* R-IVF */
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#define NV_RISCV_CSR_SMPUPA_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMPURNG 0x000005ce /* RWI4R */
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#define NV_RISCV_CSR_SMPURNG_RANGE 64-1:10 /* RWIVF */
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#define NV_RISCV_CSR_SMPURNG_RANGE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPURNG_WPRI 9:0 /* R-IVF */
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#define NV_RISCV_CSR_SMPURNG_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMPUATTR 0x000005cf /* RWI4R */
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#define NV_RISCV_CSR_SMPUATTR_WPRI2 64-1:30 /* R-IVF */
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#define NV_RISCV_CSR_SMPUATTR_WPRI2_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMPUATTR_VPR 29:29 /* RWIVF */
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#define NV_RISCV_CSR_SMPUATTR_VPR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUATTR_WPR 28:24 /* RWIVF */
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#define NV_RISCV_CSR_SMPUATTR_WPR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUATTR_L2C_RD 23:22 /* RWIVF */
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#define NV_RISCV_CSR_SMPUATTR_L2C_RD_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUATTR_L2C_WR 21:20 /* RWIVF */
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#define NV_RISCV_CSR_SMPUATTR_L2C_WR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUATTR_COHERENT 19:19 /* RWIVF */
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#define NV_RISCV_CSR_SMPUATTR_COHERENT_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUATTR_CACHEABLE 18:18 /* RWIVF */
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#define NV_RISCV_CSR_SMPUATTR_CACHEABLE_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUATTR_WPRI1 17:9 /* R-IVF */
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#define NV_RISCV_CSR_SMPUATTR_WPRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMPUATTR_WPRI0 8:6 /* R-IVF */
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#define NV_RISCV_CSR_SMPUATTR_WPRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMPUATTR_SX 5:5 /* RWIVF */
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#define NV_RISCV_CSR_SMPUATTR_SX_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUATTR_SW 4:4 /* RWIVF */
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#define NV_RISCV_CSR_SMPUATTR_SW_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUATTR_SR 3:3 /* RWIVF */
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#define NV_RISCV_CSR_SMPUATTR_SR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUATTR_UX 2:2 /* RWIVF */
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#define NV_RISCV_CSR_SMPUATTR_UX_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUATTR_UW 1:1 /* RWIVF */
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#define NV_RISCV_CSR_SMPUATTR_UW_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUATTR_UR 0:0 /* RWIVF */
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#define NV_RISCV_CSR_SMPUATTR_UR_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUIDX2 0x000005d0 /* RWI4R */
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#define NV_RISCV_CSR_SMPUIDX2_WPRI 64-1:2 /* R-IVF */
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#define NV_RISCV_CSR_SMPUIDX2_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SMPUIDX2_IDX 1:0 /* RWIVF */
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#define NV_RISCV_CSR_SMPUIDX2_IDX_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUVLD 0x000005d1 /* RWI4R */
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#define NV_RISCV_CSR_SMPUVLD_VLD 64-1:0 /* RWIVF */
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#define NV_RISCV_CSR_SMPUVLD_VLD_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SMPUDTY 0x000005d2 /* RWI4R */
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#define NV_RISCV_CSR_SMPUDTY_DTY 64-1:0 /* RWIVF */
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#define NV_RISCV_CSR_SMPUDTY_DTY_RST 0x00000000 /* RWI-V */
|
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#define NV_RISCV_CSR_SMPUACC 0x000005d3 /* RWI4R */
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#define NV_RISCV_CSR_SMPUACC_ACC 64-1:0 /* RWIVF */
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#define NV_RISCV_CSR_SMPUACC_ACC_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSYSOPEN 0x000005f8 /* RWI4R */
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#define NV_RISCV_CSR_SSYSOPEN_WPRI 63:8 /* R-IVF */
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#define NV_RISCV_CSR_SSYSOPEN_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_SSYSOPEN_L2FLHDTY 7:7 /* RWIVF */
|
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#define NV_RISCV_CSR_SSYSOPEN_L2FLHDTY_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSYSOPEN_L2CLNCOMP 6:6 /* RWIVF */
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#define NV_RISCV_CSR_SSYSOPEN_L2CLNCOMP_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSYSOPEN_L2PEERINV 5:5 /* RWIVF */
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#define NV_RISCV_CSR_SSYSOPEN_L2PEERINV_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSYSOPEN_L2SYSINV 4:4 /* RWIVF */
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#define NV_RISCV_CSR_SSYSOPEN_L2SYSINV_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSYSOPEN_FLUSH 3:3 /* RWIVF */
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#define NV_RISCV_CSR_SSYSOPEN_FLUSH_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSYSOPEN_TLBINVOP 2:2 /* RWIVF */
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#define NV_RISCV_CSR_SSYSOPEN_TLBINVOP_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSYSOPEN_TLBINVDATA1 1:1 /* RWIVF */
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#define NV_RISCV_CSR_SSYSOPEN_TLBINVDATA1_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_SSYSOPEN_BIND 0:0 /* RWIVF */
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#define NV_RISCV_CSR_SSYSOPEN_BIND_RST 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_DCACHEOP 0x000008d0 /* -W-4R */
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#define NV_RISCV_CSR_DCACHEOP_ADDR 64-1:6 /* -W-VF */
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#define NV_RISCV_CSR_DCACHEOP_RS0 5:3 /* R--VF */
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#define NV_RISCV_CSR_DCACHEOP_ADDR_MODE 2:2 /* -W-VF */
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#define NV_RISCV_CSR_DCACHEOP_ADDR_MODE_VA 0x00000000 /* -W--V */
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#define NV_RISCV_CSR_DCACHEOP_ADDR_MODE_PA 0x00000001 /* -W--V */
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#define NV_RISCV_CSR_DCACHEOP_MODE 1:0 /* -W-VF */
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#define NV_RISCV_CSR_DCACHEOP_MODE_INV_ALL 0x00000000 /* -W--V */
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#define NV_RISCV_CSR_DCACHEOP_MODE_INV_LINE 0x00000001 /* -W--V */
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#define NV_RISCV_CSR_DCACHEOP_MODE_CLR_ALL 0x00000002 /* -W--V */
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#define NV_RISCV_CSR_DCACHEOP_MODE_CLR_LINE 0x00000003 /* -W--V */
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#define NV_RISCV_CSR_CFG 0x00000895 /* RWI4R */
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#define NV_RISCV_CSR_CFG_WIRI0 64-1:13 /* R-IVF */
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#define NV_RISCV_CSR_CFG_WIRI0_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_CFG_UPOSTIO 12:12 /* RWIVF */
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#define NV_RISCV_CSR_CFG_UPOSTIO_FALSE 0x00000000 /* RWI-V */
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#define NV_RISCV_CSR_CFG_UPOSTIO_TRUE 0x00000001 /* RW--V */
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#define NV_RISCV_CSR_CFG_WIRI1 11:0 /* R-IVF */
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#define NV_RISCV_CSR_CFG_WIRI1_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_CURRUID 0x00000897 /* R-I4R */
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#define NV_RISCV_CSR_CURRUID_WPRI 64-1:8 /* R-IVF */
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#define NV_RISCV_CSR_CURRUID_WPRI_RST 0x00000000 /* R-I-V */
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#define NV_RISCV_CSR_CURRUID_UCURRUID 7:0 /* R-IVF */
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#define NV_RISCV_CSR_CURRUID_UCURRUID_RST 0x00000000 /* R-I-V */
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#endif // __ga102_dev_pmu_riscv_csr_64_h__
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