251 lines
20 KiB
C
251 lines
20 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
|
|
*
|
|
* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
|
|
* information contained herein is proprietary and confidential to NVIDIA
|
|
* Corporation. Any use, reproduction, or disclosure without the written
|
|
* permission of NVIDIA Corporation is prohibited.
|
|
*
|
|
* _NVRM_COPYRIGHT_END_
|
|
*/
|
|
|
|
#ifndef __ga102_dev_nv_p2p_h__
|
|
#define __ga102_dev_nv_p2p_h__
|
|
/* This file is autogenerated. Do not edit */
|
|
#define NV_P2P 0x0013AFFF:0x00139000 /* RW--D */
|
|
#define NV_P2P_PRIV_LEVEL_MASK 0x0013AFFC /* RW-4R */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_READ_PROTECTION 3:0 /* RWCVF */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RWC-V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_READ_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_PROTECTION 7:4 /* RWCVF */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_PROTECTION_ALL_LEVELS_ENABLED 0x0000000F /* RW--V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_PROTECTION_ONLY_LEVEL3_ENABLED 0x00000008 /* RW--V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_PROTECTION__FUSE_SIGNAL "nv_p2p_plm" /* */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE0 0x0000000F /* RWC-V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_PROTECTION_FUSE1 0x00000008 /* RW--V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_READ_VIOLATION 8:8 /* RWCVF */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_VIOLATION 9:9 /* RWCVF */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWC-V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL 10:10 /* RWCVF */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWC-V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_READ_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL 11:11 /* RWCVF */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWC-V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_WRITE_CONTROL_LOWERED 0x00000000 /* RW--V */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_ENABLE 31:12 /* RWCVF */
|
|
#define NV_P2P_PRIV_LEVEL_MASK_SOURCE_ENABLE_ALL_SOURCES_ENABLED 0x000FFFFF /* RWC-V */
|
|
#define NV_P2P_WMBTAG_L(i) (0x00139040+(i)*64) /* R-I4A */
|
|
#define NV_P2P_WMBTAG_L__SIZE_1 8 /* */
|
|
#define NV_P2P_WMBTAG_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_WMBTAG_L_PAGE_ADDR 20:0 /* R-IUF */
|
|
#define NV_P2P_WMBTAG_L_PAGE_ADDR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_WMBTAG_H(i) (0x00139044+(i)*64) /* RWI4A */
|
|
#define NV_P2P_WMBTAG_H__SIZE_1 8 /* */
|
|
#define NV_P2P_WMBTAG_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_WMBTAG_H_KIND 7:0 /* R-IUF */
|
|
#define NV_P2P_WMBTAG_H_KIND_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_WMBTAG_H_COMPTAGLINE 24:8 /* R-IUF */
|
|
#define NV_P2P_WMBTAG_H_COMPTAGLINE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_WMBTAG_H_PAGE_SIZE 25:25 /* R-IUF */
|
|
#define NV_P2P_WMBTAG_H_PAGE_SIZE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_WMBTAG_H_UNSUPPORT_READ 26:26 /* RWIVF */
|
|
#define NV_P2P_WMBTAG_H_UNSUPPORT_READ_NOT_ACTIVE 0x00000000 /* R-I-V */
|
|
#define NV_P2P_WMBTAG_H_UNSUPPORT_READ_ACTIVE 0x00000001 /* R---V */
|
|
#define NV_P2P_WMBTAG_H_UNSUPPORT_READ_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_P2P_WMBTAG_H_UNSUPPORT_WRITE 27:27 /* RWIVF */
|
|
#define NV_P2P_WMBTAG_H_UNSUPPORT_WRITE_NOT_ACTIVE 0x00000000 /* R-I-V */
|
|
#define NV_P2P_WMBTAG_H_UNSUPPORT_WRITE_ACTIVE 0x00000001 /* R---V */
|
|
#define NV_P2P_WMBTAG_H_UNSUPPORT_WRITE_CLEAR 0x00000001 /* -W--C */
|
|
#define NV_P2P_WMB_ADDR_L(i) (0x00139048+(i)*64) /* RW-4A */
|
|
#define NV_P2P_WMB_ADDR_L__SIZE_1 8 /* */
|
|
#define NV_P2P_WMB_ADDR_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_WMB_ADDR_L_ADDR 31:3 /* RWIUF */
|
|
#define NV_P2P_WMB_ADDR_L_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_P2P_WMB_ADDR_H(i) (0x0013904c+(i)*64) /* RW-4A */
|
|
#define NV_P2P_WMB_ADDR_H__SIZE_1 8 /* */
|
|
#define NV_P2P_WMB_ADDR_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_WMB_ADDR_H_ADDR 31:0 /* RWIUF */
|
|
#define NV_P2P_WMB_ADDR_H_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_P2P_WMB_DATA_L(i) (0x00139050+(i)*64) /* RW-4A */
|
|
#define NV_P2P_WMB_DATA_L__SIZE_1 8 /* */
|
|
#define NV_P2P_WMB_DATA_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_WMB_DATA_L_ADDR 31:16 /* RWIUF */
|
|
#define NV_P2P_WMB_DATA_L_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_P2P_WMB_DATA_H(i) (0x00139054+(i)*64) /* RW-4A */
|
|
#define NV_P2P_WMB_DATA_H__SIZE_1 8 /* */
|
|
#define NV_P2P_WMB_DATA_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_WMB_DATA_H_ADDR 31:0 /* RWIUF */
|
|
#define NV_P2P_WMB_DATA_H_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_P2P_RREQ_ADDR_L(i) (0x00139058+(i)*64) /* RW-4A */
|
|
#define NV_P2P_RREQ_ADDR_L__SIZE_1 8 /* */
|
|
#define NV_P2P_RREQ_ADDR_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RREQ_ADDR_L_ADDR 31:3 /* RWIUF */
|
|
#define NV_P2P_RREQ_ADDR_L_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_P2P_RREQ_ADDR_H(i) (0x0013905c+(i)*64) /* RW-4A */
|
|
#define NV_P2P_RREQ_ADDR_H__SIZE_1 8 /* */
|
|
#define NV_P2P_RREQ_ADDR_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RREQ_ADDR_H_ADDR 31:0 /* RWIUF */
|
|
#define NV_P2P_RREQ_ADDR_H_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_P2P_RREQ_CTRL(i) (0x00139060+(i)*64) /* RW-4A */
|
|
#define NV_P2P_RREQ_CTRL__SIZE_1 8 /* */
|
|
#define NV_P2P_RREQ_CTRL__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RREQ_CTRL_RREQ_MAX 9:0 /* RWIUF */
|
|
#define NV_P2P_RREQ_CTRL_RREQ_MAX_INIT 0x00000200 /* RWI-V */
|
|
#define NV_P2P_RREQ_CTRL_CPL_PENDING 25:16 /* R--VF */
|
|
#define NV_P2P_WMBOX_ADDR(i) (0x00139064+(i)*64) /* RW-4A */
|
|
#define NV_P2P_WMBOX_ADDR__SIZE_1 8 /* */
|
|
#define NV_P2P_WMBOX_ADDR__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_WMBOX_ADDR_DIS 0:0 /* RWIUF */
|
|
#define NV_P2P_WMBOX_ADDR_DIS_DISABLED 0x00000001 /* RWI-V */
|
|
#define NV_P2P_WMBOX_ADDR_DIS_ENABLED 0x00000000 /* RW--V */
|
|
#define NV_P2P_WMBOX_ADDR_ADDR 18:1 /* RWIUF */
|
|
#define NV_P2P_WMBOX_ADDR_ADDR_INIT 0x0003ffff /* RWI-V */
|
|
#define NV_P2P_WREQMB_L(i) (0x00139068+(i)*64) /* R--4A */
|
|
#define NV_P2P_WREQMB_L__SIZE_1 8 /* */
|
|
#define NV_P2P_WREQMB_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_WREQMB_L_PAGE_ADDR 20:0 /* R-IUF */
|
|
#define NV_P2P_WREQMB_L_PAGE_ADDR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_WREQMB_H(i) (0x0013906c+(i)*64) /* R--4A */
|
|
#define NV_P2P_WREQMB_H__SIZE_1 8 /* */
|
|
#define NV_P2P_WREQMB_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_WREQMB_H_KIND 7:0 /* R-IUF */
|
|
#define NV_P2P_WREQMB_H_KIND_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_WREQMB_H_COMPTAGLINE 24:8 /* R-IUF */
|
|
#define NV_P2P_WREQMB_H_COMPTAGLINE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_WREQMB_H_PAGE_SIZE 25:25 /* R-IUF */
|
|
#define NV_P2P_WREQMB_H_PAGE_SIZE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_RREQMB_L(i) (0x00139070+(i)*64) /* R--4A */
|
|
#define NV_P2P_RREQMB_L__SIZE_1 8 /* */
|
|
#define NV_P2P_RREQMB_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RREQMB_L_ADDR 31:0 /* R-IUF */
|
|
#define NV_P2P_RREQMB_L_ADDR_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_RREQMB_H(i) (0x00139074+(i)*64) /* R--4A */
|
|
#define NV_P2P_RREQMB_H__SIZE_1 8 /* */
|
|
#define NV_P2P_RREQMB_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RREQMB_H_LEN 11:4 /* R-IUF */
|
|
#define NV_P2P_RREQMB_H_LEN_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_RREQMB_H_COMPTAGLINE 29:13 /* R-IUF */
|
|
#define NV_P2P_RREQMB_H_COMPTAGLINE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_RREQMB_H_PAGE_SIZE 31:30 /* R-IUF */
|
|
#define NV_P2P_RREQMB_H_PAGE_SIZE_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_RREQMB_0(i) (0x00139078+(i)*64) /* R--4A */
|
|
#define NV_P2P_RREQMB_0__SIZE_1 8 /* */
|
|
#define NV_P2P_RREQMB_0__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RREQMB_0_KIND 7:0 /* R-IUF */
|
|
#define NV_P2P_RREQMB_0_KIND_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_RREQMB_0_NOTIFIER 8:8 /* R-IUF */
|
|
#define NV_P2P_RREQMB_0_NOTIFIER_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_RREQMB_0_NOTIFIER_DATA 31:16 /* R-IUF */
|
|
#define NV_P2P_RREQMB_0_NOTIFIER_DATA_INIT 0x00000000 /* R-I-V */
|
|
#define NV_P2P_RCOMP_ADDR_L(i) (0x001392FC+(i)*64) /* RW-4A */
|
|
#define NV_P2P_RCOMP_ADDR_L__SIZE_1 8 /* */
|
|
#define NV_P2P_RCOMP_ADDR_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMP_ADDR_L_ADDR 31:7 /* RWIUF */
|
|
#define NV_P2P_RCOMP_ADDR_L_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_P2P_RCOMP_ADDR_H(i) (0x00139300+(i)*64) /* RW-4A */
|
|
#define NV_P2P_RCOMP_ADDR_H__SIZE_1 8 /* */
|
|
#define NV_P2P_RCOMP_ADDR_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMP_ADDR_H_ADDR 31:0 /* RWIUF */
|
|
#define NV_P2P_RCOMP_ADDR_H_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_P2P_RCOMP_LIMIT_L(i) (0x00139304+(i)*64) /* RW-4A */
|
|
#define NV_P2P_RCOMP_LIMIT_L__SIZE_1 8 /* */
|
|
#define NV_P2P_RCOMP_LIMIT_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMP_LIMIT_L_ADDR 31:0 /* RWIUF */
|
|
#define NV_P2P_RCOMP_LIMIT_L_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_P2P_RCOMP_LIMIT_H(i) (0x00139308+(i)*64) /* RW-4A */
|
|
#define NV_P2P_RCOMP_LIMIT_H__SIZE_1 8 /* */
|
|
#define NV_P2P_RCOMP_LIMIT_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMP_LIMIT_H_ADDR 31:0 /* RWIUF */
|
|
#define NV_P2P_RCOMP_LIMIT_H_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_P2P_RCOMP_NOTIFIER_L(i) (0x0013930c+(i)*64) /* RW-4A */
|
|
#define NV_P2P_RCOMP_NOTIFIER_L__SIZE_1 8 /* */
|
|
#define NV_P2P_RCOMP_NOTIFIER_L__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMP_NOTIFIER_L_ADDR 31:0 /* RWIUF */
|
|
#define NV_P2P_RCOMP_NOTIFIER_L_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_P2P_RCOMP_NOTIFIER_H(i) (0x00139310+(i)*64) /* RW-4A */
|
|
#define NV_P2P_RCOMP_NOTIFIER_H__SIZE_1 8 /* */
|
|
#define NV_P2P_RCOMP_NOTIFIER_H__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMP_NOTIFIER_H_ADDR 31:0 /* RWIUF */
|
|
#define NV_P2P_RCOMP_NOTIFIER_H_ADDR_INIT 0x00000000 /* RWI-V */
|
|
#define NV_P2P_CPU 0x00139500 /* RW-4R */
|
|
#define NV_P2P_CPU__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_CPU_CPU2PEER_MAP 7:0 /* RWIVF */
|
|
#define NV_P2P_CPU_CPU2PEER_MAP_INIT 0x00000000 /* RWI-V */
|
|
#define NV_P2P_TRIGGER_READ_DW 0x00139504 /* RW-4R */
|
|
#define NV_P2P_TRIGGER_READ_DW__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER0 1:0 /* RWIVF */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER0_DW0 0x00000000 /* RWI-V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER0_DW1 0x00000001 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER0_DW2 0x00000002 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER1 3:2 /* RWIVF */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER1_DW0 0x00000000 /* RWI-V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER1_DW1 0x00000001 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER1_DW2 0x00000002 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER2 5:4 /* RWIVF */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER2_DW0 0x00000000 /* RWI-V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER2_DW1 0x00000001 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER2_DW2 0x00000002 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER3 7:6 /* RWIVF */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER3_DW0 0x00000000 /* RWI-V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER3_DW1 0x00000001 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER3_DW2 0x00000002 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER4 9:8 /* RWIVF */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER4_DW0 0x00000000 /* RWI-V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER4_DW1 0x00000001 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER4_DW2 0x00000002 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER5 11:10 /* RWIVF */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER5_DW0 0x00000000 /* RWI-V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER5_DW1 0x00000001 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER5_DW2 0x00000002 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER6 13:12 /* RWIVF */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER6_DW0 0x00000000 /* RWI-V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER6_DW1 0x00000001 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER6_DW2 0x00000002 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER7 15:14 /* RWIVF */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER7_DW0 0x00000000 /* RWI-V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER7_DW1 0x00000001 /* RW--V */
|
|
#define NV_P2P_TRIGGER_READ_DW_PEER7_DW2 0x00000002 /* RW--V */
|
|
#define NV_P2P_RCOMPMB_0(i) (0x0013A000+(i)*4) /* C--4A */
|
|
#define NV_P2P_RCOMPMB_0__SIZE_1 32 /* */
|
|
#define NV_P2P_RCOMPMB_0__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMPMB_0_VALUE 31:0 /* C--UF */
|
|
#define NV_P2P_RCOMPMB_0_VALUE_INIT 0x00000000 /* C---V */
|
|
#define NV_P2P_RCOMPMB_1(i) (0x0013A100+(i)*4) /* C--4A */
|
|
#define NV_P2P_RCOMPMB_1__SIZE_1 32 /* */
|
|
#define NV_P2P_RCOMPMB_1__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMPMB_1_VALUE 31:0 /* C--UF */
|
|
#define NV_P2P_RCOMPMB_1_VALUE_INIT 0x00000000 /* C---V */
|
|
#define NV_P2P_RCOMPMB_2(i) (0x0013A200+(i)*4) /* C--4A */
|
|
#define NV_P2P_RCOMPMB_2__SIZE_1 32 /* */
|
|
#define NV_P2P_RCOMPMB_2__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMPMB_2_VALUE 31:0 /* C--UF */
|
|
#define NV_P2P_RCOMPMB_2_VALUE_INIT 0x00000000 /* C---V */
|
|
#define NV_P2P_RCOMPMB_3(i) (0x0013A300+(i)*4) /* C--4A */
|
|
#define NV_P2P_RCOMPMB_3__SIZE_1 32 /* */
|
|
#define NV_P2P_RCOMPMB_3__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMPMB_3_VALUE 31:0 /* C--UF */
|
|
#define NV_P2P_RCOMPMB_3_VALUE_INIT 0x00000000 /* C---V */
|
|
#define NV_P2P_RCOMPMB_4(i) (0x0013A400+(i)*4) /* C--4A */
|
|
#define NV_P2P_RCOMPMB_4__SIZE_1 32 /* */
|
|
#define NV_P2P_RCOMPMB_4__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMPMB_4_VALUE 31:0 /* C--UF */
|
|
#define NV_P2P_RCOMPMB_4_VALUE_INIT 0x00000000 /* C---V */
|
|
#define NV_P2P_RCOMPMB_5(i) (0x0013A500+(i)*4) /* C--4A */
|
|
#define NV_P2P_RCOMPMB_5__SIZE_1 32 /* */
|
|
#define NV_P2P_RCOMPMB_5__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMPMB_5_VALUE 31:0 /* C--UF */
|
|
#define NV_P2P_RCOMPMB_5_VALUE_INIT 0x00000000 /* C---V */
|
|
#define NV_P2P_RCOMPMB_6(i) (0x0013A600+(i)*4) /* C--4A */
|
|
#define NV_P2P_RCOMPMB_6__SIZE_1 32 /* */
|
|
#define NV_P2P_RCOMPMB_6__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMPMB_6_VALUE 31:0 /* C--UF */
|
|
#define NV_P2P_RCOMPMB_6_VALUE_INIT 0x00000000 /* C---V */
|
|
#define NV_P2P_RCOMPMB_7(i) (0x0013A700+(i)*4) /* C--4A */
|
|
#define NV_P2P_RCOMPMB_7__SIZE_1 32 /* */
|
|
#define NV_P2P_RCOMPMB_7__PRIV_LEVEL_MASK 0x0013AFFC /* */
|
|
#define NV_P2P_RCOMPMB_7_VALUE 31:0 /* C--UF */
|
|
#define NV_P2P_RCOMPMB_7_VALUE_INIT 0x00000000 /* C---V */
|
|
#endif // __ga102_dev_nv_p2p_h__
|