1504 lines
136 KiB
C
1504 lines
136 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_ioctrl_ip_h__
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#define __ga102_dev_ioctrl_ip_h__
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/* This file is autogenerated. Do not edit */
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#define NV_IOCTRL 0x0000FFF:0x00000000 /* RW--D */
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#define NV_IOCTRL_CSPEC 0x00017FF:0x00001000 /* RW--D */
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#define NV_IOCTRL_DISC 0x0001FFF:0x00001800 /* RW--D */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0 0x00000000 /* RW-4R */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1 0x00000004 /* RW-4R */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2 0x00000008 /* RW-4R */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask2" /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK2_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3 0x0000000c /* RW-4R */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask3" /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK3_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4 0x00000010 /* RW-4R */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask4" /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK4_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5 0x00000014 /* RW-4R */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask5" /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK5_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6 0x00000018 /* RW-4R */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask6" /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK6_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7 0x0000001c /* RW-4R */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask7" /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_PRIV_LEVEL_MASK7_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_DEBUG_MISC_CTRL 0x00000800 /* RW-4R */
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#define NV_IOCTRL_DEBUG_MISC_CTRL__PRIV_LEVEL_MASK 0x00000010 /* */
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#define NV_IOCTRL_DEBUG_MISC_CTRL_GLBL_ILA_TRIG_EN 31:31 /* RWEVF */
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#define NV_IOCTRL_DEBUG_MISC_CTRL_GLBL_ILA_TRIG_EN_INIT 0x00000000 /* RWE-V */
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#define NV_IOCTRL_DEBUG_MUX_CTRL 0x00000804 /* RW-4R */
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#define NV_IOCTRL_DEBUG_MUX_CTRL__PRIV_LEVEL_MASK 0x00000010 /* */
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#define NV_IOCTRL_DEBUG_MUX_CTRL_GROUP252 3:0 /* RWEVF */
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#define NV_IOCTRL_DEBUG_MUX_CTRL_GROUP252_INIT 0x00000007 /* RWE-V */
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#define NV_IOCTRL_DEBUG_MUX_CTRL_GROUP253 7:4 /* RWEVF */
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#define NV_IOCTRL_DEBUG_MUX_CTRL_GROUP253_INIT 0x00000009 /* RWE-V */
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#define NV_IOCTRL_DEBUG_MUX_CTRL_GROUP254 11:8 /* RWEVF */
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#define NV_IOCTRL_DEBUG_MUX_CTRL_GROUP254_INIT 0x00000005 /* RWE-V */
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#define NV_IOCTRL_DEBUG_MUX_CTRL_GROUP255 15:12 /* RWEVF */
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#define NV_IOCTRL_DEBUG_MUX_CTRL_GROUP255_INIT 0x0000000a /* RWE-V */
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#define NV_IOCTRL_DEBUG_MUX_CTRL_WATCHBUSENABLE 31:31 /* RWEVF */
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#define NV_IOCTRL_DEBUG_MUX_CTRL_WATCHBUSENABLE_INIT 0x00000000 /* RWE-V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT 0x00000808 /* RW-4R */
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#define NV_IOCTRL_DEBUG_MUX_SELECT__PRIV_LEVEL_MASK 0x00000010 /* */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0 7:0 /* RWEVF */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP0 0x00000000 /* RWE-V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP1 0x00000001 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP2 0x00000002 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP3 0x00000003 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP4 0x00000004 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP5 0x00000005 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP6 0x00000006 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP7 0x00000007 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP8 0x00000008 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP9 0x00000009 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP10 0x0000000a /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP11 0x0000000b /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP12 0x0000000c /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP13 0x0000000d /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP14 0x0000000e /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP15 0x0000000f /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP16 0x00000010 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP17 0x00000011 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP18 0x00000012 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP19 0x00000013 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP20 0x00000014 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP21 0x00000015 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP22 0x00000016 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP23 0x00000017 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP24 0x00000018 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP25 0x00000019 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP26 0x0000001a /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP27 0x0000001b /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP28 0x0000001c /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP29 0x0000001d /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP30 0x0000001e /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP31 0x0000001f /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP32 0x00000020 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP33 0x00000021 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP34 0x00000022 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP35 0x00000023 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP36 0x00000024 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP37 0x00000025 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP38 0x00000026 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP39 0x00000027 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP40 0x00000028 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP41 0x00000029 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP42 0x0000002a /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP43 0x0000002b /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP44 0x0000002c /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP45 0x0000002d /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP46 0x0000002e /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP47 0x0000002f /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP48 0x00000030 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP49 0x00000031 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP50 0x00000032 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP51 0x00000033 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP52 0x00000034 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP53 0x00000035 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP54 0x00000036 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP55 0x00000037 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP56 0x00000038 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP57 0x00000039 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP58 0x0000003a /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP59 0x0000003b /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP60 0x0000003c /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP61 0x0000003d /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP62 0x0000003e /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP63 0x0000003f /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP64 0x00000040 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP65 0x00000041 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP66 0x00000042 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP67 0x00000043 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP68 0x00000044 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP69 0x00000045 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP70 0x00000046 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP71 0x00000047 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP72 0x00000048 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP73 0x00000049 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP74 0x0000004a /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP75 0x0000004b /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP76 0x0000004c /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP77 0x0000004d /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP78 0x0000004e /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP79 0x0000004f /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP80 0x00000050 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP81 0x00000051 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP82 0x00000052 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP83 0x00000053 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP84 0x00000054 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP85 0x00000055 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP86 0x00000056 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP87 0x00000057 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP88 0x00000058 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP89 0x00000059 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP90 0x0000005a /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP91 0x0000005b /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP92 0x0000005c /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP93 0x0000005d /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP94 0x0000005e /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP95 0x0000005f /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP96 0x00000060 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP97 0x00000061 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP98 0x00000062 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP99 0x00000063 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP100 0x00000064 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP101 0x00000065 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP102 0x00000066 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP103 0x00000067 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP104 0x00000068 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP105 0x00000069 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP106 0x0000006a /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP107 0x0000006b /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP108 0x0000006c /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP109 0x0000006d /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP110 0x0000006e /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP111 0x0000006f /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP112 0x00000070 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP113 0x00000071 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP114 0x00000072 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP115 0x00000073 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP116 0x00000074 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP117 0x00000075 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP118 0x00000076 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP119 0x00000077 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP120 0x00000078 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP121 0x00000079 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP122 0x0000007a /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP123 0x0000007b /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP124 0x0000007c /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP125 0x0000007d /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP126 0x0000007e /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP127 0x0000007f /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP128 0x00000080 /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP252 0x000000fc /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP253 0x000000fd /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP254 0x000000fe /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT0_GRP255 0x000000ff /* RW--V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT1 15:8 /* RWEVF */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT1_INIT 0x00000000 /* RWE-V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT2 23:16 /* RWEVF */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT2_INIT 0x00000000 /* RWE-V */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT3 31:24 /* RWEVF */
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#define NV_IOCTRL_DEBUG_MUX_SELECT_M1SELECT3_INIT 0x00000000 /* RWE-V */
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#define NV_IOCTRL_TOP_INTR_0_STATUS 0x00000200 /* R--4R */
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#define NV_IOCTRL_TOP_INTR_0_STATUS_LINK 3:0 /* R-EVF */
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#define NV_IOCTRL_TOP_INTR_0_STATUS_LINK_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_TOP_INTR_0_STATUS_COMMON 31:31 /* R-EVF */
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#define NV_IOCTRL_TOP_INTR_0_STATUS_COMMON_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_TOP_INTR_1_STATUS 0x00000204 /* R--4R */
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#define NV_IOCTRL_TOP_INTR_1_STATUS_LINK 3:0 /* R-EVF */
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#define NV_IOCTRL_TOP_INTR_1_STATUS_LINK_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_TOP_INTR_1_STATUS_COMMON 31:31 /* R-EVF */
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#define NV_IOCTRL_TOP_INTR_1_STATUS_COMMON_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_TOP_INTR0 0x00000280 /* R--4R */
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#define NV_IOCTRL_TOP_INTR0_VECTORID 31:0 /* R-EVF */
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#define NV_IOCTRL_TOP_INTR0_VECTORID_INIT 0x00000096 /* R-E-V */
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#define NV_IOCTRL_TOP_INTR1 0x00000284 /* R--4R */
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#define NV_IOCTRL_TOP_INTR1_VECTORID 31:0 /* R-EVF */
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#define NV_IOCTRL_TOP_INTR1_VECTORID_INIT 0x00000090 /* R-E-V */
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#define NV_IOCTRL_COMMON_INTR_0_MASK 0x00000220 /* RW-4R */
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#define NV_IOCTRL_COMMON_INTR_0_MASK_FATAL 0:0 /* RWIVF */
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#define NV_IOCTRL_COMMON_INTR_0_MASK_FATAL_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_COMMON_INTR_0_MASK_NONFATAL 1:1 /* RWIVF */
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#define NV_IOCTRL_COMMON_INTR_0_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_COMMON_INTR_0_MASK_CORRECTABLE 2:2 /* RWIVF */
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#define NV_IOCTRL_COMMON_INTR_0_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_COMMON_INTR_0_MASK_INTR0 3:3 /* RWIVF */
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#define NV_IOCTRL_COMMON_INTR_0_MASK_INTR0_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_COMMON_INTR_0_MASK_INTR1 4:4 /* RWIVF */
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#define NV_IOCTRL_COMMON_INTR_0_MASK_INTR1_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_COMMON_INTR_0_STATUS 0x00000224 /* R--4R */
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#define NV_IOCTRL_COMMON_INTR_0_STATUS_FATAL 0:0 /* R-EVF */
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#define NV_IOCTRL_COMMON_INTR_0_STATUS_FATAL_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_COMMON_INTR_0_STATUS_NONFATAL 1:1 /* R-EVF */
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#define NV_IOCTRL_COMMON_INTR_0_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_COMMON_INTR_0_STATUS_CORRECTABLE 2:2 /* R-EVF */
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#define NV_IOCTRL_COMMON_INTR_0_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_COMMON_INTR_0_STATUS_INTR0 3:3 /* R-EVF */
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#define NV_IOCTRL_COMMON_INTR_0_STATUS_INTR0_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_COMMON_INTR_0_STATUS_INTR1 4:4 /* R-EVF */
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#define NV_IOCTRL_COMMON_INTR_0_STATUS_INTR1_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_COMMON_INTR_1_MASK 0x00000228 /* RW-4R */
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#define NV_IOCTRL_COMMON_INTR_1_MASK_FATAL 0:0 /* RWIVF */
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#define NV_IOCTRL_COMMON_INTR_1_MASK_FATAL_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_COMMON_INTR_1_MASK_NONFATAL 1:1 /* RWIVF */
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#define NV_IOCTRL_COMMON_INTR_1_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_COMMON_INTR_1_MASK_CORRECTABLE 2:2 /* RWIVF */
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#define NV_IOCTRL_COMMON_INTR_1_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_COMMON_INTR_1_MASK_INTR0 3:3 /* RWIVF */
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#define NV_IOCTRL_COMMON_INTR_1_MASK_INTR0_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_COMMON_INTR_1_MASK_INTR1 4:4 /* RWIVF */
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#define NV_IOCTRL_COMMON_INTR_1_MASK_INTR1_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_COMMON_INTR_1_STATUS 0x0000022c /* R--4R */
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#define NV_IOCTRL_COMMON_INTR_1_STATUS_FATAL 0:0 /* R-EVF */
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#define NV_IOCTRL_COMMON_INTR_1_STATUS_FATAL_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_COMMON_INTR_1_STATUS_NONFATAL 1:1 /* R-EVF */
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#define NV_IOCTRL_COMMON_INTR_1_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_COMMON_INTR_1_STATUS_CORRECTABLE 2:2 /* R-EVF */
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#define NV_IOCTRL_COMMON_INTR_1_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_COMMON_INTR_1_STATUS_INTR0 3:3 /* R-EVF */
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#define NV_IOCTRL_COMMON_INTR_1_STATUS_INTR0_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_COMMON_INTR_1_STATUS_INTR1 4:4 /* R-EVF */
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#define NV_IOCTRL_COMMON_INTR_1_STATUS_INTR1_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_LINK_INTR_0_MASK(i) (0x00000300+(i)*0x40) /* RW-4A */
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#define NV_IOCTRL_LINK_INTR_0_MASK__SIZE_1 4 /* */
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#define NV_IOCTRL_LINK_INTR_0_MASK_FATAL 0:0 /* RWIVF */
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#define NV_IOCTRL_LINK_INTR_0_MASK_FATAL_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_LINK_INTR_0_MASK_NONFATAL 1:1 /* RWIVF */
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#define NV_IOCTRL_LINK_INTR_0_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_LINK_INTR_0_MASK_CORRECTABLE 2:2 /* RWIVF */
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#define NV_IOCTRL_LINK_INTR_0_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_LINK_INTR_0_MASK_INTR0 3:3 /* RWIVF */
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#define NV_IOCTRL_LINK_INTR_0_MASK_INTR0_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_LINK_INTR_0_MASK_INTR1 4:4 /* RWIVF */
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#define NV_IOCTRL_LINK_INTR_0_MASK_INTR1_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_LINK_INTR_0_STATUS(i) (0x00000304+(i)*0x40) /* R--4A */
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#define NV_IOCTRL_LINK_INTR_0_STATUS__SIZE_1 4 /* */
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#define NV_IOCTRL_LINK_INTR_0_STATUS_FATAL 0:0 /* R-EVF */
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#define NV_IOCTRL_LINK_INTR_0_STATUS_FATAL_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_LINK_INTR_0_STATUS_NONFATAL 1:1 /* R-EVF */
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#define NV_IOCTRL_LINK_INTR_0_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_LINK_INTR_0_STATUS_CORRECTABLE 2:2 /* R-EVF */
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#define NV_IOCTRL_LINK_INTR_0_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_LINK_INTR_0_STATUS_INTR0 3:3 /* R-EVF */
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#define NV_IOCTRL_LINK_INTR_0_STATUS_INTR0_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_LINK_INTR_0_STATUS_INTR1 4:4 /* R-EVF */
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#define NV_IOCTRL_LINK_INTR_0_STATUS_INTR1_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_LINK_INTR_1_MASK(i) (0x00000308+(i)*0x40) /* RW-4A */
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#define NV_IOCTRL_LINK_INTR_1_MASK__SIZE_1 4 /* */
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#define NV_IOCTRL_LINK_INTR_1_MASK_FATAL 0:0 /* RWIVF */
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#define NV_IOCTRL_LINK_INTR_1_MASK_FATAL_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_LINK_INTR_1_MASK_NONFATAL 1:1 /* RWIVF */
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#define NV_IOCTRL_LINK_INTR_1_MASK_NONFATAL_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_LINK_INTR_1_MASK_CORRECTABLE 2:2 /* RWIVF */
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#define NV_IOCTRL_LINK_INTR_1_MASK_CORRECTABLE_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_LINK_INTR_1_MASK_INTR0 3:3 /* RWIVF */
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#define NV_IOCTRL_LINK_INTR_1_MASK_INTR0_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_LINK_INTR_1_MASK_INTR1 4:4 /* RWIVF */
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#define NV_IOCTRL_LINK_INTR_1_MASK_INTR1_INIT 0x00000000 /* RWI-V */
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#define NV_IOCTRL_LINK_INTR_1_STATUS(i) (0x0000030c+(i)*0x40) /* R--4A */
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#define NV_IOCTRL_LINK_INTR_1_STATUS__SIZE_1 4 /* */
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#define NV_IOCTRL_LINK_INTR_1_STATUS_FATAL 0:0 /* R-EVF */
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#define NV_IOCTRL_LINK_INTR_1_STATUS_FATAL_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_LINK_INTR_1_STATUS_NONFATAL 1:1 /* R-EVF */
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#define NV_IOCTRL_LINK_INTR_1_STATUS_NONFATAL_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_LINK_INTR_1_STATUS_CORRECTABLE 2:2 /* R-EVF */
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#define NV_IOCTRL_LINK_INTR_1_STATUS_CORRECTABLE_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_LINK_INTR_1_STATUS_INTR0 3:3 /* R-EVF */
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#define NV_IOCTRL_LINK_INTR_1_STATUS_INTR0_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_LINK_INTR_1_STATUS_INTR1 4:4 /* R-EVF */
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#define NV_IOCTRL_LINK_INTR_1_STATUS_INTR1_INIT 0x00000000 /* R-E-V */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG 0x00000600 /* RW-4R */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG__PRIV_LEVEL_MASK 0x00000008 /* */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_TIMEOUT 17:0 /* RWEVF */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_TIMEOUT_INIT 0x00001000 /* RWE-V */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_SETUP_CLOCKS 22:20 /* RWEVF */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_SETUP_CLOCKS_INIT 0x00000000 /* RWE-V */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_WAIT_CLOCKS 26:24 /* RWEVF */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_WAIT_CLOCKS_INIT 0x00000000 /* RWE-V */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_HOLD_CLOCKS 29:27 /* RWEVF */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_HOLD_CLOCKS_INIT 0x00000000 /* RWE-V */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_FS_ACTION 30:30 /* RWEVF */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_FS_ACTION_ERROR 0x00000000 /* RWE-V */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_FS_ACTION_SOLDIER_ON 0x00000001 /* RW--V */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_RESET_ACTION 31:31 /* RWEVF */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_RESET_ACTION_ERROR 0x00000000 /* RWE-V */
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#define NV_IOCTRL_PLL_PRI_MASTER_SMCONFIG_RESET_ACTION_SOLDIER_ON 0x00000001 /* RW--V */
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#define NV_IOCTRL_PLL_PRI_CLOCK_GATING 0x00000604 /* RW-4R */
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#define NV_IOCTRL_PLL_PRI_CLOCK_GATING_CG1_SLCG 0:0 /* RWEVF */
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#define NV_IOCTRL_PLL_PRI_CLOCK_GATING_CG1_SLCG_ENABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_PLL_PRI_CLOCK_GATING_CG1_SLCG_DISABLED 0x00000001 /* RWE-V */
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#define NV_IOCTRL_PLL_PRI_CLOCK_GATING_CG1_SLCG__PROD 0x00000000 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0 0x00000700 /* RW-4R */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0__PRIV_LEVEL_MASK 0x0000000c /* */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_TX_FORWARD_READ 1:0 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_TX_FORWARD_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_TX_FORWARD_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_TX_FORWARD_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_TX_FORWARD_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_TX_REVERSE_READ 3:2 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_TX_REVERSE_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_TX_REVERSE_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_TX_REVERSE_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_TX_REVERSE_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_RX_FORWARD_READ 5:4 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_RX_FORWARD_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_RX_FORWARD_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_RX_FORWARD_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_RX_FORWARD_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_RX_REVERSE_READ 7:6 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_RX_REVERSE_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_RX_REVERSE_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_RX_REVERSE_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK0_RX_REVERSE_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1 0x00000704 /* RW-4R */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1__PRIV_LEVEL_MASK 0x0000000c /* */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_TX_FORWARD_READ 1:0 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_TX_FORWARD_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_TX_FORWARD_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_TX_FORWARD_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_TX_FORWARD_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_TX_REVERSE_READ 3:2 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_TX_REVERSE_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_TX_REVERSE_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_TX_REVERSE_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_TX_REVERSE_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_RX_FORWARD_READ 5:4 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_RX_FORWARD_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_RX_FORWARD_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_RX_FORWARD_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_RX_FORWARD_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_RX_REVERSE_READ 7:6 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_RX_REVERSE_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_RX_REVERSE_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_RX_REVERSE_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK1_RX_REVERSE_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2 0x00000708 /* RW-4R */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2__PRIV_LEVEL_MASK 0x0000000c /* */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_TX_FORWARD_READ 1:0 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_TX_FORWARD_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_TX_FORWARD_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_TX_FORWARD_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_TX_FORWARD_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_TX_REVERSE_READ 3:2 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_TX_REVERSE_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_TX_REVERSE_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_TX_REVERSE_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_TX_REVERSE_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_RX_FORWARD_READ 5:4 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_RX_FORWARD_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_RX_FORWARD_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_RX_FORWARD_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_RX_FORWARD_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_RX_REVERSE_READ 7:6 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_RX_REVERSE_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_RX_REVERSE_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_RX_REVERSE_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK2_RX_REVERSE_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3 0x0000070c /* RW-4R */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3__PRIV_LEVEL_MASK 0x0000000c /* */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_TX_FORWARD_READ 1:0 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_TX_FORWARD_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_TX_FORWARD_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_TX_FORWARD_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_TX_FORWARD_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_TX_REVERSE_READ 3:2 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_TX_REVERSE_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_TX_REVERSE_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_TX_REVERSE_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_TX_REVERSE_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_RX_FORWARD_READ 5:4 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_RX_FORWARD_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_RX_FORWARD_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_RX_FORWARD_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_RX_FORWARD_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_RX_REVERSE_READ 7:6 /* RWEVF */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_RX_REVERSE_READ_0001 0x00000000 /* RWE-V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_RX_REVERSE_READ_0010 0x00000001 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_RX_REVERSE_READ_0100 0x00000002 /* RW--V */
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#define NV_IOCTRL_RING_BUF_POINTERS_LINK3_RX_REVERSE_READ_1000 0x00000003 /* RW--V */
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#define NV_IOCTRL_SCRATCH_WARM 0x00000fc0 /* RW-4R */
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#define NV_IOCTRL_SCRATCH_WARM_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_SCRATCH_COLD 0x00000fc4 /* RW-4R */
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#define NV_IOCTRL_SCRATCH_COLD_DATA 31:0 /* RWIVF */
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#define NV_IOCTRL_SCRATCH_COLD_DATA_INIT 0xdeadbaad /* RWI-V */
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#define NV_IOCTRL_SCRATCH_PRIVMASK0 0x00000fd0 /* RW-4R */
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#define NV_IOCTRL_SCRATCH_PRIVMASK0__PRIV_LEVEL_MASK 0x00000000 /* */
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#define NV_IOCTRL_SCRATCH_PRIVMASK0_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_SCRATCH_PRIVMASK0_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_SCRATCH_PRIVMASK1 0x00000fd4 /* RW-4R */
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#define NV_IOCTRL_SCRATCH_PRIVMASK1__PRIV_LEVEL_MASK 0x00000004 /* */
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#define NV_IOCTRL_SCRATCH_PRIVMASK1_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_SCRATCH_PRIVMASK1_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_SCRATCH_PRIVMASK2 0x00000fd8 /* RW-4R */
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#define NV_IOCTRL_SCRATCH_PRIVMASK2__PRIV_LEVEL_MASK 0x00000008 /* */
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#define NV_IOCTRL_SCRATCH_PRIVMASK2_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_SCRATCH_PRIVMASK2_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_SCRATCH_PRIVMASK3 0x00000fdc /* RW-4R */
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#define NV_IOCTRL_SCRATCH_PRIVMASK3__PRIV_LEVEL_MASK 0x0000000c /* */
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#define NV_IOCTRL_SCRATCH_PRIVMASK3_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_SCRATCH_PRIVMASK3_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_SCRATCH_PRIVMASK4 0x00000fe0 /* RW-4R */
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#define NV_IOCTRL_SCRATCH_PRIVMASK4__PRIV_LEVEL_MASK 0x00000010 /* */
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#define NV_IOCTRL_SCRATCH_PRIVMASK4_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_SCRATCH_PRIVMASK4_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_SCRATCH_PRIVMASK5 0x00000fe4 /* RW-4R */
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#define NV_IOCTRL_SCRATCH_PRIVMASK5__PRIV_LEVEL_MASK 0x00000014 /* */
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#define NV_IOCTRL_SCRATCH_PRIVMASK5_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_SCRATCH_PRIVMASK5_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_SCRATCH_PRIVMASK6 0x00000fe8 /* RW-4R */
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#define NV_IOCTRL_SCRATCH_PRIVMASK6__PRIV_LEVEL_MASK 0x00000018 /* */
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#define NV_IOCTRL_SCRATCH_PRIVMASK6_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_SCRATCH_PRIVMASK6_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_SCRATCH_PRIVMASK7 0x00000fec /* RW-4R */
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#define NV_IOCTRL_SCRATCH_PRIVMASK7__PRIV_LEVEL_MASK 0x0000001c /* */
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#define NV_IOCTRL_SCRATCH_PRIVMASK7_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_SCRATCH_PRIVMASK7_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_DISC_REGISTERS(i) (0x00001800+(i)*0x4) /* R--4A */
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#define NV_IOCTRL_DISC_REGISTERS__SIZE_1 57 /* */
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#define NV_IOCTRL_DISC_REGISTERS_ENTRY 1:0 /* R-XVF */
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#define NV_IOCTRL_DISC_REGISTERS_ENTRY_INVALID 0x00000000 /* R---V */
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#define NV_IOCTRL_DISC_REGISTERS_ENTRY_ENUM 0x00000001 /* R---V */
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#define NV_IOCTRL_DISC_REGISTERS_ENTRY_DATA1 0x00000002 /* R---V */
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#define NV_IOCTRL_DISC_REGISTERS_ENTRY_DATA2 0x00000003 /* R---V */
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#define NV_IOCTRL_DISC_REGISTERS_CONTENTS 30:2 /* R-XVF */
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#define NV_IOCTRL_DISC_REGISTERS_CHAIN 31:31 /* R-XVF */
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#define NV_IOCTRL_DISC_REGISTERS_CHAIN_DISABLE 0x00000000 /* R---V */
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#define NV_IOCTRL_DISC_REGISTERS_CHAIN_ENABLE 0x00000001 /* R---V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0 0x00001500 /* RW-4R */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask0" /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK0_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1 0x00001504 /* RW-4R */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask1" /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK1_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2 0x00001508 /* RW-4R */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask2" /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK2_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3 0x0000150c /* RW-4R */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask3" /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK3_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4 0x00001510 /* RW-4R */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask4" /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK4_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5 0x00001514 /* RW-4R */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask5" /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK5_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6 0x00001518 /* RW-4R */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask6" /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK6_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7 0x0000151c /* RW-4R */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION 3:0 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_ENABLED 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_1_ENABLED 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0 0:0 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1 1:1 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2 2:2 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3 3:3 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION 7:4 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION__FUSE_SIGNAL "nvlink_mask7" /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_ENABLED_FUSE0 0x0000000f /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_2_AND_1_ENABLED 0x0000000e /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_2_ENABLED 0x0000000c /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_1_ENABLED_FUSE1 0x0000000a /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_AND_0_ENABLED 0x00000009 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_3_ENABLED 0x00000008 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_2_ENABLED 0x00000004 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_1_ENABLED 0x00000002 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL_0_ENABLED 0x00000001 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_ALL_LEVELS_DISABLED 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0 4:4 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL0_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1 5:5 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL1_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2 6:6 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL2_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3 7:7 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_ENABLE 0x00000001 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_PROTECTION_LEVEL3_DISABLE 0x00000000 /* */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_VIOLATION 8:8 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_READ_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_VIOLATION 9:9 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_VIOLATION_REPORT_ERROR 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_WRITE_VIOLATION_SOLDIER_ON 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL 10:10 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_SOURCE_READ_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL 11:11 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_BLOCKED 0x00000001 /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_SOURCE_WRITE_CONTROL_LOWERED_TO_0 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_SOURCE_ENABLE 31:12 /* RWIVF */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_SOURCE_ENABLE_ALL 0x000fffff /* RWI-V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_SOURCE_ENABLE_UNUSED 0x000f3fff /* RW--V */
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#define NV_IOCTRL_CSPEC_PRIV_LEVEL_MASK7_SOURCE_ENABLE_NONE 0x00000000 /* RW--V */
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#define NV_IOCTRL_CSPEC_SCRATCH_WARM 0x000017c0 /* RW-4R */
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#define NV_IOCTRL_CSPEC_SCRATCH_WARM_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_CSPEC_SCRATCH_WARM_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_CSPEC_SCRATCH_COLD 0x000017c4 /* RW-4R */
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#define NV_IOCTRL_CSPEC_SCRATCH_COLD_DATA 31:0 /* RWIVF */
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#define NV_IOCTRL_CSPEC_SCRATCH_COLD_DATA_INIT 0xdeadbaad /* RWI-V */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK0 0x000017d0 /* RW-4R */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK0__PRIV_LEVEL_MASK 0x00001500 /* */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK0_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK0_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK1 0x000017d4 /* RW-4R */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK1__PRIV_LEVEL_MASK 0x00001504 /* */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK1_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK1_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK2 0x000017d8 /* RW-4R */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK2__PRIV_LEVEL_MASK 0x00001508 /* */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK2_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK2_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK3 0x000017dc /* RW-4R */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK3__PRIV_LEVEL_MASK 0x0000150c /* */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK3_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK3_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK4 0x000017e0 /* RW-4R */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK4__PRIV_LEVEL_MASK 0x00001510 /* */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK4_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK4_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK5 0x000017e4 /* RW-4R */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK5__PRIV_LEVEL_MASK 0x00001514 /* */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK5_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK5_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK6 0x000017e8 /* RW-4R */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK6__PRIV_LEVEL_MASK 0x00001518 /* */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK6_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK6_DATA_INIT 0xdeadbaad /* RWE-V */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK7 0x000017ec /* RW-4R */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK7__PRIV_LEVEL_MASK 0x0000151c /* */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK7_DATA 31:0 /* RWEVF */
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#define NV_IOCTRL_CSPEC_SCRATCH_PRIVMASK7_DATA_INIT 0xdeadbaad /* RWE-V */
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#endif // __ga102_dev_ioctrl_ip_h__
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