66 lines
4.7 KiB
C
66 lines
4.7 KiB
C
/* _NVRM_COPYRIGHT_BEGIN_
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*
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* Copyright 2003-2016 by NVIDIA Corporation. All rights reserved. All
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* information contained herein is proprietary and confidential to NVIDIA
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* Corporation. Any use, reproduction, or disclosure without the written
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* permission of NVIDIA Corporation is prohibited.
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*
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* _NVRM_COPYRIGHT_END_
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*/
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#ifndef __ga102_dev_imp_h__
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#define __ga102_dev_imp_h__
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/* This file is autogenerated. Do not edit */
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#define NV_MCLK_MHZ_CUTOFF0 1000
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#define NV_MCLK_MHZ_HBM_CUTOFF0 1050
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#define NV_MCLK_MHZ_CUTOFF__SIZE1 2
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#define NV_PFB_HBM_RT_LAT_DRAMCLK_COMPONENT_R0 118
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#define NV_PFB_HBM_RT_LAT_NANOSEC_COMPONENT_R0 68
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#define NV_PFB_RT_LAT_LTCCLK_COMPONENT_R0 131
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#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R0 131
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#define NV_PFB_GDDR5X_RT_LAT_LTCCLK_COMPONENT_R0 131
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#define NV_PFB_GDDR5_RT_LAT_LTCCLK_COMPONENT_R0 131
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#define NV_PFB_HBM_RT_LAT_DRAMCLK_COMPONENT_R1 125
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#define NV_PFB_HBM_RT_LAT_NANOSEC_COMPONENT_R1 68
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#define NV_PFB_RT_LAT_LTCCLK_COMPONENT_R1 1458
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#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R1 1458
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#define NV_PFB_GDDR5X_RT_LAT_LTCCLK_COMPONENT_R1 1158
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#define NV_PFB_GDDR5_RT_LAT_LTCCLK_COMPONENT_R1 866
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#define NV_PFB_GDDR5_RT_LAT_DRAMCLK_COMPONENT_R0 486
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#define NV_PFB_GDDR5_RT_LAT_NANOSEC_COMPONENT_R0 564
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#define NV_PFB_GDDR5X_RT_LAT_DRAMCLK_COMPONENT_R0 682
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#define NV_PFB_GDDR5X_RT_LAT_NANOSEC_COMPONENT_R0 540
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#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R0 1434
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#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R0 62
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#define NV_PFB_GDDR5_RT_LAT_DRAMCLK_COMPONENT_R1 652
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#define NV_PFB_GDDR5_RT_LAT_NANOSEC_COMPONENT_R1 690
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#define NV_PFB_GDDR5X_RT_LAT_DRAMCLK_COMPONENT_R1 944
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#define NV_PFB_GDDR5X_RT_LAT_NANOSEC_COMPONENT_R1 708
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#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R1 1152
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#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R1 62
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#define NV_PFB_SDDR3_RT_LAT_DRAMCLK_COMPONENT_R0 488
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#define NV_PFB_SDDR3_RT_LAT_NANOSEC_COMPONENT_R0 634
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#define NV_PFB_SDDR3_RT_LAT_DRAMCLK_COMPONENT_R1 488
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#define NV_PFB_SDDR3_RT_LAT_NANOSEC_COMPONENT_R1 634
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#define NV_PFB_HUBCLKS 104
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#define NV_PFB_GDDR5_RT_LAT_DRAMCLK_COMPONENT_PER_REPLAY_CYCLE 250 // 250 cycles per CRC replay
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#define NV_PFB_GDDR5_MAX_CRC_REPLAYS 2 // 2 CRC replays
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#define NV_PFB_GDDR5X_RT_LAT_DRAMCLK_COMPONENT_PER_REPLAY_CYCLE 250 // 250 cycles per CRC replay
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#define NV_PFB_GDDR5X_MAX_CRC_REPLAYS 2 // 2 CRC replays
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#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_PER_REPLAY_CYCLE 250 // 250 cycles per CRC replay
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#define NV_PFB_GDDR6_MAX_CRC_REPLAYS 2 // 2 CRC replays
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#define NV_PFB_RT_LAT_XBARCLK_COMPONENT 159
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#define NV_PFB_RT_LAT_SYSCLK_COMPONENT 64
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#define NV_MCLK_MHZ_CUTOFF0_B 600
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#define NV_MCLK_MHZ_CUTOFF1_B 1000
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#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R0_B 123
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#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R0_B 2139
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#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R0_B 62
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#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R1_B 123
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#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R1_B 2995
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#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R1_B 62
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#define NV_PFB_GDDR6_RT_LAT_LTCCLK_COMPONENT_R2_B 123
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#define NV_PFB_GDDR6_RT_LAT_DRAMCLK_COMPONENT_R2_B 6828
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#define NV_PFB_GDDR6_RT_LAT_NANOSEC_COMPONENT_R2_B 60
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#endif // __ga102_dev_imp_h__
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